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LEDC Driver: Added back original definitions of 'duty_resolution' and 'clock_divider'. This update is to provide backward compatibility with ESP-IDF 2.1.

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This commit is contained in:
krzychb 2017-12-04 20:22:24 +01:00
parent 22489d7021
commit 421592a8eb
2 changed files with 19 additions and 11 deletions
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11
components/driver/include/driver/ledc.h
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@ -99,10 +99,13 @@ typedef struct {
* @brief Configuration parameters of LEDC Timer timer for ledc_timer_config function
*/
typedef struct {
ledc_mode_t speed_mode; /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
ledc_timer_bit_t duty_resolution; /*!< LEDC channel duty resolution */
ledc_timer_t timer_num; /*!< The timer source of channel (0 - 3) */
uint32_t freq_hz; /*!< LEDC timer frequency (Hz) */
ledc_mode_t speed_mode; /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
union {
ledc_timer_bit_t duty_resolution; /*!< LEDC channel duty resolution */
ledc_timer_bit_t bit_num __attribute__((deprecated)); /*!< Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1 */
};
ledc_timer_t timer_num; /*!< The timer source of channel (0 - 3) */
uint32_t freq_hz; /*!< LEDC timer frequency (Hz) */
} ledc_timer_config_t;
typedef intr_handle_t ledc_isr_handle_t;

19
components/soc/esp32/include/soc/ledc_struct.h
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@ -69,13 +69,18 @@ typedef volatile struct {
struct {
union {
struct {
uint32_t duty_resolution: 5; /*This register controls resolution of PWN duty by defining the bith width of timer's counter. The max bit width of the counter is 20.*/
uint32_t clock_divider: 18; /*This register is used to configure the divider of clock at the entry of timer. The least significant eight bits represent the decimal part.*/
uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/
uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/
uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/
uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/
uint32_t reserved26: 5;
uint32_t duty_resolution: 5; /*This register controls resolution of PWN duty by defining the bit width of timer's counter. The max bit width of the counter is 20.*/
uint32_t clock_divider: 18; /*This register is used to configure the divider of clock at the entry of timer. The least significant eight bits represent the decimal part.*/
uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/
uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/
uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/
uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/
uint32_t reserved26: 5;
};
struct {
uint32_t bit_num: 5 __attribute__((deprecated)); /*Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1.*/
uint32_t div_num: 18 __attribute__((deprecated)); /*Deprecated in ESP-IDF 3.0. This is an alias to 'clock_divider' for backward compatibility with ESP-IDF 2.1.*/
uint32_t place_holder: 9 __attribute__((deprecated)); /*A place holder to accommodate deprecated members*/
};
uint32_t val;
} conf;