From 3ee437057858e343a25845115bf47e80bf077cb1 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 5 May 2021 17:53:47 +1000 Subject: [PATCH] esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0 Previous linker script relied on nothing else using the .text section As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997 --- components/ulp/ld/esp32s2.ulp.riscv.ld | 1 + components/ulp/ulp_riscv/start.S | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/components/ulp/ld/esp32s2.ulp.riscv.ld b/components/ulp/ld/esp32s2.ulp.riscv.ld index 62840422fe..2134f8dd17 100644 --- a/components/ulp/ld/esp32s2.ulp.riscv.ld +++ b/components/ulp/ld/esp32s2.ulp.riscv.ld @@ -12,6 +12,7 @@ SECTIONS . = ORIGIN(ram); .text : { + *start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */ *(.text) *(.text*) } >ram diff --git a/components/ulp/ulp_riscv/start.S b/components/ulp/ulp_riscv/start.S index 1da9b755b0..949fd7fb48 100644 --- a/components/ulp/ulp_riscv/start.S +++ b/components/ulp/ulp_riscv/start.S @@ -1,4 +1,4 @@ - .section .text + .section .text.vectors .global irq_vector .global reset_vector @@ -11,6 +11,8 @@ reset_vector: irq_vector: ret + .section .text + __start: /* setup the stack pointer */ la sp, __stack_top