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Merge branch 'fix/update_doc_for_spi_slave_hd_protocol_v5.1' into 'release/v5.1'

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fix(all): update documentaion for spi slave hd protocols (v5.1)

See merge request espressif/esp-idf!24635
This commit is contained in:
morris 2023-07-10 19:39:45 +08:00
commit 24011f1e6c
4 changed files with 18 additions and 17 deletions
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1
docs/docs_not_updated/esp32c6.txt
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@ -2,4 +2,3 @@ api-guides/openthread
api-reference/network
api-reference/network/esp_openthread
api-reference/network/index
api-reference/protocols/esp_spi_slave_protocol

1
docs/docs_not_updated/esp32h2.txt
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@ -49,7 +49,6 @@ api-reference/system/inc/power_management_esp32
api-reference/system/inc/power_management_esp32s2_and_later
api-reference/protocols/esp_serial_slave_link
api-reference/protocols/esp_sdio_slave_protocol
api-reference/protocols/esp_spi_slave_protocol
api-reference/protocols/modbus
api-reference/protocols/index
about

3
docs/en/api-reference/peripherals/spi_slave_hd.rst
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@ -8,6 +8,9 @@ The half duplex (HD) mode is a special mode provided by ESP SPI Slave peripheral
There are several different types of transactions, determined by the *command* phase of the transaction. Each transaction may consist of the following phases: command, address, dummy, data. The command phase is mandatory, while the other fields may be determined by the command field. During the command, address, dummy phases, the bus is always controlled by the master, while the direction of the data phase depends on the command. The data phase can be either an in phase, for the master to write data to the slave; or an out phase, for the master to read data from the slave.
Protocol
^^^^^^^^
About the details of how master should communicate with the SPI Slave, see :doc:`/api-reference/protocols/esp_spi_slave_protocol`.
By these different transactions, the slave provide these services to the master:

30
docs/en/api-reference/protocols/esp_spi_slave_protocol.rst
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@ -11,21 +11,21 @@ ESP SPI Slave HD (Half Duplex) Mode Protocol
SPI Slave Capabilities of Espressif chips
-----------------------------------------
+--------------------+-------+----------+----------+
| | ESP32 | ESP32-S2 | ESP32-C3 |
+====================+=======+==========+==========+
| SPI Slave HD | N | Y (v2) | Y (v2) |
+--------------------+-------+----------+----------+
| Tohost intr | | N | N |
+--------------------+-------+----------+----------+
| Frhost intr | | 2 \* | 2 \* |
+--------------------+-------+----------+----------+
| TX DMA | | Y | Y |
+--------------------+-------+----------+----------+
| RX DMA | | Y | Y |
+--------------------+-------+----------+----------+
| Shared registers | | 72 | 64 |
+--------------------+-------+----------+----------+
+------------------+-------+----------+----------+----------+----------+----------+----------+
| | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C2 | ESP32-C6 | ESP32-H2 |
+------------------+-------+----------+----------+----------+----------+----------+----------+
| SPI Slave HD | N | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) | Y (v2) |
+------------------+-------+----------+----------+----------+----------+----------+----------+
| Tohost intr | | N | N | N | N | N | N |
+------------------+-------+----------+----------+----------+----------+----------+----------+
| Frhost intr | | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* | 2 \* |
+------------------+-------+----------+----------+----------+----------+----------+----------+
| TX DMA | | Y | Y | Y | Y | Y | Y |
+------------------+-------+----------+----------+----------+----------+----------+----------+
| RX DMA | | Y | Y | Y | Y | Y | Y |
+------------------+-------+----------+----------+----------+----------+----------+----------+
| Shared registers | | 72 | 64 | 64 | 64 | 64 | 64 |
+------------------+-------+----------+----------+----------+----------+----------+----------+
Introduction
------------