mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
Merge branch 'feature/s3_ulp_support_v4.4' into 'release/v4.4'
ulp: Added ULP support for esp32s3 (v4.4) See merge request espressif/esp-idf!18621
This commit is contained in:
Jiang Jiang Jian
commit
1bd2e3f9df
@ -320,6 +320,13 @@ menu "ESP32S3-Specific"
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Data is reserved at the beginning of RTC slow memory.
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config ESP32S3_ULP_COPROC_RISCV
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bool "Enable RISC-V as ULP coprocessor"
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depends on ESP32S3_ULP_COPROC_ENABLED
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default n
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help
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Set this to y to use the RISC-V coprocessor instead of the FSM-ULP.
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config ESP32S3_DEBUG_OCDAWARE
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bool "Make exception and panic handlers JTAG/OCD aware"
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default y
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -824,7 +824,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
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} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
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s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
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}
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#if defined(CONFIG_ESP32_ULP_COPROC_ENABLED) || defined(CONFIG_ESP32S2_ULP_COPROC_ENABLED)
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#if defined(CONFIG_ESP32_ULP_COPROC_ENABLED) || defined(CONFIG_ESP32S2_ULP_COPROC_ENABLED) || defined(CONFIG_ESP32S3_ULP_COPROC_ENABLED)
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else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
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s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
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}
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@ -854,8 +854,13 @@ esp_err_t esp_sleep_enable_ulp_wakeup(void)
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return ESP_ERR_INVALID_STATE;
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#endif // CONFIG_ESP32_ULP_COPROC_ENABLED
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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s_config.wakeup_triggers |= (RTC_ULP_TRIG_EN | RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN);
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#if CONFIG_ESP32S2_ULP_COPROC_RISCV || CONFIG_ESP32S3_ULP_COPROC_RISCV
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s_config.wakeup_triggers |= (RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN);
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return ESP_OK;
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#else // ULP_FSM
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s_config.wakeup_triggers |= (RTC_ULP_TRIG_EN);
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return ESP_OK;
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#endif //ESP32S2_ULP_COPROC_RISCV || ESP32S3_ULP_COPROC_RISCV
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#else
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return ESP_ERR_NOT_SUPPORTED;
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#endif
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@ -1194,7 +1199,7 @@ esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
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} else if (wakeup_cause & RTC_BT_TRIG_EN) {
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return ESP_SLEEP_WAKEUP_BT;
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2
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#if SOC_RISCV_COPROC_SUPPORTED
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} else if (wakeup_cause & RTC_COCPU_TRIG_EN) {
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return ESP_SLEEP_WAKEUP_ULP;
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} else if (wakeup_cause & RTC_COCPU_TRAP_TRIG_EN) {
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@ -121,6 +121,10 @@
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#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
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#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
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//Convenient way to replace the register ops when ulp riscv projects
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//consume this file
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#ifndef ULP_RISCV_REGISTER_OPS
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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@ -227,6 +231,7 @@
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#endif /* !__ASSEMBLER__ */
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//}}
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#endif /* !ULP_RISCV_REGISTER_OPS */
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//Periheral Clock {{
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#define APB_CLK_FREQ_ROM (40*1000000)
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@ -22,6 +22,7 @@
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#define SOC_CPU_CORES_NUM 2
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#define SOC_CACHE_SUPPORT_WRAP 1
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#define SOC_ULP_SUPPORTED 1
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#define SOC_RISCV_COPROC_SUPPORTED 1
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#define SOC_BT_SUPPORTED 1
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#define SOC_USB_OTG_SUPPORTED 1
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#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
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@ -4,7 +4,7 @@ if(NOT (IDF_TARGET STREQUAL "esp32c3") AND NOT (IDF_TARGET STREQUAL "esp32h2"))
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set(srcs "ulp.c"
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"ulp_macro.c")
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if(CONFIG_ESP32S2_ULP_COPROC_RISCV)
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if(CONFIG_ESP32S2_ULP_COPROC_RISCV OR CONFIG_ESP32S3_ULP_COPROC_RISCV)
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list(APPEND srcs "ulp_riscv.c")
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endif()
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@ -4,6 +4,6 @@ export ULP_AS := $(ULP_BINUTILS_PREFIX)as
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export ULP_LD := $(ULP_BINUTILS_PREFIX)ld
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export ULP_OBJCOPY := $(ULP_BINUTILS_PREFIX)objcopy
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export ULP_OBJDUMP := $(ULP_BINUTILS_PREFIX)objdump
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export ULP_LD_TEMPLATE := $(IDF_PATH)/components/ulp/ld/esp32.ulp.ld
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export ULP_LD_TEMPLATE := $(IDF_PATH)/components/ulp/ld/ulp_fsm.ld
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export ULP_NM := $(ULP_BINUTILS_PREFIX)nm
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export ULP_MAP_GEN := $(IDF_PATH)/components/ulp/esp32ulp_mapgen.py
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@ -1,141 +0,0 @@
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Programming ULP coprocessor using C macros (legacy)
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===================================================
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In addition to the existing binutils port for the ESP32 ULP coprocessor, it is possible to generate programs for the ULP by embedding assembly-like macros into an ESP32 application. Here is an example how this can be done::
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const ulp_insn_t program[] = {
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I_MOVI(R3, 16), // R3 <- 16
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I_LD(R0, R3, 0), // R0 <- RTC_SLOW_MEM[R3 + 0]
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I_LD(R1, R3, 1), // R1 <- RTC_SLOW_MEM[R3 + 1]
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I_ADDR(R2, R0, R1), // R2 <- R0 + R1
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I_ST(R2, R3, 2), // R2 -> RTC_SLOW_MEM[R2 + 2]
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I_HALT()
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};
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size_t load_addr = 0;
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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ulp_process_macros_and_load(load_addr, program, &size);
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ulp_run(load_addr);
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The ``program`` array is an array of ``ulp_insn_t``, i.e. ULP coprocessor instructions. Each ``I_XXX`` preprocessor define translates into a single 32-bit instruction. Arguments of these preprocessor defines can be register numbers (``R0 — R3``) and literal constants. See `ULP coprocessor instruction defines`_ section for descriptions of instructions and arguments they take.
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.. note::
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Because some of the instruction macros expand to inline function calls, defining such array in global scope will cause the compiler to produce an "initializer element is not constant" error. To fix this error, move the definition of instructions array into local scope.
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Load and store instructions use addresses expressed in 32-bit words. Address 0 corresponds to the first word of ``RTC_SLOW_MEM`` (which is address 0x50000000 as seen by the main CPUs).
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To generate branch instructions, special ``M_`` preprocessor defines are used. ``M_LABEL`` define can be used to define a branch target. Label identifier is a 16-bit integer. ``M_Bxxx`` defines can be used to generate branch instructions with target set to a particular label.
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Implementation note: these ``M_`` preprocessor defines will be translated into two ``ulp_insn_t`` values: one is a token value which contains label number, and the other is the actual instruction. ``ulp_process_macros_and_load`` function resolves the label number to the address, modifies the branch instruction to use the correct address, and removes the the extra ``ulp_insn_t`` token which contains the label numer.
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Here is an example of using labels and branches::
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const ulp_insn_t program[] = {
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I_MOVI(R0, 34), // R0 <- 34
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M_LABEL(1), // label_1
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I_MOVI(R1, 32), // R1 <- 32
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I_LD(R1, R1, 0), // R1 <- RTC_SLOW_MEM[R1]
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I_MOVI(R2, 33), // R2 <- 33
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I_LD(R2, R2, 0), // R2 <- RTC_SLOW_MEM[R2]
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I_SUBR(R3, R1, R2), // R3 <- R1 - R2
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I_ST(R3, R0, 0), // R3 -> RTC_SLOW_MEM[R0 + 0]
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I_ADDI(R0, R0, 1), // R0++
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M_BL(1, 64), // if (R0 < 64) goto label_1
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I_HALT(),
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};
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RTC_SLOW_MEM[32] = 42;
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RTC_SLOW_MEM[33] = 18;
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size_t load_addr = 0;
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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ulp_process_macros_and_load(load_addr, program, &size);
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ulp_run(load_addr);
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Application Example
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-------------------
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Demonstration of entering into deep sleep mode and waking up using several wake up sources: :example:`system/deep_sleep`.
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API Reference
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-------------
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Header File
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^^^^^^^^^^^
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.. list::
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:esp32: - :component_file:`ulp/include/esp32/ulp.h`
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:esp32s2: - :component_file:`ulp/include/esp32s2/ulp.h`
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:esp32s3: - :component_file:`ulp/include/esp32s3/ulp.h`
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Functions
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^^^^^^^^^
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.. doxygenfunction:: ulp_process_macros_and_load
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.. doxygenfunction:: ulp_run
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Error codes
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^^^^^^^^^^^
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.. doxygendefine:: ESP_ERR_ULP_BASE
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.. doxygendefine:: ESP_ERR_ULP_SIZE_TOO_BIG
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.. doxygendefine:: ESP_ERR_ULP_INVALID_LOAD_ADDR
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.. doxygendefine:: ESP_ERR_ULP_DUPLICATE_LABEL
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.. doxygendefine:: ESP_ERR_ULP_UNDEFINED_LABEL
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.. doxygendefine:: ESP_ERR_ULP_BRANCH_OUT_OF_RANGE
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ULP coprocessor registers
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^^^^^^^^^^^^^^^^^^^^^^^^^
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ULP co-processor has 4 16-bit general purpose registers. All registers have same functionality, with one exception. R0 register is used by some of the compare-and-branch instructions as a source register.
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These definitions can be used for all instructions which require a register.
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.. doxygengroup:: ulp_registers
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:content-only:
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ULP coprocessor instruction defines
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. doxygendefine:: I_DELAY
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.. doxygendefine:: I_HALT
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.. doxygendefine:: I_END
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.. doxygendefine:: I_ST
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.. doxygendefine:: I_LD
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.. doxygendefine:: I_WR_REG
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.. doxygendefine:: I_RD_REG
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.. doxygendefine:: I_BL
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.. doxygendefine:: I_BGE
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.. doxygendefine:: I_BXR
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.. doxygendefine:: I_BXI
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.. doxygendefine:: I_BXZR
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.. doxygendefine:: I_BXZI
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.. doxygendefine:: I_BXFR
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.. doxygendefine:: I_BXFI
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.. doxygendefine:: I_ADDR
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.. doxygendefine:: I_SUBR
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.. doxygendefine:: I_ANDR
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.. doxygendefine:: I_ORR
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.. doxygendefine:: I_MOVR
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.. doxygendefine:: I_LSHR
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.. doxygendefine:: I_RSHR
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.. doxygendefine:: I_ADDI
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.. doxygendefine:: I_SUBI
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.. doxygendefine:: I_ANDI
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.. doxygendefine:: I_ORI
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.. doxygendefine:: I_MOVI
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.. doxygendefine:: I_LSHI
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.. doxygendefine:: I_RSHI
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.. doxygendefine:: M_LABEL
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.. doxygendefine:: M_BL
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.. doxygendefine:: M_BGE
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.. doxygendefine:: M_BX
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.. doxygendefine:: M_BXZ
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.. doxygendefine:: M_BXF
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Defines
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^^^^^^^
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.. doxygendefine:: RTC_SLOW_MEM
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@ -17,10 +17,10 @@ string(REGEX MATCH "\\(GNU Binutils\\) (${version_pattern})" as_version ${as_out
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set(as_version ${CMAKE_MATCH_1})
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message(STATUS "Building ULP app ${ULP_APP_NAME}")
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message(STATUS "Building ULP app ${ULP_APP_NAME} for ${IDF_TARGET}")
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if(ULP_COCPU_IS_RISCV)
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set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/esp32s2.ulp.riscv.ld)
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set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/${IDF_TARGET}.ulp.riscv.ld)
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else()
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message(STATUS "ULP assembler version: ${as_version}")
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@ -38,7 +38,7 @@ else()
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the toolchain, or proceed at your own risk.")
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endif()
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set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/esp32.ulp.ld)
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set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/ulp_fsm.ld)
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endif()
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16
components/ulp/cmake/toolchain-esp32s3-ulp.cmake
Normal file
16
components/ulp/cmake/toolchain-esp32s3-ulp.cmake
Normal file
@ -0,0 +1,16 @@
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# CMake toolchain file for ULP
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set(CMAKE_SYSTEM_NAME Generic)
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# Compiler is only used for preprocessing
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# The S2 and S3 ULP are the same, so we use the same toolchain
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set(CMAKE_C_COMPILER "xtensa-esp32s2-elf-gcc")
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set(CMAKE_ASM_COMPILER "esp32s2ulp-elf-as")
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set(CMAKE_LINKER "esp32s2ulp-elf-ld")
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set(CMAKE_ASM${ASM_DIALECT}_COMPILE_OBJECT "${CMAKE_ASM${ASM_DIALECT}_COMPILER} \
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<DEFINES> <INCLUDES> -o <OBJECT> -c <SOURCE>")
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set(CMAKE_EXE_LINKER_FLAGS "-A elf32-esp32s2ulp -nostdlib" CACHE STRING "ULP Linker Base Flags")
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set(CMAKE_ASM_LINK_EXECUTABLE "${CMAKE_LINKER} <FLAGS> <CMAKE_ASM_LINK_FLAGS> \
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<LINK_FLAGS> <OBJECTS> -o <TARGET> <LINK_LIBRARIES>")
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@ -289,8 +289,6 @@ union ulp_insn {
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|
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};
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typedef union ulp_insn ulp_insn_t;
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_Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should be 4 bytes");
|
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/**
|
||||
|
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@ -1,16 +1,8 @@
|
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// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
@ -24,9 +16,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ULP_FSM_PREPARE_SLEEP_CYCLES 2 /*!< Cycles spent by FSM preparing ULP for sleep */
|
||||
#define ULP_FSM_WAKEUP_SLEEP_CYCLES 2 /*!< Cycles spent by FSM waking up ULP from sleep */
|
||||
|
||||
/**
|
||||
* @defgroup ulp_registers ULP coprocessor registers
|
||||
* @{
|
||||
@ -63,7 +52,9 @@ extern "C" {
|
||||
#define OPCODE_ADC 5 /*!< Instruction: SAR ADC measurement (not implemented yet) */
|
||||
|
||||
#define OPCODE_ST 6 /*!< Instruction: store indirect to RTC memory */
|
||||
#define SUB_OPCODE_ST 4 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */
|
||||
#define SUB_OPCODE_ST_AUTO 1 /*!< Automatic Storage Mode - Access continuous addresses. Use SUB_OPCODE_ST_OFFSET to configure the initial address before using this instruction. */
|
||||
#define SUB_OPCODE_ST_OFFSET 3 /*!< Automatic Storage Mode - Configure the initial address. */
|
||||
#define SUB_OPCODE_ST 4 /*!< Manual Storage Mode. Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */
|
||||
|
||||
#define OPCODE_ALU 7 /*!< Arithmetic instructions */
|
||||
#define SUB_OPCODE_ALU_REG 0 /*!< Arithmetic instruction, both source values are in register */
|
||||
@ -76,15 +67,23 @@ extern "C" {
|
||||
#define ALU_SEL_MOV 4 /*!< Copy value (immediate to destination register or source register to destination register */
|
||||
#define ALU_SEL_LSH 5 /*!< Shift left by given number of bits */
|
||||
#define ALU_SEL_RSH 6 /*!< Shift right by given number of bits */
|
||||
#define ALU_SEL_STAGE_INC 0 /*!< Increment stage count register */
|
||||
#define ALU_SEL_STAGE_DEC 1 /*!< Decrement stage count register */
|
||||
#define ALU_SEL_STAGE_RST 2 /*!< Reset stage count register */
|
||||
|
||||
#define OPCODE_BRANCH 8 /*!< Branch instructions */
|
||||
#define SUB_OPCODE_BX 0 /*!< Branch to absolute PC (immediate or in register) */
|
||||
#define SUB_OPCODE_B 0 /*!< Branch to a relative offset */
|
||||
#define SUB_OPCODE_BX 1 /*!< Branch to absolute PC (immediate or in register) */
|
||||
#define SUB_OPCODE_BS 2 /*!< Branch to a relative offset by comparing the stage_cnt register */
|
||||
#define BX_JUMP_TYPE_DIRECT 0 /*!< Unconditional jump */
|
||||
#define BX_JUMP_TYPE_ZERO 1 /*!< Branch if last ALU result is zero */
|
||||
#define BX_JUMP_TYPE_OVF 2 /*!< Branch if last ALU operation caused and overflow */
|
||||
#define SUB_OPCODE_B 1 /*!< Branch to a relative offset */
|
||||
#define B_CMP_L 0 /*!< Branch if R0 is less than an immediate */
|
||||
#define B_CMP_GE 1 /*!< Branch if R0 is greater than or equal to an immediate */
|
||||
#define B_CMP_G 1 /*!< Branch if R0 is greater than an immediate */
|
||||
#define B_CMP_E 2 /*!< Branch if R0 is equal to an immediate */
|
||||
#define BS_CMP_L 0 /*!< Branch if stage_cnt is less than an immediate */
|
||||
#define BS_CMP_GE 1 /*!< Branch if stage_cnt is greater than or equal to an immediate */
|
||||
#define BS_CMP_LE 2 /*!< Branch if stage_cnt is less than or equal to an immediate */
|
||||
|
||||
#define OPCODE_END 9 /*!< Stop executing the program */
|
||||
#define SUB_OPCODE_END 0 /*!< Stop executing the program and optionally wake up the chip */
|
||||
@ -99,6 +98,7 @@ extern "C" {
|
||||
#define OPCODE_MACRO 15 /*!< Not a real opcode. Used to identify labels and branches in the program */
|
||||
#define SUB_OPCODE_MACRO_LABEL 0 /*!< Label macro */
|
||||
#define SUB_OPCODE_MACRO_BRANCH 1 /*!< Branch macro */
|
||||
#define SUB_OPCODE_MACRO_LABELPC 2 /*!< Label pointer macro */
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
@ -126,7 +126,10 @@ union ulp_insn {
|
||||
struct {
|
||||
uint32_t dreg : 2; /*!< Register which contains data to store */
|
||||
uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */
|
||||
uint32_t unused1 : 6; /*!< Unused */
|
||||
uint32_t label: 2; /*!< Data label, 2-bit user defined unsigned value */
|
||||
uint32_t upper: 1; /*!< 0: write the low half-word; 1: write the high half-word */
|
||||
uint32_t wr_way: 2; /*!< 0: write the full-word; 1: with the label; 3: without the label */
|
||||
uint32_t unused1 : 1; /*!< Unused */
|
||||
uint32_t offset : 11; /*!< Offset to add to sreg */
|
||||
uint32_t unused2 : 4; /*!< Unused */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ST) */
|
||||
@ -138,7 +141,8 @@ union ulp_insn {
|
||||
uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */
|
||||
uint32_t unused1 : 6; /*!< Unused */
|
||||
uint32_t offset : 11; /*!< Offset to add to sreg */
|
||||
uint32_t unused2 : 7; /*!< Unused */
|
||||
uint32_t unused2 : 6; /*!< Unused */
|
||||
uint32_t rd_upper: 1; /*!< 0: read the high half-word; 1: read the low half-word*/
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_LD) */
|
||||
} ld; /*!< Format of LD instruction */
|
||||
|
||||
@ -150,19 +154,20 @@ union ulp_insn {
|
||||
struct {
|
||||
uint32_t dreg : 2; /*!< Register which contains target PC, expressed in words (used if .reg == 1) */
|
||||
uint32_t addr : 11; /*!< Target PC, expressed in words (used if .reg == 0) */
|
||||
uint32_t unused : 8; /*!< Unused */
|
||||
uint32_t unused1 : 8; /*!< Unused */
|
||||
uint32_t reg : 1; /*!< Target PC in register (1) or immediate (0) */
|
||||
uint32_t type : 3; /*!< Jump condition (BX_JUMP_TYPE_xxx) */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */
|
||||
uint32_t unused2 : 1; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_BX) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
|
||||
} bx; /*!< Format of BRANCH instruction (absolute address) */
|
||||
|
||||
struct {
|
||||
uint32_t imm : 16; /*!< Immediate value to compare against */
|
||||
uint32_t cmp : 1; /*!< Comparison to perform: B_CMP_L or B_CMP_GE */
|
||||
uint32_t cmp : 2; /*!< Comparison to perform: B_CMP_L or B_CMP_GE */
|
||||
uint32_t offset : 7; /*!< Absolute value of target PC offset w.r.t. current PC, expressed in words */
|
||||
uint32_t sign : 1; /*!< Sign of target PC offset: 0: positive, 1: negative */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_B) */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_B) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
|
||||
} b; /*!< Format of BRANCH instruction (relative address) */
|
||||
|
||||
@ -170,9 +175,10 @@ union ulp_insn {
|
||||
uint32_t dreg : 2; /*!< Destination register */
|
||||
uint32_t sreg : 2; /*!< Register with operand A */
|
||||
uint32_t treg : 2; /*!< Register with operand B */
|
||||
uint32_t unused : 15; /*!< Unused */
|
||||
uint32_t unused1 : 15; /*!< Unused */
|
||||
uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */
|
||||
uint32_t unused2 : 1; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */
|
||||
} alu_reg; /*!< Format of ALU instruction (both sources are registers) */
|
||||
|
||||
@ -180,12 +186,23 @@ union ulp_insn {
|
||||
uint32_t dreg : 2; /*!< Destination register */
|
||||
uint32_t sreg : 2; /*!< Register with operand A */
|
||||
uint32_t imm : 16; /*!< Immediate value of operand B */
|
||||
uint32_t unused : 1; /*!< Unused */
|
||||
uint32_t unused1: 1; /*!< Unused */
|
||||
uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */
|
||||
uint32_t unused2 : 1; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */
|
||||
} alu_imm; /*!< Format of ALU instruction (one source is an immediate) */
|
||||
|
||||
struct {
|
||||
uint32_t unused1: 4; /*!< Unused */
|
||||
uint32_t imm : 8; /*!< Immediate value */
|
||||
uint32_t unused2: 9; /*!< Unused */
|
||||
uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
|
||||
uint32_t unused3 : 1; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_CNT) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */
|
||||
} alu_cnt; /*!< Format of ALU instruction with stage count register and an immediate */
|
||||
|
||||
struct {
|
||||
uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */
|
||||
uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */
|
||||
@ -234,18 +251,11 @@ union ulp_insn {
|
||||
|
||||
struct {
|
||||
uint32_t wakeup : 1; /*!< Set to 1 to wake up chip */
|
||||
uint32_t unused : 24; /*!< Unused */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */
|
||||
uint32_t unused : 25; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */
|
||||
} end; /*!< Format of END instruction with wakeup */
|
||||
|
||||
struct {
|
||||
uint32_t cycle_sel : 4; /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */
|
||||
uint32_t unused : 21; /*!< Unused */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_SLEEP) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */
|
||||
} sleep; /*!< Format of END instruction with sleep */
|
||||
|
||||
struct {
|
||||
uint32_t label : 16; /*!< Label number */
|
||||
uint32_t unused : 8; /*!< Unused */
|
||||
@ -255,8 +265,6 @@ union ulp_insn {
|
||||
|
||||
};
|
||||
|
||||
typedef union ulp_insn ulp_insn_t;
|
||||
|
||||
_Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should be 4 bytes");
|
||||
|
||||
/**
|
||||
@ -286,7 +294,8 @@ _Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should
|
||||
* @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals.
|
||||
* @return periph_sel value for the peripheral to which this register belongs.
|
||||
*/
|
||||
static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
{
|
||||
uint32_t ret = 3;
|
||||
if (reg < DR_REG_RTCCNTL_BASE) {
|
||||
assert(0 && "invalid register base");
|
||||
@ -294,9 +303,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
ret = RD_REG_PERIPH_RTC_CNTL;
|
||||
} else if (reg < DR_REG_SENS_BASE) {
|
||||
ret = RD_REG_PERIPH_RTC_IO;
|
||||
} else if (reg < DR_REG_RTC_I2C_BASE){
|
||||
} else if (reg < DR_REG_RTC_I2C_BASE) {
|
||||
ret = RD_REG_PERIPH_SENS;
|
||||
} else if (reg < DR_REG_IO_MUX_BASE){
|
||||
} else if (reg < DR_REG_IO_MUX_BASE) {
|
||||
ret = RD_REG_PERIPH_RTC_I2C;
|
||||
} else {
|
||||
assert(0 && "invalid register base");
|
||||
@ -354,7 +363,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
*
|
||||
* To disable the timer which start ULP program, use I_END()
|
||||
* instruction. I_END instruction clears the
|
||||
* RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG
|
||||
* RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_ULP_CP_TIMER_REG
|
||||
* register, which controls the ULP timer.
|
||||
*/
|
||||
#define I_WAKE() { .end = { \
|
||||
@ -374,27 +383,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
* the currently running program, use I_HALT().
|
||||
*/
|
||||
#define I_END() \
|
||||
I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
|
||||
/**
|
||||
* Select the time interval used to run ULP program.
|
||||
*
|
||||
* This instructions selects which of the SENS_SLEEP_CYCLES_Sx
|
||||
* registers' value is used by the ULP program timer.
|
||||
* When the ULP program stops at I_HALT instruction, ULP program
|
||||
* timer start counting. When the counter reaches the value of
|
||||
* the selected SENS_SLEEP_CYCLES_Sx register, ULP program
|
||||
* start running again from the start address (passed to the ulp_run
|
||||
* function).
|
||||
* There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5.
|
||||
*
|
||||
* By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP
|
||||
* program timer.
|
||||
*/
|
||||
#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \
|
||||
.cycle_sel = timer_idx, \
|
||||
.unused = 0, \
|
||||
.sub_opcode = SUB_OPCODE_SLEEP, \
|
||||
.opcode = OPCODE_END } }
|
||||
I_WR_REG_BIT(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
|
||||
|
||||
/**
|
||||
* Perform temperature sensor measurement and store it into reg_dest.
|
||||
@ -424,45 +413,247 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.opcode = OPCODE_ADC } }
|
||||
|
||||
/**
|
||||
* Store value from register reg_val into RTC memory.
|
||||
* Store lower half-word, upper half-word or full-word data from register reg_val into RTC memory address.
|
||||
*
|
||||
* The value is written to an offset calculated by adding value of
|
||||
* This instruction can be used to write data to discontinuous addresses in the RTC_SLOW_MEM.
|
||||
* The value is written to an offset calculated by adding the value of
|
||||
* reg_addr register and offset_ field (this offset is expressed in 32-bit words).
|
||||
* 32 bits written to RTC memory are built as follows:
|
||||
* - bits [31:21] hold the PC of current instruction, expressed in 32-bit words
|
||||
* - bits [20:18] = 3'b0
|
||||
* - bits [17:16] reg_addr (0..3)
|
||||
* - bits [15:0] are assigned the contents of reg_val
|
||||
* The storage method is dictated by the wr_way and upper field settings as summarized in the following table:
|
||||
*
|
||||
* RTC_SLOW_MEM[addr + offset_] = { insn_PC[10:0], 3'b0, reg_addr, reg_val[15:0] }
|
||||
* @verbatim
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | wr_way | upper | data | operation |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Write full-word, including |
|
||||
* | 0 | X | RTC_SLOW_MEM[addr + offset_]{31:0} = {insn_PC[10:0], 3’b0, label_[1:0], reg_val[15:0]} | the PC and the data |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data with label |
|
||||
* | 1 | 0 | RTC_SLOW_MEM[addr + offset_]{15:0} = {label_[1:0], reg_val[13:0]} | in the low half-word |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data with label |
|
||||
* | 1 | 1 | RTC_SLOW_MEM[addr + offset_]{31:16} = {label_[1:0], reg_val[13:0]} | in the high half-word |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data without |
|
||||
* | 3 | 0 | RTC_SLOW_MEM[addr + offset_]{15:0} = reg_val[15:0] | label in the low half-word |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data without |
|
||||
* | 3 | 1 | RTC_SLOW_MEM[addr + offset_]{31:16} = reg_val[15:0] | label in the high half-word|
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* @endverbatim
|
||||
*
|
||||
* SUB_OPCODE_ST = manual_en:1, offset_set:0, wr_auto:0
|
||||
*/
|
||||
#define I_ST(reg_val, reg_addr, offset_) { .st = { \
|
||||
#define I_ST_MANUAL(reg_val, reg_addr, offset_, label_, upper_, wr_way_) { .st = { \
|
||||
.dreg = reg_val, \
|
||||
.sreg = reg_addr, \
|
||||
.label = label_, \
|
||||
.upper = upper_, \
|
||||
.wr_way = wr_way_, \
|
||||
.unused1 = 0, \
|
||||
.offset = offset_, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ST, \
|
||||
.opcode = OPCODE_ST } }
|
||||
|
||||
/**
|
||||
* Store value from register reg_val into RTC memory.
|
||||
*
|
||||
* I_ST() instruction provides backward compatibility for code written for esp32 to be run on esp32s2.
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = 0, upper = 0 and wr_way = 3.
|
||||
*/
|
||||
#define I_ST(reg_val, reg_addr, offset_) I_ST_MANUAL(reg_val, reg_addr, offset_, 0, 0, 3)
|
||||
|
||||
/**
|
||||
* Load value from RTC memory into reg_dest register.
|
||||
* Store value from register reg_val to lower 16 bits of the RTC memory address.
|
||||
*
|
||||
* Loads 16 LSBs from RTC memory word given by the sum of value in reg_addr and
|
||||
* value of offset_.
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = 0, upper = 0 and wr_way = 3.
|
||||
*/
|
||||
#define I_LD(reg_dest, reg_addr, offset_) { .ld = { \
|
||||
#define I_STL(reg_val, reg_addr, offset_) I_ST_MANUAL(reg_val, reg_addr, offset_, 0, 0, 3)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val to upper 16 bits of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = 0, upper = 1 and wr_way = 3.
|
||||
*/
|
||||
#define I_STH(reg_val, reg_addr, offset_) I_ST_MANUAL(reg_val, reg_addr, offset_, 0, 1, 3)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val to full 32 bit word of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with wr_way = 0.
|
||||
*/
|
||||
#define I_ST32(reg_val, reg_addr, offset_, label_) I_ST_MANUAL(reg_val, reg_addr, offset_, label_, 0, 0)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val with label to lower 16 bits of RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = label_, upper = 0 and wr_way = 1.
|
||||
*/
|
||||
#define I_STL_LABEL(reg_val, reg_addr, offset_, label_) I_ST_MANUAL(reg_val, reg_addr, offset_, label_, 0, 1)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val with label to upper 16 bits of RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = label_, upper = 1 and wr_way = 1.
|
||||
*/
|
||||
#define I_STH_LABEL(reg_val, reg_addr, offset_, label_) I_ST_MANUAL(reg_val, reg_addr, offset_, label_, 1, 1)
|
||||
|
||||
/**
|
||||
* Store lower half-word, upper half-word or full-word data from register reg_val into RTC memory address with auto-increment of the offset value.
|
||||
*
|
||||
* This instruction can be used to write data to continuous addresses in the RTC_SLOW_MEM.
|
||||
* The initial address must be set using the SUB_OPCODE_ST_OFFSET instruction before the auto store instruction is called.
|
||||
* The data written to the RTC memory address could be written to the full 32 bit word or to the lower half-word or the
|
||||
* upper half-word. The storage method is dictated by the wr_way field and the number of times the SUB_OPCODE_ST_AUTO instruction is called.
|
||||
* write_cnt indicates the later. The following table summarizes the storage method:
|
||||
*
|
||||
* @verbatim
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | wr_way | write_cnt | data | operation |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Write full-word, including |
|
||||
* | 0 | X | RTC_SLOW_MEM[addr + offset_]{31:0} = {insn_PC[10:0], 3’b0, label_[1:0], reg_val[15:0]} | the PC and the data |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data with label |
|
||||
* | 1 | odd | RTC_SLOW_MEM[addr + offset_]{15:0} = {label_[1:0], reg_val[13:0]} | in the low half-word |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data with label |
|
||||
* | 1 | even | RTC_SLOW_MEM[addr + offset_]{31:16} = {label_[1:0], reg_val[13:0]} | in the high half-word |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data without |
|
||||
* | 3 | odd | RTC_SLOW_MEM[addr + offset_]{15:0} = reg_val[15:0] | label in the low half-word |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data without |
|
||||
* | 3 | even | RTC_SLOW_MEM[addr + offset_]{31:16} = reg_val[15:0] | label in the high half-word|
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* @endverbatim
|
||||
*
|
||||
* The initial address offset is incremented after each store operation as follows:
|
||||
* - When a full-word is written, the offset is automatically incremented by 1 after each SUB_OPCODE_ST_AUTO operation.
|
||||
* - When a half-word is written (lower half-word first), the offset is automatically incremented by 1 after two
|
||||
* SUB_OPCODE_ST_AUTO operations.
|
||||
*
|
||||
* SUB_OPCODE_ST_AUTO = manual_en:0, offset_set:0, wr_auto:1
|
||||
*/
|
||||
#define I_ST_AUTO(reg_val, reg_addr, label_, wr_way_) { .st = { \
|
||||
.dreg = reg_addr, \
|
||||
.sreg = reg_val, \
|
||||
.label = label_, \
|
||||
.upper = 0, \
|
||||
.wr_way = wr_way_, \
|
||||
.unused1 = 0, \
|
||||
.offset = 0, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ST_AUTO, \
|
||||
.opcode = OPCODE_ST } }
|
||||
|
||||
/**
|
||||
* Set the initial address offset for auto-store operation
|
||||
*
|
||||
* This instruction sets the initial address of the RTC_SLOW_MEM to be used by the auto-store operation.
|
||||
* The offset is incremented automatically.
|
||||
* Refer I_ST_AUTO() for detailed explaination.
|
||||
*
|
||||
* SUB_OPCODE_ST_OFFSET = manual_en:0, offset_set:1, wr_auto:1
|
||||
*/
|
||||
#define I_STO(offset_) { .st = { \
|
||||
.dreg = 0, \
|
||||
.sreg = 0, \
|
||||
.label = 0, \
|
||||
.upper = 0, \
|
||||
.wr_way = 0, \
|
||||
.unused1 = 0, \
|
||||
.offset = offset_, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ST_OFFSET, \
|
||||
.opcode = OPCODE_ST } }
|
||||
|
||||
/**
|
||||
* Store value from register reg_val to 32 bit word of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_AUTO() instruction with label = 0 and wr_way = 3.
|
||||
* The data in reg_val will be either written to the lower half-word or the upper half-word of the RTC memory address
|
||||
* depending on the count of the number of times the I_STI() instruction is called.
|
||||
* The initial offset is automatically incremented with I_STI() is called twice.
|
||||
* Refer I_ST_AUTO() for detailed explaination.
|
||||
*/
|
||||
#define I_STI(reg_val, reg_addr) I_ST_AUTO(reg_val, reg_addr, 0, 3)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val with label to 32 bit word of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_AUTO() instruction with label = label_ and wr_way = 1.
|
||||
* The data in reg_val will be either written to the lower half-word or the upper half-word of the RTC memory address
|
||||
* depending on the count of the number of times the I_STI_LABEL() instruction is called.
|
||||
* The initial offset is automatically incremented with I_STI_LABEL() is called twice.
|
||||
* Refer I_ST_AUTO() for detailed explaination.
|
||||
*/
|
||||
#define I_STI_LABEL(reg_val, reg_addr, label_) I_ST_AUTO(reg_val, reg_addr, label_, 1)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val to full 32 bit word of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_AUTO() instruction with label = label_ and wr_way = 0.
|
||||
* The data in reg_val will be written to the RTC memory address along with the label and the PC.
|
||||
* The initial offset is automatically incremented each time the I_STI32() instruction is called.
|
||||
* Refer I_ST_AUTO() for detailed explaination.
|
||||
*/
|
||||
#define I_STI32(reg_val, reg_addr, label_) I_ST_AUTO(reg_val, reg_addr, label_, 0)
|
||||
|
||||
/**
|
||||
* Load lower half-word, upper half-word or full-word data from RTC memory address into the register reg_dest.
|
||||
*
|
||||
* This instruction reads the lower half-word or upper half-word of the RTC memory address depending on the value
|
||||
* of rd_upper_. The following table summarizes the loading method:
|
||||
*
|
||||
* @verbatim
|
||||
* |----------|------------------------------------------------------|-------------------------|
|
||||
* | rd_upper | data | operation |
|
||||
* |----------|------------------------------------------------------|-------------------------|
|
||||
* | | | Read lower half-word of |
|
||||
* | 0 | reg_dest{15:0} = RTC_SLOW_MEM[addr + offset_]{31:16} | the memory |
|
||||
* |----------|------------------------------------------------------|-------------------------|
|
||||
* | | | Read upper half-word of |
|
||||
* | 1 | reg_dest{15:0} = RTC_SLOW_MEM[addr + offset_]{15:0} | the memory |
|
||||
* |----------|------------------------------------------------------|-------------------------|
|
||||
* @endverbatim
|
||||
*
|
||||
*/
|
||||
#define I_LD_MANUAL(reg_dest, reg_addr, offset_, rd_upper_) { .ld = { \
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_addr, \
|
||||
.unused1 = 0, \
|
||||
.offset = offset_, \
|
||||
.unused2 = 0, \
|
||||
.rd_upper = rd_upper_, \
|
||||
.opcode = OPCODE_LD } }
|
||||
|
||||
/**
|
||||
* Load lower 16 bits value from RTC memory into reg_dest register.
|
||||
*
|
||||
* Loads 16 LSBs (rd_upper = 1) from RTC memory word given by the sum of value in reg_addr and
|
||||
* value of offset_.
|
||||
* I_LD() instruction provides backward compatibility for code written for esp32 to be run on esp32s2.
|
||||
*/
|
||||
#define I_LD(reg_dest, reg_addr, offset_) I_LD_MANUAL(reg_dest, reg_addr, offset_, 0)
|
||||
|
||||
/**
|
||||
* Branch relative if R0 less than immediate value.
|
||||
* Load lower 16 bits value from RTC memory into reg_dest register.
|
||||
*
|
||||
* I_LDL() instruction and I_LD() instruction can be used interchangably.
|
||||
*/
|
||||
#define I_LDL(reg_dest, reg_addr, offset_) I_LD(reg_dest, reg_addr, offset_)
|
||||
|
||||
/**
|
||||
* Load upper 16 bits value from RTC memory into reg_dest register.
|
||||
*
|
||||
* Loads 16 MSBs (rd_upper = 0) from RTC memory word given by the sum of value in reg_addr and
|
||||
* value of offset_.
|
||||
*/
|
||||
#define I_LDH(reg_dest, reg_addr, offset_) I_LD_MANUAL(reg_dest, reg_addr, offset_, 1)
|
||||
|
||||
/**
|
||||
* Branch relative if R0 register less than the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
@ -476,14 +667,28 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if R0 greater or equal than immediate value.
|
||||
* Branch relative if R0 register greater than the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BGE(pc_offset, imm_value) { .b = { \
|
||||
#define I_BG(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = B_CMP_GE, \
|
||||
.cmp = B_CMP_G, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_B, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if R0 register is equal to the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BE(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = B_CMP_E, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_B, \
|
||||
@ -498,9 +703,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
#define I_BXR(reg_pc) { .bx = { \
|
||||
.dreg = reg_pc, \
|
||||
.addr = 0, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 1, \
|
||||
.type = BX_JUMP_TYPE_DIRECT, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -512,9 +718,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
#define I_BXI(imm_pc) { .bx = { \
|
||||
.dreg = 0, \
|
||||
.addr = imm_pc, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 0, \
|
||||
.type = BX_JUMP_TYPE_DIRECT, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -527,9 +734,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
#define I_BXZR(reg_pc) { .bx = { \
|
||||
.dreg = reg_pc, \
|
||||
.addr = 0, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 1, \
|
||||
.type = BX_JUMP_TYPE_ZERO, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -541,9 +749,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
#define I_BXZI(imm_pc) { .bx = { \
|
||||
.dreg = 0, \
|
||||
.addr = imm_pc, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 0, \
|
||||
.type = BX_JUMP_TYPE_ZERO, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -556,9 +765,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
#define I_BXFR(reg_pc) { .bx = { \
|
||||
.dreg = reg_pc, \
|
||||
.addr = 0, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 1, \
|
||||
.type = BX_JUMP_TYPE_OVF, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -570,12 +780,54 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
#define I_BXFI(imm_pc) { .bx = { \
|
||||
.dreg = 0, \
|
||||
.addr = imm_pc, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 0, \
|
||||
.type = BX_JUMP_TYPE_OVF, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if stage_cnt is less than or equal to the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BSLE(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = BS_CMP_LE, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_BS, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if stage_cnt register is greater than or equal to the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BSGE(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = BS_CMP_GE, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_BS, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if stage_cnt register is less than the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BSL(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = BS_CMP_L, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_BS, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Addition: dest = src1 + src2
|
||||
@ -584,8 +836,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src1, \
|
||||
.treg = reg_src2, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_ADD, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -596,8 +849,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src1, \
|
||||
.treg = reg_src2, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_SUB, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -608,8 +862,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src1, \
|
||||
.treg = reg_src2, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_AND, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -620,8 +875,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src1, \
|
||||
.treg = reg_src2, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_OR, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -632,8 +888,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.treg = 0, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_MOV, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -644,8 +901,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.treg = reg_shift, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_LSH, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -657,8 +915,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.treg = reg_shift, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_RSH, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -669,8 +928,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_ADD, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -682,8 +942,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_SUB, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -694,8 +955,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_AND, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -706,8 +968,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_OR, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -718,8 +981,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = 0, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_MOV, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -730,8 +994,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_LSH, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -743,11 +1008,48 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_RSH, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
/**
|
||||
* Increment stage_cnt register by an immediate: stage_cnt = stage_cnt + imm
|
||||
*/
|
||||
#define I_STAGE_INC(reg_dest, reg_src, imm_) { .alu_cnt = { \
|
||||
.unused1 = 0, \
|
||||
.imm = imm_, \
|
||||
.unused2 = 0, \
|
||||
.sel = ALU_SEL_STAGE_INC, \
|
||||
.unused3 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_CNT, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
/**
|
||||
* Decrement stage_cnt register by an immediate: stage_cnt = stage_cnt - imm
|
||||
*/
|
||||
#define I_STAGE_DEC(reg_dest, reg_src, imm_) { .alu_cnt = { \
|
||||
.unused1 = 0, \
|
||||
.imm = imm_, \
|
||||
.unused2 = 0, \
|
||||
.sel = ALU_SEL_STAGE_DEC, \
|
||||
.unused3 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_CNT, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
/**
|
||||
* Reset stage_cnt register by an immediate: stage_cnt = 0
|
||||
*/
|
||||
#define I_STAGE_RST(reg_dest, reg_src, imm_) { .alu_cnt = { \
|
||||
.unused1 = 0, \
|
||||
.imm = imm_, \
|
||||
.unused2 = 0, \
|
||||
.sel = ALU_SEL_STAGE_RST, \
|
||||
.unused3 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_CNT, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
/**
|
||||
* Define a label with number label_num.
|
||||
*
|
||||
@ -784,16 +1086,28 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
I_BL(0, imm_value)
|
||||
|
||||
/**
|
||||
* Macro: branch to label label_num if R0 is greater or equal than immediate value
|
||||
* Macro: branch to label label_num if R0 is greater than immediate value
|
||||
*
|
||||
* This macro generates two ulp_insn_t values separated by a comma, and should
|
||||
* be used when defining contents of ulp_insn_t arrays. First value is not a
|
||||
* real instruction; it is a token which is removed by ulp_process_macros_and_load
|
||||
* function.
|
||||
*/
|
||||
#define M_BGE(label_num, imm_value) \
|
||||
#define M_BG(label_num, imm_value) \
|
||||
M_BRANCH(label_num), \
|
||||
I_BGE(0, imm_value)
|
||||
I_BG(0, imm_value)
|
||||
|
||||
/**
|
||||
* Macro: branch to label label_num if R0 equal to the immediate value
|
||||
*
|
||||
* This macro generates two ulp_insn_t values separated by a comma, and should
|
||||
* be used when defining contents of ulp_insn_t arrays. First value is not a
|
||||
* real instruction; it is a token which is removed by ulp_process_macros_and_load
|
||||
* function.
|
||||
*/
|
||||
#define M_BE(label_num, imm_value) \
|
||||
M_BRANCH(label_num), \
|
||||
I_BE(0, imm_value)
|
||||
|
||||
/**
|
||||
* Macro: unconditional branch to label
|
||||
@ -832,7 +1146,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
|
||||
I_BXFI(0)
|
||||
|
||||
|
||||
|
||||
#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
@ -24,9 +16,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ULP_FSM_PREPARE_SLEEP_CYCLES 2 /*!< Cycles spent by FSM preparing ULP for sleep */
|
||||
#define ULP_FSM_WAKEUP_SLEEP_CYCLES 2 /*!< Cycles spent by FSM waking up ULP from sleep */
|
||||
|
||||
/**
|
||||
* @defgroup ulp_registers ULP coprocessor registers
|
||||
* @{
|
||||
@ -63,7 +52,9 @@ extern "C" {
|
||||
#define OPCODE_ADC 5 /*!< Instruction: SAR ADC measurement (not implemented yet) */
|
||||
|
||||
#define OPCODE_ST 6 /*!< Instruction: store indirect to RTC memory */
|
||||
#define SUB_OPCODE_ST 4 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */
|
||||
#define SUB_OPCODE_ST_AUTO 1 /*!< Automatic Storage Mode - Access continuous addresses. Use SUB_OPCODE_ST_OFFSET to configure the initial address before using this instruction. */
|
||||
#define SUB_OPCODE_ST_OFFSET 3 /*!< Automatic Storage Mode - Configure the initial address. */
|
||||
#define SUB_OPCODE_ST 4 /*!< Manual Storage Mode. Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */
|
||||
|
||||
#define OPCODE_ALU 7 /*!< Arithmetic instructions */
|
||||
#define SUB_OPCODE_ALU_REG 0 /*!< Arithmetic instruction, both source values are in register */
|
||||
@ -76,15 +67,23 @@ extern "C" {
|
||||
#define ALU_SEL_MOV 4 /*!< Copy value (immediate to destination register or source register to destination register */
|
||||
#define ALU_SEL_LSH 5 /*!< Shift left by given number of bits */
|
||||
#define ALU_SEL_RSH 6 /*!< Shift right by given number of bits */
|
||||
#define ALU_SEL_STAGE_INC 0 /*!< Increment stage count register */
|
||||
#define ALU_SEL_STAGE_DEC 1 /*!< Decrement stage count register */
|
||||
#define ALU_SEL_STAGE_RST 2 /*!< Reset stage count register */
|
||||
|
||||
#define OPCODE_BRANCH 8 /*!< Branch instructions */
|
||||
#define SUB_OPCODE_BX 0 /*!< Branch to absolute PC (immediate or in register) */
|
||||
#define SUB_OPCODE_B 0 /*!< Branch to a relative offset */
|
||||
#define SUB_OPCODE_BX 1 /*!< Branch to absolute PC (immediate or in register) */
|
||||
#define SUB_OPCODE_BS 2 /*!< Branch to a relative offset by comparing the stage_cnt register */
|
||||
#define BX_JUMP_TYPE_DIRECT 0 /*!< Unconditional jump */
|
||||
#define BX_JUMP_TYPE_ZERO 1 /*!< Branch if last ALU result is zero */
|
||||
#define BX_JUMP_TYPE_OVF 2 /*!< Branch if last ALU operation caused and overflow */
|
||||
#define SUB_OPCODE_B 1 /*!< Branch to a relative offset */
|
||||
#define B_CMP_L 0 /*!< Branch if R0 is less than an immediate */
|
||||
#define B_CMP_GE 1 /*!< Branch if R0 is greater than or equal to an immediate */
|
||||
#define B_CMP_G 1 /*!< Branch if R0 is greater than an immediate */
|
||||
#define B_CMP_E 2 /*!< Branch if R0 is equal to an immediate */
|
||||
#define BS_CMP_L 0 /*!< Branch if stage_cnt is less than an immediate */
|
||||
#define BS_CMP_GE 1 /*!< Branch if stage_cnt is greater than or equal to an immediate */
|
||||
#define BS_CMP_LE 2 /*!< Branch if stage_cnt is less than or equal to an immediate */
|
||||
|
||||
#define OPCODE_END 9 /*!< Stop executing the program */
|
||||
#define SUB_OPCODE_END 0 /*!< Stop executing the program and optionally wake up the chip */
|
||||
@ -99,6 +98,7 @@ extern "C" {
|
||||
#define OPCODE_MACRO 15 /*!< Not a real opcode. Used to identify labels and branches in the program */
|
||||
#define SUB_OPCODE_MACRO_LABEL 0 /*!< Label macro */
|
||||
#define SUB_OPCODE_MACRO_BRANCH 1 /*!< Branch macro */
|
||||
#define SUB_OPCODE_MACRO_LABELPC 2 /*!< Label pointer macro */
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
@ -126,7 +126,10 @@ union ulp_insn {
|
||||
struct {
|
||||
uint32_t dreg : 2; /*!< Register which contains data to store */
|
||||
uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */
|
||||
uint32_t unused1 : 6; /*!< Unused */
|
||||
uint32_t label: 2; /*!< Data label, 2-bit user defined unsigned value */
|
||||
uint32_t upper: 1; /*!< 0: write the low half-word; 1: write the high half-word */
|
||||
uint32_t wr_way: 2; /*!< 0: write the full-word; 1: with the label; 3: without the label */
|
||||
uint32_t unused1 : 1; /*!< Unused */
|
||||
uint32_t offset : 11; /*!< Offset to add to sreg */
|
||||
uint32_t unused2 : 4; /*!< Unused */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ST) */
|
||||
@ -138,7 +141,8 @@ union ulp_insn {
|
||||
uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */
|
||||
uint32_t unused1 : 6; /*!< Unused */
|
||||
uint32_t offset : 11; /*!< Offset to add to sreg */
|
||||
uint32_t unused2 : 7; /*!< Unused */
|
||||
uint32_t unused2 : 6; /*!< Unused */
|
||||
uint32_t rd_upper: 1; /*!< 0: read the high half-word; 1: read the low half-word*/
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_LD) */
|
||||
} ld; /*!< Format of LD instruction */
|
||||
|
||||
@ -150,19 +154,20 @@ union ulp_insn {
|
||||
struct {
|
||||
uint32_t dreg : 2; /*!< Register which contains target PC, expressed in words (used if .reg == 1) */
|
||||
uint32_t addr : 11; /*!< Target PC, expressed in words (used if .reg == 0) */
|
||||
uint32_t unused : 8; /*!< Unused */
|
||||
uint32_t unused1 : 8; /*!< Unused */
|
||||
uint32_t reg : 1; /*!< Target PC in register (1) or immediate (0) */
|
||||
uint32_t type : 3; /*!< Jump condition (BX_JUMP_TYPE_xxx) */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */
|
||||
uint32_t unused2 : 1; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_BX) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
|
||||
} bx; /*!< Format of BRANCH instruction (absolute address) */
|
||||
|
||||
struct {
|
||||
uint32_t imm : 16; /*!< Immediate value to compare against */
|
||||
uint32_t cmp : 1; /*!< Comparison to perform: B_CMP_L or B_CMP_GE */
|
||||
uint32_t cmp : 2; /*!< Comparison to perform: B_CMP_L or B_CMP_GE */
|
||||
uint32_t offset : 7; /*!< Absolute value of target PC offset w.r.t. current PC, expressed in words */
|
||||
uint32_t sign : 1; /*!< Sign of target PC offset: 0: positive, 1: negative */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_B) */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_B) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */
|
||||
} b; /*!< Format of BRANCH instruction (relative address) */
|
||||
|
||||
@ -170,9 +175,10 @@ union ulp_insn {
|
||||
uint32_t dreg : 2; /*!< Destination register */
|
||||
uint32_t sreg : 2; /*!< Register with operand A */
|
||||
uint32_t treg : 2; /*!< Register with operand B */
|
||||
uint32_t unused : 15; /*!< Unused */
|
||||
uint32_t unused1 : 15; /*!< Unused */
|
||||
uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */
|
||||
uint32_t unused2 : 1; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */
|
||||
} alu_reg; /*!< Format of ALU instruction (both sources are registers) */
|
||||
|
||||
@ -180,12 +186,23 @@ union ulp_insn {
|
||||
uint32_t dreg : 2; /*!< Destination register */
|
||||
uint32_t sreg : 2; /*!< Register with operand A */
|
||||
uint32_t imm : 16; /*!< Immediate value of operand B */
|
||||
uint32_t unused : 1; /*!< Unused */
|
||||
uint32_t unused1: 1; /*!< Unused */
|
||||
uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */
|
||||
uint32_t unused2 : 1; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */
|
||||
} alu_imm; /*!< Format of ALU instruction (one source is an immediate) */
|
||||
|
||||
struct {
|
||||
uint32_t unused1: 4; /*!< Unused */
|
||||
uint32_t imm : 8; /*!< Immediate value */
|
||||
uint32_t unused2: 9; /*!< Unused */
|
||||
uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */
|
||||
uint32_t unused3 : 1; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_ALU_CNT) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */
|
||||
} alu_cnt; /*!< Format of ALU instruction with stage count register and an immediate */
|
||||
|
||||
struct {
|
||||
uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */
|
||||
uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */
|
||||
@ -201,7 +218,7 @@ union ulp_insn {
|
||||
uint32_t unused : 8; /*!< Unused */
|
||||
uint32_t low : 5; /*!< Low bit */
|
||||
uint32_t high : 5; /*!< High bit */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_RD_REG) */
|
||||
} rd_reg; /*!< Format of RD_REG instruction */
|
||||
|
||||
struct {
|
||||
@ -234,18 +251,11 @@ union ulp_insn {
|
||||
|
||||
struct {
|
||||
uint32_t wakeup : 1; /*!< Set to 1 to wake up chip */
|
||||
uint32_t unused : 24; /*!< Unused */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */
|
||||
uint32_t unused : 25; /*!< Unused */
|
||||
uint32_t sub_opcode : 2; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */
|
||||
} end; /*!< Format of END instruction with wakeup */
|
||||
|
||||
struct {
|
||||
uint32_t cycle_sel : 4; /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */
|
||||
uint32_t unused : 21; /*!< Unused */
|
||||
uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_SLEEP) */
|
||||
uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */
|
||||
} sleep; /*!< Format of END instruction with sleep */
|
||||
|
||||
struct {
|
||||
uint32_t label : 16; /*!< Label number */
|
||||
uint32_t unused : 8; /*!< Unused */
|
||||
@ -255,8 +265,6 @@ union ulp_insn {
|
||||
|
||||
};
|
||||
|
||||
typedef union ulp_insn ulp_insn_t;
|
||||
|
||||
_Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should be 4 bytes");
|
||||
|
||||
/**
|
||||
@ -355,7 +363,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
*
|
||||
* To disable the timer which start ULP program, use I_END()
|
||||
* instruction. I_END instruction clears the
|
||||
* RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG
|
||||
* RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_ULP_CP_TIMER_REG
|
||||
* register, which controls the ULP timer.
|
||||
*/
|
||||
#define I_WAKE() { .end = { \
|
||||
@ -375,27 +383,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
* the currently running program, use I_HALT().
|
||||
*/
|
||||
#define I_END() \
|
||||
I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
|
||||
/**
|
||||
* Select the time interval used to run ULP program.
|
||||
*
|
||||
* This instructions selects which of the SENS_SLEEP_CYCLES_Sx
|
||||
* registers' value is used by the ULP program timer.
|
||||
* When the ULP program stops at I_HALT instruction, ULP program
|
||||
* timer start counting. When the counter reaches the value of
|
||||
* the selected SENS_SLEEP_CYCLES_Sx register, ULP program
|
||||
* start running again from the start address (passed to the ulp_run
|
||||
* function).
|
||||
* There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5.
|
||||
*
|
||||
* By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP
|
||||
* program timer.
|
||||
*/
|
||||
#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \
|
||||
.cycle_sel = timer_idx, \
|
||||
.unused = 0, \
|
||||
.sub_opcode = SUB_OPCODE_SLEEP, \
|
||||
.opcode = OPCODE_END } }
|
||||
I_WR_REG_BIT(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
|
||||
|
||||
/**
|
||||
* Perform temperature sensor measurement and store it into reg_dest.
|
||||
@ -425,44 +413,247 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.opcode = OPCODE_ADC } }
|
||||
|
||||
/**
|
||||
* Store value from register reg_val into RTC memory.
|
||||
* Store lower half-word, upper half-word or full-word data from register reg_val into RTC memory address.
|
||||
*
|
||||
* The value is written to an offset calculated by adding value of
|
||||
* This instruction can be used to write data to discontinuous addresses in the RTC_SLOW_MEM.
|
||||
* The value is written to an offset calculated by adding the value of
|
||||
* reg_addr register and offset_ field (this offset is expressed in 32-bit words).
|
||||
* 32 bits written to RTC memory are built as follows:
|
||||
* - bits [31:21] hold the PC of current instruction, expressed in 32-bit words
|
||||
* - bits [20:16] = 5'b1
|
||||
* - bits [15:0] are assigned the contents of reg_val
|
||||
* The storage method is dictated by the wr_way and upper field settings as summarized in the following table:
|
||||
*
|
||||
* RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] }
|
||||
* @verbatim
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | wr_way | upper | data | operation |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Write full-word, including |
|
||||
* | 0 | X | RTC_SLOW_MEM[addr + offset_]{31:0} = {insn_PC[10:0], 3’b0, label_[1:0], reg_val[15:0]} | the PC and the data |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data with label |
|
||||
* | 1 | 0 | RTC_SLOW_MEM[addr + offset_]{15:0} = {label_[1:0], reg_val[13:0]} | in the low half-word |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data with label |
|
||||
* | 1 | 1 | RTC_SLOW_MEM[addr + offset_]{31:16} = {label_[1:0], reg_val[13:0]} | in the high half-word |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data without |
|
||||
* | 3 | 0 | RTC_SLOW_MEM[addr + offset_]{15:0} = reg_val[15:0] | label in the low half-word |
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data without |
|
||||
* | 3 | 1 | RTC_SLOW_MEM[addr + offset_]{31:16} = reg_val[15:0] | label in the high half-word|
|
||||
* |--------|-------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* @endverbatim
|
||||
*
|
||||
* SUB_OPCODE_ST = manual_en:1, offset_set:0, wr_auto:0
|
||||
*/
|
||||
#define I_ST(reg_val, reg_addr, offset_) { .st = { \
|
||||
#define I_ST_MANUAL(reg_val, reg_addr, offset_, label_, upper_, wr_way_) { .st = { \
|
||||
.dreg = reg_val, \
|
||||
.sreg = reg_addr, \
|
||||
.label = label_, \
|
||||
.upper = upper_, \
|
||||
.wr_way = wr_way_, \
|
||||
.unused1 = 0, \
|
||||
.offset = offset_, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ST, \
|
||||
.opcode = OPCODE_ST } }
|
||||
|
||||
/**
|
||||
* Store value from register reg_val into RTC memory.
|
||||
*
|
||||
* I_ST() instruction provides backward compatibility for code written for esp32 to be run on esp32s2.
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = 0, upper = 0 and wr_way = 3.
|
||||
*/
|
||||
#define I_ST(reg_val, reg_addr, offset_) I_ST_MANUAL(reg_val, reg_addr, offset_, 0, 0, 3)
|
||||
|
||||
/**
|
||||
* Load value from RTC memory into reg_dest register.
|
||||
* Store value from register reg_val to lower 16 bits of the RTC memory address.
|
||||
*
|
||||
* Loads 16 LSBs from RTC memory word given by the sum of value in reg_addr and
|
||||
* value of offset_.
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = 0, upper = 0 and wr_way = 3.
|
||||
*/
|
||||
#define I_LD(reg_dest, reg_addr, offset_) { .ld = { \
|
||||
#define I_STL(reg_val, reg_addr, offset_) I_ST_MANUAL(reg_val, reg_addr, offset_, 0, 0, 3)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val to upper 16 bits of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = 0, upper = 1 and wr_way = 3.
|
||||
*/
|
||||
#define I_STH(reg_val, reg_addr, offset_) I_ST_MANUAL(reg_val, reg_addr, offset_, 0, 1, 3)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val to full 32 bit word of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with wr_way = 0.
|
||||
*/
|
||||
#define I_ST32(reg_val, reg_addr, offset_, label_) I_ST_MANUAL(reg_val, reg_addr, offset_, label_, 0, 0)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val with label to lower 16 bits of RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = label_, upper = 0 and wr_way = 1.
|
||||
*/
|
||||
#define I_STL_LABEL(reg_val, reg_addr, offset_, label_) I_ST_MANUAL(reg_val, reg_addr, offset_, label_, 0, 1)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val with label to upper 16 bits of RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_MANUAL() instruction with label = label_, upper = 1 and wr_way = 1.
|
||||
*/
|
||||
#define I_STH_LABEL(reg_val, reg_addr, offset_, label_) I_ST_MANUAL(reg_val, reg_addr, offset_, label_, 1, 1)
|
||||
|
||||
/**
|
||||
* Store lower half-word, upper half-word or full-word data from register reg_val into RTC memory address with auto-increment of the offset value.
|
||||
*
|
||||
* This instruction can be used to write data to continuous addresses in the RTC_SLOW_MEM.
|
||||
* The initial address must be set using the SUB_OPCODE_ST_OFFSET instruction before the auto store instruction is called.
|
||||
* The data written to the RTC memory address could be written to the full 32 bit word or to the lower half-word or the
|
||||
* upper half-word. The storage method is dictated by the wr_way field and the number of times the SUB_OPCODE_ST_AUTO instruction is called.
|
||||
* write_cnt indicates the later. The following table summarizes the storage method:
|
||||
*
|
||||
* @verbatim
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | wr_way | write_cnt | data | operation |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Write full-word, including |
|
||||
* | 0 | X | RTC_SLOW_MEM[addr + offset_]{31:0} = {insn_PC[10:0], 3’b0, label_[1:0], reg_val[15:0]} | the PC and the data |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data with label |
|
||||
* | 1 | odd | RTC_SLOW_MEM[addr + offset_]{15:0} = {label_[1:0], reg_val[13:0]} | in the low half-word |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data with label |
|
||||
* | 1 | even | RTC_SLOW_MEM[addr + offset_]{31:16} = {label_[1:0], reg_val[13:0]} | in the high half-word |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data without |
|
||||
* | 3 | odd | RTC_SLOW_MEM[addr + offset_]{15:0} = reg_val[15:0] | label in the low half-word |
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* | | | | Store the data without |
|
||||
* | 3 | even | RTC_SLOW_MEM[addr + offset_]{31:16} = reg_val[15:0] | label in the high half-word|
|
||||
* |--------|-----------|----------------------------------------------------------------------------------------|----------------------------|
|
||||
* @endverbatim
|
||||
*
|
||||
* The initial address offset is incremented after each store operation as follows:
|
||||
* - When a full-word is written, the offset is automatically incremented by 1 after each SUB_OPCODE_ST_AUTO operation.
|
||||
* - When a half-word is written (lower half-word first), the offset is automatically incremented by 1 after two
|
||||
* SUB_OPCODE_ST_AUTO operations.
|
||||
*
|
||||
* SUB_OPCODE_ST_AUTO = manual_en:0, offset_set:0, wr_auto:1
|
||||
*/
|
||||
#define I_ST_AUTO(reg_val, reg_addr, label_, wr_way_) { .st = { \
|
||||
.dreg = reg_addr, \
|
||||
.sreg = reg_val, \
|
||||
.label = label_, \
|
||||
.upper = 0, \
|
||||
.wr_way = wr_way_, \
|
||||
.unused1 = 0, \
|
||||
.offset = 0, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ST_AUTO, \
|
||||
.opcode = OPCODE_ST } }
|
||||
|
||||
/**
|
||||
* Set the initial address offset for auto-store operation
|
||||
*
|
||||
* This instruction sets the initial address of the RTC_SLOW_MEM to be used by the auto-store operation.
|
||||
* The offset is incremented automatically.
|
||||
* Refer I_ST_AUTO() for detailed explaination.
|
||||
*
|
||||
* SUB_OPCODE_ST_OFFSET = manual_en:0, offset_set:1, wr_auto:1
|
||||
*/
|
||||
#define I_STO(offset_) { .st = { \
|
||||
.dreg = 0, \
|
||||
.sreg = 0, \
|
||||
.label = 0, \
|
||||
.upper = 0, \
|
||||
.wr_way = 0, \
|
||||
.unused1 = 0, \
|
||||
.offset = offset_, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ST_OFFSET, \
|
||||
.opcode = OPCODE_ST } }
|
||||
|
||||
/**
|
||||
* Store value from register reg_val to 32 bit word of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_AUTO() instruction with label = 0 and wr_way = 3.
|
||||
* The data in reg_val will be either written to the lower half-word or the upper half-word of the RTC memory address
|
||||
* depending on the count of the number of times the I_STI() instruction is called.
|
||||
* The initial offset is automatically incremented with I_STI() is called twice.
|
||||
* Refer I_ST_AUTO() for detailed explaination.
|
||||
*/
|
||||
#define I_STI(reg_val, reg_addr) I_ST_AUTO(reg_val, reg_addr, 0, 3)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val with label to 32 bit word of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_AUTO() instruction with label = label_ and wr_way = 1.
|
||||
* The data in reg_val will be either written to the lower half-word or the upper half-word of the RTC memory address
|
||||
* depending on the count of the number of times the I_STI_LABEL() instruction is called.
|
||||
* The initial offset is automatically incremented with I_STI_LABEL() is called twice.
|
||||
* Refer I_ST_AUTO() for detailed explaination.
|
||||
*/
|
||||
#define I_STI_LABEL(reg_val, reg_addr, label_) I_ST_AUTO(reg_val, reg_addr, label_, 1)
|
||||
|
||||
/**
|
||||
* Store value from register reg_val to full 32 bit word of the RTC memory address.
|
||||
*
|
||||
* This instruction is equivalent to calling I_ST_AUTO() instruction with label = label_ and wr_way = 0.
|
||||
* The data in reg_val will be written to the RTC memory address along with the label and the PC.
|
||||
* The initial offset is automatically incremented each time the I_STI32() instruction is called.
|
||||
* Refer I_ST_AUTO() for detailed explaination.
|
||||
*/
|
||||
#define I_STI32(reg_val, reg_addr, label_) I_ST_AUTO(reg_val, reg_addr, label_, 0)
|
||||
|
||||
/**
|
||||
* Load lower half-word, upper half-word or full-word data from RTC memory address into the register reg_dest.
|
||||
*
|
||||
* This instruction reads the lower half-word or upper half-word of the RTC memory address depending on the value
|
||||
* of rd_upper_. The following table summarizes the loading method:
|
||||
*
|
||||
* @verbatim
|
||||
* |----------|------------------------------------------------------|-------------------------|
|
||||
* | rd_upper | data | operation |
|
||||
* |----------|------------------------------------------------------|-------------------------|
|
||||
* | | | Read lower half-word of |
|
||||
* | 0 | reg_dest{15:0} = RTC_SLOW_MEM[addr + offset_]{31:16} | the memory |
|
||||
* |----------|------------------------------------------------------|-------------------------|
|
||||
* | | | Read upper half-word of |
|
||||
* | 1 | reg_dest{15:0} = RTC_SLOW_MEM[addr + offset_]{15:0} | the memory |
|
||||
* |----------|------------------------------------------------------|-------------------------|
|
||||
* @endverbatim
|
||||
*
|
||||
*/
|
||||
#define I_LD_MANUAL(reg_dest, reg_addr, offset_, rd_upper_) { .ld = { \
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_addr, \
|
||||
.unused1 = 0, \
|
||||
.offset = offset_, \
|
||||
.unused2 = 0, \
|
||||
.rd_upper = rd_upper_, \
|
||||
.opcode = OPCODE_LD } }
|
||||
|
||||
/**
|
||||
* Load lower 16 bits value from RTC memory into reg_dest register.
|
||||
*
|
||||
* Loads 16 LSBs (rd_upper = 1) from RTC memory word given by the sum of value in reg_addr and
|
||||
* value of offset_.
|
||||
* I_LD() instruction provides backward compatibility for code written for esp32 to be run on esp32s2.
|
||||
*/
|
||||
#define I_LD(reg_dest, reg_addr, offset_) I_LD_MANUAL(reg_dest, reg_addr, offset_, 0)
|
||||
|
||||
/**
|
||||
* Branch relative if R0 less than immediate value.
|
||||
* Load lower 16 bits value from RTC memory into reg_dest register.
|
||||
*
|
||||
* I_LDL() instruction and I_LD() instruction can be used interchangably.
|
||||
*/
|
||||
#define I_LDL(reg_dest, reg_addr, offset_) I_LD(reg_dest, reg_addr, offset_)
|
||||
|
||||
/**
|
||||
* Load upper 16 bits value from RTC memory into reg_dest register.
|
||||
*
|
||||
* Loads 16 MSBs (rd_upper = 0) from RTC memory word given by the sum of value in reg_addr and
|
||||
* value of offset_.
|
||||
*/
|
||||
#define I_LDH(reg_dest, reg_addr, offset_) I_LD_MANUAL(reg_dest, reg_addr, offset_, 1)
|
||||
|
||||
/**
|
||||
* Branch relative if R0 register less than the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
@ -476,14 +667,28 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if R0 greater or equal than immediate value.
|
||||
* Branch relative if R0 register greater than the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BGE(pc_offset, imm_value) { .b = { \
|
||||
#define I_BG(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = B_CMP_GE, \
|
||||
.cmp = B_CMP_G, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_B, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if R0 register is equal to the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BE(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = B_CMP_E, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_B, \
|
||||
@ -498,9 +703,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
#define I_BXR(reg_pc) { .bx = { \
|
||||
.dreg = reg_pc, \
|
||||
.addr = 0, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 1, \
|
||||
.type = BX_JUMP_TYPE_DIRECT, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -512,9 +718,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
#define I_BXI(imm_pc) { .bx = { \
|
||||
.dreg = 0, \
|
||||
.addr = imm_pc, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 0, \
|
||||
.type = BX_JUMP_TYPE_DIRECT, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -527,9 +734,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
#define I_BXZR(reg_pc) { .bx = { \
|
||||
.dreg = reg_pc, \
|
||||
.addr = 0, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 1, \
|
||||
.type = BX_JUMP_TYPE_ZERO, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -541,9 +749,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
#define I_BXZI(imm_pc) { .bx = { \
|
||||
.dreg = 0, \
|
||||
.addr = imm_pc, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 0, \
|
||||
.type = BX_JUMP_TYPE_ZERO, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -556,9 +765,10 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
#define I_BXFR(reg_pc) { .bx = { \
|
||||
.dreg = reg_pc, \
|
||||
.addr = 0, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 1, \
|
||||
.type = BX_JUMP_TYPE_OVF, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
@ -570,12 +780,54 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
#define I_BXFI(imm_pc) { .bx = { \
|
||||
.dreg = 0, \
|
||||
.addr = imm_pc, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.reg = 0, \
|
||||
.type = BX_JUMP_TYPE_OVF, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_BX, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if stage_cnt is less than or equal to the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BSLE(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = BS_CMP_LE, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_BS, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if stage_cnt register is greater than or equal to the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BSGE(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = BS_CMP_GE, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_BS, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Branch relative if stage_cnt register is less than the immediate value.
|
||||
*
|
||||
* pc_offset is expressed in words, and can be from -127 to 127
|
||||
* imm_value is a 16-bit value to compare R0 against
|
||||
*/
|
||||
#define I_BSL(pc_offset, imm_value) { .b = { \
|
||||
.imm = imm_value, \
|
||||
.cmp = BS_CMP_L, \
|
||||
.offset = abs(pc_offset), \
|
||||
.sign = (pc_offset >= 0) ? 0 : 1, \
|
||||
.sub_opcode = SUB_OPCODE_BS, \
|
||||
.opcode = OPCODE_BRANCH } }
|
||||
|
||||
/**
|
||||
* Addition: dest = src1 + src2
|
||||
@ -584,8 +836,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src1, \
|
||||
.treg = reg_src2, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_ADD, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -596,8 +849,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src1, \
|
||||
.treg = reg_src2, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_SUB, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -608,8 +862,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src1, \
|
||||
.treg = reg_src2, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_AND, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -620,8 +875,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src1, \
|
||||
.treg = reg_src2, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_OR, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -632,8 +888,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.treg = 0, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_MOV, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -644,8 +901,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.treg = reg_shift, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_LSH, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -657,8 +915,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.treg = reg_shift, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_RSH, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_REG, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -669,8 +928,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_ADD, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -682,8 +942,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_SUB, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -694,8 +955,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_AND, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -706,8 +968,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_OR, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -718,8 +981,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = 0, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_MOV, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -730,8 +994,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_LSH, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
@ -743,11 +1008,48 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
.dreg = reg_dest, \
|
||||
.sreg = reg_src, \
|
||||
.imm = imm_, \
|
||||
.unused = 0, \
|
||||
.unused1 = 0, \
|
||||
.sel = ALU_SEL_RSH, \
|
||||
.unused2 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_IMM, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
/**
|
||||
* Increment stage_cnt register by an immediate: stage_cnt = stage_cnt + imm
|
||||
*/
|
||||
#define I_STAGE_INC(reg_dest, reg_src, imm_) { .alu_cnt = { \
|
||||
.unused1 = 0, \
|
||||
.imm = imm_, \
|
||||
.unused2 = 0, \
|
||||
.sel = ALU_SEL_STAGE_INC, \
|
||||
.unused3 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_CNT, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
/**
|
||||
* Decrement stage_cnt register by an immediate: stage_cnt = stage_cnt - imm
|
||||
*/
|
||||
#define I_STAGE_DEC(reg_dest, reg_src, imm_) { .alu_cnt = { \
|
||||
.unused1 = 0, \
|
||||
.imm = imm_, \
|
||||
.unused2 = 0, \
|
||||
.sel = ALU_SEL_STAGE_DEC, \
|
||||
.unused3 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_CNT, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
/**
|
||||
* Reset stage_cnt register by an immediate: stage_cnt = 0
|
||||
*/
|
||||
#define I_STAGE_RST(reg_dest, reg_src, imm_) { .alu_cnt = { \
|
||||
.unused1 = 0, \
|
||||
.imm = imm_, \
|
||||
.unused2 = 0, \
|
||||
.sel = ALU_SEL_STAGE_RST, \
|
||||
.unused3 = 0, \
|
||||
.sub_opcode = SUB_OPCODE_ALU_CNT, \
|
||||
.opcode = OPCODE_ALU } }
|
||||
|
||||
/**
|
||||
* Define a label with number label_num.
|
||||
*
|
||||
@ -784,16 +1086,28 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
I_BL(0, imm_value)
|
||||
|
||||
/**
|
||||
* Macro: branch to label label_num if R0 is greater or equal than immediate value
|
||||
* Macro: branch to label label_num if R0 is greater than immediate value
|
||||
*
|
||||
* This macro generates two ulp_insn_t values separated by a comma, and should
|
||||
* be used when defining contents of ulp_insn_t arrays. First value is not a
|
||||
* real instruction; it is a token which is removed by ulp_process_macros_and_load
|
||||
* function.
|
||||
*/
|
||||
#define M_BGE(label_num, imm_value) \
|
||||
#define M_BG(label_num, imm_value) \
|
||||
M_BRANCH(label_num), \
|
||||
I_BGE(0, imm_value)
|
||||
I_BG(0, imm_value)
|
||||
|
||||
/**
|
||||
* Macro: branch to label label_num if R0 equal to the immediate value
|
||||
*
|
||||
* This macro generates two ulp_insn_t values separated by a comma, and should
|
||||
* be used when defining contents of ulp_insn_t arrays. First value is not a
|
||||
* real instruction; it is a token which is removed by ulp_process_macros_and_load
|
||||
* function.
|
||||
*/
|
||||
#define M_BE(label_num, imm_value) \
|
||||
M_BRANCH(label_num), \
|
||||
I_BE(0, imm_value)
|
||||
|
||||
/**
|
||||
* Macro: unconditional branch to label
|
||||
@ -831,8 +1145,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
|
||||
M_BRANCH(label_num), \
|
||||
I_BXFI(0)
|
||||
|
||||
|
||||
|
||||
#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
43
components/ulp/include/esp32s3/ulp_riscv.h
Normal file
43
components/ulp/include/esp32s3/ulp_riscv.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include "esp_err.h"
|
||||
#include "ulp_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Run the program loaded into RTC memory
|
||||
* @return ESP_OK on success
|
||||
*/
|
||||
esp_err_t ulp_riscv_run(void);
|
||||
|
||||
/**
|
||||
* @brief Load ULP-RISC-V program binary into RTC memory
|
||||
*
|
||||
* Different than ULP FSM, the binary program has no special format, it is the ELF
|
||||
* file generated by RISC-V toolchain converted to binary format using objcopy.
|
||||
*
|
||||
* Linker script in components/ulp/ld/esp32s3.ulp.riscv.ld produces ELF files which
|
||||
* correspond to this format. This linker script produces binaries with load_addr == 0.
|
||||
*
|
||||
* @param program_binary pointer to program binary
|
||||
* @param program_size_bytes size of the program binary
|
||||
* @return
|
||||
* - ESP_OK on success
|
||||
* - ESP_ERR_INVALID_SIZE if program_size_bytes is more than 8KiB
|
||||
*/
|
||||
esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -1,20 +1,12 @@
|
||||
// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
/* This file contains definitions that are common between esp32/ulp.h
|
||||
and esp32s2/ulp.h
|
||||
/* This file contains definitions that are common between esp32/ulp.h,
|
||||
esp32s2/ulp.h and esp32s3/ulp.h
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
@ -111,6 +103,22 @@ esp_err_t ulp_run(uint32_t entry_point);
|
||||
*/
|
||||
esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us);
|
||||
|
||||
/**
|
||||
* @brief Stop the ULP timer
|
||||
*
|
||||
* @note This will stop the ULP from waking up if halted, but will not abort any program
|
||||
* currently executing on the ULP.
|
||||
*/
|
||||
void ulp_timer_stop(void);
|
||||
|
||||
/**
|
||||
* @brief Resume the ULP timer
|
||||
*
|
||||
* @note This will resume an already configured timer, but does no other configuration
|
||||
*
|
||||
*/
|
||||
void ulp_timer_resume(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
48
components/ulp/ld/esp32s3.ulp.riscv.ld
Normal file
48
components/ulp/ld/esp32s3.ulp.riscv.ld
Normal file
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "sdkconfig.h"
|
||||
|
||||
ENTRY(reset_vector)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram(RW) : ORIGIN = 0, LENGTH = CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(ram);
|
||||
.text :
|
||||
{
|
||||
*start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
|
||||
*(.text)
|
||||
*(.text*)
|
||||
} >ram
|
||||
|
||||
.rodata ALIGN(4):
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
} > ram
|
||||
|
||||
.data ALIGN(4):
|
||||
{
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.sdata)
|
||||
*(.sdata*)
|
||||
} > ram
|
||||
|
||||
.bss ALIGN(4) :
|
||||
{
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(.sbss)
|
||||
*(.sbss*)
|
||||
} >ram
|
||||
|
||||
__stack_top = ORIGIN(ram) + LENGTH(ram);
|
||||
}
|
||||
@ -1,7 +1,14 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#if CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
|
||||
#define LOCAL_ULP_COPROC_RESERVE_MEM CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
|
||||
#elif CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
|
||||
#define LOCAL_ULP_COPROC_RESERVE_MEM CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
|
||||
#else
|
||||
#define LOCAL_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
|
||||
#endif
|
||||
@ -31,20 +31,19 @@ function(ulp_embed_binary app_name s_sources exp_dep_srcs)
|
||||
|
||||
idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER)
|
||||
idf_build_get_property(idf_path IDF_PATH)
|
||||
idf_build_get_property(idf_target IDF_TARGET)
|
||||
idf_build_get_property(python PYTHON)
|
||||
idf_build_get_property(extra_cmake_args EXTRA_CMAKE_ARGS)
|
||||
|
||||
if(IDF_TARGET STREQUAL "esp32")
|
||||
set(TOOLCHAIN_FLAG ${idf_path}/components/ulp/cmake/toolchain-esp32-ulp.cmake)
|
||||
set(TOOLCHAIN_FLAG ${idf_path}/components/ulp/cmake/toolchain-${idf_target}-ulp.cmake)
|
||||
set(ULP_IS_RISCV OFF)
|
||||
endif()
|
||||
|
||||
if(IDF_TARGET STREQUAL "esp32s2")
|
||||
if(CONFIG_ESP32S2_ULP_COPROC_RISCV STREQUAL "y")
|
||||
set(TOOLCHAIN_FLAG ${idf_path}/components/ulp/cmake/toolchain-esp32s2-ulp-riscv.cmake)
|
||||
elseif(IDF_TARGET STREQUAL "esp32s2" OR IDF_TARGET STREQUAL "esp32s3")
|
||||
if(CONFIG_ESP32S2_ULP_COPROC_RISCV STREQUAL "y" OR CONFIG_ESP32S3_ULP_COPROC_RISCV STREQUAL "y")
|
||||
set(TOOLCHAIN_FLAG ${idf_path}/components/ulp/cmake/toolchain-ulp-riscv.cmake)
|
||||
set(ULP_IS_RISCV ON)
|
||||
else()
|
||||
set(TOOLCHAIN_FLAG ${idf_path}/components/ulp/cmake/toolchain-esp32s2-ulp.cmake)
|
||||
set(TOOLCHAIN_FLAG ${idf_path}/components/ulp/cmake/toolchain-${idf_target}-ulp.cmake)
|
||||
set(ULP_IS_RISCV OFF)
|
||||
endif()
|
||||
endif()
|
||||
@ -60,6 +59,7 @@ function(ulp_embed_binary app_name s_sources exp_dep_srcs)
|
||||
-DCOMPONENT_DIR=${COMPONENT_DIR}
|
||||
-DCOMPONENT_INCLUDES=$<TARGET_PROPERTY:${COMPONENT_TARGET},INTERFACE_INCLUDE_DIRECTORIES>
|
||||
-DIDF_PATH=${idf_path}
|
||||
-DIDF_TARGET=${idf_target}
|
||||
-DSDKCONFIG_HEADER=${SDKCONFIG_HEADER}
|
||||
-DPYTHON=${python}
|
||||
-DULP_COCPU_IS_RISCV=${ULP_IS_RISCV}
|
||||
|
||||
@ -1,16 +1,20 @@
|
||||
if(IDF_TARGET STREQUAL "esp32s3")
|
||||
return()
|
||||
if(IDF_TARGET STREQUAL "esp32")
|
||||
set(src_dirs "ulp_fsm")
|
||||
set(ulp_sources "ulp_fsm/ulp/test_jumps.S")
|
||||
elseif(IDF_TARGET STREQUAL "esp32s2" OR IDF_TARGET STREQUAL "esp32s3")
|
||||
if(CONFIG_ESP32S2_ULP_COPROC_RISCV OR CONFIG_ESP32S3_ULP_COPROC_RISCV)
|
||||
set(src_dirs "ulp_riscv")
|
||||
set(ulp_sources "ulp_riscv/ulp/test_main.c")
|
||||
else()
|
||||
set(src_dirs "ulp_fsm")
|
||||
set(ulp_sources "ulp_fsm/ulp/test_jumps.S")
|
||||
endif()
|
||||
endif()
|
||||
idf_component_register(SRC_DIRS ${IDF_TARGET}
|
||||
|
||||
idf_component_register(SRC_DIRS ${src_dirs}
|
||||
PRIV_INCLUDE_DIRS .
|
||||
PRIV_REQUIRES cmock ulp soc esp_common driver)
|
||||
|
||||
if(IDF_TARGET STREQUAL "esp32")
|
||||
set(ulp_sources "ulp/test_jumps_esp32.S")
|
||||
elseif(IDF_TARGET STREQUAL "esp32s2")
|
||||
set(ulp_sources "ulp_riscv/test_main.c")
|
||||
endif()
|
||||
|
||||
set(ulp_app_name ulp_test_app)
|
||||
set(ulp_exp_dep_srcs ${IDF_TARGET})
|
||||
set(ulp_exp_dep_srcs ${src_dirs})
|
||||
ulp_embed_binary(${ulp_app_name} "${ulp_sources}" "${ulp_exp_dep_srcs}")
|
||||
|
||||
@ -1,460 +0,0 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <freertos/FreeRTOS.h>
|
||||
#include <freertos/task.h>
|
||||
#include <freertos/semphr.h>
|
||||
|
||||
#include <unity.h>
|
||||
#include "esp_attr.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_sleep.h"
|
||||
|
||||
#include "esp32/ulp.h"
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/sens_reg.h"
|
||||
#include "driver/rtc_io.h"
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
static void hexdump(const uint32_t* src, size_t count) {
|
||||
for (size_t i = 0; i < count; ++i) {
|
||||
printf("%08x ", *src);
|
||||
++src;
|
||||
if ((i + 1) % 4 == 0) {
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("ulp add test", "[ulp]")
|
||||
{
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R3, 16),
|
||||
I_LD(R0, R3, 0),
|
||||
I_LD(R1, R3, 1),
|
||||
I_ADDR(R2, R0, R1),
|
||||
I_ST(R2, R3, 2),
|
||||
I_HALT()
|
||||
};
|
||||
RTC_SLOW_MEM[16] = 10;
|
||||
RTC_SLOW_MEM[17] = 11;
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
|
||||
esp_rom_delay_us(1000);
|
||||
hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
|
||||
TEST_ASSERT_EQUAL(10 + 11, RTC_SLOW_MEM[18] & 0xffff);
|
||||
}
|
||||
|
||||
TEST_CASE("ulp branch test", "[ulp]")
|
||||
{
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R0, 34), // r0 = dst
|
||||
M_LABEL(1),
|
||||
I_MOVI(R1, 32),
|
||||
I_LD(R1, R1, 0), // r1 = mem[33]
|
||||
I_MOVI(R2, 33),
|
||||
I_LD(R2, R2, 0), // r2 = mem[34]
|
||||
I_SUBR(R3, R1, R2), // r3 = r1 - r2
|
||||
I_ST(R3, R0, 0), // dst[0] = r3
|
||||
I_ADDI(R0, R0, 1),
|
||||
M_BL(1, 64),
|
||||
I_HALT(),
|
||||
};
|
||||
RTC_SLOW_MEM[32] = 42;
|
||||
RTC_SLOW_MEM[33] = 18;
|
||||
hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
ulp_process_macros_and_load(0, program, &size);
|
||||
ulp_run(0);
|
||||
printf("\n\n");
|
||||
hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
|
||||
for (int i = 34; i < 64; ++i) {
|
||||
TEST_ASSERT_EQUAL(42 - 18, RTC_SLOW_MEM[i] & 0xffff);
|
||||
}
|
||||
TEST_ASSERT_EQUAL(0, RTC_SLOW_MEM[64]);
|
||||
}
|
||||
|
||||
TEST_CASE("ulp wakeup test", "[ulp][ignore]")
|
||||
{
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, 1024),
|
||||
M_LABEL(1),
|
||||
I_DELAY(32000),
|
||||
I_SUBI(R1, R1, 1),
|
||||
M_BXZ(3),
|
||||
I_RSHI(R3, R1, 5), // R3 = R1 / 32
|
||||
I_ST(R1, R3, 16),
|
||||
M_BX(1),
|
||||
M_LABEL(3),
|
||||
I_MOVI(R2, 42),
|
||||
I_MOVI(R3, 15),
|
||||
I_ST(R2, R3, 0),
|
||||
I_WAKE(),
|
||||
I_END(),
|
||||
I_HALT()
|
||||
};
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
ulp_process_macros_and_load(0, program, &size);
|
||||
ulp_run(0);
|
||||
esp_sleep_enable_ulp_wakeup();
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
TEST_CASE("ulp can write and read peripheral registers", "[ulp]")
|
||||
{
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
REG_WRITE(RTC_CNTL_STORE1_REG, 0x89abcdef);
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, 64),
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 0, 15),
|
||||
I_ST(R0, R1, 0),
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 4, 11),
|
||||
I_ST(R0, R1, 1),
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 16, 31),
|
||||
I_ST(R0, R1, 2),
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 20, 27),
|
||||
I_ST(R0, R1, 3),
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89),
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab),
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd),
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef),
|
||||
I_LD(R0, R1, 4),
|
||||
I_ADDI(R0, R0, 1),
|
||||
I_ST(R0, R1, 4),
|
||||
I_END(),
|
||||
I_HALT()
|
||||
};
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
vTaskDelay(100/portTICK_PERIOD_MS);
|
||||
|
||||
TEST_ASSERT_EQUAL_HEX32(0xefcdab89, REG_READ(RTC_CNTL_STORE0_REG));
|
||||
TEST_ASSERT_EQUAL_HEX16(0xcdef, RTC_SLOW_MEM[64] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0xde, RTC_SLOW_MEM[65] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0x89ab, RTC_SLOW_MEM[66] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0x9a, RTC_SLOW_MEM[67] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX32(1 | (15 << 21) | (1 << 16), RTC_SLOW_MEM[68]);
|
||||
}
|
||||
|
||||
TEST_CASE("ULP I_WR_REG instruction test", "[ulp]")
|
||||
{
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
typedef struct {
|
||||
int low;
|
||||
int width;
|
||||
} wr_reg_test_item_t;
|
||||
|
||||
const wr_reg_test_item_t test_items[] = {
|
||||
{0, 1}, {0, 2}, {0, 3}, {0, 4}, {0, 5}, {0, 6}, {0, 7}, {0, 8},
|
||||
{3, 1}, {3, 2}, {3, 3}, {3, 4}, {3, 5}, {3, 6}, {3, 7}, {3, 8},
|
||||
{15, 1}, {15, 2}, {15, 3}, {15, 4}, {15, 5}, {15, 6}, {15, 7}, {15, 8},
|
||||
{16, 1}, {16, 2}, {16, 3}, {16, 4}, {16, 5}, {16, 6}, {16, 7}, {16, 8},
|
||||
{18, 1}, {18, 2}, {18, 3}, {18, 4}, {18, 5}, {18, 6}, {18, 7}, {18, 8},
|
||||
{24, 1}, {24, 2}, {24, 3}, {24, 4}, {24, 5}, {24, 6}, {24, 7}, {24, 8},
|
||||
};
|
||||
|
||||
const size_t test_items_count =
|
||||
sizeof(test_items)/sizeof(test_items[0]);
|
||||
for (size_t i = 0; i < test_items_count; ++i) {
|
||||
const uint32_t mask = (uint32_t) (((1ULL << test_items[i].width) - 1) << test_items[i].low);
|
||||
const uint32_t not_mask = ~mask;
|
||||
printf("#%2d: low: %2d width: %2d mask: %08x expected: %08x ", i,
|
||||
test_items[i].low, test_items[i].width,
|
||||
mask, not_mask);
|
||||
|
||||
REG_WRITE(RTC_CNTL_STORE0_REG, 0xffffffff);
|
||||
REG_WRITE(RTC_CNTL_STORE1_REG, 0x00000000);
|
||||
const ulp_insn_t program[] = {
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG,
|
||||
test_items[i].low,
|
||||
test_items[i].low + test_items[i].width - 1,
|
||||
0),
|
||||
I_WR_REG(RTC_CNTL_STORE1_REG,
|
||||
test_items[i].low,
|
||||
test_items[i].low + test_items[i].width - 1,
|
||||
0xff & ((1 << test_items[i].width) - 1)),
|
||||
I_END(),
|
||||
I_HALT()
|
||||
};
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
ulp_process_macros_and_load(0, program, &size);
|
||||
ulp_run(0);
|
||||
vTaskDelay(10/portTICK_PERIOD_MS);
|
||||
uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);
|
||||
uint32_t set = REG_READ(RTC_CNTL_STORE1_REG);
|
||||
printf("clear: %08x set: %08x\n", clear, set);
|
||||
TEST_ASSERT_EQUAL_HEX32(not_mask, clear);
|
||||
TEST_ASSERT_EQUAL_HEX32(mask, set);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
|
||||
{
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R0, 0), // R0 is LED state
|
||||
I_MOVI(R2, 16), // loop R2 from 16 down to 0
|
||||
M_LABEL(4),
|
||||
I_SUBI(R2, R2, 1),
|
||||
M_BXZ(6),
|
||||
I_ADDI(R0, R0, 1), // R0 = (R0 + 1) % 2
|
||||
I_ANDI(R0, R0, 0x1),
|
||||
M_BL(0, 1), // if R0 < 1 goto 0
|
||||
M_LABEL(1),
|
||||
I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 1), // RTC_GPIO12 = 1
|
||||
M_BX(2), // goto 2
|
||||
M_LABEL(0), // 0:
|
||||
I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 0), // RTC_GPIO12 = 0
|
||||
M_LABEL(2), // 2:
|
||||
I_MOVI(R1, 100), // loop R1 from 100 down to 0
|
||||
M_LABEL(3),
|
||||
I_SUBI(R1, R1, 1),
|
||||
M_BXZ(5),
|
||||
I_DELAY(32000), // delay for a while
|
||||
M_BX(3),
|
||||
M_LABEL(5),
|
||||
M_BX(4),
|
||||
M_LABEL(6),
|
||||
I_WAKE(), // wake up the SoC
|
||||
I_END(), // stop ULP program timer
|
||||
I_HALT()
|
||||
};
|
||||
const gpio_num_t led_gpios[] = {
|
||||
GPIO_NUM_2,
|
||||
GPIO_NUM_0,
|
||||
GPIO_NUM_4
|
||||
};
|
||||
for (size_t i = 0; i < sizeof(led_gpios)/sizeof(led_gpios[0]); ++i) {
|
||||
rtc_gpio_init(led_gpios[i]);
|
||||
rtc_gpio_set_direction(led_gpios[i], RTC_GPIO_MODE_OUTPUT_ONLY);
|
||||
rtc_gpio_set_level(led_gpios[i], 0);
|
||||
}
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
ulp_process_macros_and_load(0, program, &size);
|
||||
ulp_run(0);
|
||||
esp_sleep_enable_ulp_wakeup();
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
TEST_CASE("ulp power consumption in deep sleep", "[ulp][ignore]")
|
||||
{
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 4 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
ulp_insn_t insn = I_HALT();
|
||||
memcpy(&RTC_SLOW_MEM[0], &insn, sizeof(insn));
|
||||
|
||||
REG_WRITE(SENS_ULP_CP_SLEEP_CYC0_REG, 0x8000);
|
||||
|
||||
ulp_run(0);
|
||||
|
||||
esp_sleep_enable_ulp_wakeup();
|
||||
esp_sleep_enable_timer_wakeup(10 * 1000000);
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
TEST_CASE("ulp timer setting", "[ulp]")
|
||||
{
|
||||
/*
|
||||
* Run a simple ULP program which increments the counter, for one second.
|
||||
* Program calls I_HALT each time and gets restarted by the timer.
|
||||
* Compare the expected number of times the program runs with the actual.
|
||||
*/
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
|
||||
const int offset = 6;
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 0), // load counter
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 0), // save counter
|
||||
I_HALT(),
|
||||
};
|
||||
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size && "data offset needs to be greater or equal to program size");
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
// disable the ULP program timer — we will enable it later
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
|
||||
const uint32_t cycles_to_test[] = {0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000};
|
||||
const size_t tests_count = sizeof(cycles_to_test) / sizeof(cycles_to_test[0]);
|
||||
for (size_t i = 0; i < tests_count; ++i) {
|
||||
// zero out the counter
|
||||
RTC_SLOW_MEM[offset] = 0;
|
||||
// set the number of slow clock cycles
|
||||
REG_WRITE(SENS_ULP_CP_SLEEP_CYC0_REG, cycles_to_test[i]);
|
||||
// enable the timer and wait for a second
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
vTaskDelay(1000 / portTICK_PERIOD_MS);
|
||||
// get the counter value and stop the timer
|
||||
uint32_t counter = RTC_SLOW_MEM[offset] & 0xffff;
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
// compare the actual and expected numbers of iterations of ULP program
|
||||
float expected_period = (cycles_to_test[i] + 16) / (float) rtc_clk_slow_freq_get_hz() + 5 / 8e6f;
|
||||
float error = 1.0f - counter * expected_period;
|
||||
printf("%u\t%u\t%.01f\t%.04f\n", cycles_to_test[i], counter, 1.0f / expected_period, error);
|
||||
// Should be within 15%
|
||||
TEST_ASSERT_INT_WITHIN(15, 0, (int) error * 100);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("ulp can use TSENS in deep sleep", "[ulp][ignore]")
|
||||
{
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
|
||||
printf("\n\n");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
|
||||
// Allow TSENS to be controlled by the ULP
|
||||
SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
|
||||
|
||||
// data start offset
|
||||
size_t offset = 20;
|
||||
// number of samples to collect
|
||||
RTC_SLOW_MEM[offset] = (CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
|
||||
// sample counter
|
||||
RTC_SLOW_MEM[offset + 1] = 0;
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 1), // r2 <- counter
|
||||
I_LD(R3, R1, 0), // r3 <- length
|
||||
I_SUBI(R3, R3, 1), // end = length - 1
|
||||
I_SUBR(R3, R3, R2), // r3 = length - counter
|
||||
M_BXF(1), // if overflow goto 1:
|
||||
I_WR_REG(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_S, SENS_FORCE_XPD_SAR_S + 1, 3),
|
||||
I_TSENS(R0, 16383), // r0 <- tsens
|
||||
I_WR_REG(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_S, SENS_FORCE_XPD_SAR_S + 1, 0),
|
||||
I_ST(R0, R2, offset + 4),
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 1), // save counter
|
||||
I_HALT(), // enter sleep
|
||||
M_LABEL(1), // done with measurements
|
||||
I_END(), // stop ULP timer
|
||||
I_WAKE(), // initiate wakeup
|
||||
I_HALT()
|
||||
};
|
||||
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size);
|
||||
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
esp_sleep_enable_timer_wakeup(4000000);
|
||||
esp_sleep_enable_ulp_wakeup();
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
|
||||
TEST_CASE("can use ADC in deep sleep", "[ulp][ignore]")
|
||||
{
|
||||
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
hexdump(RTC_SLOW_MEM, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM / 4);
|
||||
printf("\n\n");
|
||||
memset(RTC_SLOW_MEM, 0, CONFIG_ESP32_ULP_COPROC_RESERVE_MEM);
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR1_BIT_WIDTH, 3, SENS_SAR1_BIT_WIDTH_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR2_BIT_WIDTH, 3, SENS_SAR2_BIT_WIDTH_S);
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_READ_CTRL_REG, SENS_SAR1_SAMPLE_BIT, 0x3, SENS_SAR1_SAMPLE_BIT_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_SAMPLE_BIT, 0x3, SENS_SAR2_SAMPLE_BIT_S);
|
||||
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_MEAS2_START_FORCE);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_MEAS1_START_FORCE);
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_AMP, 2, SENS_FORCE_XPD_AMP_S);
|
||||
|
||||
// SAR1 invert result
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DATA_INV);
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR2_DATA_INV);
|
||||
|
||||
|
||||
// const int adc = 1;
|
||||
// const int channel = 1;
|
||||
// const int atten = 3;
|
||||
// const int gpio_num = 0;
|
||||
|
||||
const int adc = 0;
|
||||
const int channel = 0;
|
||||
const int atten = 0;
|
||||
const int gpio_num = 36;
|
||||
|
||||
rtc_gpio_init(gpio_num);
|
||||
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_SAR1_EN_PAD_FORCE_M);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_SAR2_EN_PAD_FORCE_M);
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_ATTEN1_REG, 3, atten, 2 * channel); //set SAR1 attenuation
|
||||
SET_PERI_REG_BITS(SENS_SAR_ATTEN2_REG, 3, atten, 2 * channel); //set SAR2 attenuation
|
||||
|
||||
// data start offset
|
||||
size_t offset = 20;
|
||||
// number of samples to collect
|
||||
RTC_SLOW_MEM[offset] = (CONFIG_ESP32_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
|
||||
// sample counter
|
||||
RTC_SLOW_MEM[offset + 1] = 0;
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 1), // r2 <- counter
|
||||
I_LD(R3, R1, 0), // r3 <- length
|
||||
I_SUBI(R3, R3, 1), // end = length - 1
|
||||
I_SUBR(R3, R3, R2), // r3 = length - counter
|
||||
M_BXF(1), // if overflow goto 1:
|
||||
I_ADC(R0, adc, channel), // r0 <- ADC
|
||||
I_ST(R0, R2, offset + 4),
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 1), // save counter
|
||||
I_HALT(),
|
||||
M_LABEL(1), // done with measurements
|
||||
I_END(), // stop ULP program timer
|
||||
I_HALT()
|
||||
};
|
||||
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size);
|
||||
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
esp_sleep_enable_timer_wakeup(4000000);
|
||||
esp_deep_sleep_start();
|
||||
}
|
||||
@ -1,25 +0,0 @@
|
||||
#include <unistd.h>
|
||||
#include "unity.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "esp32/ulp.h"
|
||||
#include "ulp_test_app.h"
|
||||
|
||||
|
||||
extern const uint8_t ulp_test_app_bin_start[] asm("_binary_ulp_test_app_bin_start");
|
||||
extern const uint8_t ulp_test_app_bin_end[] asm("_binary_ulp_test_app_bin_end");
|
||||
|
||||
|
||||
TEST_CASE("jumps condition", "[ulp]")
|
||||
{
|
||||
esp_err_t err = ulp_load_binary(0, ulp_test_app_bin_start,
|
||||
(ulp_test_app_bin_end - ulp_test_app_bin_start) / sizeof(uint32_t));
|
||||
TEST_ESP_OK(err);
|
||||
|
||||
REG_CLR_BIT(RTC_CNTL_INT_RAW_REG, RTC_CNTL_ULP_CP_INT_RAW);
|
||||
TEST_ESP_OK(ulp_run(&ulp_test_jumps - RTC_SLOW_MEM));
|
||||
usleep(10000);
|
||||
|
||||
TEST_ASSERT_NOT_EQUAL(0, REG_GET_BIT(RTC_CNTL_INT_RAW_REG, RTC_CNTL_ULP_CP_INT_RAW));
|
||||
TEST_ASSERT_EQUAL(0, ulp_jumps_fail & UINT16_MAX);
|
||||
TEST_ASSERT_EQUAL(1, ulp_jumps_pass & UINT16_MAX);
|
||||
}
|
||||
680
components/ulp/test/ulp_fsm/test_ulp.c
Normal file
680
components/ulp/test/ulp_fsm/test_ulp.c
Normal file
@ -0,0 +1,680 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <freertos/FreeRTOS.h>
|
||||
#include <freertos/task.h>
|
||||
#include <freertos/semphr.h>
|
||||
|
||||
#include <unity.h>
|
||||
#include "esp_attr.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_sleep.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/sens_reg.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "driver/rtc_io.h"
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/ulp.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/ulp.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/ulp.h"
|
||||
#endif
|
||||
|
||||
#include "ulp_test_app.h"
|
||||
|
||||
extern const uint8_t ulp_test_app_bin_start[] asm("_binary_ulp_test_app_bin_start");
|
||||
extern const uint8_t ulp_test_app_bin_end[] asm("_binary_ulp_test_app_bin_end");
|
||||
|
||||
#define HEX_DUMP_DEBUG 0
|
||||
|
||||
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#define COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#define COPROC_RESERVE_MEM CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#define COPROC_RESERVE_MEM CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
|
||||
#endif
|
||||
|
||||
static void hexdump(const uint32_t* src, size_t count) {
|
||||
#if HEX_DUMP_DEBUG
|
||||
for (size_t i = 0; i < count; ++i) {
|
||||
printf("%08x ", *src);
|
||||
++src;
|
||||
if ((i + 1) % 4 == 0) {
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
(void)src;
|
||||
(void)count;
|
||||
#endif
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM addition test", "[ulp]")
|
||||
{
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/* ULP co-processor program to add data in 2 memory locations using ULP macros */
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R3, 16), // r3 = 16
|
||||
I_LD(R0, R3, 0), // r0 = mem[r3 + 0]
|
||||
I_LD(R1, R3, 1), // r1 = mem[r3 + 1]
|
||||
I_ADDR(R2, R0, R1), // r2 = r0 + r1
|
||||
I_ST(R2, R3, 2), // mem[r3 + 2] = r2
|
||||
I_HALT() // halt
|
||||
};
|
||||
|
||||
/* Load the memory regions used by the ULP co-processor */
|
||||
RTC_SLOW_MEM[16] = 10;
|
||||
RTC_SLOW_MEM[17] = 11;
|
||||
|
||||
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
|
||||
|
||||
/* Wait for the ULP co-processor to finish up */
|
||||
esp_rom_delay_us(1000);
|
||||
hexdump(RTC_SLOW_MEM, 20);
|
||||
|
||||
/* Verify the test results */
|
||||
TEST_ASSERT_EQUAL(10 + 11, RTC_SLOW_MEM[18] & 0xffff);
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM subtraction and branch test", "[ulp]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/* ULP co-processor program to perform subtractions and branch to a label */
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R0, 34), // r0 = 34
|
||||
M_LABEL(1), // define a label with label number as 1
|
||||
I_MOVI(R1, 32), // r1 = 32
|
||||
I_LD(R1, R1, 0), // r1 = mem[32 + 0]
|
||||
I_MOVI(R2, 33), // r2 = 33
|
||||
I_LD(R2, R2, 0), // r2 = mem[33 + 0]
|
||||
I_SUBR(R3, R1, R2), // r3 = r1 - r2
|
||||
I_ST(R3, R0, 0), // mem[r0 + 0] = r3
|
||||
I_ADDI(R0, R0, 1), // r0 = r0 + 1
|
||||
M_BL(1, 64), // branch to label 1 if r0 < 64
|
||||
I_HALT(), // halt
|
||||
};
|
||||
|
||||
/* Load the memory regions used by the ULP co-processor */
|
||||
RTC_SLOW_MEM[32] = 42;
|
||||
RTC_SLOW_MEM[33] = 18;
|
||||
|
||||
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
|
||||
printf("\n\n");
|
||||
|
||||
/* Wait for the ULP co-processor to finish up */
|
||||
esp_rom_delay_us(1000);
|
||||
hexdump(RTC_SLOW_MEM, 50);
|
||||
|
||||
/* Verify the test results */
|
||||
for (int i = 34; i < 64; ++i) {
|
||||
TEST_ASSERT_EQUAL(42 - 18, RTC_SLOW_MEM[i] & 0xffff);
|
||||
}
|
||||
TEST_ASSERT_EQUAL(0, RTC_SLOW_MEM[64]);
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM JUMPS instruction test", "[ulp]")
|
||||
{
|
||||
/*
|
||||
* Load the ULP binary.
|
||||
*
|
||||
* This ULP program is written in assembly. Please refer associated .S file.
|
||||
*/
|
||||
esp_err_t err = ulp_load_binary(0, ulp_test_app_bin_start,
|
||||
(ulp_test_app_bin_end - ulp_test_app_bin_start) / sizeof(uint32_t));
|
||||
TEST_ESP_OK(err);
|
||||
|
||||
/* Clear ULP FSM raw interrupt */
|
||||
REG_CLR_BIT(RTC_CNTL_INT_RAW_REG, RTC_CNTL_ULP_CP_INT_RAW);
|
||||
|
||||
/* Run the ULP coprocessor */
|
||||
TEST_ESP_OK(ulp_run(&ulp_test_jumps - RTC_SLOW_MEM));
|
||||
|
||||
/* Wait for the ULP co-processor to finish up */
|
||||
esp_rom_delay_us(1000);
|
||||
|
||||
/* Verify that ULP FSM issued an interrupt to wake up the main CPU */
|
||||
TEST_ASSERT_NOT_EQUAL(0, REG_GET_BIT(RTC_CNTL_INT_RAW_REG, RTC_CNTL_ULP_CP_INT_RAW));
|
||||
|
||||
/* Verify the test results */
|
||||
TEST_ASSERT_EQUAL(0, ulp_jumps_fail & UINT16_MAX);
|
||||
TEST_ASSERT_EQUAL(1, ulp_jumps_pass & UINT16_MAX);
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM light-sleep wakeup test", "[ulp]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/* ULP co-processor program to perform some activities and wakeup the main CPU from deep-sleep */
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, 1024), // r1 = 1024
|
||||
M_LABEL(1), // define label 1
|
||||
I_DELAY(32000), // add a delay (NOP for 32000 cycles)
|
||||
I_SUBI(R1, R1, 1), // r1 = r1 - 1
|
||||
M_BXZ(3), // branch to label 3 if ALU value is 0. (r1 = 0)
|
||||
I_RSHI(R3, R1, 5), // r3 = r1 / 32
|
||||
I_ST(R1, R3, 16), // mem[r3 + 16] = r1
|
||||
M_BX(1), // loop to label 1
|
||||
M_LABEL(3), // define label 3
|
||||
I_MOVI(R2, 42), // r2 = 42
|
||||
I_MOVI(R3, 15), // r3 = 15
|
||||
I_ST(R2, R3, 0), // mem[r3 + 0] = r2
|
||||
I_WAKE(), // wake the SoC from deep-sleep
|
||||
I_END(), // stop ULP timer
|
||||
I_HALT() // halt
|
||||
};
|
||||
|
||||
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
|
||||
/* Enter Light Sleep */
|
||||
TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
|
||||
|
||||
/* Wait for wakeup from ULP FSM Coprocessor */
|
||||
printf("cause %d\r\n", esp_sleep_get_wakeup_cause());
|
||||
TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM deep-sleep wakeup test", "[ulp][reset=SW_CPU_RESET][ignore]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clearout the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/* ULP co-processor program to perform some activities and wakeup the main CPU from deep-sleep */
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, 1024), // r1 = 1024
|
||||
M_LABEL(1), // define label 1
|
||||
I_DELAY(32000), // add a delay (NOP for 32000 cycles)
|
||||
I_SUBI(R1, R1, 1), // r1 = r1 - 1
|
||||
M_BXZ(3), // branch to label 3 if ALU value is 0. (r1 = 0)
|
||||
I_RSHI(R3, R1, 5), // r3 = r1 / 32
|
||||
I_ST(R1, R3, 16), // mem[r3 + 16] = r1
|
||||
M_BX(1), // loop to label 1
|
||||
M_LABEL(3), // define label 3
|
||||
I_MOVI(R2, 42), // r2 = 42
|
||||
I_MOVI(R3, 15), // r3 = 15
|
||||
I_ST(R2, R3, 0), // mem[r3 + 0] = r2
|
||||
I_WAKE(), // wake the SoC from deep-sleep
|
||||
I_END(), // stop ULP timer
|
||||
I_HALT() // halt
|
||||
};
|
||||
|
||||
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
|
||||
/* Enter Deep Sleep */
|
||||
esp_deep_sleep_start();
|
||||
UNITY_TEST_FAIL(__LINE__, "Should not get here!");
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clear ULP timer */
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/* ULP co-processor program to read from and write to peripheral registers */
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, 64), // r1 = 64
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 0, 15), // r0 = REG_READ(RTC_CNTL_STORE1_REG[15:0])
|
||||
I_ST(R0, R1, 0), // mem[r1 + 0] = r0
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 4, 11), // r0 = REG_READ(RTC_CNTL_STORE1_REG[11:4])
|
||||
I_ST(R0, R1, 1), // mem[r1 + 1] = r0
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 16, 31), // r0 = REG_READ(RTC_CNTL_STORE1_REG[31:16])
|
||||
I_ST(R0, R1, 2), // mem[r1 + 2] = r0
|
||||
I_RD_REG(RTC_CNTL_STORE1_REG, 20, 27), // r0 = REG_READ(RTC_CNTL_STORE1_REG[27:20])
|
||||
I_ST(R0, R1, 3), // mem[r1 + 3] = r0
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89), // REG_WRITE(RTC_CNTL_STORE0_REG[7:0], 0x89)
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab), // REG_WRITE(RTC_CNTL_STORE0_REG[15:8], 0xab)
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd), // REG_WRITE(RTC_CNTL_STORE0_REG[23:16], 0xcd)
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef), // REG_WRITE(RTC_CNTL_STORE0_REG[31:24], 0xef)
|
||||
I_LD(R0, R1, 4), // r0 = mem[r1 + 4]
|
||||
I_ADDI(R0, R0, 1), // r0 = r0 + 1
|
||||
I_ST(R0, R1, 4), // mem[r1 + 4] = r0
|
||||
I_END(), // stop ULP timer
|
||||
I_HALT() // halt
|
||||
};
|
||||
|
||||
/* Set data in the peripheral register to be read by the ULP co-processor */
|
||||
REG_WRITE(RTC_CNTL_STORE1_REG, 0x89abcdef);
|
||||
|
||||
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
|
||||
/* Wait for the ULP co-processor to finish up */
|
||||
vTaskDelay(100/portTICK_PERIOD_MS);
|
||||
|
||||
/* Verify the test results */
|
||||
TEST_ASSERT_EQUAL_HEX32(0xefcdab89, REG_READ(RTC_CNTL_STORE0_REG));
|
||||
TEST_ASSERT_EQUAL_HEX16(0xcdef, RTC_SLOW_MEM[64] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0xde, RTC_SLOW_MEM[65] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0x89ab, RTC_SLOW_MEM[66] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(0x9a, RTC_SLOW_MEM[67] & 0xffff);
|
||||
TEST_ASSERT_EQUAL_HEX16(1, RTC_SLOW_MEM[68] & 0xffff);
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/* Define the test set */
|
||||
typedef struct {
|
||||
int low;
|
||||
int width;
|
||||
} wr_reg_test_item_t;
|
||||
|
||||
const wr_reg_test_item_t test_items[] = {
|
||||
{0, 1}, {0, 2}, {0, 3}, {0, 4}, {0, 5}, {0, 6}, {0, 7}, {0, 8},
|
||||
{3, 1}, {3, 2}, {3, 3}, {3, 4}, {3, 5}, {3, 6}, {3, 7}, {3, 8},
|
||||
{15, 1}, {15, 2}, {15, 3}, {15, 4}, {15, 5}, {15, 6}, {15, 7}, {15, 8},
|
||||
{16, 1}, {16, 2}, {16, 3}, {16, 4}, {16, 5}, {16, 6}, {16, 7}, {16, 8},
|
||||
{18, 1}, {18, 2}, {18, 3}, {18, 4}, {18, 5}, {18, 6}, {18, 7}, {18, 8},
|
||||
{24, 1}, {24, 2}, {24, 3}, {24, 4}, {24, 5}, {24, 6}, {24, 7}, {24, 8},
|
||||
};
|
||||
|
||||
const size_t test_items_count =
|
||||
sizeof(test_items)/sizeof(test_items[0]);
|
||||
for (size_t i = 0; i < test_items_count; ++i) {
|
||||
const uint32_t mask = (uint32_t) (((1ULL << test_items[i].width) - 1) << test_items[i].low);
|
||||
const uint32_t not_mask = ~mask;
|
||||
printf("#%2d: low: %2d width: %2d mask: %08x expected: %08x ", i,
|
||||
test_items[i].low, test_items[i].width,
|
||||
mask, not_mask);
|
||||
|
||||
/* Set all bits in RTC_CNTL_STORE0_REG and reset all bits in RTC_CNTL_STORE1_REG */
|
||||
REG_WRITE(RTC_CNTL_STORE0_REG, 0xffffffff);
|
||||
REG_WRITE(RTC_CNTL_STORE1_REG, 0x00000000);
|
||||
|
||||
/* ULP co-processor program to write to peripheral registers */
|
||||
const ulp_insn_t program[] = {
|
||||
I_WR_REG(RTC_CNTL_STORE0_REG,
|
||||
test_items[i].low,
|
||||
test_items[i].low + test_items[i].width - 1,
|
||||
0),
|
||||
I_WR_REG(RTC_CNTL_STORE1_REG,
|
||||
test_items[i].low,
|
||||
test_items[i].low + test_items[i].width - 1,
|
||||
0xff & ((1 << test_items[i].width) - 1)),
|
||||
I_END(),
|
||||
I_HALT()
|
||||
};
|
||||
|
||||
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
|
||||
/* Wait for the ULP co-processor to finish up */
|
||||
vTaskDelay(10/portTICK_PERIOD_MS);
|
||||
|
||||
/* Verify the test results */
|
||||
uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);
|
||||
uint32_t set = REG_READ(RTC_CNTL_STORE1_REG);
|
||||
printf("clear: %08x set: %08x\n", clear, set);
|
||||
TEST_ASSERT_EQUAL_HEX32(not_mask, clear);
|
||||
TEST_ASSERT_EQUAL_HEX32(mask, set);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM controls RTC_IO", "[ulp][ignore]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/* ULP co-processor program to toggle LED */
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R0, 0), // r0 is LED state
|
||||
I_MOVI(R2, 16), // loop r2 from 16 down to 0
|
||||
M_LABEL(4), // define label 4
|
||||
I_SUBI(R2, R2, 1), // r2 = r2 - 1
|
||||
M_BXZ(6), // branch to label 6 if r2 = 0
|
||||
I_ADDI(R0, R0, 1), // r0 = (r0 + 1) % 2
|
||||
I_ANDI(R0, R0, 0x1),
|
||||
M_BL(0, 1), // if r0 < 1 goto 0
|
||||
M_LABEL(1), // define label 1
|
||||
I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 1), // RTC_GPIO12 = 1
|
||||
M_BX(2), // goto 2
|
||||
M_LABEL(0), // define label 0
|
||||
I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 0), // RTC_GPIO12 = 0
|
||||
M_LABEL(2), // define label 2
|
||||
I_MOVI(R1, 100), // loop R1 from 100 down to 0
|
||||
M_LABEL(3), // define label 3
|
||||
I_SUBI(R1, R1, 1), // r1 = r1 - 1
|
||||
M_BXZ(5), // branch to label 5 if r1 = 0
|
||||
I_DELAY(32000), // delay for a while
|
||||
M_BX(3), // goto 3
|
||||
M_LABEL(5), // define label 5
|
||||
M_BX(4), // loop back to label 4
|
||||
M_LABEL(6), // define label 6
|
||||
I_WAKE(), // wake up the SoC
|
||||
I_END(), // stop ULP program timer
|
||||
I_HALT()
|
||||
};
|
||||
|
||||
/* Configure LED GPIOs */
|
||||
const gpio_num_t led_gpios[] = {
|
||||
GPIO_NUM_2,
|
||||
GPIO_NUM_0,
|
||||
GPIO_NUM_4
|
||||
};
|
||||
for (size_t i = 0; i < sizeof(led_gpios)/sizeof(led_gpios[0]); ++i) {
|
||||
rtc_gpio_init(led_gpios[i]);
|
||||
rtc_gpio_set_direction(led_gpios[i], RTC_GPIO_MODE_OUTPUT_ONLY);
|
||||
rtc_gpio_set_level(led_gpios[i], 0);
|
||||
}
|
||||
|
||||
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
|
||||
/* Enter Deep Sleep */
|
||||
esp_deep_sleep_start();
|
||||
UNITY_TEST_FAIL(__LINE__, "Should not get here!");
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM power consumption in deep sleep", "[ulp][ignore]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 4 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/* Put the ULP coprocessor in halt state */
|
||||
ulp_insn_t insn = I_HALT();
|
||||
memcpy(&RTC_SLOW_MEM[0], &insn, sizeof(insn));
|
||||
|
||||
/* Set ULP timer */
|
||||
ulp_set_wakeup_period(0, 0x8000);
|
||||
|
||||
/* Run the ULP coprocessor */
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
TEST_ASSERT(esp_sleep_enable_timer_wakeup(10 * 1000000) == ESP_OK);
|
||||
|
||||
/* Enter Deep Sleep */
|
||||
esp_deep_sleep_start();
|
||||
UNITY_TEST_FAIL(__LINE__, "Should not get here!");
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM timer setting", "[ulp]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
/*
|
||||
* Run a simple ULP program which increments the counter, for one second.
|
||||
* Program calls I_HALT each time and gets restarted by the timer.
|
||||
* Compare the expected number of times the program runs with the actual.
|
||||
*/
|
||||
const int offset = 6;
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 0), // load counter
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 0), // save counter
|
||||
I_HALT(),
|
||||
};
|
||||
|
||||
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size && "data offset needs to be greater or equal to program size");
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
|
||||
/* Disable the ULP program timer — we will enable it later */
|
||||
ulp_timer_stop();
|
||||
|
||||
/* Define the test data */
|
||||
const uint32_t cycles_to_test[] = { 10000, // 10 ms
|
||||
20000, // 20 ms
|
||||
50000, // 50 ms
|
||||
100000, // 100 ms
|
||||
200000, // 200 ms
|
||||
500000, // 500 ms
|
||||
1000000 }; // 1 sec
|
||||
const size_t tests_count = sizeof(cycles_to_test) / sizeof(cycles_to_test[0]);
|
||||
|
||||
for (size_t i = 0; i < tests_count; ++i) {
|
||||
// zero out the counter
|
||||
RTC_SLOW_MEM[offset] = 0;
|
||||
// set the ulp timer period
|
||||
ulp_set_wakeup_period(0, cycles_to_test[i]);
|
||||
// enable the timer and wait for a second
|
||||
ulp_timer_resume();
|
||||
vTaskDelay(1000 / portTICK_PERIOD_MS);
|
||||
// stop the timer and get the counter value
|
||||
ulp_timer_stop();
|
||||
uint32_t counter = RTC_SLOW_MEM[offset] & 0xffff;
|
||||
// calculate the expected counter value and allow a tolerance of 15%
|
||||
uint32_t expected_counter = 1000000 / cycles_to_test[i];
|
||||
uint32_t tolerance = (expected_counter * 15 / 100);
|
||||
tolerance = tolerance ? tolerance : 1; // Keep a tolerance of at least 1 count
|
||||
printf("expected: %u\t tolerance: +/- %u\t actual: %u\n", expected_counter, tolerance, counter);
|
||||
// Should be within 15%
|
||||
TEST_ASSERT_INT_WITHIN(tolerance, expected_counter, counter);
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM can use temperature sensor (TSENS) in deep sleep", "[ulp][ignore]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
// Allow TSENS to be controlled by the ULP
|
||||
SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, SENS_FORCE_XPD_SAR_FSM, SENS_FORCE_XPD_SAR_S);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, SENS_FORCE_XPD_SAR_FSM, SENS_FORCE_XPD_SAR_S);
|
||||
SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL2_REG, SENS_TSENS_CLKGATE_EN);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_TSENS_CLK_EN);
|
||||
#endif
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
|
||||
|
||||
// data start offset
|
||||
size_t offset = 20;
|
||||
// number of samples to collect
|
||||
RTC_SLOW_MEM[offset] = (COPROC_RESERVE_MEM) / 4 - offset - 8;
|
||||
// sample counter
|
||||
RTC_SLOW_MEM[offset + 1] = 0;
|
||||
|
||||
/* ULP co-processor program to record temperature sensor readings */
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 1), // r2 <- counter
|
||||
I_LD(R3, R1, 0), // r3 <- length
|
||||
I_SUBI(R3, R3, 1), // end = length - 1
|
||||
I_SUBR(R3, R3, R2), // r3 = length - counter
|
||||
M_BXF(1), // if overflow goto 1:
|
||||
I_TSENS(R0, 16383), // r0 <- tsens
|
||||
I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] <- r0
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 1), // save counter
|
||||
I_HALT(), // enter sleep
|
||||
M_LABEL(1), // done with measurements
|
||||
I_END(), // stop ULP timer
|
||||
I_WAKE(), // initiate wakeup
|
||||
I_HALT()
|
||||
};
|
||||
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size);
|
||||
|
||||
/* Run the ULP coprocessor */
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
TEST_ASSERT(esp_sleep_enable_timer_wakeup(10 * 1000000) == ESP_OK);
|
||||
|
||||
/* Enter Deep Sleep */
|
||||
esp_deep_sleep_start();
|
||||
UNITY_TEST_FAIL(__LINE__, "Should not get here!");
|
||||
}
|
||||
|
||||
TEST_CASE("ULP FSM can use ADC in deep sleep", "[ulp][ignore]")
|
||||
{
|
||||
assert(COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
|
||||
|
||||
const int adc = 0;
|
||||
const int channel = 0;
|
||||
const int atten = 0;
|
||||
|
||||
/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
|
||||
memset(RTC_SLOW_MEM, 0, COPROC_RESERVE_MEM);
|
||||
|
||||
#if defined(CONFIG_IDF_TARGET_ESP32)
|
||||
// Configure SAR ADCn resolution
|
||||
SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR1_BIT_WIDTH, 3, SENS_SAR1_BIT_WIDTH_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR2_BIT_WIDTH, 3, SENS_SAR2_BIT_WIDTH_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_READ_CTRL_REG, SENS_SAR1_SAMPLE_BIT, 0x3, SENS_SAR1_SAMPLE_BIT_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_SAMPLE_BIT, 0x3, SENS_SAR2_SAMPLE_BIT_S);
|
||||
|
||||
// SAR ADCn is started by ULP FSM
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_MEAS2_START_FORCE);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_MEAS1_START_FORCE);
|
||||
|
||||
// Use ULP FSM to power up SAR ADCn
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_AMP, 2, SENS_FORCE_XPD_AMP_S);
|
||||
|
||||
// SAR ADCn invert result
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DATA_INV);
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR2_DATA_INV);
|
||||
|
||||
// Set SAR ADCn pad enable bitmap to be controlled by ULP FSM
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_SAR1_EN_PAD_FORCE_M);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_SAR2_EN_PAD_FORCE_M);
|
||||
#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
|
||||
// SAR ADCn is started by ULP FSM
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL2_REG, SENS_MEAS2_START_FORCE);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_CTRL2_REG, SENS_MEAS1_START_FORCE);
|
||||
|
||||
// Use ULP FSM to power up/down SAR ADCn
|
||||
SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS1_CTRL1_REG, SENS_FORCE_XPD_AMP, 2, SENS_FORCE_XPD_AMP_S);
|
||||
|
||||
// SAR1 invert result
|
||||
SET_PERI_REG_MASK(SENS_SAR_READER1_CTRL_REG, SENS_SAR1_DATA_INV);
|
||||
SET_PERI_REG_MASK(SENS_SAR_READER2_CTRL_REG, SENS_SAR2_DATA_INV);
|
||||
|
||||
// Set SAR ADCn pad enable bitmap to be controlled by ULP FSM
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_CTRL2_REG, SENS_SAR1_EN_PAD_FORCE_M);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL2_REG, SENS_SAR2_EN_PAD_FORCE_M);
|
||||
|
||||
// Enable SAR ADCn clock gate on esp32s3
|
||||
#if CONFIG_IDF_TARGET_ESP32S3
|
||||
SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_SARADC_CLK_EN);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
SET_PERI_REG_BITS(SENS_SAR_ATTEN1_REG, 3, atten, 2 * channel); //set SAR1 attenuation
|
||||
SET_PERI_REG_BITS(SENS_SAR_ATTEN2_REG, 3, atten, 2 * channel); //set SAR2 attenuation
|
||||
|
||||
// data start offset
|
||||
size_t offset = 20;
|
||||
// number of samples to collect
|
||||
RTC_SLOW_MEM[offset] = (COPROC_RESERVE_MEM) / 4 - offset - 8;
|
||||
// sample counter
|
||||
RTC_SLOW_MEM[offset + 1] = 0;
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R1, offset), // r1 <- offset
|
||||
I_LD(R2, R1, 1), // r2 <- counter
|
||||
I_LD(R3, R1, 0), // r3 <- length
|
||||
I_SUBI(R3, R3, 1), // end = length - 1
|
||||
I_SUBR(R3, R3, R2), // r3 = length - counter
|
||||
M_BXF(1), // if overflow goto 1:
|
||||
I_ADC(R0, adc, channel), // r0 <- ADC
|
||||
I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] = r0
|
||||
I_ADDI(R2, R2, 1), // counter += 1
|
||||
I_ST(R2, R1, 1), // save counter
|
||||
I_HALT(), // enter sleep
|
||||
M_LABEL(1), // done with measurements
|
||||
I_END(), // stop ULP program timer
|
||||
I_HALT()
|
||||
};
|
||||
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
|
||||
assert(offset >= size);
|
||||
|
||||
/* Run the ULP coprocessor */
|
||||
TEST_ESP_OK(ulp_run(0));
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
TEST_ASSERT(esp_sleep_enable_timer_wakeup(10 * 1000000) == ESP_OK);
|
||||
|
||||
/* Enter Deep Sleep */
|
||||
esp_deep_sleep_start();
|
||||
UNITY_TEST_FAIL(__LINE__, "Should not get here!");
|
||||
}
|
||||
@ -1,3 +1,8 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "soc/soc_ulp.h"
|
||||
@ -1,70 +0,0 @@
|
||||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "ulp_riscv/ulp_riscv.h"
|
||||
#include "ulp_riscv/ulp_riscv_utils.h"
|
||||
|
||||
typedef enum{
|
||||
RISCV_READ_WRITE_TEST = 1,
|
||||
RISCV_DEEP_SLEEP_WAKEUP_TEST,
|
||||
RISCV_LIGHT_SLEEP_WAKEUP_TEST,
|
||||
RISCV_NO_COMMAND,
|
||||
} riscv_test_commands_t;
|
||||
|
||||
typedef enum {
|
||||
RISCV_COMMAND_OK = 1,
|
||||
RISCV_COMMAND_NOK,
|
||||
RISCV_COMMAND_INVALID,
|
||||
} riscv_test_command_reply_t;
|
||||
|
||||
#define XOR_MASK 0xDEADBEEF
|
||||
|
||||
volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND;
|
||||
volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID;
|
||||
volatile uint32_t riscv_test_data_in = 0;
|
||||
volatile uint32_t riscv_test_data_out = 0;
|
||||
|
||||
void handle_commands(riscv_test_commands_t cmd)
|
||||
{
|
||||
switch (cmd) {
|
||||
case RISCV_READ_WRITE_TEST:
|
||||
riscv_test_data_out =riscv_test_data_in ^ XOR_MASK;
|
||||
main_cpu_reply = RISCV_COMMAND_OK;
|
||||
break;
|
||||
|
||||
case RISCV_DEEP_SLEEP_WAKEUP_TEST:
|
||||
case RISCV_LIGHT_SLEEP_WAKEUP_TEST:
|
||||
main_cpu_reply = RISCV_COMMAND_OK;
|
||||
break;
|
||||
|
||||
default:
|
||||
main_cpu_reply = RISCV_COMMAND_NOK;
|
||||
break;
|
||||
}
|
||||
ulp_riscv_wakeup_main_processor();
|
||||
}
|
||||
|
||||
int main (void)
|
||||
{
|
||||
while (1) {
|
||||
handle_commands(main_cpu_command);
|
||||
break;
|
||||
}
|
||||
|
||||
/* ulp_riscv_shutdown() is called automatically when main exits */
|
||||
return 0;
|
||||
}
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
@ -18,10 +10,16 @@
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/sens_reg.h"
|
||||
#include "soc/rtc_periph.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/ulp.h"
|
||||
#include "esp32s2/ulp_riscv.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/ulp.h"
|
||||
#include "esp32s3/ulp_riscv.h"
|
||||
#endif
|
||||
#include "ulp_test_app.h"
|
||||
#include "unity.h"
|
||||
#include <sys/time.h>
|
||||
|
||||
typedef enum{
|
||||
RISCV_READ_WRITE_TEST = 1,
|
||||
@ -33,9 +31,11 @@ typedef enum{
|
||||
typedef enum {
|
||||
RISCV_COMMAND_OK = 1,
|
||||
RISCV_COMMAND_NOK,
|
||||
RISCV_COMMAND_INVALID,
|
||||
} riscv_test_command_reply_t;
|
||||
|
||||
#define XOR_MASK 0xDEADBEEF
|
||||
#define ULP_WAKEUP_PERIOD 1000000 // 1 second
|
||||
|
||||
extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_test_app_bin_start");
|
||||
extern const uint8_t ulp_main_bin_end[] asm("_binary_ulp_test_app_bin_end");
|
||||
@ -47,7 +47,7 @@ static void load_and_start_ulp_firmware(void)
|
||||
TEST_ASSERT(ulp_riscv_load_binary(ulp_main_bin_start,
|
||||
(ulp_main_bin_end - ulp_main_bin_start)) == ESP_OK);
|
||||
|
||||
TEST_ASSERT(ulp_set_wakeup_period(0, 1000000) == ESP_OK);
|
||||
TEST_ASSERT(ulp_set_wakeup_period(0, ULP_WAKEUP_PERIOD) == ESP_OK);
|
||||
TEST_ASSERT(ulp_riscv_run() == ESP_OK);
|
||||
|
||||
firmware_loaded = true;
|
||||
@ -57,37 +57,87 @@ static void load_and_start_ulp_firmware(void)
|
||||
TEST_CASE("ULP-RISC-V and main CPU are able to exchange data", "[ulp][ignore]")
|
||||
{
|
||||
const uint32_t test_data = 0x12345678;
|
||||
struct timeval start, end;
|
||||
|
||||
/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
|
||||
load_and_start_ulp_firmware();
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
|
||||
/* Setup test data */
|
||||
ulp_riscv_test_data_in = test_data ^ XOR_MASK;
|
||||
ulp_main_cpu_command = RISCV_READ_WRITE_TEST;
|
||||
|
||||
/* Enter Light Sleep */
|
||||
TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
|
||||
TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
|
||||
TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
|
||||
|
||||
/* Wait for wakeup from ULP RISC-V Coprocessor */
|
||||
TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
|
||||
|
||||
/* Wait till we receive the correct command response */
|
||||
gettimeofday(&start, NULL);
|
||||
while (ulp_command_resp != RISCV_READ_WRITE_TEST)
|
||||
;
|
||||
gettimeofday(&end, NULL);
|
||||
printf("Response time %ld ms\n", (end.tv_sec - start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000);
|
||||
|
||||
/* Verify test data */
|
||||
TEST_ASSERT(ulp_command_resp == RISCV_READ_WRITE_TEST);
|
||||
TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
|
||||
printf("data out: 0x%X, expected: 0x%X \n", ulp_riscv_test_data_out, test_data);
|
||||
TEST_ASSERT(test_data == ulp_riscv_test_data_out);
|
||||
|
||||
/* Clear test data */
|
||||
ulp_main_cpu_command = RISCV_NO_COMMAND;
|
||||
}
|
||||
|
||||
TEST_CASE("ULP-RISC-V is able to wakeup main CPU from light sleep", "[ulp][ignore]")
|
||||
{
|
||||
struct timeval start, end;
|
||||
|
||||
/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
|
||||
load_and_start_ulp_firmware();
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
|
||||
/* Setup test data */
|
||||
ulp_main_cpu_command = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
|
||||
|
||||
/* Enter Light Sleep */
|
||||
TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
|
||||
|
||||
/* Wait for wakeup from ULP RISC-V Coprocessor */
|
||||
TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
|
||||
|
||||
/* Wait till we receive the correct command response */
|
||||
gettimeofday(&start, NULL);
|
||||
while (ulp_command_resp != RISCV_LIGHT_SLEEP_WAKEUP_TEST)
|
||||
;
|
||||
gettimeofday(&end, NULL);
|
||||
printf("Response time %ld ms\n", (end.tv_sec - start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000);
|
||||
|
||||
/* Verify test data */
|
||||
TEST_ASSERT(ulp_command_resp == RISCV_LIGHT_SLEEP_WAKEUP_TEST);
|
||||
TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
|
||||
|
||||
/* Clear test data */
|
||||
ulp_main_cpu_command = RISCV_NO_COMMAND;
|
||||
}
|
||||
|
||||
TEST_CASE("ULP-RISC-V is able to wakeup main CPU from deep sleep", "[ulp][reset=SW_CPU_RESET][ignore]")
|
||||
{
|
||||
/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
|
||||
load_and_start_ulp_firmware();
|
||||
|
||||
/* Setup wakeup triggers */
|
||||
TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
|
||||
|
||||
/* Setup test data */
|
||||
ulp_main_cpu_command = RISCV_DEEP_SLEEP_WAKEUP_TEST;
|
||||
|
||||
/* Enter Deep Sleep */
|
||||
esp_deep_sleep_start();
|
||||
UNITY_TEST_FAIL(__LINE__, "Should not get here!");
|
||||
}
|
||||
92
components/ulp/test/ulp_riscv/ulp/test_main.c
Normal file
92
components/ulp/test/ulp_riscv/ulp/test_main.c
Normal file
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "ulp_riscv/ulp_riscv.h"
|
||||
#include "ulp_riscv/ulp_riscv_utils.h"
|
||||
|
||||
typedef enum{
|
||||
RISCV_READ_WRITE_TEST = 1,
|
||||
RISCV_DEEP_SLEEP_WAKEUP_TEST,
|
||||
RISCV_LIGHT_SLEEP_WAKEUP_TEST,
|
||||
RISCV_NO_COMMAND,
|
||||
} riscv_test_commands_t;
|
||||
|
||||
typedef enum {
|
||||
RISCV_COMMAND_OK = 1,
|
||||
RISCV_COMMAND_NOK,
|
||||
RISCV_COMMAND_INVALID,
|
||||
} riscv_test_command_reply_t;
|
||||
|
||||
#define XOR_MASK 0xDEADBEEF
|
||||
|
||||
volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND;
|
||||
volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID;
|
||||
volatile riscv_test_commands_t command_resp = RISCV_NO_COMMAND;
|
||||
volatile uint32_t riscv_test_data_in = 0;
|
||||
volatile uint32_t riscv_test_data_out = 0;
|
||||
|
||||
void handle_commands(riscv_test_commands_t cmd)
|
||||
{
|
||||
switch (cmd) {
|
||||
case RISCV_READ_WRITE_TEST:
|
||||
/* Echo the command ID back to the main CPU */
|
||||
command_resp = RISCV_READ_WRITE_TEST;
|
||||
|
||||
/* Process test data */
|
||||
riscv_test_data_out = riscv_test_data_in ^ XOR_MASK;
|
||||
|
||||
/* Set the command reply status */
|
||||
main_cpu_reply = RISCV_COMMAND_OK;
|
||||
|
||||
/* Wakeup the main CPU */
|
||||
ulp_riscv_wakeup_main_processor();
|
||||
break;
|
||||
|
||||
case RISCV_DEEP_SLEEP_WAKEUP_TEST:
|
||||
/* Echo the command ID back to the main CPU */
|
||||
command_resp = RISCV_DEEP_SLEEP_WAKEUP_TEST;
|
||||
|
||||
/* Set the command reply status */
|
||||
main_cpu_reply = RISCV_COMMAND_OK;
|
||||
|
||||
/* Wakeup the main CPU */
|
||||
ulp_riscv_wakeup_main_processor();
|
||||
break;
|
||||
|
||||
case RISCV_LIGHT_SLEEP_WAKEUP_TEST:
|
||||
/* Echo the command ID back to the main CPU */
|
||||
command_resp = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
|
||||
|
||||
/* Set the command reply status */
|
||||
main_cpu_reply = RISCV_COMMAND_OK;
|
||||
|
||||
/* Wakeup the main CPU */
|
||||
ulp_riscv_wakeup_main_processor();
|
||||
break;
|
||||
|
||||
case RISCV_NO_COMMAND:
|
||||
main_cpu_reply = RISCV_COMMAND_OK;
|
||||
break;
|
||||
|
||||
default:
|
||||
main_cpu_reply = RISCV_COMMAND_NOK;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int main (void)
|
||||
{
|
||||
while (1) {
|
||||
handle_commands(main_cpu_command);
|
||||
break;
|
||||
}
|
||||
|
||||
/* ulp_riscv_shutdown() is called automatically when main exits */
|
||||
return 0;
|
||||
}
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
@ -69,7 +61,13 @@ esp_err_t ulp_run(uint32_t entry_point)
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M);
|
||||
// enable ULP timer
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
#else
|
||||
|
||||
/* Reset COCPU when power on. */
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_RESET);
|
||||
esp_rom_delay_us(20);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_RESET);
|
||||
|
||||
// disable ULP timer
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
// wait for at least 1 RTC_SLOW_CLK cycle
|
||||
@ -81,8 +79,10 @@ esp_err_t ulp_run(uint32_t entry_point)
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG ,RTC_CNTL_ULP_CP_CLK_FO);
|
||||
// ULP FSM sends the DONE signal.
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
|
||||
/* Set the number of cycles of ULP_TIMER sleep, the wait time required to start ULP */
|
||||
REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE, 100);
|
||||
#if CONFIG_IDF_TARGET_ESP32S3
|
||||
/* Set the CLKGATE_EN signal on esp32s3 */
|
||||
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLKGATE_EN);
|
||||
#endif
|
||||
/* Clear interrupt COCPU status */
|
||||
REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR | RTC_CNTL_COCPU_TRAP_INT_CLR | RTC_CNTL_ULP_CP_INT_CLR);
|
||||
// 1: start with timer. wait ULP_TIMER cnt timer.
|
||||
@ -154,7 +154,7 @@ esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us)
|
||||
}
|
||||
REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t),
|
||||
SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles);
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
||||
#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
|
||||
if (period_index > 4) {
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
@ -177,3 +177,21 @@ esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us)
|
||||
#endif
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
void ulp_timer_stop(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
#else
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
#endif
|
||||
}
|
||||
|
||||
void ulp_timer_resume(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
#else
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -16,17 +16,25 @@
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#include "esp_attr.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp32/ulp.h"
|
||||
#include "ulp_private.h"
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/sens_reg.h"
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/ulp.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/ulp.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/ulp.h"
|
||||
#endif
|
||||
|
||||
|
||||
static const char* TAG = "ulp";
|
||||
|
||||
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
@ -19,9 +11,15 @@
|
||||
#include "esp_attr.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_log.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/clk.h"
|
||||
#include "esp32s2/ulp.h"
|
||||
#include "esp32s2/ulp_riscv.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/clk.h"
|
||||
#include "esp32s3/ulp.h"
|
||||
#include "esp32s3/ulp_riscv.h"
|
||||
#endif
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
@ -31,6 +29,7 @@
|
||||
|
||||
esp_err_t ulp_riscv_run(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
/* Reset COCPU when power on. */
|
||||
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
|
||||
esp_rom_delay_us(20);
|
||||
@ -55,6 +54,48 @@ esp_err_t ulp_riscv_run(void)
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
|
||||
return ESP_OK;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
/* Reset COCPU when power on. */
|
||||
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
|
||||
esp_rom_delay_us(20);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
|
||||
|
||||
/* Disable ULP timer */
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
/* wait for at least 1 RTC_SLOW_CLK cycle */
|
||||
esp_rom_delay_us(20);
|
||||
|
||||
/* We do not select RISC-V as the Coprocessor here as this could lead to a hang
|
||||
* in the main CPU. Instead, we reset RTC_CNTL_COCPU_SEL after we have enabled the ULP timer.
|
||||
*
|
||||
* IDF-4510
|
||||
*/
|
||||
//CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
|
||||
|
||||
/* Select ULP-RISC-V to send the DONE signal */
|
||||
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
|
||||
|
||||
/* Set the CLKGATE_EN signal */
|
||||
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLKGATE_EN);
|
||||
|
||||
/* start ULP_TIMER */
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
|
||||
|
||||
/* Select RISC-V as the ULP_TIMER trigger target
|
||||
* Selecting the RISC-V as the Coprocessor at the end is a workaround
|
||||
* for the hang issue recorded in IDF-4510.
|
||||
*/
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
|
||||
|
||||
/* Clear any spurious wakeup trigger interrupts upon ULP startup */
|
||||
esp_rom_delay_us(20);
|
||||
REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR | RTC_CNTL_COCPU_TRAP_INT_CLR | RTC_CNTL_ULP_CP_INT_CLR);
|
||||
|
||||
return ESP_OK;
|
||||
#endif
|
||||
}
|
||||
|
||||
esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes)
|
||||
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
@ -55,7 +47,11 @@ typedef enum {
|
||||
|
||||
static inline void ulp_riscv_gpio_init(gpio_num_t gpio_num)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
SET_PERI_REG_MASK(SENS_SAR_IO_MUX_CONF_REG, SENS_IOMUX_CLK_GATE_EN_M);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_IOMUX_CLK_EN_M);
|
||||
#endif
|
||||
SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_MUX_SEL);
|
||||
REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_FUN_SEL, 0);
|
||||
}
|
||||
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
@ -63,10 +55,14 @@ void __attribute__((noreturn)) ulp_riscv_shutdown(void);
|
||||
__ccount; })
|
||||
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
/* These are only approximate default numbers, the default frequency
|
||||
of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting
|
||||
*/
|
||||
#define ULP_RISCV_CYCLES_PER_US 8.5
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#define ULP_RISCV_CYCLES_PER_US 17.5
|
||||
#endif
|
||||
#define ULP_RISCV_CYCLES_PER_MS ULP_RISCV_CYCLES_PER_US*1000
|
||||
|
||||
/**
|
||||
|
||||
@ -80,7 +80,9 @@ FTDI_JTAG_DOCS = ['api-guides/jtag-debugging/configure-ft2232h-jtag.rst']
|
||||
USB_SERIAL_JTAG_DOCS = ['api-guides/jtag-debugging/configure-builtin-jtag.rst',
|
||||
'api-guides/usb-serial-jtag-console.rst']
|
||||
|
||||
ULP_DOCS = ['api-guides/ulp.rst', 'api-guides/ulp_macros.rst']
|
||||
ULP_DOCS = ['api-guides/ulp.rst',
|
||||
'api-guides/ulp_macros.rst',
|
||||
'api-guides/ulp_instruction_set.rst']
|
||||
|
||||
RISCV_COPROC_DOCS = ['api-guides/ulp-risc-v.rst',]
|
||||
|
||||
@ -89,8 +91,7 @@ XTENSA_DOCS = ['api-guides/hlinterrupts.rst',
|
||||
|
||||
RISCV_DOCS = [] # type: list[str]
|
||||
|
||||
ESP32_DOCS = ['api-guides/ulp_instruction_set.rst',
|
||||
'api-reference/system/himem.rst',
|
||||
ESP32_DOCS = ['api-reference/system/himem.rst',
|
||||
'api-guides/romconsole.rst',
|
||||
'api-reference/system/ipc.rst',
|
||||
'security/secure-boot-v1.rst',
|
||||
@ -99,7 +100,6 @@ ESP32_DOCS = ['api-guides/ulp_instruction_set.rst',
|
||||
'hw-reference/esp32/**'] + LEGACY_DOCS + FTDI_JTAG_DOCS
|
||||
|
||||
ESP32S2_DOCS = ['hw-reference/esp32s2/**',
|
||||
'api-guides/ulps2_instruction_set.rst',
|
||||
'api-guides/usb-console.rst',
|
||||
'api-reference/peripherals/ds.rst',
|
||||
'api-reference/peripherals/spi_slave_hd.rst',
|
||||
|
||||
@ -8,6 +8,8 @@ INPUT += \
|
||||
$(PROJECT_PATH)/components/driver/include/driver/pcnt.h \
|
||||
$(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/touch_sensor_channel.h \
|
||||
$(PROJECT_PATH)/components/driver/$(IDF_TARGET)/include/driver/touch_sensor.h \
|
||||
$(PROJECT_PATH)/components/ulp/include/esp32s3/ulp_riscv.h \
|
||||
$(PROJECT_PATH)/components/ulp/include/$(IDF_TARGET)/ulp.h \
|
||||
$(PROJECT_PATH)/components/usb/include/usb/usb_helpers.h \
|
||||
$(PROJECT_PATH)/components/usb/include/usb/usb_host.h \
|
||||
$(PROJECT_PATH)/components/usb/include/usb/usb_types_ch9.h \
|
||||
|
||||
@ -1,37 +1,26 @@
|
||||
ULP-RISC-V Coprocessor programming
|
||||
ULP RISC-V Coprocessor programming
|
||||
==================================
|
||||
:link_to_translation:`zh_CN:[中文]`
|
||||
|
||||
.. only:: esp32s3
|
||||
The ULP RISC-V coprocessor is a variant of the ULP present in {IDF_TARGET_NAME}. Similar to ULP FSM, the ULP RISC-V coprocessor can perform tasks such as sensor readings while the main CPU stays in low power modes. The main difference between ULP FSM and ULP RISC-V is that the latter can be programmed in C using standard GNU tools. The ULP RISC-V coprocessor can access the RTC_SLOW_MEM memory region, and registers in RTC_CNTL, RTC_IO, and SARADC peripherals. The RISC-V processor is a 32-bit fixed point machine. Its instruction set is based on RV32IMC which includes hardware multiplication and division, and compressed code.
|
||||
|
||||
.. warning::
|
||||
|
||||
This feature is not supported in v4.4
|
||||
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
|
||||
The ULP-RISC-V coprocessor is a variant of the ULP, present in ESP32-S2. Similar to ULP, ULP RISC-V coprocessor can perform tasks such as sensor readings while the main CPU stays in low power modes. The main difference from the FSM ULP is this variant can be programmed in C using standard GNU tools. The ULP-RISC-V coprocessor can access the RTC_SLOW_MEM memory region, and registers in RTC_CNTL, RTC_IO, and SARADC peripherals. The RISC-V processor is a 32-bit, fixed point machine. Its instruction set is based on RV32IMC which includes hardware multiplication and division, and compressed code.
|
||||
|
||||
Installing the ULP-RISC-V Toolchain
|
||||
Installing the ULP RISC-V Toolchain
|
||||
-----------------------------------
|
||||
|
||||
The ULP-RISC-V coprocessor code is written in C (assembly is also possible) and compiled using RISC-V toolchain based on GCC.
|
||||
The ULP RISC-V coprocessor code is written in C (assembly is also possible) and compiled using the RISC-V toolchain based on GCC.
|
||||
|
||||
If you have already set up ESP-IDF with CMake build system according to the :doc:`Getting Started Guide <../../get-started/index>`, then the toolchain should already be installed.
|
||||
|
||||
.. note: In earlier versions of ESP-IDF, RISC-V toolchain had a different prefix: `riscv-none-embed-gcc`.
|
||||
|
||||
Compiling the ULP-RISC-V Code
|
||||
Compiling the ULP RISC-V Code
|
||||
-----------------------------
|
||||
|
||||
To compile the ULP-RISC-V code as part of the component, the following steps must be taken:
|
||||
To compile the ULP RISC-V code as part of the component, the following steps must be taken:
|
||||
|
||||
1. The ULP-RISC-V code, written in C or assembly (must use the `.S` extension), must be placed into a separate directory inside the component directory, for instance `ulp/`.
|
||||
1. The ULP RISC-V code, written in C or assembly (must use the `.S` extension), must be placed in a separate directory inside the component directory, for instance, `ulp/`.
|
||||
|
||||
.. note: When registering the component (via ``idf_component_register``), this directory should not be added to the ``SRC_DIRS`` argument as it is currently done for the FSM ULP. See the step below for how to properly add ULP source files
|
||||
.. note: When registering the component (via ``idf_component_register``), this directory should not be added to the ``SRC_DIRS`` argument as it is currently done for the ULP FSM. See the step below for how to properly add ULP source files.
|
||||
|
||||
2. Call ``ulp_embed_binary`` from the component CMakeLists.txt after registration. For example::
|
||||
|
||||
@ -44,13 +33,9 @@ To compile the ULP-RISC-V code as part of the component, the following steps mus
|
||||
|
||||
ulp_embed_binary(${ulp_app_name} "${ulp_sources}" "${ulp_exp_dep_srcs}")
|
||||
|
||||
The first argument to ``ulp_embed_binary`` specifies the ULP binary name. The name specified here will also be used by other generated artifacts
|
||||
such as the ELF file, map file, header file and linker export file. The second argument specifies the ULP source files.
|
||||
Finally, the third argument specifies the list of component source files which include the header file to be generated.
|
||||
This list is needed to build the dependencies correctly and ensure that the generated header file will be created before any of these files are compiled.
|
||||
See section below for the concept of generated header files for ULP applications.
|
||||
The first argument to ``ulp_embed_binary`` specifies the ULP binary name. The name specified here will also be used by other generated artifacts such as the ELF file, map file, header file and linker export file. The second argument specifies the ULP source files. Finally, the third argument specifies the list of component source files which include the header file to be generated. This list is needed to build the dependencies correctly and ensure that the generated header file will be created before any of these files are compiled. See the section below for the concept of generated header files for ULP applications.
|
||||
|
||||
3. Build the application as usual (e.g. `idf.py app`)
|
||||
3. Build the application as usual (e.g. `idf.py app`).
|
||||
|
||||
Inside, the build system will take the following steps to build ULP program:
|
||||
|
||||
@ -58,22 +43,22 @@ To compile the ULP-RISC-V code as part of the component, the following steps mus
|
||||
|
||||
2. **Run the linker script template through the C preprocessor.** The template is located in ``components/ulp/ld`` directory.
|
||||
|
||||
4. **Link the object files into an output ELF file** (``ulp_app_name.elf``). The Map file (``ulp_app_name.map``) generated at this stage may be useful for debugging purposes.
|
||||
3. **Link the object files into an output ELF file** (``ulp_app_name.elf``). The Map file (``ulp_app_name.map``) generated at this stage may be useful for debugging purposes.
|
||||
|
||||
5. **Dump the contents of the ELF file into a binary** (``ulp_app_name.bin``) which can then be embedded into the application.
|
||||
4. **Dump the contents of the ELF file into a binary** (``ulp_app_name.bin``) which can then be embedded into the application.
|
||||
|
||||
6. **Generate a list of global symbols** (``ulp_app_name.sym``) in the ELF file using ``riscv32-esp-elf-nm``.
|
||||
5. **Generate a list of global symbols** (``ulp_app_name.sym``) in the ELF file using ``riscv32-esp-elf-nm``.
|
||||
|
||||
7. **Create an LD export script and header file** (``ulp_app_name.ld`` and ``ulp_app_name.h``) containing the symbols from ``ulp_app_name.sym``. This is done using the ``esp32ulp_mapgen.py`` utility.
|
||||
6. **Create an LD export script and a header file** (``ulp_app_name.ld`` and ``ulp_app_name.h``) containing the symbols from ``ulp_app_name.sym``. This is done using the ``esp32ulp_mapgen.py`` utility.
|
||||
|
||||
8. **Add the generated binary to the list of binary files** to be embedded into the application.
|
||||
7. **Add the generated binary to the list of binary files** to be embedded into the application.
|
||||
|
||||
Accessing the ULP-RISC-V Program Variables
|
||||
Accessing the ULP RISC-V Program Variables
|
||||
------------------------------------------
|
||||
|
||||
Global symbols defined in the ULP-RISC-V program may be used inside the main program.
|
||||
Global symbols defined in the ULP RISC-V program may be used inside the main program.
|
||||
|
||||
For example, the ULP-RISC-V program may define a variable ``measurement_count`` which will define the number of ADC measurements the program needs to make before waking up the chip from deep sleep
|
||||
For example, the ULP RISC-V program may define a variable ``measurement_count`` which will define the number of ADC measurements the program needs to make before waking up the chip from deep sleep.
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
@ -87,9 +72,9 @@ For example, the ULP-RISC-V program may define a variable ``measurement_count``
|
||||
...do something.
|
||||
}
|
||||
|
||||
The main program can access the global ULP-RISC-V program variables, the build system makes this possible by generating the ``${ULP_APP_NAME}.h`` and ``${ULP_APP_NAME}.ld`` files which define the global symbols present in the ULP program. Each global symbol defined in the ULP program is included in these files and are prefixed with ``ulp_``.
|
||||
The main program can access the global ULP RISC-V program variables as the build system makes this possible by generating the ``${ULP_APP_NAME}.h`` and ``${ULP_APP_NAME}.ld`` files which define the global symbols present in the ULP RISC-V program. Each global symbol defined in the ULP RISC-V program is included in these files and are prefixed with ``ulp_``.
|
||||
|
||||
The header file contains the declaration of the symbol
|
||||
The header file contains the declaration of the symbol:
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
@ -101,7 +86,7 @@ The generated linker script file defines the locations of symbols in RTC_SLOW_ME
|
||||
|
||||
PROVIDE ( ulp_measurement_count = 0x50000060 );
|
||||
|
||||
To access the ULP-RISC-V program variables from the main program, the generated header file should be included using an ``include`` statement. This will allow the ULP program variables to be accessed as regular variables
|
||||
To access the ULP RISC-V program variables from the main program, the generated header file should be included using an ``include`` statement. This will allow the ULP RISC-V program variables to be accessed as regular variables.
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
@ -111,14 +96,14 @@ To access the ULP-RISC-V program variables from the main program, the generated
|
||||
ulp_measurement_count = 64;
|
||||
}
|
||||
|
||||
Starting the ULP-RISC-V Program
|
||||
Starting the ULP RISC-V Program
|
||||
-------------------------------
|
||||
|
||||
To run a ULP-RISC-V program, the main application needs to load the ULP program into RTC memory using the :cpp:func:`ulp_riscv_load_binary` function, and then start it using the :cpp:func:`ulp_riscv_run` function.
|
||||
To run a ULP RISC-V program, the main application needs to load the ULP program into RTC memory using the :cpp:func:`ulp_riscv_load_binary` function, and then start it using the :cpp:func:`ulp_riscv_run` function.
|
||||
|
||||
Note that `CONFIG_ESP32S2_ULP_COPROC_ENABLED` and `CONFIG_ESP32S2_ULP_COPROC_RISCV` options must be enabled in menuconfig to reserve memory for the ULP. "RTC slow memory reserved for coprocessor" option must be set to a value sufficient to store ULP code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one.
|
||||
Note that `CONFIG_{IDF_TARGET_CFG_PREFIX}_ULP_COPROC_ENABLED` and `CONFIG_{IDF_TARGET_CFG_PREFIX}_ULP_COPROC_RISCV` options must be enabled in menuconfig to work with ULP RISC-V. To reserve memory for the ULP, the ``RTC slow memory reserved for coprocessor`` option must be set to a value big enough to store ULP RISC-V code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one.
|
||||
|
||||
Each ULP-RISC-V program is embedded into the ESP-IDF application as a binary blob. The application can reference this blob and load it in the following way (suppose ULP_APP_NAME was defined to ``ulp_app_name``)
|
||||
Each ULP RISC-V program is embedded into the ESP-IDF application as a binary blob. The application can reference this blob and load it in the following way (suppose ULP_APP_NAME was defined to ``ulp_app_name``):
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
@ -130,28 +115,33 @@ Each ULP-RISC-V program is embedded into the ESP-IDF application as a binary blo
|
||||
(bin_end - bin_start)) );
|
||||
}
|
||||
|
||||
.. doxygenfunction:: ulp_riscv_load_binary()
|
||||
|
||||
Once the program is loaded into RTC memory, the application can start it, calling the :cpp:func:`ulp_riscv_run` function
|
||||
Once the program is loaded into RTC memory, the application can start it by calling the :cpp:func:`ulp_riscv_run` function:
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
ESP_ERROR_CHECK( ulp_riscv_run() );
|
||||
|
||||
.. doxygenfunction:: ulp_riscv_run()
|
||||
|
||||
ULP-RISC-V Program Flow
|
||||
ULP RISC-V Program Flow
|
||||
-----------------------
|
||||
|
||||
{IDF_TARGET_RTC_CLK_FRE:default="150kHz", esp32s2="90kHz"}
|
||||
{IDF_TARGET_RTC_CLK_FRE:default="150kHz", esp32s2="90kHz", esp32s3="136kHz"}
|
||||
|
||||
The ULP-RISC-V coprocessor is started by a timer. The timer is started once :cpp:func:`ulp_riscv_run` is called. The timer counts the number of RTC_SLOW_CLK ticks (by default, produced by an internal {IDF_TARGET_RTC_CLK_FRE} RC oscillator). The number of ticks is set using ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register. When starting the ULP, ``RTC_CNTL_ULP_CP_TIMER_1_REG`` will be used to set the number of timer ticks.
|
||||
The ULP RISC-V coprocessor is started by a timer. The timer is started once :cpp:func:`ulp_riscv_run` is called. The timer counts the number of RTC_SLOW_CLK ticks (by default, produced by an internal {IDF_TARGET_RTC_CLK_FRE} RC oscillator). The number of ticks is set using ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register. When starting the ULP, ``RTC_CNTL_ULP_CP_TIMER_1_REG`` will be used to set the number of timer ticks.
|
||||
|
||||
The application can set ULP timer period values (RTC_CNTL_ULP_CP_TIMER_1_REG) using the :cpp:func:`ulp_set_wakeup_period` function.
|
||||
|
||||
Once the timer counts the number of ticks set in the ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register, the ULP coprocessor will power up and start running the program from the entry point set in the call to :cpp:func:`ulp_riscv_run`.
|
||||
Once the timer counts the number of ticks set in the ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register, the ULP RISC-V coprocessor will power up and start running the program from the entry point set in the call to :cpp:func:`ulp_riscv_run`.
|
||||
|
||||
The program runs until the field ``RTC_CNTL_COCPU_DONE`` in register ``RTC_CNTL_COCPU_CTRL_REG`` gets written or when a trap occurs due to illegal processor state. Once the program halts, the ULP coprocessor will power down, and the timer will be started again.
|
||||
The program runs until the field ``RTC_CNTL_COCPU_DONE`` in register ``RTC_CNTL_COCPU_CTRL_REG`` gets written or when a trap occurs due to illegal processor state. Once the program halts, the ULP RISC-V coprocessor will power down, and the timer will be started again.
|
||||
|
||||
To disable the timer (effectively preventing the ULP program from running again), please clear the ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` bit in the ``RTC_CNTL_STATE0_REG`` register. This can be done both from the ULP code and from the main program.
|
||||
To disable the timer (effectively preventing the ULP program from running again), please clear the ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` bit in the ``RTC_CNTL_ULP_CP_TIMER_REG`` register. This can be done both from the ULP code and from the main program.
|
||||
|
||||
Application Examples
|
||||
--------------------
|
||||
|
||||
* ULP RISC-V Coprocessor polls GPIO while main CPU is in deep sleep: :example:`system/ulp_riscv/gpio`.
|
||||
|
||||
API Reference
|
||||
-------------
|
||||
|
||||
.. include-build-file:: inc/ulp_riscv.inc
|
||||
|
||||
@ -3,41 +3,42 @@ ULP Coprocessor programming
|
||||
|
||||
:link_to_translation:`zh_CN:[中文]`
|
||||
|
||||
.. only:: esp32s3
|
||||
The Ultra Low Power (ULP) coprocessor is a simple finite state machine (FSM) which is designed to perform measurements using the ADC, temperature sensor, and external I2C sensors, while the main processors are in deep sleep mode. The ULP coprocessor can access the RTC_SLOW_MEM memory region, and registers in the RTC_CNTL, RTC_IO, and SARADC peripherals. The ULP coprocessor uses fixed-width 32-bit instructions, 32-bit memory addressing, and has 4 general-purpose 16-bit registers. This coprocessor is referred to as `ULP FSM` in ESP-IDF.
|
||||
|
||||
.. warning::
|
||||
.. only:: esp32s2 or esp32s3
|
||||
|
||||
This feature is not supported in v4.4
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
:esp32: Instruction set reference for ESP32 ULP <ulp_instruction_set>
|
||||
:esp32s2: Instruction set reference for ESP32-S2 ULP <ulps2_instruction_set>
|
||||
Programming using macros (legacy) <ulp_macros>
|
||||
|
||||
|
||||
The ULP (Ultra Low Power) coprocessor is a simple FSM (Finite State Machine) which is designed to perform measurements using the ADC, temperature sensor, and external I2C sensors, while the main processors are in deep sleep mode. The ULP coprocessor can access the RTC_SLOW_MEM memory region, and registers in RTC_CNTL, RTC_IO, and SARADC peripherals. The ULP coprocessor uses fixed-width 32-bit instructions, 32-bit memory addressing, and has 4 general-purpose 16-bit registers.
|
||||
{IDF_TARGET_NAME} provides a second type of ULP coprocessor which is based on a RISC-V instruction set architecture. For details regarding `ULP RISC-V` refer :doc:`ULP-RISC-V Coprocessor <./ulp-risc-v>`.
|
||||
|
||||
Installing the Toolchain
|
||||
------------------------
|
||||
|
||||
The ULP coprocessor code is written in assembly and compiled using the `binutils-esp32ulp toolchain`_.
|
||||
The ULP FSM coprocessor code is written in assembly and compiled using the `binutils-esp32ulp toolchain`_.
|
||||
|
||||
If you have already set up ESP-IDF with CMake build system according to the :doc:`Getting Started Guide <../../get-started/index>`, then the ULP toolchain will already be installed.
|
||||
If you have already set up ESP-IDF with CMake build system according to the :doc:`Getting Started Guide <../../get-started/index>`, then the ULP FSM toolchain will already be installed.
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
If you are using ESP-IDF with the legacy GNU Make based build system, refer to the instructions on this page: :doc:`ulp-legacy`.
|
||||
|
||||
Programming ULP FSM
|
||||
-------------------
|
||||
|
||||
The ULP FSM can be programmed using the supported instruction set. Alternatively, the ULP FSM coprocessor can also be programmed using C Macros on the main CPU. Theses two methods are described in the following section:
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
Instruction set reference for {IDF_TARGET_NAME} ULP <ulp_instruction_set>
|
||||
Programming using macros (legacy) <ulp_macros>
|
||||
|
||||
Compiling the ULP Code
|
||||
-----------------------
|
||||
|
||||
To compile the ULP code as part of the component, the following steps must be taken:
|
||||
To compile the ULP FSM code as part of the component, the following steps must be taken:
|
||||
|
||||
1. The ULP code, written in assembly, must be added to one or more files with `.S` extension. These files must be placed into a separate directory inside the component directory, for instance `ulp/`.
|
||||
1. The ULP FSM code, written in assembly, must be added to one or more files with `.S` extension. These files must be placed into a separate directory inside the component directory, for instance, `ulp/`.
|
||||
|
||||
.. note: When registering the component (via ``idf_component_register``), this directory should not be added to the ``SRC_DIRS`` argument. The logic behind this is that the ESP-IDF build system will compile files found in ``SRC_DIRS`` based on their extensions. For ``.S`` files, ``{IDF_TARGET_TOOLCHAIN_PREFIX}-as`` assembler is used. This is not desirable for ULP assembly files, so the easiest way to achieve the distinction is by placing ULP assembly files into a separate directory. The ULP assembly source files should also **not** be added to ``SRCS`` for the same reason. See the step below for how to properly add ULP assembly source files.
|
||||
.. note: When registering the component (via ``idf_component_register``), this directory should not be added to the ``SRC_DIRS`` argument. The logic behind this is that the ESP-IDF build system will compile files found in ``SRC_DIRS`` based on their extensions. For ``.S`` files, ``{IDF_TARGET_TOOLCHAIN_PREFIX}-as`` assembler is used. This is not desirable for ULP FSM assembly files, so the easiest way to achieve the distinction is by placing ULP FSM assembly files into a separate directory. The ULP FSM assembly source files should also **not** be added to ``SRCS`` for the same reason. See the step below for how to properly add ULP FSM assembly source files.
|
||||
|
||||
2. Call ``ulp_embed_binary`` from the component CMakeLists.txt after registration. For example::
|
||||
|
||||
@ -50,11 +51,11 @@ To compile the ULP code as part of the component, the following steps must be ta
|
||||
|
||||
ulp_embed_binary(${ulp_app_name} "${ulp_s_sources}" "${ulp_exp_dep_srcs}")
|
||||
|
||||
The first argument to ``ulp_embed_binary`` specifies the ULP binary name. The name specified here will also be used by other generated artifacts such as the ELF file, map file, header file and linker export file. The second argument specifies the ULP assembly source files. Finally, the third argument specifies the list of component source files which include the header file to be generated. This list is needed to build the dependencies correctly and ensure that the generated header file will be created before any of these files are compiled. See section below for the concept of generated header files for ULP applications.
|
||||
The first argument to ``ulp_embed_binary`` specifies the ULP FSM binary name. The name specified here will also be used by other generated artifacts such as the ELF file, map file, header file and linker export file. The second argument specifies the ULP FSM assembly source files. Finally, the third argument specifies the list of component source files which include the header file to be generated. This list is needed to build the dependencies correctly and ensure that the generated header file will be created before any of these files are compiled. See the section below for the concept of generated header files for ULP applications.
|
||||
|
||||
3. Build the application as usual (e.g. `idf.py app`)
|
||||
3. Build the application as usual (e.g. `idf.py app`).
|
||||
|
||||
Inside, the build system will take the following steps to build ULP program:
|
||||
Inside, the build system will take the following steps to build ULP FSM program:
|
||||
|
||||
1. **Run each assembly file (foo.S) through the C preprocessor.** This step generates the preprocessed assembly files (foo.ulp.S) in the component build directory. This step also generates dependency files (foo.ulp.d).
|
||||
|
||||
@ -68,21 +69,21 @@ To compile the ULP code as part of the component, the following steps must be ta
|
||||
|
||||
6. **Generate a list of global symbols** (``ulp_app_name.sym``) in the ELF file using ``esp32ulp-elf-nm``.
|
||||
|
||||
7. **Create an LD export script and header file** (``ulp_app_name.ld`` and ``ulp_app_name.h``) containing the symbols from ``ulp_app_name.sym``. This is done using the ``esp32ulp_mapgen.py`` utility.
|
||||
7. **Create an LD export script and a header file** (``ulp_app_name.ld`` and ``ulp_app_name.h``) containing the symbols from ``ulp_app_name.sym``. This is done using the ``esp32ulp_mapgen.py`` utility.
|
||||
|
||||
8. **Add the generated binary to the list of binary files** to be embedded into the application.
|
||||
|
||||
Accessing the ULP Program Variables
|
||||
-------------------------------------
|
||||
Accessing the ULP FSM Program Variables
|
||||
---------------------------------------
|
||||
|
||||
Global symbols defined in the ULP program may be used inside the main program.
|
||||
Global symbols defined in the ULP FSM program may be used inside the main program.
|
||||
|
||||
For example, the ULP program may define a variable ``measurement_count`` which will define the number of ADC measurements the program needs to make before waking up the chip from deep sleep::
|
||||
For example, the ULP FSM program may define a variable ``measurement_count`` which will define the number of ADC measurements the program needs to make before waking up the chip from deep sleep::
|
||||
|
||||
.global measurement_count
|
||||
measurement_count: .long 0
|
||||
|
||||
/* later, use measurement_count */
|
||||
// later, use measurement_count
|
||||
move r3, measurement_count
|
||||
ld r3, r3, 0
|
||||
|
||||
@ -107,18 +108,18 @@ To access the ULP program variables from the main program, the generated header
|
||||
ulp_measurement_count = 64;
|
||||
}
|
||||
|
||||
Note that the ULP program can only use lower 16 bits of each 32-bit word in RTC memory, because the registers are 16-bit, and there is no instruction to load from the high part of the word.
|
||||
.. only:: esp32
|
||||
|
||||
Likewise, the ULP store instruction writes register value into the lower 16 bits part of the 32-bit word. The upper 16 bits are written with a value which depends on the address of the store instruction, thus when reading variables written by the ULP, the main application needs to mask the upper 16 bits, e.g.::
|
||||
Note that the ULP FSM program can only use the lower 16 bits of each 32-bit word in RTC memory, because the registers are 16-bit, and there is no instruction to load from the high part of the word. Likewise, the ULP store instruction writes register values into the lower 16 bits of the 32-bit word in RTC memory. The upper 16 bits are written with a value which depends on the address of the store instruction, thus when reading variables written by the ULP coprocessor, the main application needs to mask the upper 16 bits, e.g.::
|
||||
|
||||
printf("Last measurement value: %d\n", ulp_last_measurement & UINT16_MAX);
|
||||
printf("Last measurement value: %d\n", ulp_last_measurement & UINT16_MAX);
|
||||
|
||||
Starting the ULP Program
|
||||
------------------------
|
||||
Starting the ULP FSM Program
|
||||
----------------------------
|
||||
|
||||
To run a ULP program, the main application needs to load the ULP program into RTC memory using the ``ulp_load_binary`` function, and then start it using the ``ulp_run`` function.
|
||||
To run a ULP FSM program, the main application needs to load the ULP program into RTC memory using the :cpp:func:`ulp_load_binary` function, and then start it using the :cpp:func:`ulp_run` function.
|
||||
|
||||
Note that "Enable Ultra Low Power (ULP) Coprocessor" option must be enabled in menuconfig to reserve memory for the ULP. "RTC slow memory reserved for coprocessor" option must be set to a value sufficient to store ULP code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one.
|
||||
Note that the ``Enable Ultra Low Power (ULP) Coprocessor`` option must be enabled in menuconfig to work with ULP. To select the type of ULP to be used, the ``ULP Co-processor type`` option must be set. To reserve memory for the ULP, the ``RTC slow memory reserved for coprocessor`` option must be set to a value big enough to store ULP code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one.
|
||||
|
||||
Each ULP program is embedded into the ESP-IDF application as a binary blob. The application can reference this blob and load it in the following way (suppose ULP_APP_NAME was defined to ``ulp_app_name``)::
|
||||
|
||||
@ -127,60 +128,62 @@ Each ULP program is embedded into the ESP-IDF application as a binary blob. The
|
||||
|
||||
void start_ulp_program() {
|
||||
ESP_ERROR_CHECK( ulp_load_binary(
|
||||
0 /* load address, set to 0 when using default linker scripts */,
|
||||
0 // load address, set to 0 when using default linker scripts
|
||||
bin_start,
|
||||
(bin_end - bin_start) / sizeof(uint32_t)) );
|
||||
}
|
||||
|
||||
.. doxygenfunction:: ulp_load_binary
|
||||
|
||||
Once the program is loaded into RTC memory, the application can start it, passing the address of the entry point to the ``ulp_run`` function::
|
||||
Once the program is loaded into RTC memory, the application can start it by passing the address of the entry point to the ``ulp_run`` function::
|
||||
|
||||
ESP_ERROR_CHECK( ulp_run(&ulp_entry - RTC_SLOW_MEM) );
|
||||
|
||||
.. doxygenfunction:: ulp_run
|
||||
|
||||
Declaration of the entry point symbol comes from the generated header file mentioned above, ``${ULP_APP_NAME}.h``. In the assembly source of the ULP application, this symbol must be marked as ``.global``::
|
||||
Declaration of the entry point symbol comes from the generated header file mentioned above, ``${ULP_APP_NAME}.h``. In the assembly source of the ULP FSM application, this symbol must be marked as ``.global``::
|
||||
|
||||
|
||||
.global entry
|
||||
entry:
|
||||
/* code starts here */
|
||||
// code starts here
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
ESP32 ULP program flow
|
||||
-----------------------
|
||||
|
||||
ESP32 ULP coprocessor is started by a timer. The timer is started once ``ulp_run`` is called. The timer counts a number of RTC_SLOW_CLK ticks (by default, produced by an internal 150 kHz RC oscillator). The number of ticks is set using ``SENS_ULP_CP_SLEEP_CYCx_REG`` registers (x = 0..4). When starting the ULP for the first time, ``SENS_ULP_CP_SLEEP_CYC0_REG`` will be used to set the number of timer ticks. Later the ULP program can select another ``SENS_ULP_CP_SLEEP_CYCx_REG`` register using ``sleep`` instruction.
|
||||
ESP32 ULP coprocessor is started by a timer. The timer is started once :cpp:func:`ulp_run` is called. The timer counts a number of RTC_SLOW_CLK ticks (by default, produced by an internal 150 kHz RC oscillator). The number of ticks is set using ``SENS_ULP_CP_SLEEP_CYCx_REG`` registers (x = 0..4). When starting the ULP for the first time, ``SENS_ULP_CP_SLEEP_CYC0_REG`` will be used to set the number of timer ticks. Later the ULP program can select another ``SENS_ULP_CP_SLEEP_CYCx_REG`` register using ``sleep`` instruction.
|
||||
|
||||
The application can set ULP timer period values (SENS_ULP_CP_SLEEP_CYCx_REG, x = 0..4) using ``ulp_set_wakeup_period`` function.
|
||||
|
||||
.. doxygenfunction:: ulp_set_wakeup_period
|
||||
Once the timer counts the number of ticks set in the selected ``SENS_ULP_CP_SLEEP_CYCx_REG`` register, ULP coprocessor powers up and starts running the program from the entry point set in the call to :cpp:func:`ulp_run`.
|
||||
|
||||
Once the timer counts the number of ticks set in the selected ``SENS_ULP_CP_SLEEP_CYCx_REG`` register, ULP coprocessor powers up and starts running the program from the entry point set in the call to ``ulp_run``.
|
||||
|
||||
The program runs until it encounters a ``halt`` instruction or an illegal instruction. Once the program halts, ULP coprocessor powers down, and the timer is started again.
|
||||
The program runs until it encounters a ``halt`` instruction or an illegal instruction. Once the program halts the ULP coprocessor powers down and the timer is started again.
|
||||
|
||||
To disable the timer (effectively preventing the ULP program from running again), clear the ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` bit in the ``RTC_CNTL_STATE0_REG`` register. This can be done both from ULP code and from the main program.
|
||||
|
||||
|
||||
.. only:: esp32s2
|
||||
.. only:: esp32s2 or esp32s3
|
||||
|
||||
ESP32-S2 ULP program flow
|
||||
-------------------------
|
||||
{IDF_TARGET_NAME} ULP program flow
|
||||
----------------------------------
|
||||
|
||||
ESP32-S2 ULP coprocessor is started by a timer. The timer is started once ``ulp_run`` is called. The timer counts a number of RTC_SLOW_CLK ticks (by default, produced by an internal 90 kHz RC oscillator). The number of ticks is set using ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register.
|
||||
{IDF_TARGET_NAME} ULP coprocessor is started by a timer. The timer is started once :cpp:func:`ulp_run` is called. The timer counts a number of RTC_SLOW_CLK ticks (by default, produced by an internal 90 kHz RC oscillator). The number of ticks is set using ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register.
|
||||
|
||||
The application can set ULP timer period values by ``ulp_set_wakeup_period`` function.
|
||||
The application can set ULP timer period values by :cpp:func:`ulp_set_wakeup_period` function.
|
||||
|
||||
.. doxygenfunction:: ulp_set_wakeup_period
|
||||
|
||||
Once the timer counts the number of ticks set in the selected ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register, ULP coprocessor powers up and starts running the program from the entry point set in the call to ``ulp_run``.
|
||||
Once the timer counts the number of ticks set in the selected ``RTC_CNTL_ULP_CP_TIMER_1_REG`` register, ULP coprocessor powers up and starts running the program from the entry point set in the call to :cpp:func:`ulp_run`.
|
||||
|
||||
The program runs until it encounters a ``halt`` instruction or an illegal instruction. Once the program halts, ULP coprocessor powers down, and the timer is started again.
|
||||
|
||||
To disable the timer (effectively preventing the ULP program from running again), clear the ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` bit in the ``RTC_CNTL_STATE0_REG`` register.This can be done both from ULP code and from the main program.
|
||||
To disable the timer (effectively preventing the ULP program from running again), clear the ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` bit in the ``RTC_CNTL_ULP_CP_TIMER_REG`` register. This can be done both from ULP code and from the main program.
|
||||
|
||||
Application Examples
|
||||
--------------------
|
||||
|
||||
.. _binutils-esp32ulp toolchain: https://github.com/espressif/binutils-esp32ulp
|
||||
* ULP FSM Coprocessor counts pulses on an IO while main CPU is in deep sleep: :example:`system/ulp_fsm/ulp`.
|
||||
* ULP FSM Coprocessor polls ADC in while main CPU is in deep sleep: :example:`system/ulp_fsm/ulp_adc`.
|
||||
|
||||
API Reference
|
||||
-------------
|
||||
|
||||
.. include-build-file:: inc/ulp_common.inc
|
||||
|
||||
.. _binutils-esp32ulp toolchain: https://github.com/espressif/binutils-esp32ulp
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1 +1,58 @@
|
||||
.. include:: ../../../components/ulp/README.rst
|
||||
Programming ULP FSM coprocessor using C macros (legacy)
|
||||
=======================================================
|
||||
|
||||
In addition to the existing binutils port for the {IDF_TARGET_NAME} ULP coprocessor, it is possible to generate programs for the ULP FSM coprocessor by embedding assembly-like macros into an {IDF_TARGET_NAME} application. Here is an example how this can be done::
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R3, 16), // R3 <- 16
|
||||
I_LD(R0, R3, 0), // R0 <- RTC_SLOW_MEM[R3 + 0]
|
||||
I_LD(R1, R3, 1), // R1 <- RTC_SLOW_MEM[R3 + 1]
|
||||
I_ADDR(R2, R0, R1), // R2 <- R0 + R1
|
||||
I_ST(R2, R3, 2), // R2 -> RTC_SLOW_MEM[R2 + 2]
|
||||
I_HALT()
|
||||
};
|
||||
size_t load_addr = 0;
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
ulp_process_macros_and_load(load_addr, program, &size);
|
||||
ulp_run(load_addr);
|
||||
|
||||
The ``program`` array is an array of ``ulp_insn_t``, i.e. ULP coprocessor instructions. Each ``I_XXX`` preprocessor define translates into a single 32-bit instruction. Arguments of these preprocessor defines can be register numbers (``R0 — R3``) and literal constants. See the API reference section at the end of this guide for descriptions of instructions and arguments they take.
|
||||
|
||||
.. note::
|
||||
|
||||
Because some of the instruction macros expand to inline function calls, defining such array in global scope will cause the compiler to produce an "initializer element is not constant" error. To fix this error, move the definition of instructions array into local scope.
|
||||
|
||||
.. note::
|
||||
Load, store and move instructions use **addresses expressed in 32-bit words**. Address 0 corresponds to the first word of ``RTC_SLOW_MEM``.
|
||||
This is different to how address arguments are handled in assembly code of the same instructions. See the section :ref:`ulp-fsm-addressing` for more details for reference.
|
||||
|
||||
To generate branch instructions, special ``M_`` preprocessor defines are used. ``M_LABEL`` define can be used to define a branch target. Label identifier is a 16-bit integer. ``M_Bxxx`` defines can be used to generate branch instructions with target set to a particular label.
|
||||
|
||||
Implementation note: these ``M_`` preprocessor defines will be translated into two ulp_insn_t values: one is a token value which contains label number, and the other is the actual instruction. ``ulp_process_macros_and_load`` function resolves the label number to the address, modifies the branch instruction to use the correct address, and removes the the extra ``ulp_insn_t`` token which contains the label numer.
|
||||
|
||||
Here is an example of using labels and branches::
|
||||
|
||||
const ulp_insn_t program[] = {
|
||||
I_MOVI(R0, 34), // R0 <- 34
|
||||
M_LABEL(1), // label_1
|
||||
I_MOVI(R1, 32), // R1 <- 32
|
||||
I_LD(R1, R1, 0), // R1 <- RTC_SLOW_MEM[R1]
|
||||
I_MOVI(R2, 33), // R2 <- 33
|
||||
I_LD(R2, R2, 0), // R2 <- RTC_SLOW_MEM[R2]
|
||||
I_SUBR(R3, R1, R2), // R3 <- R1 - R2
|
||||
I_ST(R3, R0, 0), // R3 -> RTC_SLOW_MEM[R0 + 0]
|
||||
I_ADDI(R0, R0, 1), // R0++
|
||||
M_BL(1, 64), // if (R0 < 64) goto label_1
|
||||
I_HALT(),
|
||||
};
|
||||
RTC_SLOW_MEM[32] = 42;
|
||||
RTC_SLOW_MEM[33] = 18;
|
||||
size_t load_addr = 0;
|
||||
size_t size = sizeof(program)/sizeof(ulp_insn_t);
|
||||
ulp_process_macros_and_load(load_addr, program, &size);
|
||||
ulp_run(load_addr);
|
||||
|
||||
API Reference
|
||||
-------------
|
||||
|
||||
.. include-build-file:: inc/ulp.inc
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -81,7 +81,7 @@ API Reference
|
||||
|
||||
For example see :idf_file:`docs/en/api-reference/network/esp_wifi.rst`
|
||||
|
||||
1. Optionally, rather that using ``*.inc`` files, you may want to describe API in you own way. See :idf_file:`docs/en/api-guides/ulp.rst` for example.
|
||||
1. Optionally, rather that using ``*.inc`` files, you may want to describe API in you own way. See :idf_file:`docs/en/api-reference/storage/fatfs.rst` for example.
|
||||
|
||||
Below is the list of common ``.. doxygen...::`` directives:
|
||||
|
||||
|
||||
@ -57,6 +57,7 @@ get-started-cmake/get-started-pico-kit-v3 hw-reference/esp32/get-started-p
|
||||
api-guides/build-system-cmake api-guides/build-system
|
||||
api-guides/ulp-cmake api-guides/ulp
|
||||
api-guides/unit-tests-cmake api-guides/unit-tests
|
||||
api-guides/ulps2_instruction_set.rst api-guides/ulp_extended_instruction_set.rst
|
||||
|
||||
api-reference/network/tcpip_adapter api-reference/network/esp_netif
|
||||
|
||||
|
||||
@ -39,7 +39,7 @@ API 指南
|
||||
工具 <tools/index>
|
||||
:SOC_ULP_SUPPORTED: ULP 协处理器 <ulp>
|
||||
:esp32: ULP (传统 GNU Make) <ulp-legacy>
|
||||
:esp32s2: ULP-RISC-V 协处理器 <ulp-risc-v>
|
||||
:SOC_RISCV_COPROC_SUPPORTED: ULP-RISC-V 协处理器 <ulp-risc-v>
|
||||
单元测试 (Target) <unit-tests>
|
||||
单元测试 (Linux Host) <linux-host-testing>
|
||||
:esp32: 单元测试 (传统 GNU Make) <unit-tests-legacy>
|
||||
|
||||
@ -1,37 +1,26 @@
|
||||
ULP-RISC-V 协处理器编程
|
||||
ULP RISC-V 协处理器编程
|
||||
==================================
|
||||
:link_to_translation:`en:[English]`
|
||||
|
||||
.. only:: esp32s3
|
||||
ULP RISC-V 协处理器是 ULP 的一种变体，用于 {IDF_TARGET_NAME}。与 ULP FSM 类似，ULP RISC-V 协处理器可以在主处理器处于低功耗模式时执行传感器读数等任务。其与 ULP FSM 的主要区别在于，ULP RISC-V 可以通过标准 GNU 工具使用 C 语言进行编程。ULP RISC-V 可以访问 RTC_SLOW_MEM 内存区域及 RTC_CNTL、RTC_IO、SARADC 等外设的寄存器。RISC-V 处理器是一种 32 位定点处理器，指令集基于 RV32IMC，包括硬件乘除法和压缩指令。
|
||||
|
||||
.. warning::
|
||||
|
||||
此功能不适用于 v4.4 版本。
|
||||
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
|
||||
ULP-RISC-V 协处理器是 ULP 的一种变体，用于 ESP32-S2。与 ULP 类似，ULP-RISC-V 协处理器可以在主处理器处于低功耗模式时执行传感器读数等任务。与 ULP-FSM 不同，ULP-RISC-V 可以通过标准 GNU 工具使用 C 语言进行编程。ULP-RISC-V 可以访问 RTC_SLOW_MEM 内存区域及 RTC_CNTL、RTC_IO、SARADC 等外设的寄存器。RISC-V 处理器是一种 32 位定点处理器，指令集基于 RV32IMC，包括硬件乘除法和压缩指令。
|
||||
|
||||
安装 ULP-RISC-V 工具链
|
||||
安装 ULP RISC-V 工具链
|
||||
-----------------------------------
|
||||
|
||||
ULP-RISC-V 协处理器代码以 C 语言编写（也可能是汇编语言），使用基于 GCC 的 RISC-V 工具链进行编译。
|
||||
ULP RISC-V 协处理器代码以 C 语言（或汇编语言）编写，使用基于 GCC 的 RISC-V 工具链进行编译。
|
||||
|
||||
如果你已依照 :doc:`快速入门指南 <../../get-started/index>` 中的介绍安装好了 ESP-IDF 及其 CMake 构建系统，那么 ULP-RISC-V 工具链已经被默认安装到了你的开发环境中。
|
||||
如果您已依照 :doc:`快速入门指南 <./../get-started/index>` 中的介绍安装好了 ESP-IDF 及其 CMake 构建系统，那么 ULP RISC-V 工具链已经被默认安装到了您的开发环境中。
|
||||
|
||||
.. note: 在早期版本的ESP-IDF中，RISC-V工具链具有不同的名称：`riscv-none-embed-gcc`。
|
||||
|
||||
编译 ULP-RISC-V 代码
|
||||
编译 ULP RISC-V 代码
|
||||
-----------------------------
|
||||
|
||||
要将 ULP-RISC-V 代码编译为某组件的一部分，必须执行以下步骤：
|
||||
要将 ULP RISC-V 代码编译为某组件的一部分，必须执行以下步骤：
|
||||
|
||||
1. ULP-RISC-V 代码以 C 语言或汇编语言编写（必须使用 `.S` 扩展名)，必须放在组件目录中一个独立的目录中，例如 `ulp/`。
|
||||
1. ULP RISC-V 代码以 C 语言或汇编语言编写（必须使用 `.S` 扩展名)，必须放在组件目录中一个独立的目录中，例如 `ulp/`。
|
||||
|
||||
.. note: 当注册组件时（通过 ``idf_component_register``），该目录不应被添加至 ``SRC_DIRS`` 参数，因为目前 ULP-FSM 需要进行此步骤。如何正确添加 ULP 源文件，请见以下步骤。
|
||||
.. note: 当注册组件时（通过 ``idf_component_register``），该目录不应被添加至 ``SRC_DIRS`` 参数，因为目前该步骤需用于 ULP FSM。如何正确添加 ULP 源文件，请见以下步骤。
|
||||
|
||||
2. 注册后从组件 CMakeLists.txt 中调用 ``ulp_embed_binary`` 示例如下::
|
||||
|
||||
@ -44,13 +33,9 @@ ULP-RISC-V 协处理器代码以 C 语言编写（也可能是汇编语言），
|
||||
|
||||
ulp_embed_binary(${ulp_app_name} "${ulp_sources}" "${ulp_exp_dep_srcs}")
|
||||
|
||||
``ulp_embed_binary`` 的第一个参数指定生成的 ULP 二进制文件名。生成的其他文件，
|
||||
如 ELF 文件、.map 文件、头文件和链接器导出文件等也可使用此名称。第二个参数指定 ULP 源文件。
|
||||
最后，第三个参数指定组件源文件列表，其中包括生成的头文件。
|
||||
此列表用以正确构建依赖，并确保在构建过程中先生成后编译包含头文件的源文件。
|
||||
请参考下文，查看为 ULP 应用程序生成的头文件等相关概念。
|
||||
``ulp_embed_binary`` 的第一个参数指定生成的 ULP 二进制文件名。生成的其他文件，如 ELF 文件、.map 文件、头文件和链接器导出文件等也可使用此名称。第二个参数指定 ULP 源文件。最后，第三个参数指定组件源文件列表，其中包括生成的头文件。此列表用以正确构建依赖，并确保在构建过程中先生成后编译包含头文件的源文件。请参考下文，查看为 ULP 应用程序生成的头文件等相关概念。
|
||||
|
||||
3. 使用常规方法（例如 `idf.py app`）编译应用程序
|
||||
3. 使用常规方法（例如 `idf.py app`）编译应用程序。
|
||||
|
||||
在内部，构建系统将按照以下步骤编译 ULP 程序：
|
||||
|
||||
@ -58,22 +43,22 @@ ULP-RISC-V 协处理器代码以 C 语言编写（也可能是汇编语言），
|
||||
|
||||
2. **通过 C 预处理器运行链接器脚本模版。** 模版位于 ``components/ulp/ld`` 目录中。
|
||||
|
||||
4. **将目标文件链接到 ELF 输出文件** (``ulp_app_name.elf``)。此步骤生成的 .Map 文件默认用于调试 (``ulp_app_name.map``)。
|
||||
3. **将目标文件链接到 ELF 输出文件** (``ulp_app_name.elf``)。此步骤生成的 .map 文件默认用于调试 (``ulp_app_name.map``)。
|
||||
|
||||
5. **将 ELF 文件中的内容转储为二进制文件** (``ulp_app_name.bin``)，以便嵌入到应用程序中。
|
||||
4. **将 ELF 文件中的内容转储为二进制文件** (``ulp_app_name.bin``)，以便嵌入到应用程序中。
|
||||
|
||||
6. 使用 ``riscv32-esp-elf-nm`` 在 ELF 文件中 **生成全局符号列表** (``ulp_app_name.sym``)。
|
||||
5. 使用 ``riscv32-esp-elf-nm`` 在 ELF 文件中 **生成全局符号列表** (``ulp_app_name.sym``)。
|
||||
|
||||
7. **创建 LD 导出脚本和头文件** （``ulp_app_name.ld`` 和 ``ulp_app_name.h``），包含来自 ``ulp_app_name.sym`` 的符号。此步骤可借助 ``esp32ulp_mapgen.py`` 工具来完成。
|
||||
6. **创建 LD 导出脚本和头文件** （``ulp_app_name.ld`` 和 ``ulp_app_name.h``），包含来自 ``ulp_app_name.sym`` 的符号。此步骤可借助 ``esp32ulp_mapgen.py`` 工具来完成。
|
||||
|
||||
8. **将生成的二进制文件添加到要嵌入应用程序的二进制文件列表中。**
|
||||
7. **将生成的二进制文件添加到要嵌入应用程序的二进制文件列表中。**
|
||||
|
||||
访问 ULP-RISC-V 程序变量
|
||||
访问 ULP RISC-V 程序变量
|
||||
----------------------------
|
||||
|
||||
在 ULP-RISC-V 程序中定义的全局符号也可以在主程序中使用。
|
||||
在 ULP RISC-V 程序中定义的全局符号也可以在主程序中使用。
|
||||
|
||||
例如，ULP-RISC-V 程序可以定义 ``measurement_count`` 变量，此变量可以定义程序从深度睡眠中唤醒芯片之前需要进行的 ADC 测量的次数。
|
||||
例如，ULP RISC-V 程序可以定义 ``measurement_count`` 变量，此变量可以定义程序从深度睡眠中唤醒芯片之前需要进行的 ADC 测量的次数。
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
@ -87,21 +72,21 @@ ULP-RISC-V 协处理器代码以 C 语言编写（也可能是汇编语言），
|
||||
...do something.
|
||||
}
|
||||
|
||||
构建系统生成定义 ULP 编程中全局符号的 ``${ULP_APP_NAME}.h`` 和 ``${ULP_APP_NAME}.ld`` 文件，使主程序能够访问全局 ULP-RISC-V 程序变量。上述两个文件包含 ULP 程序中定义的所有全局符号，且这些符号均以 ``ulp_`` 开头，。
|
||||
构建系统生成定义 ULP 编程中全局符号的 ``${ULP_APP_NAME}.h`` 和 ``${ULP_APP_NAME}.ld`` 文件，使主程序能够访问全局 ULP RISC-V 程序变量。上述两个文件包含 ULP RISC-V 程序中定义的所有全局符号，且这些符号均以 ``ulp_`` 开头。
|
||||
|
||||
头文件包含对此类符号的声明
|
||||
头文件包含对此类符号的声明：
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
extern uint32_t ulp_measurement_count;
|
||||
|
||||
注意，所有符号（包括变量、数组、函数）均被声明为 ``uint32_t``。 函数和数组需要先获取符号地址、再转换为适当的类型。
|
||||
注意，所有符号（包括变量、数组、函数）均被声明为 ``uint32_t``。函数和数组需要先获取符号地址，再转换为适当的类型。
|
||||
|
||||
生成的链接器文本定义了符号在 RTC_SLOW_MEM 中的位置::
|
||||
|
||||
PROVIDE ( ulp_measurement_count = 0x50000060 );
|
||||
|
||||
要从主程序访问 ULP-RISC-V 程序变量，需使用 ``include`` 语句包含生成的头文件。这样，就可以像访问常规变量一样访问 ULP 程序变量。
|
||||
要从主程序访问 ULP RISC-V 程序变量，需使用 ``include`` 语句包含生成的头文件。这样，就可以像访问常规变量一样访问 ULP RISC-V 程序变量。
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
@ -111,14 +96,14 @@ ULP-RISC-V 协处理器代码以 C 语言编写（也可能是汇编语言），
|
||||
ulp_measurement_count = 64;
|
||||
}
|
||||
|
||||
启动 ULP-RISC-V 程序
|
||||
启动 ULP RISC-V 程序
|
||||
-------------------------------
|
||||
|
||||
要运行 ULP-RISC-V 程序，主程序需要调用 :cpp:func:`ulp_riscv_load_binary` 函数，将 ULP 程序加载到 RTC 内存中，然后调用 :cpp:func:`ulp_riscv_run` 函数，启动 ULP-RISC-V 程序。
|
||||
要运行 ULP RISC-V 程序，主程序需要调用 :cpp:func:`ulp_riscv_load_binary` 函数，将 ULP 程序加载到 RTC 内存中，然后调用 :cpp:func:`ulp_riscv_run` 函数，启动 ULP RISC-V 程序。
|
||||
|
||||
注意，必须在 menuconfig 中启用 `CONFIG_ESP32S2_ULP_COPROC_ENABLED` 和 `CONFIG_ESP32S2_ULP_COPROC_RISCV` 选项，以便为 ULP 预留内存。"RTC slow memory reserved for coprocessor" 选项设置的值必须足够存储 ULP 代码和数据。如果应用程序组件包含多个 ULP 程序，RTC 内存必须足以容纳最大的程序。
|
||||
注意，必须在 menuconfig 中启用 `CONFIG_{IDF_TARGET_CFG_PREFIX}_ULP_COPROC_ENABLED` 和 `CONFIG_{IDF_TARGET_CFG_PREFIX}_ULP_COPROC_RISCV` 选项，以便正常运行 ULP RISC-V 程序。``RTC slow memory reserved for coprocessor`` 选项设置的值必须足够存储 ULP RISC-V 代码和数据。如果应用程序组件包含多个 ULP 程序，RTC 内存必须足以容纳最大的程序。
|
||||
|
||||
每个 ULP-RISC-V 程序均以二进制 BLOB 的形式嵌入到 ESP-IDF 应用程序中。应用程序可以引用此 BLOB，并以下面的方式加载此 BLOB（假设 ULP_APP_NAME 已被定义为 ``ulp_app_name``）：
|
||||
每个 ULP RISC-V 程序均以二进制 BLOB 的形式嵌入到 ESP-IDF 应用程序中。应用程序可以引用此 BLOB，并以下面的方式加载此 BLOB（假设 ULP_APP_NAME 已被定义为 ``ulp_app_name``）：
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
@ -130,26 +115,34 @@ ULP-RISC-V 协处理器代码以 C 语言编写（也可能是汇编语言），
|
||||
(bin_end - bin_start)) );
|
||||
}
|
||||
|
||||
.. doxygenfunction:: ulp_riscv_load_binary()
|
||||
|
||||
一旦上述程序加载到 RTC 内存后，应用程序即可调用 :cpp:func:`ulp_riscv_run` 函数启动此程序：
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
ESP_ERROR_CHECK( ulp_riscv_run() );
|
||||
|
||||
.. doxygenfunction:: ulp_riscv_run()
|
||||
|
||||
ULP-RISC-V 程序流
|
||||
ULP RISC-V 程序流
|
||||
-----------------------
|
||||
|
||||
ULP-RISC-V 协处理器由定时器启动，调用 :cpp:func:`ulp_riscv_run` 即可启动定时器。定时器为 RTC_SLOW_CLK 的 Tick 事件计数（默认情况下，Tick 由内部 90 kHz RC 振荡器产生）。Tick 数值使用 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 寄存器设置。启用 ULP 时，使用 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 设置定时器 Tick 数值。
|
||||
{IDF_TARGET_RTC_CLK_FRE:default="150kHz", esp32s2="90kHz", esp32s3="136kHz"}
|
||||
|
||||
ULP RISC-V 协处理器由定时器启动，调用 :cpp:func:`ulp_riscv_run` 即可启动定时器。定时器为 RTC_SLOW_CLK 的 Tick 事件计数（默认情况下，Tick 由内部 90 kHz RC 振荡器产生）。Tick 数值使用 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 寄存器设置。启用 ULP 时，使用 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 设置定时器 Tick 数值。
|
||||
|
||||
此应用程序可以调用 :cpp:func:`ulp_set_wakeup_period` 函数来设置 ULP 定时器周期值 (RTC_CNTL_ULP_CP_TIMER_1_REG)。
|
||||
|
||||
一旦定时器数到 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 寄存器中设置的 Tick 数，ULP 协处理器就会启动，并调用 :cpp:func:`ulp_riscv_run` 的入口点开始运行程序。
|
||||
一旦定时器数到 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 寄存器中设置的 Tick 数，ULP RISC-V 协处理器就会启动，并调用 :cpp:func:`ulp_riscv_run` 的入口点开始运行程序。
|
||||
|
||||
程序保持运行，直至 ``RTC_CNTL_COCPU_CTRL_REG`` 寄存器中的 ``RTC_CNTL_COCPU_DONE`` 字段被置位或因非法处理器状态出现陷阱。一旦程序停止，ULP 协处理器会关闭电源，定时器再次启动。
|
||||
程序保持运行，直至 ``RTC_CNTL_COCPU_CTRL_REG`` 寄存器中的 ``RTC_CNTL_COCPU_DONE`` 字段被置位或因非法处理器状态出现陷阱。一旦程序停止，ULP RISC-V 协处理器会关闭电源，定时器再次启动。
|
||||
|
||||
如需禁用定时器（有效防止 ULP 程序再次运行），请清除 ``RTC_CNTL_STATE0_REG`` 寄存器中的 ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` 位，此项操作可在 ULP 代码或主程序中进行。
|
||||
|
||||
应用示例
|
||||
--------------------
|
||||
|
||||
* 主处理器处于 Deep-sleep 状态时，ULP RISC-V 协处理器轮询 GPIO：:example:`system/ulp_riscv/gpio`。
|
||||
* 主处理器处于 Deep-sleep 状态时，ULP RISC-V 协处理器读取外部温度传感器：:example:`system/ulp_riscv/ds18b20_onewire`。
|
||||
|
||||
API 参考
|
||||
-------------
|
||||
|
||||
.. include-build-file:: inc/ulp_riscv.inc
|
||||
|
||||
@ -3,41 +3,42 @@ ULP 协处理器编程
|
||||
|
||||
:link_to_translation:`en:[English]`
|
||||
|
||||
.. only:: esp32s3
|
||||
ULP（Ultra Low Power，超低功耗）协处理器是一种简单的有限状态机 (FSM)，可以在主处理器处于深度睡眠模式时，使用 ADC、温度传感器和外部 I2C 传感器执行测量操作。ULP 协处理器可以访问 RTC_SLOW_MEM 内存区域及 RTC_CNTL、RTC_IO、SARADC 外设中的寄存器。ULP 协处理器使用 32 位固定宽度的指令，32 位内存寻址，配备 4 个 16 位通用寄存器。在 ESP-IDF 项目中，此协处理器被称作 `ULP FSM`。
|
||||
|
||||
.. warning::
|
||||
.. only:: esp32s2 or esp32s3
|
||||
|
||||
此功能不适用于 v4.4 版本。
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
:esp32: ESP32 ULP 指令集参考 <ulp_instruction_set>
|
||||
:esp32s2: ESP32-S2 ULP 指令集参考 <ulps2_instruction_set>
|
||||
使用宏进行编程（遗留） <ulp_macros>
|
||||
|
||||
|
||||
ULP（Ultra Low Power 超低功耗）协处理器是一种简单的有限状态机 (FSM)，可以在主处理器处于深度睡眠模式时，使用 ADC、温度传感器和外部 I2C 传感器执行测量操作。ULP 协处理器可以访问 RTC_SLOW_MEM 内存区域及 RTC_CNTL、RTC_IO、SARADC 外设中的寄存器。ULP 协处理器使用 32 位固定宽度的指令，32 位内存寻址，配备 4 个 16 位通用寄存器。
|
||||
{IDF_TARGET_NAME} 基于 RISC-V 指令集架构提供另一种 ULP 协处理器。关于 `ULP RISC-V` 的详细信息，请参考 :doc:`ULP-RISC-V Coprocessor <./ulp-risc-v>`。
|
||||
|
||||
安装工具链
|
||||
----------
|
||||
|
||||
ULP 协处理器代码是用汇编语言编写的，并使用 `binutils-esp32ulp 工具链`_ 进行编译。
|
||||
ULP FSM 协处理器代码由汇编语言编写，使用 `binutils-esp32ulp 工具链`_ 进行编译。
|
||||
|
||||
如果你已经按照 :doc:`快速入门指南 <../../get-started/index>` 中的介绍安装好了 ESP-IDF 及其 CMake 构建系统，那么 ULP 工具链已经被默认安装到了你的开发环境中。
|
||||
如果您已经按照 :doc:`快速入门指南 <../../../get-started/index>` 中的介绍安装好了 ESP-IDF 及其 CMake 构建系统，那么 ULP 工具链已经被默认安装到了您的开发环境中。
|
||||
|
||||
编写 ULP FSM
|
||||
-------------------
|
||||
|
||||
使用受支持的指令集即可编写 ULP FSM 协处理器，此外也可使用主处理器上的 C 语言宏进行编程。以下小节分别介绍了这两种方法：
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
{IDF_TARGET_NAME} ULP 指令集参考 <ulp_instruction_set>
|
||||
使用宏进行编程（遗留） <ulp_macros>
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
如果你的 ESP-IDF 仍在使用传统的基于 GNU Make 的构建系统，请参考 :doc:`ulp-legacy` 一文中的说明，完成工具链的安装。
|
||||
|
||||
编译 ULP 代码
|
||||
-------------
|
||||
--------------
|
||||
|
||||
若需要将 ULP 代码编译为某组件的一部分，则必须执行以下步骤：
|
||||
若需要将 ULP FSM 代码编译为某组件的一部分，则必须执行以下步骤：
|
||||
|
||||
1. 用汇编语言编写的 ULP 代码必须导入到一个或多个 `.S` 扩展文件中，且这些文件必须放在组件目录中一个独立的目录中，例如 `ulp/`。
|
||||
1. 用汇编语言编写的 ULP FSM 代码必须导入到一个或多个 `.S` 扩展文件中，且这些文件必须放在组件目录中一个独立的目录中，例如 `ulp/`。
|
||||
|
||||
.. note: 在注册组件（通过 ``idf_component_register``）时，不应将该目录添加到 ``SRC_DIRS`` 参数中。因为 ESP-IDF 构建系统将基于文件扩展名编译在 ``SRC_DIRS`` 中搜索到的文件。对于 ``.S`` 文件，使用的是 ``{IDF_TARGET_TOOLCHAIN_PREFIX}-as`` 汇编器。但这并不适用于 ULP 程序集文件，因此体现这种区别最简单的方式就是将 ULP 程序集文件放到单独的目录中。同样，ULP 程序集源文件也 **不应该** 添加到 ``SRCS`` 中。请参考如下步骤，查看如何正确添加 ULP 程序集源文件。
|
||||
.. note: 在注册组件（通过 ``idf_component_register``）时，不应将该目录添加到 ``SRC_DIRS`` 参数中。因为 ESP-IDF 构建系统将基于文件扩展名编译在 ``SRC_DIRS`` 中搜索到的文件。对于 ``.S`` 文件，使用的是 ``{IDF_TARGET_TOOLCHAIN_PREFIX}-as`` 汇编器。但这并不适用于 ULP FSM 程序集文件，因此体现这种区别最简单的方式就是将 ULP FSM 程序集文件放到单独的目录中。同样，ULP FSM 程序集源文件也 **不应该** 添加到 ``SRCS`` 中。请参考如下步骤，查看如何正确添加 ULP FSM 程序集源文件。
|
||||
|
||||
2. 注册后从组件 CMakeLists.txt 中调用 ``ulp_embed_binary`` 示例如下::
|
||||
|
||||
@ -50,11 +51,11 @@ ULP 协处理器代码是用汇编语言编写的，并使用 `binutils-esp32ulp
|
||||
|
||||
ulp_embed_binary(${ulp_app_name} "${ulp_s_sources}" "${ulp_exp_dep_srcs}")
|
||||
|
||||
``ulp_embed_binary`` 的第一个参数为 ULP 二进制文件命名。指定的此名称也用于生成的其他文件，如：ELF 文件、.map 文件、头文件和链接器导出文件。第二个参数指定 ULP 程序集源文件。最后，第三个参数指定组件源文件列表，其中包括被生成的头文件。此列表用以建立正确的依赖项，并确保在编译这些文件之前先创建生成的头文件。有关 ULP 应用程序生成的头文件等相关概念，请参考下文。
|
||||
``ulp_embed_binary`` 的第一个参数为 ULP 二进制文件命名。指定的此名称也用于生成的其他文件，如：ELF 文件、.map 文件、头文件和链接器导出文件。第二个参数指定 ULP FSM 程序集源文件。最后，第三个参数指定组件源文件列表，其中包括被生成的头文件。此列表用以建立正确的依赖项，并确保在编译这些文件之前先创建生成的头文件。有关 ULP FSM 应用程序生成的头文件等相关概念，请参考下文。
|
||||
|
||||
3. 使用常规方法（例如 `idf.py app`）编译应用程序
|
||||
3. 使用常规方法（例如 `idf.py app`）编译应用程序。
|
||||
|
||||
在内部，构建系统将按照以下步骤编译 ULP 程序：
|
||||
在内部，构建系统将按照以下步骤编译 ULP FSM 程序：
|
||||
|
||||
1. **通过 C 预处理器运行每个程序集文件 (foo.S)。** 此步骤在组件编译目录中生成预处理的程序集文件 (foo.ulp.S)，同时生成依赖文件 (foo.ulp.d)。
|
||||
|
||||
@ -62,7 +63,7 @@ ULP 协处理器代码是用汇编语言编写的，并使用 `binutils-esp32ulp
|
||||
|
||||
3. **通过 C 预处理器运行链接器脚本模板。** 模板位于 ``components/ulp/ld`` 目录中。
|
||||
|
||||
4. **将目标文件链接到 ELF 输出文件** (``ulp_app_name.elf``)。此步骤生成的.map 文件 (``ulp_app_name.map``) 默认用于调试。
|
||||
4. **将目标文件链接到 ELF 输出文件** (``ulp_app_name.elf``)。此步骤生成的 .map 文件 (``ulp_app_name.map``) 默认用于调试。
|
||||
|
||||
5. **将 ELF 文件中的内容转储为二进制文件** (``ulp_app_name.bin``)，以便嵌入到应用程序中。
|
||||
|
||||
@ -72,17 +73,17 @@ ULP 协处理器代码是用汇编语言编写的，并使用 `binutils-esp32ulp
|
||||
|
||||
8. **将生成的二进制文件添加到要嵌入应用程序的二进制文件列表中。**
|
||||
|
||||
访问 ULP 程序变量
|
||||
-----------------
|
||||
访问 ULP FSM 程序变量
|
||||
------------------------
|
||||
|
||||
在 ULP 程序中定义的全局符号也可以在主程序中使用。
|
||||
在 ULP FSM 程序中定义的全局符号也可以在主程序中使用。
|
||||
|
||||
例如，ULP 程序可以定义 ``measurement_count`` 变量，此变量可以定义程序从深度睡眠中唤醒芯片之前需要进行的 ADC 测量的次数::
|
||||
例如，ULP FSM 程序可以定义 ``measurement_count`` 变量，此变量可以定义程序从深度睡眠中唤醒芯片之前需要进行的 ADC 测量的次数::
|
||||
|
||||
.global measurement_count
|
||||
measurement_count: .long 0
|
||||
|
||||
/* later, use measurement_count */
|
||||
// later, use measurement_count
|
||||
move r3, measurement_count
|
||||
ld r3, r3, 0
|
||||
|
||||
@ -107,18 +108,18 @@ ULP 协处理器代码是用汇编语言编写的，并使用 `binutils-esp32ulp
|
||||
ulp_measurement_count = 64;
|
||||
}
|
||||
|
||||
注意，ULP 程序在 RTC 内存中只能使用 32 位字的低 16 位，因为寄存器是 16 位的，并且不具备从字的高位加载的指令。
|
||||
.. only:: esp32
|
||||
|
||||
同样，ULP 储存指令将寄存器值写入 32 位字的低 16 位中。高 16 位写入的值取决于储存指令的地址，因此在读取 ULP 写的变量时，主应用程序需要屏蔽高 16 位，例如::
|
||||
注意，ULP FSM 程序在 RTC 内存中只能使用 32 位字的低 16 位，因为寄存器是 16 位的，并且不具备从字的高位加载的指令。同样，ULP 储存指令将寄存器值写入 32 位字的低 16 位中。高 16 位写入的值取决于储存指令的地址，因此在读取 ULP 协处理器写的变量时，主应用程序需要屏蔽高 16 位，例如::
|
||||
|
||||
printf("Last measurement value: %d\n", ulp_last_measurement & UINT16_MAX);
|
||||
printf("Last measurement value: %d\n", ulp_last_measurement & UINT16_MAX);
|
||||
|
||||
启动 ULP 程序
|
||||
-------------
|
||||
启动 ULP FSM 程序
|
||||
--------------------
|
||||
|
||||
要运行 ULP 程序，主应用程序需要调用 ``ulp_load_binary`` 函数将 ULP 程序加载到 RTC 内存中，然后调用 ``ulp_run`` 函数，启动 ULP 程序。
|
||||
要运行 ULP FSM 程序，主应用程序需要调用 :cpp:func:`ulp_load_binary` 函数将 ULP 程序加载到 RTC 内存中，然后调用 :cpp:func:`ulp_run` 函数，启动 ULP 程序。
|
||||
|
||||
注意，在 menuconfig 中必须启用 "Enable Ultra Low Power (ULP) Coprocessor" 选项，以便为 ULP 预留内存。"RTC slow memory reserved for coprocessor" 选项设置的值必须足够储存 ULP 代码和数据。如果应用程序组件包含多个 ULP 程序，则 RTC 内存必须足以容纳最大的程序。
|
||||
注意，在 menuconfig 中必须启用 ``Enable Ultra Low Power (ULP) Coprocessor`` 选项，以便正常运行 ULP，并且必须设置 ``ULP Co-processor type`` 选项，以便选择要使用的 ULP 类型。 ``RTC slow memory reserved for coprocessor`` 选项设置的值必须足够储存 ULP 代码和数据。如果应用程序组件包含多个 ULP 程序，则 RTC 内存必须足以容纳最大的程序。
|
||||
|
||||
每个 ULP 程序均以二进制 BLOB 的形式嵌入到 ESP-IDF 应用程序中。应用程序可以引用此 BLOB，并以下面的方式加载此 BLOB（假设 ULP_APP_NAME 已被定义为 ``ulp_app_name``）::
|
||||
|
||||
@ -127,60 +128,62 @@ ULP 协处理器代码是用汇编语言编写的，并使用 `binutils-esp32ulp
|
||||
|
||||
void start_ulp_program() {
|
||||
ESP_ERROR_CHECK( ulp_load_binary(
|
||||
0 /* load address, set to 0 when using default linker scripts */,
|
||||
0 // load address, set to 0 when using default linker scripts
|
||||
bin_start,
|
||||
(bin_end - bin_start) / sizeof(uint32_t)) );
|
||||
}
|
||||
|
||||
.. doxygenfunction:: ulp_load_binary
|
||||
|
||||
一旦上述程序加载到 RTC 内存后，应用程序即可启动此程序，并将入口点的地址传递给 ``ulp_run`` 函数::
|
||||
|
||||
ESP_ERROR_CHECK( ulp_run(&ulp_entry - RTC_SLOW_MEM) );
|
||||
|
||||
.. doxygenfunction:: ulp_run
|
||||
|
||||
上述生成的头文件 ``${ULP_APP_NAME}.h`` 声明了入口点符号。在 ULP 应用程序的汇编源代码中，此符号必须标记为 ``.global``::
|
||||
|
||||
|
||||
.global entry
|
||||
entry:
|
||||
/* code starts here */
|
||||
// code starts here
|
||||
|
||||
.. only:: esp32
|
||||
|
||||
ESP32 ULP 程序流
|
||||
------------------
|
||||
-------------------
|
||||
|
||||
ESP32 ULP 协处理器由定时器启动，而调用 ``ulp_run`` 则可启动此定时器。定时器为 RTC_SLOW_CLK 的 Tick 事件计数（默认情况下，Tick 由内部 150 KHz RC 振荡器生成）。使用 ``SENS_ULP_CP_SLEEP_CYCx_REG`` 寄存器 (x = 0..4) 设置 Tick 数值。第一次启动 ULP 时，使用 ``SENS_ULP_CP_SLEEP_CYC0_REG`` 设置定时器 Tick 数值，之后，ULP 程序可以使用 ``sleep`` 指令来选择另一个 ``SENS_ULP_CP_SLEEP_CYCx_REG`` 寄存器。
|
||||
ESP32 ULP 协处理器由定时器启动，而调用 :cpp:func:`ulp_run` 则可启动此定时器。定时器为 RTC_SLOW_CLK 的 Tick 事件计数（默认情况下，Tick 由内部 150 KHz RC 振荡器生成）。使用 ``SENS_ULP_CP_SLEEP_CYCx_REG`` 寄存器 (x = 0..4) 设置 Tick 数值。第一次启动 ULP 时，使用 ``SENS_ULP_CP_SLEEP_CYC0_REG`` 设置定时器 Tick 数值，之后，ULP 程序可以使用 ``sleep`` 指令来选择另一个 ``SENS_ULP_CP_SLEEP_CYCx_REG`` 寄存器。
|
||||
|
||||
此应用程序可以调用 ``ulp_set_wakeup_period`` 函数来设置 ULP 定时器周期值 (SENS_ULP_CP_SLEEP_CYCx_REG, x = 0..4)。
|
||||
|
||||
.. doxygenfunction:: ulp_set_wakeup_period
|
||||
|
||||
一旦定时器计数到 ``SENS_ULP_CP_SLEEP_CYCx_REG`` 寄存器设定的 Tick 数值，ULP 协处理器就会启动，并调用 ``ulp_run`` 的入口点开始运行程序。
|
||||
一旦定时器计数到 ``SENS_ULP_CP_SLEEP_CYCx_REG`` 寄存器设定的 Tick 数值，ULP 协处理器就会启动，并调用 :cpp:func:`ulp_run` 的入口点开始运行程序。
|
||||
|
||||
程序保持运行，直到遇到 ``halt`` 指令或非法指令。一旦程序停止，ULP 协处理器电源关闭，定时器再次启动。
|
||||
|
||||
如果想禁用定时器（有效防止 ULP 程序再次运行），可在 ULP 代码或主程序中清除 ``RTC_CNTL_STATE0_REG`` 寄存器中的 ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` 位。
|
||||
|
||||
|
||||
.. only:: esp32s2
|
||||
.. only:: esp32s2 or esp32s3
|
||||
|
||||
ESP32-S2 ULP 程序流
|
||||
--------------------
|
||||
{IDF_TARGET_NAME} ULP 程序流
|
||||
----------------------------
|
||||
|
||||
ESP32-S2 ULP 协处理器由定时器启动，调用 ``ulp_run`` 则可启动此定时器。定时器为 RTC_SLOW_CLK 的 Tick 事件计数（默认情况下，Tick 由内部 90 KHz RC 振荡器生成）。使用 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 寄存器设置 Tick 数值。
|
||||
{IDF_TARGET_NAME} ULP 协处理器由定时器启动，调用 :cpp:func:`ulp_run` 则可启动此定时器。定时器为 RTC_SLOW_CLK 的 Tick 事件计数（默认情况下，Tick 由内部 90 KHz RC 振荡器生成）。使用 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 寄存器设置 Tick 数值。
|
||||
|
||||
此应用程序可以调用 ``ulp_set_wakeup_period`` 函数来设置 ULP 定时器周期值。
|
||||
此应用程序可以调用 :cpp:func:`ulp_set_wakeup_period` 函数来设置 ULP 定时器周期值。
|
||||
|
||||
.. doxygenfunction:: ulp_set_wakeup_period
|
||||
|
||||
一旦定时器计数到 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 寄存器设定的 Tick 数值，ULP 协处理器就会启动，并调用 ``ulp_run`` 的入口点开始运行程序。
|
||||
一旦定时器计数到 ``RTC_CNTL_ULP_CP_TIMER_1_REG`` 寄存器设定的 Tick 数值，ULP 协处理器就会启动，并调用 :cpp:func:`ulp_run` 的入口点开始运行程序。
|
||||
|
||||
程序保持运行，直到遇到 ``halt`` 指令或非法指令。一旦程序停止，ULP 协处理器电源关闭，定时器再次启动。
|
||||
|
||||
如果想禁用定时器（有效防止 ULP 程序再次运行），可在 ULP 代码或主程序中清除 ``RTC_CNTL_STATE0_REG`` 寄存器中的 ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` 位。
|
||||
如果想禁用定时器（有效防止 ULP 程序再次运行），可在 ULP 代码或主程序中清除 ``RTC_CNTL_ULP_CP_TIMER_REG`` 寄存器中的 ``RTC_CNTL_ULP_CP_SLP_TIMER_EN`` 位。
|
||||
|
||||
应用示例
|
||||
--------------------
|
||||
|
||||
.. _binutils-esp32ulp 工具链: https://github.com/espressif/binutils-esp32ulp
|
||||
* 主处理器处于 Deep-sleep 状态时，ULP FSM 协处理器对 IO 脉冲进行计数：:example:`system/ulp_fsm/ulp`。
|
||||
* 主处理器处于 Deep-sleep 状态时，ULP FSM 协处理器轮询 ADC：:example:`system/ulp_fsm/ulp_adc`。
|
||||
|
||||
API 参考
|
||||
-------------
|
||||
|
||||
.. include-build-file:: inc/ulp_common.inc
|
||||
|
||||
.. _binutils-esp32ulp 工具链: https://github.com/espressif/binutils-esp32ulp
|
||||
|
||||
@ -1 +1 @@
|
||||
.. include:: ../../en/api-guides/ulp_instruction_set.rst
|
||||
.. include:: ../../en/api-guides/ulp_instruction_set.rst
|
||||
|
||||
@ -1 +1 @@
|
||||
.. include:: ../../en/api-guides/ulp_macros.rst
|
||||
.. include:: ../../en/api-guides/ulp_macros.rst
|
||||
|
||||
@ -1 +0,0 @@
|
||||
.. include:: ../../en/api-guides/ulps2_instruction_set.rst
|
||||
@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 |
|
||||
| ----------------- | ----- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- |
|
||||
|
||||
# Deep Sleep Example
|
||||
|
||||
|
||||
@ -24,6 +24,10 @@
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/ulp.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/ulp.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/ulp.h"
|
||||
#endif
|
||||
|
||||
#if SOC_TOUCH_SENSOR_NUM > 0
|
||||
|
||||
@ -1,17 +1,17 @@
|
||||
| Supported Targets | ESP32 |
|
||||
| ----------------- | ----- |
|
||||
| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- |
|
||||
|
||||
# ULP Pulse Counting Example
|
||||
|
||||
This example demonstrates how to program the ULP coprocessor to count pulses on an IO while the main CPUs are either running some other code or are in deep sleep. See the README.md file in the upper level 'examples' directory for more information about examples.
|
||||
This example demonstrates how to program the ULP FSM coprocessor to count pulses on an IO while the main CPUs are either running some other code or are in deep sleep. See the README.md file in the upper level 'examples' directory for more information about examples.
|
||||
|
||||
ULP program written in assembly can be found across `ulp/pulse_cnt.S` and `ulp/wake_up.S` (demonstrating multiple ULP source files). The build system assembles and links this program, converts it into binary format, and embeds it into the .rodata section of the ESP-IDF application.
|
||||
|
||||
|
||||
At runtime, the main code running on the ESP32 (found in main.c) loads ULP program into the `RTC_SLOW_MEM` memory region using `ulp_load_binary` function. Main code configures the ULP program by setting up values of some variables and then starts it using `ulp_run`. Once the ULP program is started, it runs periodically, with the period set by the main program. The main program enables ULP wakeup source and puts the chip into deep sleep mode.
|
||||
|
||||
When the ULP program finds an edge in the input signal, it performs debouncing and increments the variable maintaining the total edge count. Once the edge count reaches certain value (set by the main program), ULP triggers wake up from deep sleep. Note that the ULP program keeps running and monitoring the input signal even when the SoC is woken up.
|
||||
|
||||
Upon wakeup, the main program saves total edge count into NVS and returns to deep sleep.
|
||||
Upon wakeup, the main program saves total edge count into NVS and returns to deep sleep.
|
||||
|
||||
In this example the input signal is connected to GPIO0. Note that this pin was chosen because most development boards have a button connected to it, so the pulses to be counted can be generated by pressing the button. For real world applications this is not a good choice of a pin, because GPIO0 also acts as a bootstrapping pin. To change the pin number, check the ESP32 Chip Pin List document and adjust `gpio_num` and `ulp_io_number` variables in main.c.
|
||||
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ULP Example: pulse counting
|
||||
|
||||
This example code is in the Public Domain (or CC0 licensed, at your option.)
|
||||
@ -22,9 +27,11 @@
|
||||
/* ULP assembly files are passed through C preprocessor first, so include directives
|
||||
and C macros may be used in these files
|
||||
*/
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "soc/soc_ulp.h"
|
||||
#include "soc/sens_reg.h"
|
||||
|
||||
/* Define variables, which go into .bss section (zero-initialized data) */
|
||||
.bss
|
||||
@ -70,6 +77,14 @@ entry:
|
||||
move r3, io_number
|
||||
ld r3, r3, 0
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
/* ESP32S2 powers down RTC periph when entering deep sleep and thus by association SENS_SAR_IO_MUX_CONF_REG */
|
||||
WRITE_RTC_FIELD(SENS_SAR_IO_MUX_CONF_REG, SENS_IOMUX_CLK_GATE_EN, 1)
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
/* ESP32S3 powers down RTC periph when entering deep sleep and thus by association SENS_SAR_PERI_CLK_GATE_CONF_REG */
|
||||
WRITE_RTC_FIELD(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_IOMUX_CLK_EN, 1);
|
||||
#endif
|
||||
|
||||
/* Lower 16 IOs and higher need to be handled separately,
|
||||
* because r0-r3 registers are 16 bit wide.
|
||||
* Check which IO this is.
|
||||
|
||||
@ -16,7 +16,15 @@
|
||||
#include "soc/rtc_periph.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "driver/rtc_io.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/ulp.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/ulp.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/ulp.h"
|
||||
#endif
|
||||
|
||||
#include "ulp_main.h"
|
||||
|
||||
extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_main_bin_start");
|
||||
@ -28,6 +36,7 @@ static void update_pulse_count(void);
|
||||
void app_main(void)
|
||||
{
|
||||
esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
|
||||
printf("cause %d\n", cause);
|
||||
if (cause != ESP_SLEEP_WAKEUP_ULP) {
|
||||
printf("Not ULP wakeup, initializing ULP\n");
|
||||
init_ulp_program();
|
||||
@ -74,12 +83,15 @@ static void init_ulp_program(void)
|
||||
rtc_gpio_pullup_dis(gpio_num);
|
||||
rtc_gpio_hold_en(gpio_num);
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
/* Disconnect GPIO12 and GPIO15 to remove current drain through
|
||||
* pullup/pulldown resistors.
|
||||
* pullup/pulldown resistors on modules which have these (e.g. ESP32-WROVER)
|
||||
* GPIO12 may be pulled high to select flash voltage.
|
||||
*/
|
||||
rtc_gpio_isolate(GPIO_NUM_12);
|
||||
rtc_gpio_isolate(GPIO_NUM_15);
|
||||
#endif // CONFIG_IDF_TARGET_ESP32
|
||||
|
||||
esp_deep_sleep_disable_rom_logging(); // suppress boot messages
|
||||
|
||||
/* Set ULP wake up period to T = 20ms.
|
||||
|
||||
@ -1,6 +1,3 @@
|
||||
# Enable ULP
|
||||
CONFIG_ESP32_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=1024
|
||||
# Set log level to Warning to produce clean output
|
||||
CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
|
||||
CONFIG_BOOTLOADER_LOG_LEVEL=2
|
||||
|
||||
3
examples/system/ulp_fsm/ulp/sdkconfig.defaults.esp32
Normal file
3
examples/system/ulp_fsm/ulp/sdkconfig.defaults.esp32
Normal file
@ -0,0 +1,3 @@
|
||||
# Enable ULP
|
||||
CONFIG_ESP32_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=1024
|
||||
3
examples/system/ulp_fsm/ulp/sdkconfig.defaults.esp32s2
Normal file
3
examples/system/ulp_fsm/ulp/sdkconfig.defaults.esp32s2
Normal file
@ -0,0 +1,3 @@
|
||||
# Enable ULP
|
||||
CONFIG_ESP32S2_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=1024
|
||||
3
examples/system/ulp_fsm/ulp/sdkconfig.defaults.esp32s3
Normal file
3
examples/system/ulp_fsm/ulp/sdkconfig.defaults.esp32s3
Normal file
@ -0,0 +1,3 @@
|
||||
# Enable ULP
|
||||
CONFIG_ESP32S3_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=1024
|
||||
@ -1,4 +1,3 @@
|
||||
CONFIG_IDF_TARGET="esp32s2"
|
||||
# Enable ULP
|
||||
CONFIG_ESP32S2_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32S2_ULP_COPROC_RISCV=y
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
| Supported Targets | ESP32-S2 |
|
||||
| ----------------- | -------- |
|
||||
| Supported Targets | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- |
|
||||
|
||||
# ULP-RISC-V simple example with GPIO Polling:
|
||||
|
||||
This example demonstrates how to program the ULP-RISC-V coprocessor to poll a gpio and wakeup the main CPU when it changes its state;
|
||||
|
||||
ULP program written in C can be found across `ulp/main.c`. The build system compiles and links this program, converts it into binary format, and embeds it into the .rodata section of the ESP-IDF application.
|
||||
|
||||
|
||||
At runtime, the application running inside the main CPU loads ULP program into the `RTC_SLOW_MEM` memory region using `ulp_riscv_load_binary` function. The main code then configures the ULP wakeup period and starts the coprocessor by using `ulp_riscv_run`. Once the ULP program is started, it runs periodically, with the period set by the main program. The main program enables ULP wakeup source and puts the chip into deep sleep mode.
|
||||
|
||||
When the ULP program finds an state changing in the pin, it saves the current state and sends a wakeup signal to the main CPU.
|
||||
@ -19,13 +19,13 @@ In this example the input signal is connected to GPIO0. Note that this pin was c
|
||||
## Example output
|
||||
|
||||
```
|
||||
Not a ULP wakeup, initializing it!
|
||||
Not a ULP wakeup, initializing it!
|
||||
Entering in deep sleep
|
||||
|
||||
...
|
||||
|
||||
ULP-RISC-V woke up the main CPU!
|
||||
ULP-RISC-V read changes in GPIO_0 current is: High
|
||||
ULP-RISC-V woke up the main CPU!
|
||||
ULP-RISC-V read changes in GPIO_0 current is: High
|
||||
Entering in deep sleep
|
||||
|
||||
```
|
||||
@ -1,13 +1,14 @@
|
||||
from __future__ import unicode_literals
|
||||
|
||||
import re
|
||||
import time
|
||||
|
||||
import tiny_test_fw
|
||||
import ttfw_idf
|
||||
from tiny_test_fw import DUT
|
||||
|
||||
|
||||
@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2'])
|
||||
@ttfw_idf.idf_example_test(env_tag='Example_GENERIC', target=['esp32s2', 'esp32s3'])
|
||||
def test_examples_ulp_riscv(env, extra_data): # type: (tiny_test_fw.Env.Env, None) -> None # pylint: disable=unused-argument
|
||||
dut = env.get_dut('ulp_riscv', 'examples/system/ulp_riscv/gpio')
|
||||
dut.start_app()
|
||||
@ -16,6 +17,9 @@ def test_examples_ulp_riscv(env, extra_data): # type: (tiny_test_fw.Env.Env, No
|
||||
'Entering in deep sleep',
|
||||
timeout=30)
|
||||
|
||||
# Give the chip time to enter deepsleep
|
||||
time.sleep(1)
|
||||
|
||||
# Run two times to make sure device sleep
|
||||
# and wake up properly
|
||||
for i in range(0, 2):
|
||||
|
||||
@ -1,8 +1,3 @@
|
||||
CONFIG_IDF_TARGET="esp32s2"
|
||||
# Enable ULP
|
||||
CONFIG_ESP32S2_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32S2_ULP_COPROC_RISCV=y
|
||||
CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=4096
|
||||
# Set log level to Warning to produce clean output
|
||||
CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
|
||||
CONFIG_BOOTLOADER_LOG_LEVEL=2
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
# Enable ULP
|
||||
CONFIG_ESP32S2_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32S2_ULP_COPROC_RISCV=y
|
||||
CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=4096
|
||||
@ -0,0 +1,4 @@
|
||||
# Enable ULP
|
||||
CONFIG_ESP32S3_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32S3_ULP_COPROC_RISCV=y
|
||||
CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=4096
|
||||
@ -1 +1,5 @@
|
||||
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240=y
|
||||
|
||||
CONFIG_ESP32S3_ULP_COPROC_ENABLED=y
|
||||
CONFIG_ESP32S3_ULP_COPROC_RISCV=y
|
||||
CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=4096
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user