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docs: fix syntax errors in only:: blocks

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Ivan Grokhotkov 2021-08-23 19:27:30 +02:00 committed by bot
parent 1a19014d3d
commit 19a75177a8
2 changed files with 2 additions and 2 deletions
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2
docs/en/api-reference/storage/spi_flash_concurrency.rst
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@ -24,7 +24,7 @@ There are no such constraints and impacts for flash chips on other SPI buses tha
For differences between IRAM, DRAM, and flash cache, please refer to the :ref:`application memory layout <memory-layout>` documentation. For differences between IRAM, DRAM, and flash cache, please refer to the :ref:`application memory layout <memory-layout>` documentation.
.. only: not CONFIG_FREERTOS_UNICORE .. only:: not CONFIG_FREERTOS_UNICORE
To avoid reading flash cache accidentally, when one CPU initiates a flash write or erase operation, the other CPU is put into a blocked state, and all non-IRAM-safe interrupts are disabled on all CPUs until the flash operation completes. To avoid reading flash cache accidentally, when one CPU initiates a flash write or erase operation, the other CPU is put into a blocked state, and all non-IRAM-safe interrupts are disabled on all CPUs until the flash operation completes.

2
docs/zh_CN/api-reference/storage/spi_flash_concurrency.rst
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@ -24,7 +24,7 @@ SPI1 Flash 并发约束
请参阅 :ref:`应用程序内存分布 <memory-layout>`，查看 IRAM、DRAM 和 flash cache 的区别。 请参阅 :ref:`应用程序内存分布 <memory-layout>`，查看 IRAM、DRAM 和 flash cache 的区别。
.. only: not CONFIG_FREERTOS_UNICORE .. only:: not CONFIG_FREERTOS_UNICORE
为避免意外读取 flash cache，一个 CPU 在启动 flash 写入或擦除操作时，另一个 CPU 将阻塞，并且在 flash 操作完成前，所有 CPU 上，所有的非 IRAM 安全的中断都会被禁用。 为避免意外读取 flash cache，一个 CPU 在启动 flash 写入或擦除操作时，另一个 CPU 将阻塞，并且在 flash 操作完成前，所有 CPU 上，所有的非 IRAM 安全的中断都会被禁用。