diff --git a/docs/en/api-reference/storage/spi_flash_concurrency.rst b/docs/en/api-reference/storage/spi_flash_concurrency.rst index 8e6e581768..a226b0a15a 100644 --- a/docs/en/api-reference/storage/spi_flash_concurrency.rst +++ b/docs/en/api-reference/storage/spi_flash_concurrency.rst @@ -24,7 +24,7 @@ There are no such constraints and impacts for flash chips on other SPI buses tha For differences between IRAM, DRAM, and flash cache, please refer to the :ref:`application memory layout ` documentation. -.. only: not CONFIG_FREERTOS_UNICORE +.. only:: not CONFIG_FREERTOS_UNICORE To avoid reading flash cache accidentally, when one CPU initiates a flash write or erase operation, the other CPU is put into a blocked state, and all non-IRAM-safe interrupts are disabled on all CPUs until the flash operation completes. diff --git a/docs/zh_CN/api-reference/storage/spi_flash_concurrency.rst b/docs/zh_CN/api-reference/storage/spi_flash_concurrency.rst index a5000ba3ac..4df013c0b5 100644 --- a/docs/zh_CN/api-reference/storage/spi_flash_concurrency.rst +++ b/docs/zh_CN/api-reference/storage/spi_flash_concurrency.rst @@ -24,7 +24,7 @@ SPI1 Flash 并发约束 请参阅 :ref:`应用程序内存分布 `，查看 IRAM、DRAM 和 flash cache 的区别。 -.. only: not CONFIG_FREERTOS_UNICORE +.. only:: not CONFIG_FREERTOS_UNICORE 为避免意外读取 flash cache，一个 CPU 在启动 flash 写入或擦除操作时，另一个 CPU 将阻塞，并且在 flash 操作完成前，所有 CPU 上，所有的非 IRAM 安全的中断都会被禁用。