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Merge branch 'fix/fix_cache_panic_c61_on_psram_board' into 'master'
cache: fixed cache panic init flow on psram board See merge request espressif/esp-idf!32701
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commit
11831cc0db
@ -61,12 +61,15 @@ void esp_cache_err_int_init(void)
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esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* On the hardware side, start by clearing all the bits responsible for cache access error */
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cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* Then enable cache access error interrupts. */
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cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* Enable the fail tracer */
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/**
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* Here we
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* 1. enable the cache fail tracer to take cache error interrupt into effect.
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* 2. clear potential cache error interrupt raw bits
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* 3. enable cache error interrupt en bits
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*/
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cache_ll_l1_enable_fail_tracer(0, true);
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cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* Enable the interrupts for cache error. */
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ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
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@ -60,12 +60,15 @@ void esp_cache_err_int_init(void)
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esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* On the hardware side, start by clearing all the bits responsible for cache access error */
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cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* Then enable cache access error interrupts. */
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cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* Enable the fail tracer */
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/**
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* Here we
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* 1. enable the cache fail tracer to take cache error interrupt into effect.
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* 2. clear potential cache error interrupt raw bits
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* 3. enable cache error interrupt en bits
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*/
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cache_ll_l1_enable_fail_tracer(0, true);
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cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* Enable the interrupts for cache error. */
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ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
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