From e58d6080343da07fffc25bc2761d0e0363629e92 Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 8 Aug 2024 17:51:02 +0800 Subject: [PATCH] fix(cache): fixed cache panic init flow on psram board --- .../esp_system/port/soc/esp32c5/cache_err_int.c | 13 ++++++++----- .../esp_system/port/soc/esp32c61/cache_err_int.c | 13 ++++++++----- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/components/esp_system/port/soc/esp32c5/cache_err_int.c b/components/esp_system/port/soc/esp32c5/cache_err_int.c index 3f5eccb7a3..0a86015545 100644 --- a/components/esp_system/port/soc/esp32c5/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c5/cache_err_int.c @@ -61,12 +61,15 @@ void esp_cache_err_int_init(void) esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); - /* On the hardware side, start by clearing all the bits responsible for cache access error */ - cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - /* Then enable cache access error interrupts. */ - cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - /* Enable the fail tracer */ + /** + * Here we + * 1. enable the cache fail tracer to take cache error interrupt into effect. + * 2. clear potential cache error interrupt raw bits + * 3. enable cache error interrupt en bits + */ cache_ll_l1_enable_fail_tracer(0, true); + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM); diff --git a/components/esp_system/port/soc/esp32c61/cache_err_int.c b/components/esp_system/port/soc/esp32c61/cache_err_int.c index 63b15acf28..e17c32f49d 100644 --- a/components/esp_system/port/soc/esp32c61/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c61/cache_err_int.c @@ -60,12 +60,15 @@ void esp_cache_err_int_init(void) esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); - /* On the hardware side, start by clearing all the bits responsible for cache access error */ - cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - /* Then enable cache access error interrupts. */ - cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); - /* Enable the fail tracer */ + /** + * Here we + * 1. enable the cache fail tracer to take cache error interrupt into effect. + * 2. clear potential cache error interrupt raw bits + * 3. enable cache error interrupt en bits + */ cache_ll_l1_enable_fail_tracer(0, true); + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Enable the interrupts for cache error. */ ESP_INTR_ENABLE(ETS_CACHEERR_INUM);