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Merge branch 'feature/add_esp32c5_beta3_soc_header_files_part2' into 'master'

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feat(esp32c5): add esp32c5-beta3 soc header files (stage2, part2)

See merge request espressif/esp-idf!27500
This commit is contained in:
Kevin (Lao Kaiyao) 2023-11-30 14:35:54 +08:00
commit 11461aff62
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368
components/soc/esp32c5/include/soc/aes_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* Key material key_0 configure register
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* Key material key_1 configure register
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
#define AES_KEY_1 0xFFFFFFFFU
#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S)
#define AES_KEY_1_V 0xFFFFFFFFU
#define AES_KEY_1_S 0
/** AES_KEY_2_REG register
* Key material key_2 configure register
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
#define AES_KEY_2 0xFFFFFFFFU
#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S)
#define AES_KEY_2_V 0xFFFFFFFFU
#define AES_KEY_2_S 0
/** AES_KEY_3_REG register
* Key material key_3 configure register
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
#define AES_KEY_3 0xFFFFFFFFU
#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S)
#define AES_KEY_3_V 0xFFFFFFFFU
#define AES_KEY_3_S 0
/** AES_KEY_4_REG register
* Key material key_4 configure register
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
#define AES_KEY_4 0xFFFFFFFFU
#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S)
#define AES_KEY_4_V 0xFFFFFFFFU
#define AES_KEY_4_S 0
/** AES_KEY_5_REG register
* Key material key_5 configure register
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
#define AES_KEY_5 0xFFFFFFFFU
#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S)
#define AES_KEY_5_V 0xFFFFFFFFU
#define AES_KEY_5_S 0
/** AES_KEY_6_REG register
* Key material key_6 configure register
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
#define AES_KEY_6 0xFFFFFFFFU
#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S)
#define AES_KEY_6_V 0xFFFFFFFFU
#define AES_KEY_6_S 0
/** AES_KEY_7_REG register
* Key material key_7 configure register
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
#define AES_KEY_7 0xFFFFFFFFU
#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S)
#define AES_KEY_7_V 0xFFFFFFFFU
#define AES_KEY_7_S 0
/** AES_TEXT_IN_0_REG register
* source text material text_in_0 configure register
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* source text material text_in_1 configure register
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
#define AES_TEXT_IN_1 0xFFFFFFFFU
#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
#define AES_TEXT_IN_1_V 0xFFFFFFFFU
#define AES_TEXT_IN_1_S 0
/** AES_TEXT_IN_2_REG register
* source text material text_in_2 configure register
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
#define AES_TEXT_IN_2 0xFFFFFFFFU
#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
#define AES_TEXT_IN_2_V 0xFFFFFFFFU
#define AES_TEXT_IN_2_S 0
/** AES_TEXT_IN_3_REG register
* source text material text_in_3 configure register
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
#define AES_TEXT_IN_3 0xFFFFFFFFU
#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
#define AES_TEXT_IN_3_V 0xFFFFFFFFU
#define AES_TEXT_IN_3_S 0
/** AES_TEXT_OUT_0_REG register
* result text material text_out_0 configure register
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* result text material text_out_1 configure register
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
#define AES_TEXT_OUT_1 0xFFFFFFFFU
#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
#define AES_TEXT_OUT_1_V 0xFFFFFFFFU
#define AES_TEXT_OUT_1_S 0
/** AES_TEXT_OUT_2_REG register
* result text material text_out_2 configure register
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
#define AES_TEXT_OUT_2 0xFFFFFFFFU
#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
#define AES_TEXT_OUT_2_V 0xFFFFFFFFU
#define AES_TEXT_OUT_2_S 0
/** AES_TEXT_OUT_3_REG register
* result text material text_out_3 configure register
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
#define AES_TEXT_OUT_3 0xFFFFFFFFU
#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
#define AES_TEXT_OUT_3_V 0xFFFFFFFFU
#define AES_TEXT_OUT_3_S 0
/** AES_MODE_REG register
* AES Mode register
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_TRIGGER_REG register
* AES trigger register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* AES state register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* DMA-AES working mode register
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* AES cipher block mode register
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* AES block number register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function configure register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_INT_CLEAR_REG register
* AES Interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* AES Interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x3FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x3FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* AES-DMA exit config
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: key register */
/** Type of key_0 register
* Key material key_0 configure register
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_0_reg_t;
/** Type of key_1 register
* Key material key_1 configure register
*/
typedef union {
struct {
/** key_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_1 that is a part of key material.
*/
uint32_t key_1:32;
};
uint32_t val;
} aes_key_1_reg_t;
/** Type of key_2 register
* Key material key_2 configure register
*/
typedef union {
struct {
/** key_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_2 that is a part of key material.
*/
uint32_t key_2:32;
};
uint32_t val;
} aes_key_2_reg_t;
/** Type of key_3 register
* Key material key_3 configure register
*/
typedef union {
struct {
/** key_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_3 that is a part of key material.
*/
uint32_t key_3:32;
};
uint32_t val;
} aes_key_3_reg_t;
/** Type of key_4 register
* Key material key_4 configure register
*/
typedef union {
struct {
/** key_4 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_4 that is a part of key material.
*/
uint32_t key_4:32;
};
uint32_t val;
} aes_key_4_reg_t;
/** Type of key_5 register
* Key material key_5 configure register
*/
typedef union {
struct {
/** key_5 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_5 that is a part of key material.
*/
uint32_t key_5:32;
};
uint32_t val;
} aes_key_5_reg_t;
/** Type of key_6 register
* Key material key_6 configure register
*/
typedef union {
struct {
/** key_6 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_6 that is a part of key material.
*/
uint32_t key_6:32;
};
uint32_t val;
} aes_key_6_reg_t;
/** Type of key_7 register
* Key material key_7 configure register
*/
typedef union {
struct {
/** key_7 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_7 that is a part of key material.
*/
uint32_t key_7:32;
};
uint32_t val;
} aes_key_7_reg_t;
/** Group: text in register */
/** Type of text_in_0 register
* source text material text_in_0 configure register
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_0_reg_t;
/** Type of text_in_1 register
* source text material text_in_1 configure register
*/
typedef union {
struct {
/** text_in_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_1 that is a part of source text material.
*/
uint32_t text_in_1:32;
};
uint32_t val;
} aes_text_in_1_reg_t;
/** Type of text_in_2 register
* source text material text_in_2 configure register
*/
typedef union {
struct {
/** text_in_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_2 that is a part of source text material.
*/
uint32_t text_in_2:32;
};
uint32_t val;
} aes_text_in_2_reg_t;
/** Type of text_in_3 register
* source text material text_in_3 configure register
*/
typedef union {
struct {
/** text_in_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_3 that is a part of source text material.
*/
uint32_t text_in_3:32;
};
uint32_t val;
} aes_text_in_3_reg_t;
/** Group: text out register */
/** Type of text_out_0 register
* result text material text_out_0 configure register
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_0_reg_t;
/** Type of text_out_1 register
* result text material text_out_1 configure register
*/
typedef union {
struct {
/** text_out_1 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_1 that is a part of result text material.
*/
uint32_t text_out_1:32;
};
uint32_t val;
} aes_text_out_1_reg_t;
/** Type of text_out_2 register
* result text material text_out_2 configure register
*/
typedef union {
struct {
/** text_out_2 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_2 that is a part of result text material.
*/
uint32_t text_out_2:32;
};
uint32_t val;
} aes_text_out_2_reg_t;
/** Type of text_out_3 register
* result text material text_out_3 configure register
*/
typedef union {
struct {
/** text_out_3 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_3 that is a part of result text material.
*/
uint32_t text_out_3:32;
};
uint32_t val;
} aes_text_out_3_reg_t;
/** Group: Configuration register */
/** Type of mode register
* AES Mode register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
* AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of block_mode register
* AES cipher block mode register
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* AES block number register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Those bits stores the number of Plaintext/ciphertext block.
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function configure register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Group: Control/Status register */
/** Type of trigger register
* AES trigger register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Set this bit to start AES calculation.
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of state register
* AES state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
* idle, 1: busy, 2: calculation_done.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Type of dma_enable register
* DMA-AES working mode register
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of dma_exit register
* AES-DMA exit config
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Set this register to leave calculation done stage. Recommend to use it after
* software finishes reading DMA's output buffer.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Group: memory type */
/** Group: interrupt register */
/** Type of int_clear register
* AES Interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Set this bit to clear the AES interrupt.
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* AES Interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538513936;
* This bits stores the version information of AES.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} aes_date_reg_t;
typedef struct {
volatile aes_key_0_reg_t key_0;
volatile aes_key_1_reg_t key_1;
volatile aes_key_2_reg_t key_2;
volatile aes_key_3_reg_t key_3;
volatile aes_key_4_reg_t key_4;
volatile aes_key_5_reg_t key_5;
volatile aes_key_6_reg_t key_6;
volatile aes_key_7_reg_t key_7;
volatile aes_text_in_0_reg_t text_in_0;
volatile aes_text_in_1_reg_t text_in_1;
volatile aes_text_in_2_reg_t text_in_2;
volatile aes_text_in_3_reg_t text_in_3;
volatile aes_text_out_0_reg_t text_out_0;
volatile aes_text_out_1_reg_t text_out_1;
volatile aes_text_out_2_reg_t text_out_2;
volatile aes_text_out_3_reg_t text_out_3;
volatile aes_mode_reg_t mode;
uint32_t reserved_044;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
uint32_t reserved_0a0[3];
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
} aes_dev_t;
extern aes_dev_t AES;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** DS_Y_MEM register
* memory that stores Y
*/
#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
#define DS_Y_MEM_SIZE_BYTES 512
/** DS_M_MEM register
* memory that stores M
*/
#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
#define DS_M_MEM_SIZE_BYTES 512
/** DS_RB_MEM register
* memory that stores Rb
*/
#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
#define DS_RB_MEM_SIZE_BYTES 512
/** DS_BOX_MEM register
* memory that stores BOX
*/
#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
#define DS_BOX_MEM_SIZE_BYTES 48
/** DS_IV_MEM register
* memory that stores IV
*/
#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
#define DS_IV_MEM_SIZE_BYTES 16
/** DS_X_MEM register
* memory that stores X
*/
#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
#define DS_X_MEM_SIZE_BYTES 512
/** DS_Z_MEM register
* memory that stores Z
*/
#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
#define DS_Z_MEM_SIZE_BYTES 512
/** DS_SET_START_REG register
* DS start control register
*/
#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
/** DS_SET_START : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
#define DS_SET_START (BIT(0))
#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S)
#define DS_SET_START_V 0x00000001U
#define DS_SET_START_S 0
/** DS_SET_CONTINUE_REG register
* DS continue control register
*/
#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
#define DS_SET_CONTINUE (BIT(0))
#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
#define DS_SET_CONTINUE_V 0x00000001U
#define DS_SET_CONTINUE_S 0
/** DS_SET_FINISH_REG register
* DS finish control register
*/
#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
#define DS_SET_FINISH (BIT(0))
#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S)
#define DS_SET_FINISH_V 0x00000001U
#define DS_SET_FINISH_S 0
/** DS_QUERY_BUSY_REG register
* DS query busy register
*/
#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
#define DS_QUERY_BUSY (BIT(0))
#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
#define DS_QUERY_BUSY_V 0x00000001U
#define DS_QUERY_BUSY_S 0
/** DS_QUERY_KEY_WRONG_REG register
* DS query key-wrong counter register
*/
#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
#define DS_QUERY_KEY_WRONG 0x0000000FU
#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
#define DS_QUERY_KEY_WRONG_V 0x0000000FU
#define DS_QUERY_KEY_WRONG_S 0
/** DS_QUERY_CHECK_REG register
* DS query check result register
*/
#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
#define DS_MD_ERROR (BIT(0))
#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S)
#define DS_MD_ERROR_V 0x00000001U
#define DS_MD_ERROR_S 0
/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
#define DS_PADDING_BAD (BIT(1))
#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
#define DS_PADDING_BAD_V 0x00000001U
#define DS_PADDING_BAD_S 1
/** DS_DATE_REG register
* DS version control register
*/
#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
#define DS_DATE 0x3FFFFFFFU
#define DS_DATE_M (DS_DATE_V << DS_DATE_S)
#define DS_DATE_V 0x3FFFFFFFU
#define DS_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: memory type */
/** Group: Control/Status registers */
/** Type of set_start register
* DS start control register
*/
typedef union {
struct {
/** set_start : WT; bitpos: [0]; default: 0;
* set this bit to start DS operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_start_reg_t;
/** Type of set_continue register
* DS continue control register
*/
typedef union {
struct {
/** set_continue : WT; bitpos: [0]; default: 0;
* set this bit to continue DS operation.
*/
uint32_t set_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_continue_reg_t;
/** Type of set_finish register
* DS finish control register
*/
typedef union {
struct {
/** set_finish : WT; bitpos: [0]; default: 0;
* Set this bit to finish DS process.
*/
uint32_t set_finish:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_set_finish_reg_t;
/** Type of query_busy register
* DS query busy register
*/
typedef union {
struct {
/** query_busy : RO; bitpos: [0]; default: 0;
* digital signature state. 1'b0: idle, 1'b1: busy
*/
uint32_t query_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ds_query_busy_reg_t;
/** Type of query_key_wrong register
* DS query key-wrong counter register
*/
typedef union {
struct {
/** query_key_wrong : RO; bitpos: [3:0]; default: 0;
* digital signature key wrong counter
*/
uint32_t query_key_wrong:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ds_query_key_wrong_reg_t;
/** Type of query_check register
* DS query check result register
*/
typedef union {
struct {
/** md_error : RO; bitpos: [0]; default: 0;
* MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
*/
uint32_t md_error:1;
/** padding_bad : RO; bitpos: [1]; default: 0;
* padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
*/
uint32_t padding_bad:1;
uint32_t reserved_2:30;
};
uint32_t val;
} ds_query_check_reg_t;
/** Group: version control register */
/** Type of date register
* DS version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* ds version information
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} ds_date_reg_t;
typedef struct {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];
volatile uint32_t box[12];
volatile uint32_t iv[4];
uint32_t reserved_640[112];
volatile uint32_t x[128];
volatile uint32_t z[128];
uint32_t reserved_c00[128];
volatile ds_set_start_reg_t set_start;
volatile ds_set_continue_reg_t set_continue;
volatile ds_set_finish_reg_t set_finish;
volatile ds_query_busy_reg_t query_busy;
volatile ds_query_key_wrong_reg_t query_key_wrong;
volatile ds_query_check_reg_t query_check;
uint32_t reserved_e18[2];
volatile ds_date_reg_t date;
} ds_dev_t;
extern ds_dev_t DS;
#ifndef __cplusplus
_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ATOMIC_ADDR_LOCK_REG register
* hardware lock regsiter
*/
#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
* read to acquire hardware lock, write to release hardware lock
*/
#define ATOMIC_LOCK 0x00000003U
#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S)
#define ATOMIC_LOCK_V 0x00000003U
#define ATOMIC_LOCK_S 0
/** ATOMIC_LR_ADDR_REG register
* gloable lr address regsiter
*/
#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
* backup gloable address
*/
#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S)
#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_ADDR_S 0
/** ATOMIC_LR_VALUE_REG register
* gloable lr value regsiter
*/
#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
* backup gloable value
*/
#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S)
#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU
#define ATOMIC_GLOABLE_LR_VALUE_S 0
/** ATOMIC_LOCK_STATUS_REG register
* lock status regsiter
*/
#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
* read hareware lock status for debug
*/
#define ATOMIC_LOCK_STATUS 0x00000003U
#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
#define ATOMIC_LOCK_STATUS_V 0x00000003U
#define ATOMIC_LOCK_STATUS_S 0
/** ATOMIC_COUNTER_REG register
* wait counter register
*/
#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10)
/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0;
* delay counter
*/
#define ATOMIC_WAIT_COUNTER 0x0000FFFFU
#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S)
#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU
#define ATOMIC_WAIT_COUNTER_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of addr_lock register
* hardware lock regsiter
*/
typedef union {
struct {
/** lock : R/W; bitpos: [1:0]; default: 0;
* read to acquire hardware lock, write to release hardware lock
*/
uint32_t lock:2;
uint32_t reserved_2:30;
};
uint32_t val;
} atomic_addr_lock_reg_t;
/** Type of lr_addr register
* gloable lr address regsiter
*/
typedef union {
struct {
/** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0;
* backup gloable address
*/
uint32_t gloable_lr_addr:32;
};
uint32_t val;
} atomic_lr_addr_reg_t;
/** Type of lr_value register
* gloable lr value regsiter
*/
typedef union {
struct {
/** gloable_lr_value : R/W; bitpos: [31:0]; default: 0;
* backup gloable value
*/
uint32_t gloable_lr_value:32;
};
uint32_t val;
} atomic_lr_value_reg_t;
/** Type of lock_status register
* lock status regsiter
*/
typedef union {
struct {
/** lock_status : RO; bitpos: [1:0]; default: 0;
* read hareware lock status for debug
*/
uint32_t lock_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} atomic_lock_status_reg_t;
/** Type of counter register
* wait counter register
*/
typedef union {
struct {
/** wait_counter : R/W; bitpos: [15:0]; default: 0;
* delay counter
*/
uint32_t wait_counter:16;
uint32_t reserved_16:16;
};
uint32_t val;
} atomic_counter_reg_t;
typedef struct {
volatile atomic_addr_lock_reg_t addr_lock;
volatile atomic_lr_addr_reg_t lr_addr;
volatile atomic_lr_value_reg_t lr_value;
volatile atomic_lock_status_reg_t lock_status;
volatile atomic_counter_reg_t counter;
} atomic_dev_t;
extern atomic_dev_t ATOMIC_LOCKER;
#ifndef __cplusplus
_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* Process control register 0.
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* Configure purpose.
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* Configure key.
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* Finish initial configuration.
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* Process control register 1.
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* Process control register 2.
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* Process control register 3.
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* Process control register 4.
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate register 0.
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate register 1.
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Error register.
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy register.
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Process control register 5.
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* Process control register 6.
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Jtag register 1.
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Date register.
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of set_start register
* Process control register 0.
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Start hmac operation.
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_purpose register
* Configure purpose.
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Set hmac parameter purpose.
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* Configure key.
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Set hmac parameter key.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of set_para_finish register
* Finish initial configuration.
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Finish hmac configuration.
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* Process control register 1.
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Call SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* Process control register 2.
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Continue typical hmac.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* Process control register 3.
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Start hardware padding.
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* Process control register 4.
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* After read result from upstream, then let hmac back to idle.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate register 0.
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream JTAG.
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate register 1.
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Clear result from hmac downstream DS.
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of set_message_pad register
* Process control register 5.
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Start software padding.
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* Process control register 6.
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Don't have to do padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Turn on JTAG verification.
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Type of wr_jtag register
* Jtag register 1.
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* 32-bit of key to be compared.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Status Register */
/** Type of query_error register
* Error register.
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Hmac configuration state. 0: key are agree with purpose. 1: error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy register.
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Hmac state. 1'b0: idle. 1'b1: busy
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Group: Memory Type */
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 538969624;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
uint32_t reserved_070[4];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
extern hmac_dev_t HMAC;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
*/
#define HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYS_BASE + 0x0)
/** HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
*/
#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S)
#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S 0
/** HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
/** HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
*/
#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
/** HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
*/
#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
/** HP_SYS_SRAM_USAGE_CONF_REG register
* HP memory usage configuration register
*/
#define HP_SYS_SRAM_USAGE_CONF_REG (DR_REG_HP_SYS_BASE + 0x4)
/** HP_SYS_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
#define HP_SYS_SRAM_USAGE 0x0000000FU
#define HP_SYS_SRAM_USAGE_M (HP_SYS_SRAM_USAGE_V << HP_SYS_SRAM_USAGE_S)
#define HP_SYS_SRAM_USAGE_V 0x0000000FU
#define HP_SYS_SRAM_USAGE_S 8
/** HP_SYS_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
#define HP_SYS_MAC_DUMP_ALLOC (BIT(16))
#define HP_SYS_MAC_DUMP_ALLOC_M (HP_SYS_MAC_DUMP_ALLOC_V << HP_SYS_MAC_DUMP_ALLOC_S)
#define HP_SYS_MAC_DUMP_ALLOC_V 0x00000001U
#define HP_SYS_MAC_DUMP_ALLOC_S 16
/** HP_SYS_SEC_DPA_CONF_REG register
* HP anti-DPA security configuration register
*/
#define HP_SYS_SEC_DPA_CONF_REG (DR_REG_HP_SYS_BASE + 0x8)
/** HP_SYS_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0.
*/
#define HP_SYS_SEC_DPA_LEVEL 0x00000003U
#define HP_SYS_SEC_DPA_LEVEL_M (HP_SYS_SEC_DPA_LEVEL_V << HP_SYS_SEC_DPA_LEVEL_S)
#define HP_SYS_SEC_DPA_LEVEL_V 0x00000003U
#define HP_SYS_SEC_DPA_LEVEL_S 0
/** HP_SYS_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
* This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
*/
#define HP_SYS_SEC_DPA_CFG_SEL (BIT(2))
#define HP_SYS_SEC_DPA_CFG_SEL_M (HP_SYS_SEC_DPA_CFG_SEL_V << HP_SYS_SEC_DPA_CFG_SEL_S)
#define HP_SYS_SEC_DPA_CFG_SEL_V 0x00000001U
#define HP_SYS_SEC_DPA_CFG_SEL_S 2
/** HP_SYS_CPU_PERI_TIMEOUT_CONF_REG register
* CPU_PERI_TIMEOUT configuration register
*/
#define HP_SYS_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0xc)
/** HP_SYS_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYS_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYS_CPU_PERI_TIMEOUT_THRES_M (HP_SYS_CPU_PERI_TIMEOUT_THRES_V << HP_SYS_CPU_PERI_TIMEOUT_THRES_S)
#define HP_SYS_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYS_CPU_PERI_TIMEOUT_THRES_S 0
/** HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
* registers
*/
#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG register
* CPU_PERI_TIMEOUT_ADDR register
*/
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x10)
/** HP_SYS_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_M (HP_SYS_CPU_PERI_TIMEOUT_ADDR_V << HP_SYS_CPU_PERI_TIMEOUT_ADDR_S)
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_S 0
/** HP_SYS_CPU_PERI_TIMEOUT_UID_REG register
* CPU_PERI_TIMEOUT_UID register
*/
#define HP_SYS_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x14)
/** HP_SYS_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYS_CPU_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYS_CPU_PERI_TIMEOUT_UID_M (HP_SYS_CPU_PERI_TIMEOUT_UID_V << HP_SYS_CPU_PERI_TIMEOUT_UID_S)
#define HP_SYS_CPU_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYS_CPU_PERI_TIMEOUT_UID_S 0
/** HP_SYS_HP_PERI_TIMEOUT_CONF_REG register
* HP_PERI_TIMEOUT configuration register
*/
#define HP_SYS_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x18)
/** HP_SYS_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYS_HP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYS_HP_PERI_TIMEOUT_THRES_M (HP_SYS_HP_PERI_TIMEOUT_THRES_V << HP_SYS_HP_PERI_TIMEOUT_THRES_S)
#define HP_SYS_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYS_HP_PERI_TIMEOUT_THRES_S 0
/** HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
*/
#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYS_HP_PERI_TIMEOUT_ADDR_REG register
* HP_PERI_TIMEOUT_ADDR register
*/
#define HP_SYS_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x1c)
/** HP_SYS_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYS_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYS_HP_PERI_TIMEOUT_ADDR_M (HP_SYS_HP_PERI_TIMEOUT_ADDR_V << HP_SYS_HP_PERI_TIMEOUT_ADDR_S)
#define HP_SYS_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYS_HP_PERI_TIMEOUT_ADDR_S 0
/** HP_SYS_HP_PERI_TIMEOUT_UID_REG register
* HP_PERI_TIMEOUT_UID register
*/
#define HP_SYS_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x20)
/** HP_SYS_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYS_HP_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYS_HP_PERI_TIMEOUT_UID_M (HP_SYS_HP_PERI_TIMEOUT_UID_V << HP_SYS_HP_PERI_TIMEOUT_UID_S)
#define HP_SYS_HP_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYS_HP_PERI_TIMEOUT_UID_S 0
/** HP_SYS_SDIO_CTRL_REG register
* SDIO Control configuration register
*/
#define HP_SYS_SDIO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x30)
/** HP_SYS_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
#define HP_SYS_DIS_SDIO_PROB (BIT(0))
#define HP_SYS_DIS_SDIO_PROB_M (HP_SYS_DIS_SDIO_PROB_V << HP_SYS_DIS_SDIO_PROB_S)
#define HP_SYS_DIS_SDIO_PROB_V 0x00000001U
#define HP_SYS_DIS_SDIO_PROB_S 0
/** HP_SYS_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
#define HP_SYS_SDIO_WIN_ACCESS_EN (BIT(1))
#define HP_SYS_SDIO_WIN_ACCESS_EN_M (HP_SYS_SDIO_WIN_ACCESS_EN_V << HP_SYS_SDIO_WIN_ACCESS_EN_S)
#define HP_SYS_SDIO_WIN_ACCESS_EN_V 0x00000001U
#define HP_SYS_SDIO_WIN_ACCESS_EN_S 1
/** HP_SYS_ROM_TABLE_LOCK_REG register
* Rom-Table lock register
*/
#define HP_SYS_ROM_TABLE_LOCK_REG (DR_REG_HP_SYS_BASE + 0x38)
/** HP_SYS_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
* XXXX
*/
#define HP_SYS_ROM_TABLE_LOCK (BIT(0))
#define HP_SYS_ROM_TABLE_LOCK_M (HP_SYS_ROM_TABLE_LOCK_V << HP_SYS_ROM_TABLE_LOCK_S)
#define HP_SYS_ROM_TABLE_LOCK_V 0x00000001U
#define HP_SYS_ROM_TABLE_LOCK_S 0
/** HP_SYS_ROM_TABLE_REG register
* Rom-Table register
*/
#define HP_SYS_ROM_TABLE_REG (DR_REG_HP_SYS_BASE + 0x3c)
/** HP_SYS_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
* XXXX
*/
#define HP_SYS_ROM_TABLE 0xFFFFFFFFU
#define HP_SYS_ROM_TABLE_M (HP_SYS_ROM_TABLE_V << HP_SYS_ROM_TABLE_S)
#define HP_SYS_ROM_TABLE_V 0xFFFFFFFFU
#define HP_SYS_ROM_TABLE_S 0
/** HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG register
* Core Debug runstall configure register
*/
#define HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x40)
/** HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
* Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
*/
#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0))
#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S)
#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V 0x00000001U
#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S 0
/** HP_SYS_CORE_RUNSTALLED : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
* not stalled.
*/
#define HP_SYS_CORE_RUNSTALLED (BIT(1))
#define HP_SYS_CORE_RUNSTALLED_M (HP_SYS_CORE_RUNSTALLED_V << HP_SYS_CORE_RUNSTALLED_S)
#define HP_SYS_CORE_RUNSTALLED_V 0x00000001U
#define HP_SYS_CORE_RUNSTALLED_S 1
/** HP_SYS_SPROM_CTRL_REG register
* reserved
*/
#define HP_SYS_SPROM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
/** HP_SYS_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
* reserved
*/
#define HP_SYS_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYS_SPROM_MEM_AUX_CTRL_M (HP_SYS_SPROM_MEM_AUX_CTRL_V << HP_SYS_SPROM_MEM_AUX_CTRL_S)
#define HP_SYS_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYS_SPROM_MEM_AUX_CTRL_S 0
/** HP_SYS_SPRAM_CTRL_REG register
* reserved
*/
#define HP_SYS_SPRAM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x74)
/** HP_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
#define HP_SYS_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYS_SPRAM_MEM_AUX_CTRL_M (HP_SYS_SPRAM_MEM_AUX_CTRL_V << HP_SYS_SPRAM_MEM_AUX_CTRL_S)
#define HP_SYS_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYS_SPRAM_MEM_AUX_CTRL_S 0
/** HP_SYS_SPRF_CTRL_REG register
* reserved
*/
#define HP_SYS_SPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x78)
/** HP_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
#define HP_SYS_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYS_SPRF_MEM_AUX_CTRL_M (HP_SYS_SPRF_MEM_AUX_CTRL_V << HP_SYS_SPRF_MEM_AUX_CTRL_S)
#define HP_SYS_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYS_SPRF_MEM_AUX_CTRL_S 0
/** HP_SYS_SDPRF_CTRL_REG register
* reserved
*/
#define HP_SYS_SDPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x7c)
/** HP_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
#define HP_SYS_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define HP_SYS_SDPRF_MEM_AUX_CTRL_M (HP_SYS_SDPRF_MEM_AUX_CTRL_V << HP_SYS_SDPRF_MEM_AUX_CTRL_S)
#define HP_SYS_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define HP_SYS_SDPRF_MEM_AUX_CTRL_S 0
/** HP_SYS_AUDIO_CODEX_CTRL0_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEX_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x80)
/** HP_SYS_DAC_IN_R1_IE : R/W; bitpos: [0]; default: 1;
* reserved
*/
#define HP_SYS_DAC_IN_R1_IE (BIT(0))
#define HP_SYS_DAC_IN_R1_IE_M (HP_SYS_DAC_IN_R1_IE_V << HP_SYS_DAC_IN_R1_IE_S)
#define HP_SYS_DAC_IN_R1_IE_V 0x00000001U
#define HP_SYS_DAC_IN_R1_IE_S 0
/** HP_SYS_DAC_IN_R1_OE : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYS_DAC_IN_R1_OE (BIT(1))
#define HP_SYS_DAC_IN_R1_OE_M (HP_SYS_DAC_IN_R1_OE_V << HP_SYS_DAC_IN_R1_OE_S)
#define HP_SYS_DAC_IN_R1_OE_V 0x00000001U
#define HP_SYS_DAC_IN_R1_OE_S 1
/** HP_SYS_DAC_IN_R0_IE : R/W; bitpos: [2]; default: 1;
* reserved
*/
#define HP_SYS_DAC_IN_R0_IE (BIT(2))
#define HP_SYS_DAC_IN_R0_IE_M (HP_SYS_DAC_IN_R0_IE_V << HP_SYS_DAC_IN_R0_IE_S)
#define HP_SYS_DAC_IN_R0_IE_V 0x00000001U
#define HP_SYS_DAC_IN_R0_IE_S 2
/** HP_SYS_DAC_IN_R0_OE : R/W; bitpos: [3]; default: 0;
* reserved
*/
#define HP_SYS_DAC_IN_R0_OE (BIT(3))
#define HP_SYS_DAC_IN_R0_OE_M (HP_SYS_DAC_IN_R0_OE_V << HP_SYS_DAC_IN_R0_OE_S)
#define HP_SYS_DAC_IN_R0_OE_V 0x00000001U
#define HP_SYS_DAC_IN_R0_OE_S 3
/** HP_SYS_ADC_DATA_4_IE : R/W; bitpos: [4]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_4_IE (BIT(4))
#define HP_SYS_ADC_DATA_4_IE_M (HP_SYS_ADC_DATA_4_IE_V << HP_SYS_ADC_DATA_4_IE_S)
#define HP_SYS_ADC_DATA_4_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_4_IE_S 4
/** HP_SYS_ADC_DATA_4_OE : R/W; bitpos: [5]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_4_OE (BIT(5))
#define HP_SYS_ADC_DATA_4_OE_M (HP_SYS_ADC_DATA_4_OE_V << HP_SYS_ADC_DATA_4_OE_S)
#define HP_SYS_ADC_DATA_4_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_4_OE_S 5
/** HP_SYS_ADC_DATA_3_IE : R/W; bitpos: [6]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_3_IE (BIT(6))
#define HP_SYS_ADC_DATA_3_IE_M (HP_SYS_ADC_DATA_3_IE_V << HP_SYS_ADC_DATA_3_IE_S)
#define HP_SYS_ADC_DATA_3_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_3_IE_S 6
/** HP_SYS_ADC_DATA_3_OE : R/W; bitpos: [7]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_3_OE (BIT(7))
#define HP_SYS_ADC_DATA_3_OE_M (HP_SYS_ADC_DATA_3_OE_V << HP_SYS_ADC_DATA_3_OE_S)
#define HP_SYS_ADC_DATA_3_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_3_OE_S 7
/** HP_SYS_ADC_DATA_2_IE : R/W; bitpos: [8]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_2_IE (BIT(8))
#define HP_SYS_ADC_DATA_2_IE_M (HP_SYS_ADC_DATA_2_IE_V << HP_SYS_ADC_DATA_2_IE_S)
#define HP_SYS_ADC_DATA_2_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_2_IE_S 8
/** HP_SYS_ADC_DATA_2_OE : R/W; bitpos: [9]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_2_OE (BIT(9))
#define HP_SYS_ADC_DATA_2_OE_M (HP_SYS_ADC_DATA_2_OE_V << HP_SYS_ADC_DATA_2_OE_S)
#define HP_SYS_ADC_DATA_2_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_2_OE_S 9
/** HP_SYS_ADC_DATA_1_IE : R/W; bitpos: [10]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_1_IE (BIT(10))
#define HP_SYS_ADC_DATA_1_IE_M (HP_SYS_ADC_DATA_1_IE_V << HP_SYS_ADC_DATA_1_IE_S)
#define HP_SYS_ADC_DATA_1_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_1_IE_S 10
/** HP_SYS_ADC_DATA_1_OE : R/W; bitpos: [11]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_1_OE (BIT(11))
#define HP_SYS_ADC_DATA_1_OE_M (HP_SYS_ADC_DATA_1_OE_V << HP_SYS_ADC_DATA_1_OE_S)
#define HP_SYS_ADC_DATA_1_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_1_OE_S 11
/** HP_SYS_ADC_DATA_0_IE : R/W; bitpos: [12]; default: 0;
* reserved
*/
#define HP_SYS_ADC_DATA_0_IE (BIT(12))
#define HP_SYS_ADC_DATA_0_IE_M (HP_SYS_ADC_DATA_0_IE_V << HP_SYS_ADC_DATA_0_IE_S)
#define HP_SYS_ADC_DATA_0_IE_V 0x00000001U
#define HP_SYS_ADC_DATA_0_IE_S 12
/** HP_SYS_ADC_DATA_0_OE : R/W; bitpos: [13]; default: 1;
* reserved
*/
#define HP_SYS_ADC_DATA_0_OE (BIT(13))
#define HP_SYS_ADC_DATA_0_OE_M (HP_SYS_ADC_DATA_0_OE_V << HP_SYS_ADC_DATA_0_OE_S)
#define HP_SYS_ADC_DATA_0_OE_V 0x00000001U
#define HP_SYS_ADC_DATA_0_OE_S 13
/** HP_SYS_ADC_CK_DATA_IE : R/W; bitpos: [14]; default: 0;
* reserved
*/
#define HP_SYS_ADC_CK_DATA_IE (BIT(14))
#define HP_SYS_ADC_CK_DATA_IE_M (HP_SYS_ADC_CK_DATA_IE_V << HP_SYS_ADC_CK_DATA_IE_S)
#define HP_SYS_ADC_CK_DATA_IE_V 0x00000001U
#define HP_SYS_ADC_CK_DATA_IE_S 14
/** HP_SYS_ADC_CK_DATA_OE : R/W; bitpos: [15]; default: 1;
* reserved
*/
#define HP_SYS_ADC_CK_DATA_OE (BIT(15))
#define HP_SYS_ADC_CK_DATA_OE_M (HP_SYS_ADC_CK_DATA_OE_V << HP_SYS_ADC_CK_DATA_OE_S)
#define HP_SYS_ADC_CK_DATA_OE_V 0x00000001U
#define HP_SYS_ADC_CK_DATA_OE_S 15
/** HP_SYS_DATE_REG register
* Date register.
*/
#define HP_SYS_DATE_REG (DR_REG_HP_SYS_BASE + 0x3fc)
/** HP_SYS_DATE : R/W; bitpos: [27:0]; default: 36720768;
* HP-SYSTEM date information/ HP-SYSTEM version information.
*/
#define HP_SYS_DATE 0x0FFFFFFFU
#define HP_SYS_DATE_M (HP_SYS_DATE_V << HP_SYS_DATE_S)
#define HP_SYS_DATE_V 0x0FFFFFFFU
#define HP_SYS_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/include/soc/hp_system_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of external_device_encrypt_decrypt_control register
* EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
*/
typedef union {
struct {
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
*/
uint32_t enable_spi_manual_encrypt:1;
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t enable_download_db_encrypt:1;
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
* Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
*/
uint32_t enable_download_g0cb_decrypt:1;
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
* Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
*/
uint32_t enable_download_manual_encrypt:1;
uint32_t reserved_4:28;
};
uint32_t val;
} hp_sys_external_device_encrypt_decrypt_control_reg_t;
/** Type of sram_usage_conf register
* HP memory usage configuration register
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** sram_usage : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
uint32_t sram_usage:4;
uint32_t reserved_12:4;
/** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
*/
uint32_t mac_dump_alloc:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hp_sys_sram_usage_conf_reg_t;
/** Type of sec_dpa_conf register
* HP anti-DPA security configuration register
*/
typedef union {
struct {
/** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0.
*/
uint32_t sec_dpa_level:2;
/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
* This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
* (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
*/
uint32_t sec_dpa_cfg_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
} hp_sys_sec_dpa_conf_reg_t;
/** Type of sdio_ctrl register
* SDIO Control configuration register
*/
typedef union {
struct {
/** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
* Set this bit as 1 to disable SDIO_PROB function. disable by default.
*/
uint32_t dis_sdio_prob:1;
/** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
* Enable sdio slave to access other peripherals on the chip
*/
uint32_t sdio_win_access_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_sys_sdio_ctrl_reg_t;
/** Type of rom_table_lock register
* Rom-Table lock register
*/
typedef union {
struct {
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
* XXXX
*/
uint32_t rom_table_lock:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_sys_rom_table_lock_reg_t;
/** Type of rom_table register
* Rom-Table register
*/
typedef union {
struct {
/** rom_table : R/W; bitpos: [31:0]; default: 0;
* XXXX
*/
uint32_t rom_table:32;
};
uint32_t val;
} hp_sys_rom_table_reg_t;
/** Type of core_debug_runstall_conf register
* Core Debug runstall configure register
*/
typedef union {
struct {
/** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
* Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
*/
uint32_t core_debug_runstall_enable:1;
/** core_runstalled : RO; bitpos: [1]; default: 0;
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
* not stalled.
*/
uint32_t core_runstalled:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_sys_core_debug_runstall_conf_reg_t;
/** Type of sprom_ctrl register
* reserved
*/
typedef union {
struct {
/** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
* reserved
*/
uint32_t sprom_mem_aux_ctrl:32;
};
uint32_t val;
} hp_sys_sprom_ctrl_reg_t;
/** Type of spram_ctrl register
* reserved
*/
typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
uint32_t spram_mem_aux_ctrl:32;
};
uint32_t val;
} hp_sys_spram_ctrl_reg_t;
/** Type of sprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* reserved
*/
uint32_t sprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_sys_sprf_ctrl_reg_t;
/** Type of sdprf_ctrl register
* reserved
*/
typedef union {
struct {
/** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
* reserved
*/
uint32_t sdprf_mem_aux_ctrl:32;
};
uint32_t val;
} hp_sys_sdprf_ctrl_reg_t;
/** Type of audio_codex_ctrl0 register
* reserved
*/
typedef union {
struct {
/** dac_in_r1_ie : R/W; bitpos: [0]; default: 1;
* reserved
*/
uint32_t dac_in_r1_ie:1;
/** dac_in_r1_oe : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t dac_in_r1_oe:1;
/** dac_in_r0_ie : R/W; bitpos: [2]; default: 1;
* reserved
*/
uint32_t dac_in_r0_ie:1;
/** dac_in_r0_oe : R/W; bitpos: [3]; default: 0;
* reserved
*/
uint32_t dac_in_r0_oe:1;
/** adc_data_4_ie : R/W; bitpos: [4]; default: 0;
* reserved
*/
uint32_t adc_data_4_ie:1;
/** adc_data_4_oe : R/W; bitpos: [5]; default: 1;
* reserved
*/
uint32_t adc_data_4_oe:1;
/** adc_data_3_ie : R/W; bitpos: [6]; default: 0;
* reserved
*/
uint32_t adc_data_3_ie:1;
/** adc_data_3_oe : R/W; bitpos: [7]; default: 1;
* reserved
*/
uint32_t adc_data_3_oe:1;
/** adc_data_2_ie : R/W; bitpos: [8]; default: 0;
* reserved
*/
uint32_t adc_data_2_ie:1;
/** adc_data_2_oe : R/W; bitpos: [9]; default: 1;
* reserved
*/
uint32_t adc_data_2_oe:1;
/** adc_data_1_ie : R/W; bitpos: [10]; default: 0;
* reserved
*/
uint32_t adc_data_1_ie:1;
/** adc_data_1_oe : R/W; bitpos: [11]; default: 1;
* reserved
*/
uint32_t adc_data_1_oe:1;
/** adc_data_0_ie : R/W; bitpos: [12]; default: 0;
* reserved
*/
uint32_t adc_data_0_ie:1;
/** adc_data_0_oe : R/W; bitpos: [13]; default: 1;
* reserved
*/
uint32_t adc_data_0_oe:1;
/** adc_ck_data_ie : R/W; bitpos: [14]; default: 0;
* reserved
*/
uint32_t adc_ck_data_ie:1;
/** adc_ck_data_oe : R/W; bitpos: [15]; default: 1;
* reserved
*/
uint32_t adc_ck_data_oe:1;
uint32_t reserved_16:16;
};
uint32_t val;
} hp_sys_audio_codex_ctrl0_reg_t;
/** Group: Timeout Register */
/** Type of cpu_peri_timeout_conf register
* CPU_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t cpu_peri_timeout_thres:16;
/** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t cpu_peri_timeout_int_clear:1;
/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing cpu peripheral
* registers
*/
uint32_t cpu_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_conf_reg_t;
/** Type of cpu_peri_timeout_addr register
* CPU_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t cpu_peri_timeout_addr:32;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_addr_reg_t;
/** Type of cpu_peri_timeout_uid register
* CPU_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t cpu_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_sys_cpu_peri_timeout_uid_reg_t;
/** Type of hp_peri_timeout_conf register
* HP_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t hp_peri_timeout_thres:16;
/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t hp_peri_timeout_int_clear:1;
/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
*/
uint32_t hp_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_sys_hp_peri_timeout_conf_reg_t;
/** Type of hp_peri_timeout_addr register
* HP_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t hp_peri_timeout_addr:32;
};
uint32_t val;
} hp_sys_hp_peri_timeout_addr_reg_t;
/** Type of hp_peri_timeout_uid register
* HP_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t hp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_sys_hp_peri_timeout_uid_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720768;
* HP-SYSTEM date information/ HP-SYSTEM version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} hp_sys_date_reg_t;
typedef struct {
volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf;
volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf;
volatile hp_sys_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
volatile hp_sys_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
volatile hp_sys_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
uint32_t reserved_024[3];
volatile hp_sys_sdio_ctrl_reg_t sdio_ctrl;
uint32_t reserved_034;
volatile hp_sys_rom_table_lock_reg_t rom_table_lock;
volatile hp_sys_rom_table_reg_t rom_table;
volatile hp_sys_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
uint32_t reserved_044[11];
volatile hp_sys_sprom_ctrl_reg_t sprom_ctrl;
volatile hp_sys_spram_ctrl_reg_t spram_ctrl;
volatile hp_sys_sprf_ctrl_reg_t sprf_ctrl;
volatile hp_sys_sdprf_ctrl_reg_t sdprf_ctrl;
volatile hp_sys_audio_codex_ctrl0_reg_t audio_codex_ctrl0;
uint32_t reserved_084[222];
volatile hp_sys_date_reg_t date;
} hp_sys_dev_t;
extern hp_sys_dev_t HP_SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_sys_dev_t) == 0x400, "Invalid size of hp_sys_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
* register description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
/** INTPRI_DATE_REG register
* register description
*/
#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784;
* Need add description
*/
#define INTPRI_DATE 0x0FFFFFFFU
#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
#define INTPRI_DATE_V 0x0FFFFFFFU
#define INTPRI_DATE_S 0
/** INTPRI_CLOCK_GATE_REG register
* register description
*/
#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
* Need add description
*/
#define INTPRI_CLK_EN (BIT(0))
#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
#define INTPRI_CLK_EN_V 0x00000001U
#define INTPRI_CLK_EN_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Interrupt Registers */
/** Type of cpu_intr_from_cpu_0 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_0:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_0_reg_t;
/** Type of cpu_intr_from_cpu_1 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_1:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_1_reg_t;
/** Type of cpu_intr_from_cpu_2 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_2:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_2_reg_t;
/** Type of cpu_intr_from_cpu_3 register
* register description
*/
typedef union {
struct {
/** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
* Need add description
*/
uint32_t cpu_intr_from_cpu_3:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_cpu_intr_from_cpu_3_reg_t;
/** Group: Version Registers */
/** Type of date register
* register description
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36712784;
* Need add description
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} intpri_date_reg_t;
/** Group: Configuration Registers */
/** Type of clock_gate register
* register description
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Need add description
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} intpri_clock_gate_reg_t;
typedef struct {
uint32_t reserved_000[36];
volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
volatile intpri_date_reg_t date;
volatile intpri_clock_gate_reg_t clock_gate;
} intpri_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(intpri_dev_t) == 0xa8, "Invalid size of intpri_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configure Registers */
/** Type of pin_ctrl register
* Clock Output Configuration Register
*/
typedef union {
struct {
/** clk_out1 : R/W; bitpos: [4:0]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
* CLK_OUT_out1 can be found in peripheral output signals.
*/
uint32_t clk_out1:5;
/** clk_out2 : R/W; bitpos: [9:5]; default: 15;
* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
* CLK_OUT_out2 can be found in peripheral output signals.
*/
uint32_t clk_out2:5;
/** clk_out3 : R/W; bitpos: [14:10]; default: 7;
* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
* CLK_OUT_out3 can be found in peripheral output signals.
*/
uint32_t clk_out3:5;
uint32_t reserved_15:17;
};
uint32_t val;
} io_mux_pin_ctrl_reg_t;
/** Type of gpion register
* IO MUX Configure Register for pad XTAL_32K_P
*/
typedef union {
struct {
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
* Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled.
*/
uint32_t gpion_mcu_oe:1;
/** gpion_slp_sel : R/W; bitpos: [1]; default: 0;
* Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
*/
uint32_t gpion_slp_sel:1;
/** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
* Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0:
* internal pull-down disabled.
*/
uint32_t gpion_mcu_wpd:1;
/** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
* Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0:
* internal pull-up disabled.
*/
uint32_t gpion_mcu_wpu:1;
/** gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
* Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled.
*/
uint32_t gpion_mcu_ie:1;
/** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2:
* ~20mA. 3: ~40mA.
*/
uint32_t gpion_mcu_drv:2;
/** gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
* Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down
* disabled.
*/
uint32_t gpion_fun_wpd:1;
/** gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
* Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up
* disabled.
*/
uint32_t gpion_fun_wpu:1;
/** gpion_fun_ie : R/W; bitpos: [9]; default: 0;
* Input enable of the pad. 1: input enabled. 0: input disabled.
*/
uint32_t gpion_fun_ie:1;
/** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
* Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA.
*/
uint32_t gpion_fun_drv:2;
/** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2.
* etc.
*/
uint32_t gpion_mcu_sel:3;
/** gpion_filter_en : R/W; bitpos: [15]; default: 0;
* Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled.
*/
uint32_t gpion_filter_en:1;
/** gpion_hys_en : R/W; bitpos: [16]; default: 0;
* Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0:
* Hysteresis disabled.
*/
uint32_t gpion_hys_en:1;
/** gpion_hys_sel : R/W; bitpos: [17]; default: 0;
* Select enabling signals of the pad from software and efuse hardware. 1: Select
* enabling siganl from slftware. 0: Select enabling signal from efuse hardware.
*/
uint32_t gpion_hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} io_mux_gpion_reg_t;
/** Type of date register
* IO MUX Version Control Register
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [27:0]; default: 36708704;
* Version control register
*/
uint32_t reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} io_mux_date_reg_t;
typedef struct {
volatile io_mux_pin_ctrl_reg_t pin_ctrl;
volatile io_mux_gpion_reg_t gpion[27];
uint32_t reserved_070[35];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** KEYMNG_CLK_REG register
* Key Manager clock gate control register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define KEYMNG_CLK_EN (BIT(0))
#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
#define KEYMNG_CLK_EN_V 0x00000001U
#define KEYMNG_CLK_EN_S 0
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_MEM_CG_FORCE_ON_S 1
/** KEYMNG_INT_RAW_REG register
* Key Manager interrupt raw register, valid in level.
*/
#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_RAW_S 0
/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_RAW_S 1
/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_POST_DONE_INT_RAW_S 2
/** KEYMNG_INT_ST_REG register
* Key Manager interrupt status register.
*/
#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ST_S 0
/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ST_S 1
/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ST (BIT(2))
#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ST_S 2
/** KEYMNG_INT_ENA_REG register
* Key Manager interrupt enable register.
*/
#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ENA_S 0
/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ENA_S 1
/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ENA_S 2
/** KEYMNG_INT_CLR_REG register
* Key Manager interrupt clear register.
*/
#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_CLR_S 0
/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_CLR_S 1
/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_POST_DONE_INT_CLR_S 2
/** KEYMNG_STATIC_REG register
* Key Manager static configuration register
*/
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [1:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key
*/
#define KEYMNG_USE_EFUSE_KEY 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
#define KEYMNG_USE_EFUSE_KEY_V 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_S 0
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_S 4
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY (BIT(9))
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_S 9
/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
* xts-aes-128.
*/
#define KEYMNG_XTS_AES_KEY_LEN (BIT(10))
#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U
#define KEYMNG_XTS_AES_KEY_LEN_S 10
/** KEYMNG_LOCK_REG register
* Key Manager static configuration locker register
*/
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [1:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x00000003U
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5))
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5
/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_xts_aes_key_len.
*/
#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6))
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6
/** KEYMNG_CONF_REG register
* Key Manager configuration register
*/
#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
#define KEYMNG_KGEN_MODE 0x00000007U
#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
#define KEYMNG_KGEN_MODE_V 0x00000007U
#define KEYMNG_KGEN_MODE_S 0
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
* xts_256_2_key. 4. xts_128_key. others: reserved.
*/
#define KEYMNG_KEY_PURPOSE 0x0000000FU
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
#define KEYMNG_KEY_PURPOSE_S 3
/** KEYMNG_START_REG register
* Key Manager control register
*/
#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
/** KEYMNG_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
#define KEYMNG_START (BIT(0))
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
#define KEYMNG_START_V 0x00000001U
#define KEYMNG_START_S 0
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
#define KEYMNG_CONTINUE (BIT(1))
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
#define KEYMNG_CONTINUE_V 0x00000001U
#define KEYMNG_CONTINUE_S 1
/** KEYMNG_STATE_REG register
* Key Manager state register
*/
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define KEYMNG_STATE 0x00000003U
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
#define KEYMNG_STATE_V 0x00000003U
#define KEYMNG_STATE_S 0
/** KEYMNG_RESULT_REG register
* Key Manager operation result register
*/
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
#define KEYMNG_PROC_RESULT (BIT(0))
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
#define KEYMNG_PROC_RESULT_V 0x00000001U
#define KEYMNG_PROC_RESULT_S 0
/** KEYMNG_KEY_VLD_REG register
* Key Manager key status register
*/
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_VLD_S 0
/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_XTS_VLD (BIT(1))
#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
#define KEYMNG_KEY_XTS_VLD_V 0x00000001U
#define KEYMNG_KEY_XTS_VLD_S 1
/** KEYMNG_HUK_VLD_REG register
* Key Manager HUK status register
*/
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
#define KEYMNG_HUK_VALID (BIT(0))
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
#define KEYMNG_HUK_VALID_V 0x00000001U
#define KEYMNG_HUK_VALID_S 0
/** KEYMNG_DATE_REG register
* Version control register
*/
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
* Key Manager version control register.
*/
#define KEYMNG_DATE 0x0FFFFFFFU
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
#define KEYMNG_DATE_V 0x0FFFFFFFU
#define KEYMNG_DATE_S 0
/** KEYMNG_ASSIST_INFO_MEM register
* The memory that stores assist key info.
*/
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_PUBLIC_INFO_MEM register
* The memory that stores public key info.
*/
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_SW_INIT_KEY_MEM register
* The memory that stores software written init key.
*/
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* Key Manager clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Key Manager interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_raw_reg_t;
/** Type of int_st register
* Key Manager interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_st_reg_t;
/** Type of int_ena register
* Key Manager interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_ena_reg_t;
/** Type of int_clr register
* Key Manager interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_clr_reg_t;
/** Group: Static configuration registers */
/** Type of static register
* Key Manager static configuration register
*/
typedef union {
struct {
/** use_efuse_key : R/W; bitpos: [1:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key
*/
uint32_t use_efuse_key:2;
uint32_t reserved_2:2;
/** rnd_switch_cycle : R/W; bitpos: [8:4]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
uint32_t rnd_switch_cycle:5;
/** use_sw_init_key : R/W; bitpos: [9]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
uint32_t use_sw_init_key:1;
/** xts_aes_key_len : R/W; bitpos: [10]; default: 0;
* Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
* xts-aes-128.
*/
uint32_t xts_aes_key_len:1;
uint32_t reserved_11:21;
};
uint32_t val;
} keymng_static_reg_t;
/** Type of lock register
* Key Manager static configuration locker register
*/
typedef union {
struct {
/** use_efuse_key_lock : R/W1; bitpos: [1:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
uint32_t use_efuse_key_lock:2;
uint32_t reserved_2:2;
/** rnd_switch_cycle_lock : R/W1; bitpos: [4]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
uint32_t rnd_switch_cycle_lock:1;
/** use_sw_init_key_lock : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
uint32_t use_sw_init_key_lock:1;
/** xts_aes_key_len_lock : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_xts_aes_key_len.
*/
uint32_t xts_aes_key_len_lock:1;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_lock_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* Key Manager configuration register
*/
typedef union {
struct {
/** kgen_mode : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
uint32_t kgen_mode:3;
/** key_purpose : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
* xts_256_2_key. 4. xts_128_key. others: reserved.
*/
uint32_t key_purpose:4;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* Key Manager control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
uint32_t continue:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_start_reg_t;
/** Group: State registers */
/** Type of state register
* Key Manager state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_state_reg_t;
/** Group: Result registers */
/** Type of result register
* Key Manager operation result register
*/
typedef union {
struct {
/** proc_result : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
uint32_t proc_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_result_reg_t;
/** Type of key_vld register
* Key Manager key status register
*/
typedef union {
struct {
/** key_ecdsa_vld : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_ecdsa_vld:1;
/** key_xts_vld : RO; bitpos: [1]; default: 0;
* The status bit for key_xts. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_xts_vld:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_key_vld_reg_t;
/** Type of huk_vld register
* Key Manager HUK status register
*/
typedef union {
struct {
/** huk_valid : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
uint32_t huk_valid:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_huk_vld_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36720704;
* Key Manager version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} keymng_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile keymng_clk_reg_t clk;
volatile keymng_int_raw_reg_t int_raw;
volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static;
volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start;
volatile keymng_state_reg_t state;
volatile keymng_result_reg_t result;
volatile keymng_key_vld_reg_t key_vld;
volatile keymng_huk_vld_reg_t huk_vld;
uint32_t reserved_038[49];
volatile keymng_date_reg_t date;
volatile uint32_t assist_info[16];
volatile uint32_t public_info[16];
volatile uint32_t sw_init_key[8];
} keymng_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
* need_des
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6))
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6
/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7))
#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7
/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
* need_des
*/
#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8
/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18
/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28))
#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_CNT_CLR_S 28
/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29))
#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INTR_ENA_S 29
/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30))
#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_SEL_S 30
/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_ENA_S 31
/** LP_ANA_BOD_MODE1_CNTL_REG register
* need_des
*/
#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE1_RESET_ENA_S 31
/** LP_ANA_CK_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANA_FIB_ENABLE_REG register
* need_des
*/
#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
*/
#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_S 0
/** LP_ANA_INT_RAW_REG register
* need_des
*/
#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_RAW_S 31
/** LP_ANA_INT_ST_REG register
* need_des
*/
#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ST_S 31
/** LP_ANA_INT_ENA_REG register
* need_des
*/
#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ENA_S 31
/** LP_ANA_INT_CLR_REG register
* need_des
*/
#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_CLR_S 31
/** LP_ANA_LP_INT_RAW_REG register
* need_des
*/
#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31
/** LP_ANA_LP_INT_ST_REG register
* need_des
*/
#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31
/** LP_ANA_LP_INT_ENA_REG register
* need_des
*/
#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31
/** LP_ANA_LP_INT_CLR_REG register
* need_des
*/
#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31
/** LP_ANA_DATE_REG register
* need_des
*/
#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 35660384;
* need_des
*/
#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_S 0
/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_CLK_EN (BIT(31))
#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
#define LP_ANA_CLK_EN_V 0x00000001U
#define LP_ANA_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of bod_mode0_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
* need_des
*/
uint32_t bod_mode0_close_flash_ena:1;
/** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
* need_des
*/
uint32_t bod_mode0_pd_rf_ena:1;
/** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
* need_des
*/
uint32_t bod_mode0_intr_wait:10;
/** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
* need_des
*/
uint32_t bod_mode0_reset_wait:10;
/** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t bod_mode0_cnt_clr:1;
/** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t bod_mode0_intr_ena:1;
/** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t bod_mode0_reset_sel:1;
/** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode0_cntl_reg_t;
/** Type of bod_mode1_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode1_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode1_cntl_reg_t;
/** Type of ck_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
/** Type of fib_enable register
* need_des
*/
typedef union {
struct {
/** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
* need_des
*/
uint32_t ana_fib_ena:32;
};
uint32_t val;
} lp_ana_fib_enable_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_int_raw:1;
};
uint32_t val;
} lp_ana_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_int_st:1;
};
uint32_t val;
} lp_ana_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_int_ena:1;
};
uint32_t val;
} lp_ana_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_int_clr:1;
};
uint32_t val;
} lp_ana_int_clr_reg_t;
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_lp_int_raw:1;
};
uint32_t val;
} lp_ana_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_lp_int_st:1;
};
uint32_t val;
} lp_ana_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_lp_int_ena:1;
};
uint32_t val;
} lp_ana_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t bod_mode0_lp_int_clr:1;
};
uint32_t val;
} lp_ana_lp_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lp_ana_date : R/W; bitpos: [30:0]; default: 35660384;
* need_des
*/
uint32_t lp_ana_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_ana_date_reg_t;
typedef struct {
volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
volatile lp_ana_fib_enable_reg_t fib_enable;
volatile lp_ana_int_raw_reg_t int_raw;
volatile lp_ana_int_st_reg_t int_st;
volatile lp_ana_int_ena_reg_t int_ena;
volatile lp_ana_int_clr_reg_t int_clr;
volatile lp_ana_lp_int_raw_reg_t lp_int_raw;
volatile lp_ana_lp_int_st_reg_t lp_int_st;
volatile lp_ana_lp_int_ena_reg_t lp_int_ena;
volatile lp_ana_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_030[243];
volatile lp_ana_date_reg_t date;
} lp_ana_dev_t;
extern lp_ana_dev_t LP_ANA_PERI;
#ifndef __cplusplus
_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_AON_STORE0_REG register
* need_des
*/
#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S)
#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE0_S 0
/** LP_AON_STORE1_REG register
* need_des
*/
#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S)
#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE1_S 0
/** LP_AON_STORE2_REG register
* need_des
*/
#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S)
#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE2_S 0
/** LP_AON_STORE3_REG register
* need_des
*/
#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S)
#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE3_S 0
/** LP_AON_STORE4_REG register
* need_des
*/
#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S)
#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE4_S 0
/** LP_AON_STORE5_REG register
* need_des
*/
#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S)
#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE5_S 0
/** LP_AON_STORE6_REG register
* need_des
*/
#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S)
#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE6_S 0
/** LP_AON_STORE7_REG register
* need_des
*/
#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S)
#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE7_S 0
/** LP_AON_STORE8_REG register
* need_des
*/
#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S)
#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE8_S 0
/** LP_AON_STORE9_REG register
* need_des
*/
#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S)
#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE9_S 0
/** LP_AON_GPIO_MUX_REG register
* need_des
*/
#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_MUX_SEL 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU
#define LP_AON_GPIO_MUX_SEL_S 0
/** LP_AON_GPIO_HOLD0_REG register
* need_des
*/
#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_S 0
/** LP_AON_GPIO_HOLD1_REG register
* need_des
*/
#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD1_S 0
/** LP_AON_SYS_CFG_REG register
* need_des
*/
#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30))
#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U
#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30
/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_HPSYS_SW_RESET (BIT(31))
#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
#define LP_AON_HPSYS_SW_RESET_V 0x00000001U
#define LP_AON_HPSYS_SW_RESET_S 31
/** LP_AON_CPUCORE0_CFG_REG register
* need_des
*/
#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_S 0
/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_SW_RESET (BIT(28))
#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_SW_RESET_S 28
/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29))
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29
/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30))
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U
#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30
/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31))
#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U
#define LP_AON_CPU_CORE0_DRESET_MASK_S 31
/** LP_AON_IO_MUX_REG register
* need_des
*/
#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31))
#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U
#define LP_AON_IO_MUX_RESET_DISABLE_S 31
/** LP_AON_EXT_WAKEUP_CNTL_REG register
* need_des
*/
#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_STATUS_S 0
/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14))
#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U
#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14
/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_SEL_S 15
/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_LV 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU
#define LP_AON_EXT_WAKEUP_LV_S 23
/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_EXT_WAKEUP_FILTER (BIT(31))
#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U
#define LP_AON_EXT_WAKEUP_FILTER_S 31
/** LP_AON_USB_REG register
* need_des
*/
#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_USB_RESET_DISABLE (BIT(31))
#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
#define LP_AON_USB_RESET_DISABLE_V 0x00000001U
#define LP_AON_USB_RESET_DISABLE_S 31
/** LP_AON_LPBUS_REG register
* need_des
*/
#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28))
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28
/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29))
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29
/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30))
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30
/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LP_AON_FAST_MEM_MUX_SEL (BIT(31))
#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_S 31
/** LP_AON_SDIO_ACTIVE_REG register
* need_des
*/
#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
#define LP_AON_SDIO_ACT_DNUM 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU
#define LP_AON_SDIO_ACT_DNUM_S 22
/** LP_AON_LPCORE_REG register
* need_des
*/
#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0
/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1))
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U
#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1
/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_LPCORE_DISABLE (BIT(31))
#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
#define LP_AON_LPCORE_DISABLE_V 0x00000001U
#define LP_AON_LPCORE_DISABLE_S 31
/** LP_AON_SAR_CCT_REG register
* need_des
*/
#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
#define LP_AON_SAR2_PWDET_CCT 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U
#define LP_AON_SAR2_PWDET_CCT_S 29
/** LP_AON_MODEM_BUS_REG register
* need_des
*/
#define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58)
/** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_MODEM_SYNC_BRIDGE_EN (BIT(31))
#define LP_AON_MODEM_SYNC_BRIDGE_EN_M (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S)
#define LP_AON_MODEM_SYNC_BRIDGE_EN_V 0x00000001U
#define LP_AON_MODEM_SYNC_BRIDGE_EN_S 31
/** LP_AON_AUDIO_CODEC_CTRL_REG register
* need_des
*/
#define LP_AON_AUDIO_CODEC_CTRL_REG (DR_REG_LP_AON_BASE + 0x5c)
/** LP_AON_RTC_XPD_SDADC : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define LP_AON_RTC_XPD_SDADC (BIT(0))
#define LP_AON_RTC_XPD_SDADC_M (LP_AON_RTC_XPD_SDADC_V << LP_AON_RTC_XPD_SDADC_S)
#define LP_AON_RTC_XPD_SDADC_V 0x00000001U
#define LP_AON_RTC_XPD_SDADC_S 0
/** LP_AON_RTC_EN_CLK_AUDIO_DAC : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define LP_AON_RTC_EN_CLK_AUDIO_DAC (BIT(1))
#define LP_AON_RTC_EN_CLK_AUDIO_DAC_M (LP_AON_RTC_EN_CLK_AUDIO_DAC_V << LP_AON_RTC_EN_CLK_AUDIO_DAC_S)
#define LP_AON_RTC_EN_CLK_AUDIO_DAC_V 0x00000001U
#define LP_AON_RTC_EN_CLK_AUDIO_DAC_S 1
/** LP_AON_RTC_XPD_BIAS_AUDIO_DAC : R/W; bitpos: [2]; default: 0;
* need_des
*/
#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC (BIT(2))
#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_M (LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V << LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S)
#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V 0x00000001U
#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S 2
/** LP_AON_RTC_XPD_PLLA : R/W; bitpos: [3]; default: 1;
* need_des
*/
#define LP_AON_RTC_XPD_PLLA (BIT(3))
#define LP_AON_RTC_XPD_PLLA_M (LP_AON_RTC_XPD_PLLA_V << LP_AON_RTC_XPD_PLLA_S)
#define LP_AON_RTC_XPD_PLLA_V 0x00000001U
#define LP_AON_RTC_XPD_PLLA_S 3
/** LP_AON_SPRAM_CTRL_REG register
* need_des
*/
#define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60)
/** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
#define LP_AON_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
#define LP_AON_SPRAM_MEM_AUX_CTRL_M (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S)
#define LP_AON_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define LP_AON_SPRAM_MEM_AUX_CTRL_S 0
/** LP_AON_SPRF_CTRL_REG register
* need_des
*/
#define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64)
/** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
#define LP_AON_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
#define LP_AON_SPRF_MEM_AUX_CTRL_M (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S)
#define LP_AON_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
#define LP_AON_SPRF_MEM_AUX_CTRL_S 0
/** LP_AON_DATE_REG register
* need_des
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36720768;
* need_des
*/
#define LP_AON_DATE 0x7FFFFFFFU
#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S)
#define LP_AON_DATE_V 0x7FFFFFFFU
#define LP_AON_DATE_S 0
/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_CLK_EN (BIT(31))
#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
#define LP_AON_CLK_EN_V 0x00000001U
#define LP_AON_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

491
components/soc/esp32c5/include/soc/lp_aon_struct.h Normal file
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@ -0,0 +1,491 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of store0 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store0:32;
};
uint32_t val;
} lp_aon_store0_reg_t;
/** Type of store1 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store1:32;
};
uint32_t val;
} lp_aon_store1_reg_t;
/** Type of store2 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store2 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store2:32;
};
uint32_t val;
} lp_aon_store2_reg_t;
/** Type of store3 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store3 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store3:32;
};
uint32_t val;
} lp_aon_store3_reg_t;
/** Type of store4 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store4 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store4:32;
};
uint32_t val;
} lp_aon_store4_reg_t;
/** Type of store5 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store5 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store5:32;
};
uint32_t val;
} lp_aon_store5_reg_t;
/** Type of store6 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store6 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store6:32;
};
uint32_t val;
} lp_aon_store6_reg_t;
/** Type of store7 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store7 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store7:32;
};
uint32_t val;
} lp_aon_store7_reg_t;
/** Type of store8 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store8 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store8:32;
};
uint32_t val;
} lp_aon_store8_reg_t;
/** Type of store9 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store9 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store9:32;
};
uint32_t val;
} lp_aon_store9_reg_t;
/** Type of gpio_mux register
* need_des
*/
typedef union {
struct {
/** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t gpio_mux_sel:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_aon_gpio_mux_reg_t;
/** Type of gpio_hold0 register
* need_des
*/
typedef union {
struct {
/** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t gpio_hold0:32;
};
uint32_t val;
} lp_aon_gpio_hold0_reg_t;
/** Type of gpio_hold1 register
* need_des
*/
typedef union {
struct {
/** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t gpio_hold1:32;
};
uint32_t val;
} lp_aon_gpio_hold1_reg_t;
/** Type of sys_cfg register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** force_download_boot : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t force_download_boot:1;
/** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t hpsys_sw_reset:1;
};
uint32_t val;
} lp_aon_sys_cfg_reg_t;
/** Type of cpucore0_cfg register
* need_des
*/
typedef union {
struct {
/** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t cpu_core0_sw_stall:8;
uint32_t reserved_8:20;
/** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t cpu_core0_sw_reset:1;
/** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t cpu_core0_ocd_halt_on_reset:1;
/** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t cpu_core0_stat_vector_sel:1;
/** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t cpu_core0_dreset_mask:1;
};
uint32_t val;
} lp_aon_cpucore0_cfg_reg_t;
/** Type of io_mux register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t io_mux_reset_disable:1;
};
uint32_t val;
} lp_aon_io_mux_reg_t;
/** Type of ext_wakeup_cntl register
* need_des
*/
typedef union {
struct {
/** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
* need_des
*/
uint32_t ext_wakeup_status:8;
uint32_t reserved_8:6;
/** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
* need_des
*/
uint32_t ext_wakeup_status_clr:1;
/** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
* need_des
*/
uint32_t ext_wakeup_sel:8;
/** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
uint32_t ext_wakeup_lv:8;
/** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ext_wakeup_filter:1;
};
uint32_t val;
} lp_aon_ext_wakeup_cntl_reg_t;
/** Type of usb register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** usb_reset_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t usb_reset_disable:1;
};
uint32_t val;
} lp_aon_usb_reg_t;
/** Type of lpbus register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_fsm_idle:1;
/** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_sel_status:1;
/** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t fast_mem_mux_sel_update:1;
/** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t fast_mem_mux_sel:1;
};
uint32_t val;
} lp_aon_lpbus_reg_t;
/** Type of sdio_active register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
* need_des
*/
uint32_t sdio_act_dnum:10;
};
uint32_t val;
} lp_aon_sdio_active_reg_t;
/** Type of lpcore register
* need_des
*/
typedef union {
struct {
/** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t lpcore_etm_wakeup_flag_clr:1;
/** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t lpcore_etm_wakeup_flag:1;
uint32_t reserved_2:29;
/** lpcore_disable : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lpcore_disable:1;
};
uint32_t val;
} lp_aon_lpcore_reg_t;
/** Type of sar_cct register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
* need_des
*/
uint32_t sar2_pwdet_cct:3;
};
uint32_t val;
} lp_aon_sar_cct_reg_t;
/** Type of modem_bus register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** modem_sync_bridge_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t modem_sync_bridge_en:1;
};
uint32_t val;
} lp_aon_modem_bus_reg_t;
/** Type of audio_codec_ctrl register
* need_des
*/
typedef union {
struct {
/** rtc_xpd_sdadc : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t rtc_xpd_sdadc:1;
/** rtc_en_clk_audio_dac : R/W; bitpos: [1]; default: 0;
* need_des
*/
uint32_t rtc_en_clk_audio_dac:1;
/** rtc_xpd_bias_audio_dac : R/W; bitpos: [2]; default: 0;
* need_des
*/
uint32_t rtc_xpd_bias_audio_dac:1;
/** rtc_xpd_plla : R/W; bitpos: [3]; default: 1;
* need_des
*/
uint32_t rtc_xpd_plla:1;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_aon_audio_codec_ctrl_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 36720768;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_aon_date_reg_t;
/** Group: Configuration Register */
/** Type of spram_ctrl register
* need_des
*/
typedef union {
struct {
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
uint32_t spram_mem_aux_ctrl:32;
};
uint32_t val;
} lp_aon_spram_ctrl_reg_t;
/** Type of sprf_ctrl register
* need_des
*/
typedef union {
struct {
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
* need_des
*/
uint32_t sprf_mem_aux_ctrl:32;
};
uint32_t val;
} lp_aon_sprf_ctrl_reg_t;
typedef struct {
volatile lp_aon_store0_reg_t store0;
volatile lp_aon_store1_reg_t store1;
volatile lp_aon_store2_reg_t store2;
volatile lp_aon_store3_reg_t store3;
volatile lp_aon_store4_reg_t store4;
volatile lp_aon_store5_reg_t store5;
volatile lp_aon_store6_reg_t store6;
volatile lp_aon_store7_reg_t store7;
volatile lp_aon_store8_reg_t store8;
volatile lp_aon_store9_reg_t store9;
volatile lp_aon_gpio_mux_reg_t gpio_mux;
volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
volatile lp_aon_sys_cfg_reg_t sys_cfg;
volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
volatile lp_aon_io_mux_reg_t io_mux;
volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
volatile lp_aon_usb_reg_t usb;
volatile lp_aon_lpbus_reg_t lpbus;
volatile lp_aon_sdio_active_reg_t sdio_active;
volatile lp_aon_lpcore_reg_t lpcore;
volatile lp_aon_sar_cct_reg_t sar_cct;
volatile lp_aon_modem_bus_reg_t modem_bus;
volatile lp_aon_audio_codec_ctrl_reg_t audio_codec_ctrl;
volatile lp_aon_spram_ctrl_reg_t spram_ctrl;
volatile lp_aon_sprf_ctrl_reg_t sprf_ctrl;
uint32_t reserved_068[229];
volatile lp_aon_date_reg_t date;
} lp_aon_dev_t;
extern lp_aon_dev_t LP_AON;
#ifndef __cplusplus
_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/include/soc/lp_apm0_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM0_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM0_REGION_FILTER_EN 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM0_REGION_FILTER_EN_S 0
/** LP_APM0_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_START_S 0
/** LP_APM0_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION0_ADDR_END_S 0
/** LP_APM0_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_X (BIT(0))
#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S)
#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_X_S 0
/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_W (BIT(1))
#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S)
#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_W_S 1
/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION0_R0_PMS_R (BIT(2))
#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S)
#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R0_PMS_R_S 2
/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_X (BIT(4))
#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S)
#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_X_S 4
/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_W (BIT(5))
#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S)
#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_W_S 5
/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION0_R1_PMS_R (BIT(6))
#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S)
#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R1_PMS_R_S 6
/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_X (BIT(8))
#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S)
#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_X_S 8
/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_W (BIT(9))
#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S)
#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_W_S 9
/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION0_R2_PMS_R (BIT(10))
#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S)
#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION0_R2_PMS_R_S 10
/** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM0_REGION0_LOCK (BIT(11))
#define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S)
#define LP_APM0_REGION0_LOCK_V 0x00000001U
#define LP_APM0_REGION0_LOCK_S 11
/** LP_APM0_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_START_S 0
/** LP_APM0_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION1_ADDR_END_S 0
/** LP_APM0_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_X (BIT(0))
#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S)
#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_X_S 0
/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_W (BIT(1))
#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S)
#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_W_S 1
/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION1_R0_PMS_R (BIT(2))
#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S)
#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R0_PMS_R_S 2
/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_X (BIT(4))
#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S)
#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_X_S 4
/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_W (BIT(5))
#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S)
#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_W_S 5
/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION1_R1_PMS_R (BIT(6))
#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S)
#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R1_PMS_R_S 6
/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_X (BIT(8))
#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S)
#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_X_S 8
/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_W (BIT(9))
#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S)
#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_W_S 9
/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION1_R2_PMS_R (BIT(10))
#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S)
#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION1_R2_PMS_R_S 10
/** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region1 configuration
*/
#define LP_APM0_REGION1_LOCK (BIT(11))
#define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S)
#define LP_APM0_REGION1_LOCK_V 0x00000001U
#define LP_APM0_REGION1_LOCK_S 11
/** LP_APM0_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_START_S 0
/** LP_APM0_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION2_ADDR_END_S 0
/** LP_APM0_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_X (BIT(0))
#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S)
#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_X_S 0
/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_W (BIT(1))
#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S)
#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_W_S 1
/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION2_R0_PMS_R (BIT(2))
#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S)
#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R0_PMS_R_S 2
/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_X (BIT(4))
#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S)
#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_X_S 4
/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_W (BIT(5))
#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S)
#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_W_S 5
/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION2_R1_PMS_R (BIT(6))
#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S)
#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R1_PMS_R_S 6
/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_X (BIT(8))
#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S)
#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_X_S 8
/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_W (BIT(9))
#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S)
#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_W_S 9
/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION2_R2_PMS_R (BIT(10))
#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S)
#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION2_R2_PMS_R_S 10
/** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region2 configuration
*/
#define LP_APM0_REGION2_LOCK (BIT(11))
#define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S)
#define LP_APM0_REGION2_LOCK_V 0x00000001U
#define LP_APM0_REGION2_LOCK_S 11
/** LP_APM0_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_START_S 0
/** LP_APM0_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM0_REGION3_ADDR_END_S 0
/** LP_APM0_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_X (BIT(0))
#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S)
#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_X_S 0
/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_W (BIT(1))
#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S)
#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_W_S 1
/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM0_REGION3_R0_PMS_R (BIT(2))
#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S)
#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R0_PMS_R_S 2
/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_X (BIT(4))
#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S)
#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_X_S 4
/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_W (BIT(5))
#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S)
#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_W_S 5
/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM0_REGION3_R1_PMS_R (BIT(6))
#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S)
#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R1_PMS_R_S 6
/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_X (BIT(8))
#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S)
#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_X_S 8
/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_W (BIT(9))
#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S)
#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_W_S 9
/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM0_REGION3_R2_PMS_R (BIT(10))
#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S)
#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM0_REGION3_R2_PMS_R_S 10
/** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region3 configuration
*/
#define LP_APM0_REGION3_LOCK (BIT(11))
#define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S)
#define LP_APM0_REGION3_LOCK_V 0x00000001U
#define LP_APM0_REGION3_LOCK_S 11
/** LP_APM0_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM0_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S)
#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM0_M0_PMS_FUNC_EN_S 0
/** LP_APM0_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_STATUS_S 0
/** LP_APM0_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S)
#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM0_M0_REGION_STATUS_CLR_S 0
/** LP_APM0_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM0_M0_EXCEPTION_REGION_S 0
/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM0_M0_EXCEPTION_MODE_S 16
/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM0_M0_EXCEPTION_ID_S 18
/** LP_APM0_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM0_M0_EXCEPTION_ADDR_S 0
/** LP_APM0_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM0_M0_APM_INT_EN (BIT(0))
#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
#define LP_APM0_M0_APM_INT_EN_V 0x00000001U
#define LP_APM0_M0_APM_INT_EN_S 0
/** LP_APM0_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM0_CLK_EN (BIT(0))
#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
#define LP_APM0_CLK_EN_V 0x00000001U
#define LP_APM0_CLK_EN_S 0
/** LP_APM0_DATE_REG register
* Version register
*/
#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664;
* reg_date
*/
#define LP_APM0_DATE 0x0FFFFFFFU
#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S)
#define LP_APM0_DATE_V 0x0FFFFFFFU
#define LP_APM0_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm0_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm0_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm0_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm0_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm0_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm0_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm0_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm0_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm0_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
/** region0_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t region0_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
/** region1_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region1 configuration
*/
uint32_t region1_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
/** region2_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region2 configuration
*/
uint32_t region2_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
/** region3_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region3 configuration
*/
uint32_t region3_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm0_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm0_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm0_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm0_m0_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm0_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725664;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm0_date_reg_t;
typedef struct {
volatile lp_apm0_region_filter_en_reg_t region_filter_en;
volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm0_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm0_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm0_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm0_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm0_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm0_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm0_func_ctrl_reg_t func_ctrl;
volatile lp_apm0_m0_status_reg_t m0_status;
volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm0_int_en_reg_t int_en;
volatile lp_apm0_clock_gate_reg_t clock_gate;
uint32_t reserved_0e0[455];
volatile lp_apm0_date_reg_t date;
} lp_apm0_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/include/soc/lp_apm_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_APM_REGION_FILTER_EN_REG register
* Region filter enable register
*/
#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
#define LP_APM_REGION_FILTER_EN 0x0000000FU
#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
#define LP_APM_REGION_FILTER_EN_V 0x0000000FU
#define LP_APM_REGION_FILTER_EN_S 0
/** LP_APM_REGION0_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_START_S 0
/** LP_APM_REGION0_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION0_ADDR_END_S 0
/** LP_APM_REGION0_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_X (BIT(0))
#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S)
#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_X_S 0
/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_W (BIT(1))
#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S)
#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_W_S 1
/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION0_R0_PMS_R (BIT(2))
#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S)
#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R0_PMS_R_S 2
/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_X (BIT(4))
#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S)
#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_X_S 4
/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_W (BIT(5))
#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S)
#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_W_S 5
/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION0_R1_PMS_R (BIT(6))
#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S)
#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R1_PMS_R_S 6
/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_X (BIT(8))
#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S)
#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_X_S 8
/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_W (BIT(9))
#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S)
#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_W_S 9
/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION0_R2_PMS_R (BIT(10))
#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S)
#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION0_R2_PMS_R_S 10
/** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
#define LP_APM_REGION0_LOCK (BIT(11))
#define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S)
#define LP_APM_REGION0_LOCK_V 0x00000001U
#define LP_APM_REGION0_LOCK_S 11
/** LP_APM_REGION1_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_START_S 0
/** LP_APM_REGION1_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION1_ADDR_END_S 0
/** LP_APM_REGION1_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_X (BIT(0))
#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S)
#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_X_S 0
/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_W (BIT(1))
#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S)
#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_W_S 1
/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION1_R0_PMS_R (BIT(2))
#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S)
#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R0_PMS_R_S 2
/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_X (BIT(4))
#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S)
#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_X_S 4
/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_W (BIT(5))
#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S)
#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_W_S 5
/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION1_R1_PMS_R (BIT(6))
#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S)
#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R1_PMS_R_S 6
/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_X (BIT(8))
#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S)
#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_X_S 8
/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_W (BIT(9))
#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S)
#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_W_S 9
/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION1_R2_PMS_R (BIT(10))
#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S)
#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION1_R2_PMS_R_S 10
/** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region1 configuration
*/
#define LP_APM_REGION1_LOCK (BIT(11))
#define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S)
#define LP_APM_REGION1_LOCK_V 0x00000001U
#define LP_APM_REGION1_LOCK_S 11
/** LP_APM_REGION2_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_START_S 0
/** LP_APM_REGION2_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION2_ADDR_END_S 0
/** LP_APM_REGION2_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_X (BIT(0))
#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S)
#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_X_S 0
/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_W (BIT(1))
#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S)
#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_W_S 1
/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION2_R0_PMS_R (BIT(2))
#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S)
#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R0_PMS_R_S 2
/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_X (BIT(4))
#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S)
#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_X_S 4
/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_W (BIT(5))
#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S)
#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_W_S 5
/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION2_R1_PMS_R (BIT(6))
#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S)
#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R1_PMS_R_S 6
/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_X (BIT(8))
#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S)
#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_X_S 8
/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_W (BIT(9))
#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S)
#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_W_S 9
/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION2_R2_PMS_R (BIT(10))
#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S)
#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION2_R2_PMS_R_S 10
/** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region2 configuration
*/
#define LP_APM_REGION2_LOCK (BIT(11))
#define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S)
#define LP_APM_REGION2_LOCK_V 0x00000001U
#define LP_APM_REGION2_LOCK_S 11
/** LP_APM_REGION3_ADDR_START_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_START_S 0
/** LP_APM_REGION3_ADDR_END_REG register
* Region address register
*/
#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU
#define LP_APM_REGION3_ADDR_END_S 0
/** LP_APM_REGION3_PMS_ATTR_REG register
* Region access authority attribute register
*/
#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_X (BIT(0))
#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S)
#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_X_S 0
/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_W (BIT(1))
#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S)
#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_W_S 1
/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
#define LP_APM_REGION3_R0_PMS_R (BIT(2))
#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S)
#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R0_PMS_R_S 2
/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_X (BIT(4))
#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S)
#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_X_S 4
/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_W (BIT(5))
#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S)
#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_W_S 5
/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
#define LP_APM_REGION3_R1_PMS_R (BIT(6))
#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S)
#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R1_PMS_R_S 6
/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_X (BIT(8))
#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S)
#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_X_S 8
/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_W (BIT(9))
#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S)
#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_W_S 9
/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
#define LP_APM_REGION3_R2_PMS_R (BIT(10))
#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S)
#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U
#define LP_APM_REGION3_R2_PMS_R_S 10
/** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region3 configuration
*/
#define LP_APM_REGION3_LOCK (BIT(11))
#define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S)
#define LP_APM_REGION3_LOCK_V 0x00000001U
#define LP_APM_REGION3_LOCK_S 11
/** LP_APM_FUNC_CTRL_REG register
* PMS function control register
*/
#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
#define LP_APM_M0_PMS_FUNC_EN (BIT(0))
#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S)
#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M0_PMS_FUNC_EN_S 0
/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
#define LP_APM_M1_PMS_FUNC_EN (BIT(1))
#define LP_APM_M1_PMS_FUNC_EN_M (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S)
#define LP_APM_M1_PMS_FUNC_EN_V 0x00000001U
#define LP_APM_M1_PMS_FUNC_EN_S 1
/** LP_APM_M0_STATUS_REG register
* M0 status register
*/
#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M0_EXCEPTION_STATUS_S 0
/** LP_APM_M0_STATUS_CLR_REG register
* M0 status clear register
*/
#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M0_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S)
#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M0_REGION_STATUS_CLR_S 0
/** LP_APM_M0_EXCEPTION_INFO0_REG register
* M0 exception_info0 register
*/
#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M0_EXCEPTION_REGION_S 0
/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M0_EXCEPTION_MODE 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M0_EXCEPTION_MODE_S 16
/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M0_EXCEPTION_ID 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M0_EXCEPTION_ID_S 18
/** LP_APM_M0_EXCEPTION_INFO1_REG register
* M0 exception_info1 register
*/
#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M0_EXCEPTION_ADDR_S 0
/** LP_APM_M1_STATUS_REG register
* M1 status register
*/
#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U
#define LP_APM_M1_EXCEPTION_STATUS_S 0
/** LP_APM_M1_STATUS_CLR_REG register
* M1 status clear register
*/
#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc)
/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
#define LP_APM_M1_REGION_STATUS_CLR (BIT(0))
#define LP_APM_M1_REGION_STATUS_CLR_M (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S)
#define LP_APM_M1_REGION_STATUS_CLR_V 0x00000001U
#define LP_APM_M1_REGION_STATUS_CLR_S 0
/** LP_APM_M1_EXCEPTION_INFO0_REG register
* M1 exception_info0 register
*/
#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU
#define LP_APM_M1_EXCEPTION_REGION_S 0
/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
#define LP_APM_M1_EXCEPTION_MODE 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S)
#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U
#define LP_APM_M1_EXCEPTION_MODE_S 16
/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
#define LP_APM_M1_EXCEPTION_ID 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S)
#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU
#define LP_APM_M1_EXCEPTION_ID_S 18
/** LP_APM_M1_EXCEPTION_INFO1_REG register
* M1 exception_info1 register
*/
#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4)
/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S)
#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU
#define LP_APM_M1_EXCEPTION_ADDR_S 0
/** LP_APM_INT_EN_REG register
* APM interrupt enable register
*/
#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
#define LP_APM_M0_APM_INT_EN (BIT(0))
#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
#define LP_APM_M0_APM_INT_EN_V 0x00000001U
#define LP_APM_M0_APM_INT_EN_S 0
/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
* APM M1 interrupt enable
*/
#define LP_APM_M1_APM_INT_EN (BIT(1))
#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
#define LP_APM_M1_APM_INT_EN_V 0x00000001U
#define LP_APM_M1_APM_INT_EN_S 1
/** LP_APM_CLOCK_GATE_REG register
* clock gating register
*/
#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_APM_CLK_EN (BIT(0))
#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
#define LP_APM_CLK_EN_V 0x00000001U
#define LP_APM_CLK_EN_S 0
/** LP_APM_DATE_REG register
* Version register
*/
#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664;
* reg_date
*/
#define LP_APM_DATE 0x0FFFFFFFU
#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S)
#define LP_APM_DATE_V 0x0FFFFFFFU
#define LP_APM_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Region filter enable register */
/** Type of region_filter_en register
* Region filter enable register
*/
typedef union {
struct {
/** region_filter_en : R/W; bitpos: [3:0]; default: 1;
* Region filter enable
*/
uint32_t region_filter_en:4;
uint32_t reserved_4:28;
};
uint32_t val;
} lp_apm_region_filter_en_reg_t;
/** Group: Region address register */
/** Type of region0_addr_start register
* Region address register
*/
typedef union {
struct {
/** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region0
*/
uint32_t region0_addr_start:32;
};
uint32_t val;
} lp_apm_region0_addr_start_reg_t;
/** Type of region0_addr_end register
* Region address register
*/
typedef union {
struct {
/** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region0
*/
uint32_t region0_addr_end:32;
};
uint32_t val;
} lp_apm_region0_addr_end_reg_t;
/** Type of region1_addr_start register
* Region address register
*/
typedef union {
struct {
/** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region1
*/
uint32_t region1_addr_start:32;
};
uint32_t val;
} lp_apm_region1_addr_start_reg_t;
/** Type of region1_addr_end register
* Region address register
*/
typedef union {
struct {
/** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region1
*/
uint32_t region1_addr_end:32;
};
uint32_t val;
} lp_apm_region1_addr_end_reg_t;
/** Type of region2_addr_start register
* Region address register
*/
typedef union {
struct {
/** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region2
*/
uint32_t region2_addr_start:32;
};
uint32_t val;
} lp_apm_region2_addr_start_reg_t;
/** Type of region2_addr_end register
* Region address register
*/
typedef union {
struct {
/** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region2
*/
uint32_t region2_addr_end:32;
};
uint32_t val;
} lp_apm_region2_addr_end_reg_t;
/** Type of region3_addr_start register
* Region address register
*/
typedef union {
struct {
/** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
* Start address of region3
*/
uint32_t region3_addr_start:32;
};
uint32_t val;
} lp_apm_region3_addr_start_reg_t;
/** Type of region3_addr_end register
* Region address register
*/
typedef union {
struct {
/** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
* End address of region3
*/
uint32_t region3_addr_end:32;
};
uint32_t val;
} lp_apm_region3_addr_end_reg_t;
/** Group: Region access authority attribute register */
/** Type of region0_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region0_r0_pms_x:1;
/** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region0_r0_pms_w:1;
/** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region0_r0_pms_r:1;
uint32_t reserved_3:1;
/** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region0_r1_pms_x:1;
/** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region0_r1_pms_w:1;
/** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region0_r1_pms_r:1;
uint32_t reserved_7:1;
/** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region0_r2_pms_x:1;
/** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region0_r2_pms_w:1;
/** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region0_r2_pms_r:1;
/** region0_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region0 configuration
*/
uint32_t region0_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_region0_pms_attr_reg_t;
/** Type of region1_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region1_r0_pms_x:1;
/** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region1_r0_pms_w:1;
/** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region1_r0_pms_r:1;
uint32_t reserved_3:1;
/** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region1_r1_pms_x:1;
/** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region1_r1_pms_w:1;
/** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region1_r1_pms_r:1;
uint32_t reserved_7:1;
/** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region1_r2_pms_x:1;
/** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region1_r2_pms_w:1;
/** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region1_r2_pms_r:1;
/** region1_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region1 configuration
*/
uint32_t region1_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_region1_pms_attr_reg_t;
/** Type of region2_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region2_r0_pms_x:1;
/** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region2_r0_pms_w:1;
/** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region2_r0_pms_r:1;
uint32_t reserved_3:1;
/** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region2_r1_pms_x:1;
/** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region2_r1_pms_w:1;
/** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region2_r1_pms_r:1;
uint32_t reserved_7:1;
/** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region2_r2_pms_x:1;
/** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region2_r2_pms_w:1;
/** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region2_r2_pms_r:1;
/** region2_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region2 configuration
*/
uint32_t region2_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_region2_pms_attr_reg_t;
/** Type of region3_pms_attr register
* Region access authority attribute register
*/
typedef union {
struct {
/** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
* Region execute authority in REE_MODE0
*/
uint32_t region3_r0_pms_x:1;
/** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
* Region write authority in REE_MODE0
*/
uint32_t region3_r0_pms_w:1;
/** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
* Region read authority in REE_MODE0
*/
uint32_t region3_r0_pms_r:1;
uint32_t reserved_3:1;
/** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
* Region execute authority in REE_MODE1
*/
uint32_t region3_r1_pms_x:1;
/** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
* Region write authority in REE_MODE1
*/
uint32_t region3_r1_pms_w:1;
/** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
* Region read authority in REE_MODE1
*/
uint32_t region3_r1_pms_r:1;
uint32_t reserved_7:1;
/** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
* Region execute authority in REE_MODE2
*/
uint32_t region3_r2_pms_x:1;
/** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
* Region write authority in REE_MODE2
*/
uint32_t region3_r2_pms_w:1;
/** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
* Region read authority in REE_MODE2
*/
uint32_t region3_r2_pms_r:1;
/** region3_lock : R/W; bitpos: [11]; default: 0;
* Set 1 to lock region3 configuration
*/
uint32_t region3_lock:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_apm_region3_pms_attr_reg_t;
/** Group: PMS function control register */
/** Type of func_ctrl register
* PMS function control register
*/
typedef union {
struct {
/** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
* PMS M0 function enable
*/
uint32_t m0_pms_func_en:1;
/** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
* PMS M1 function enable
*/
uint32_t m1_pms_func_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_func_ctrl_reg_t;
/** Group: M0 status register */
/** Type of m0_status register
* M0 status register
*/
typedef union {
struct {
/** m0_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m0_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m0_status_reg_t;
/** Group: M0 status clear register */
/** Type of m0_status_clr register
* M0 status clear register
*/
typedef union {
struct {
/** m0_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m0_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m0_status_clr_reg_t;
/** Group: M0 exception_info0 register */
/** Type of m0_exception_info0 register
* M0 exception_info0 register
*/
typedef union {
struct {
/** m0_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m0_exception_region:4;
uint32_t reserved_4:12;
/** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m0_exception_mode:2;
/** m0_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m0_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m0_exception_info0_reg_t;
/** Group: M0 exception_info1 register */
/** Type of m0_exception_info1 register
* M0 exception_info1 register
*/
typedef union {
struct {
/** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m0_exception_addr:32;
};
uint32_t val;
} lp_apm_m0_exception_info1_reg_t;
/** Group: M1 status register */
/** Type of m1_status register
* M1 status register
*/
typedef union {
struct {
/** m1_exception_status : RO; bitpos: [1:0]; default: 0;
* Exception status
*/
uint32_t m1_exception_status:2;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_m1_status_reg_t;
/** Group: M1 status clear register */
/** Type of m1_status_clr register
* M1 status clear register
*/
typedef union {
struct {
/** m1_region_status_clr : WT; bitpos: [0]; default: 0;
* Clear exception status
*/
uint32_t m1_region_status_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_m1_status_clr_reg_t;
/** Group: M1 exception_info0 register */
/** Type of m1_exception_info0 register
* M1 exception_info0 register
*/
typedef union {
struct {
/** m1_exception_region : RO; bitpos: [3:0]; default: 0;
* Exception region
*/
uint32_t m1_exception_region:4;
uint32_t reserved_4:12;
/** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
* Exception mode
*/
uint32_t m1_exception_mode:2;
/** m1_exception_id : RO; bitpos: [22:18]; default: 0;
* Exception id information
*/
uint32_t m1_exception_id:5;
uint32_t reserved_23:9;
};
uint32_t val;
} lp_apm_m1_exception_info0_reg_t;
/** Group: M1 exception_info1 register */
/** Type of m1_exception_info1 register
* M1 exception_info1 register
*/
typedef union {
struct {
/** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
* Exception addr
*/
uint32_t m1_exception_addr:32;
};
uint32_t val;
} lp_apm_m1_exception_info1_reg_t;
/** Group: APM interrupt enable register */
/** Type of int_en register
* APM interrupt enable register
*/
typedef union {
struct {
/** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
* APM M0 interrupt enable
*/
uint32_t m0_apm_int_en:1;
/** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
* APM M1 interrupt enable
*/
uint32_t m1_apm_int_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_apm_int_en_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_apm_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 35725664;
* reg_date
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_apm_date_reg_t;
typedef struct {
volatile lp_apm_region_filter_en_reg_t region_filter_en;
volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr;
volatile lp_apm_region1_addr_start_reg_t region1_addr_start;
volatile lp_apm_region1_addr_end_reg_t region1_addr_end;
volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr;
volatile lp_apm_region2_addr_start_reg_t region2_addr_start;
volatile lp_apm_region2_addr_end_reg_t region2_addr_end;
volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr;
volatile lp_apm_region3_addr_start_reg_t region3_addr_start;
volatile lp_apm_region3_addr_end_reg_t region3_addr_end;
volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr;
uint32_t reserved_034[36];
volatile lp_apm_func_ctrl_reg_t func_ctrl;
volatile lp_apm_m0_status_reg_t m0_status;
volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
volatile lp_apm_m1_status_reg_t m1_status;
volatile lp_apm_m1_status_clr_reg_t m1_status_clr;
volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0;
volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1;
volatile lp_apm_int_en_reg_t int_en;
volatile lp_apm_clock_gate_reg_t clock_gate;
uint32_t reserved_0f0[3];
volatile lp_apm_date_reg_t date;
} lp_apm_dev_t;
extern lp_apm_dev_t LP_APM;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/include/soc/lp_clkrst_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_CLKRST_LP_CLK_CONF_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_S 0
/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
* need_des
*/
#define LP_CLKRST_FAST_CLK_SEL 0x00000003U
#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U
#define LP_CLKRST_FAST_CLK_SEL_S 2
/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_S 4
/** LP_CLKRST_LP_CLK_PO_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
* need_des
*/
#define LP_CLKRST_AON_SLOW_OEN (BIT(0))
#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_AON_SLOW_OEN_S 0
/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
* need_des
*/
#define LP_CLKRST_AON_FAST_OEN (BIT(1))
#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U
#define LP_CLKRST_AON_FAST_OEN_S 1
/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
* need_des
*/
#define LP_CLKRST_SOSC_OEN (BIT(2))
#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
#define LP_CLKRST_SOSC_OEN_V 0x00000001U
#define LP_CLKRST_SOSC_OEN_S 2
/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
* need_des
*/
#define LP_CLKRST_FOSC_OEN (BIT(3))
#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
#define LP_CLKRST_FOSC_OEN_V 0x00000001U
#define LP_CLKRST_FOSC_OEN_S 3
/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
* need_des
*/
#define LP_CLKRST_OSC32K_OEN (BIT(4))
#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
#define LP_CLKRST_OSC32K_OEN_V 0x00000001U
#define LP_CLKRST_OSC32K_OEN_S 4
/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
* need_des
*/
#define LP_CLKRST_XTAL32K_OEN (BIT(5))
#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U
#define LP_CLKRST_XTAL32K_OEN_S 5
/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
* need_des
*/
#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6))
#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U
#define LP_CLKRST_CORE_EFUSE_OEN_S 6
/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
* need_des
*/
#define LP_CLKRST_SLOW_OEN (BIT(7))
#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
#define LP_CLKRST_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_SLOW_OEN_S 7
/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
* need_des
*/
#define LP_CLKRST_FAST_OEN (BIT(8))
#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
#define LP_CLKRST_FAST_OEN_V 0x00000001U
#define LP_CLKRST_FAST_OEN_S 8
/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
* need_des
*/
#define LP_CLKRST_RNG_OEN (BIT(9))
#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
#define LP_CLKRST_RNG_OEN_V 0x00000001U
#define LP_CLKRST_RNG_OEN_S 9
/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
* need_des
*/
#define LP_CLKRST_LPBUS_OEN (BIT(10))
#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
#define LP_CLKRST_LPBUS_OEN_V 0x00000001U
#define LP_CLKRST_LPBUS_OEN_S 10
/** LP_CLKRST_LP_CLK_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_FAST_ORI_GATE (BIT(31))
#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U
#define LP_CLKRST_FAST_ORI_GATE_S 31
/** LP_CLKRST_LP_RST_EN_REG register
* need_des
*/
#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
/** LP_CLKRST_HUK_RESET_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LP_CLKRST_HUK_RESET_EN (BIT(27))
#define LP_CLKRST_HUK_RESET_EN_M (LP_CLKRST_HUK_RESET_EN_V << LP_CLKRST_HUK_RESET_EN_S)
#define LP_CLKRST_HUK_RESET_EN_V 0x00000001U
#define LP_CLKRST_HUK_RESET_EN_S 27
/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28))
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28
/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29))
#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U
#define LP_CLKRST_LP_TIMER_RESET_EN_S 29
/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_WDT_RESET_EN (BIT(30))
#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U
#define LP_CLKRST_WDT_RESET_EN_S 30
/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31))
#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U
#define LP_CLKRST_ANA_PERI_RESET_EN_S 31
/** LP_CLKRST_RESET_CAUSE_REG register
* need_des
*/
#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
* need_des
*/
#define LP_CLKRST_RESET_CAUSE 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU
#define LP_CLKRST_RESET_CAUSE_S 0
/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5))
#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_S 5
/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29))
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29
/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30))
#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30
/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31))
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31
/** LP_CLKRST_CPU_RESET_REG register
* need_des
*/
#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
* write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
* reset feature
*/
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21))
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21
/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
* need_des
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22
/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25))
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U
#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25
/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
* need_des
*/
#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU
#define LP_CLKRST_CPU_STALL_WAIT_S 26
/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CPU_STALL_EN (BIT(31))
#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U
#define LP_CLKRST_CPU_STALL_EN_S 31
/** LP_CLKRST_FOSC_CNTL_REG register
* need_des
*/
#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
#define LP_CLKRST_FOSC_DFREQ 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_S 22
/** LP_CLKRST_RC32K_CNTL_REG register
* need_des
*/
#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
#define LP_CLKRST_RC32K_DFREQ 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_S 22
/** LP_CLKRST_CLK_TO_HP_REG register
* need_des
*/
#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28))
#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_XTAL32K_S 28
/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_SOSC (BIT(29))
#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_SOSC_S 29
/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_OSC32K (BIT(30))
#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_OSC32K_S 30
/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LP_CLKRST_ICG_HP_FOSC (BIT(31))
#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_FOSC_S 31
/** LP_CLKRST_LPMEM_FORCE_REG register
* need_des
*/
#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31))
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31
/** LP_CLKRST_LPPERI_REG register
* need_des
*/
#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28)
/** LP_CLKRST_HUK_CLK_SEL : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LP_CLKRST_HUK_CLK_SEL (BIT(29))
#define LP_CLKRST_HUK_CLK_SEL_M (LP_CLKRST_HUK_CLK_SEL_V << LP_CLKRST_HUK_CLK_SEL_S)
#define LP_CLKRST_HUK_CLK_SEL_V 0x00000001U
#define LP_CLKRST_HUK_CLK_SEL_S 29
/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30))
#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S)
#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_I2C_CLK_SEL_S 30
/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31))
#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S)
#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U
#define LP_CLKRST_LP_UART_CLK_SEL_S 31
/** LP_CLKRST_XTAL32K_REG register
* need_des
*/
#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
#define LP_CLKRST_DRES_XTAL32K 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_S 22
/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
#define LP_CLKRST_DGM_XTAL32K 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_S 25
/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_DBUF_XTAL32K (BIT(28))
#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U
#define LP_CLKRST_DBUF_XTAL32K_S 28
/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
#define LP_CLKRST_DAC_XTAL32K 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_S 29
/** LP_CLKRST_DATE_REG register
* need_des
*/
#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36720768;
* need_des
*/
#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_S 0
/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_CLK_EN (BIT(31))
#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
#define LP_CLKRST_CLK_EN_V 0x00000001U
#define LP_CLKRST_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
* need_des
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
* need_des
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
* need_des
*/
uint32_t fast_clk_sel:2;
/** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0;
* need_des
*/
uint32_t lp_peri_div_num:8;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_clkrst_lp_clk_conf_reg_t;
/** Type of lp_clk_po_en register
* need_des
*/
typedef union {
struct {
/** aon_slow_oen : R/W; bitpos: [0]; default: 1;
* need_des
*/
uint32_t aon_slow_oen:1;
/** aon_fast_oen : R/W; bitpos: [1]; default: 1;
* need_des
*/
uint32_t aon_fast_oen:1;
/** sosc_oen : R/W; bitpos: [2]; default: 1;
* need_des
*/
uint32_t sosc_oen:1;
/** fosc_oen : R/W; bitpos: [3]; default: 1;
* need_des
*/
uint32_t fosc_oen:1;
/** osc32k_oen : R/W; bitpos: [4]; default: 1;
* need_des
*/
uint32_t osc32k_oen:1;
/** xtal32k_oen : R/W; bitpos: [5]; default: 1;
* need_des
*/
uint32_t xtal32k_oen:1;
/** core_efuse_oen : R/W; bitpos: [6]; default: 1;
* need_des
*/
uint32_t core_efuse_oen:1;
/** slow_oen : R/W; bitpos: [7]; default: 1;
* need_des
*/
uint32_t slow_oen:1;
/** fast_oen : R/W; bitpos: [8]; default: 1;
* need_des
*/
uint32_t fast_oen:1;
/** rng_oen : R/W; bitpos: [9]; default: 1;
* need_des
*/
uint32_t rng_oen:1;
/** lpbus_oen : R/W; bitpos: [10]; default: 1;
* need_des
*/
uint32_t lpbus_oen:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_po_en_reg_t;
/** Type of lp_clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** fast_ori_gate : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t fast_ori_gate:1;
};
uint32_t val;
} lp_clkrst_lp_clk_en_reg_t;
/** Type of lp_rst_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** huk_reset_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t huk_reset_en:1;
/** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t aon_efuse_core_reset_en:1;
/** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_timer_reset_en:1;
/** wdt_reset_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t wdt_reset_en:1;
/** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_peri_reset_en:1;
};
uint32_t val;
} lp_clkrst_lp_rst_en_reg_t;
/** Type of reset_cause register
* need_des
*/
typedef union {
struct {
/** reset_cause : RO; bitpos: [4:0]; default: 0;
* need_des
*/
uint32_t reset_cause:5;
/** core0_reset_flag : RO; bitpos: [5]; default: 1;
* need_des
*/
uint32_t core0_reset_flag:1;
uint32_t reserved_6:23;
/** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t core0_reset_cause_clr:1;
/** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t core0_reset_flag_set:1;
/** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t core0_reset_flag_clr:1;
};
uint32_t val;
} lp_clkrst_reset_cause_reg_t;
/** Type of cpu_reset register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1;
* write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
* reset feature
*/
uint32_t hpcore0_lockup_reset_en:1;
/** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
* need_des
*/
uint32_t rtc_wdt_cpu_reset_length:3;
/** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t rtc_wdt_cpu_reset_en:1;
/** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
* need_des
*/
uint32_t cpu_stall_wait:5;
/** cpu_stall_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t cpu_stall_en:1;
};
uint32_t val;
} lp_clkrst_cpu_reset_reg_t;
/** Type of fosc_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t fosc_dfreq:10;
};
uint32_t val;
} lp_clkrst_fosc_cntl_reg_t;
/** Type of rc32k_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
* need_des
*/
uint32_t rc32k_dfreq:10;
};
uint32_t val;
} lp_clkrst_rc32k_cntl_reg_t;
/** Type of clk_to_hp register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t icg_hp_xtal32k:1;
/** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t icg_hp_sosc:1;
/** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t icg_hp_osc32k:1;
/** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t icg_hp_fosc:1;
};
uint32_t val;
} lp_clkrst_clk_to_hp_reg_t;
/** Type of lpmem_force register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lpmem_clk_force_on:1;
};
uint32_t val;
} lp_clkrst_lpmem_force_reg_t;
/** Type of lpperi register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** huk_clk_sel : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t huk_clk_sel:1;
/** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_i2c_clk_sel:1;
/** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_uart_clk_sel:1;
};
uint32_t val;
} lp_clkrst_lpperi_reg_t;
/** Type of xtal32k register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
* need_des
*/
uint32_t dres_xtal32k:3;
/** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
* need_des
*/
uint32_t dgm_xtal32k:3;
/** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t dbuf_xtal32k:1;
/** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
* need_des
*/
uint32_t dac_xtal32k:3;
};
uint32_t val;
} lp_clkrst_xtal32k_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** clkrst_date : R/W; bitpos: [30:0]; default: 36720768;
* need_des
*/
uint32_t clkrst_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_clkrst_date_reg_t;
typedef struct {
volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
volatile lp_clkrst_reset_cause_reg_t reset_cause;
volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
volatile lp_clkrst_lpperi_reg_t lpperi;
volatile lp_clkrst_xtal32k_reg_t xtal32k;
uint32_t reserved_030[243];
volatile lp_clkrst_date_reg_t date;
} lp_clkrst_dev_t;
extern lp_clkrst_dev_t LP_CLKRST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of out_data register
* need des
*/
typedef union {
struct {
/** lp_gpio_out_data : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t lp_gpio_out_data:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_reg_t;
/** Type of out_data_w1ts register
* need des
*/
typedef union {
struct {
/** lp_gpio_out_data_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t lp_gpio_out_data_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_w1ts_reg_t;
/** Type of out_data_w1tc register
* need des
*/
typedef union {
struct {
/** lp_gpio_out_data_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t lp_gpio_out_data_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_data_w1tc_reg_t;
/** Type of out_enable register
* need des
*/
typedef union {
struct {
/** lp_gpio_enable : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t lp_gpio_enable:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_reg_t;
/** Type of out_enable_w1ts register
* need des
*/
typedef union {
struct {
/** lp_gpio_enable_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t lp_gpio_enable_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_w1ts_reg_t;
/** Type of out_enable_w1tc register
* need des
*/
typedef union {
struct {
/** lp_gpio_enable_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t lp_gpio_enable_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_out_enable_w1tc_reg_t;
/** Type of status register
* need des
*/
typedef union {
struct {
/** lp_gpio_status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
* set lp gpio output data
*/
uint32_t lp_gpio_status_interrupt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_reg_t;
/** Type of status_w1ts register
* need des
*/
typedef union {
struct {
/** lp_gpio_status_w1ts : WT; bitpos: [7:0]; default: 0;
* set one time output data
*/
uint32_t lp_gpio_status_w1ts:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_w1ts_reg_t;
/** Type of status_w1tc register
* need des
*/
typedef union {
struct {
/** lp_gpio_status_w1tc : WT; bitpos: [7:0]; default: 0;
* clear one time output data
*/
uint32_t lp_gpio_status_w1tc:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_w1tc_reg_t;
/** Type of in register
* need des
*/
typedef union {
struct {
/** lp_gpio_in_data_next : RO; bitpos: [7:0]; default: 0;
* need des
*/
uint32_t lp_gpio_in_data_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_in_reg_t;
/** Type of pin0 register
* need des
*/
typedef union {
struct {
/** lp_gpio0_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio0_sync_bypass:2;
/** lp_gpio0_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio0_pad_driver:1;
/** lp_gpio0_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio0_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio0_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio0_int_type:3;
/** lp_gpio0_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio0_wakeup_enable:1;
/** lp_gpio0_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio0_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin0_reg_t;
/** Type of pin1 register
* need des
*/
typedef union {
struct {
/** lp_gpio1_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio1_sync_bypass:2;
/** lp_gpio1_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio1_pad_driver:1;
/** lp_gpio1_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio1_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio1_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio1_int_type:3;
/** lp_gpio1_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio1_wakeup_enable:1;
/** lp_gpio1_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio1_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin1_reg_t;
/** Type of pin2 register
* need des
*/
typedef union {
struct {
/** lp_gpio2_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio2_sync_bypass:2;
/** lp_gpio2_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio2_pad_driver:1;
/** lp_gpio2_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio2_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio2_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio2_int_type:3;
/** lp_gpio2_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio2_wakeup_enable:1;
/** lp_gpio2_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio2_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin2_reg_t;
/** Type of pin3 register
* need des
*/
typedef union {
struct {
/** lp_gpio3_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio3_sync_bypass:2;
/** lp_gpio3_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio3_pad_driver:1;
/** lp_gpio3_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio3_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio3_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio3_int_type:3;
/** lp_gpio3_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio3_wakeup_enable:1;
/** lp_gpio3_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio3_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin3_reg_t;
/** Type of pin4 register
* need des
*/
typedef union {
struct {
/** lp_gpio4_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio4_sync_bypass:2;
/** lp_gpio4_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio4_pad_driver:1;
/** lp_gpio4_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio4_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio4_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio4_int_type:3;
/** lp_gpio4_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio4_wakeup_enable:1;
/** lp_gpio4_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio4_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin4_reg_t;
/** Type of pin5 register
* need des
*/
typedef union {
struct {
/** lp_gpio5_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio5_sync_bypass:2;
/** lp_gpio5_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio5_pad_driver:1;
/** lp_gpio5_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio5_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio5_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio5_int_type:3;
/** lp_gpio5_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio5_wakeup_enable:1;
/** lp_gpio5_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio5_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin5_reg_t;
/** Type of pin6 register
* need des
*/
typedef union {
struct {
/** lp_gpio6_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio6_sync_bypass:2;
/** lp_gpio6_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio6_pad_driver:1;
/** lp_gpio6_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio6_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio6_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio6_int_type:3;
/** lp_gpio6_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio6_wakeup_enable:1;
/** lp_gpio6_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio6_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin6_reg_t;
/** Type of pin7 register
* need des
*/
typedef union {
struct {
/** lp_gpio7_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio7_sync_bypass:2;
/** lp_gpio7_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio7_pad_driver:1;
/** lp_gpio7_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio7_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio7_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio7_int_type:3;
/** lp_gpio7_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio7_wakeup_enable:1;
/** lp_gpio7_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio7_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin7_reg_t;
/** Type of gpio0 register
* need des
*/
typedef union {
struct {
/** lp_gpio0_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_oe:1;
/** lp_gpio0_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio0_slp_sel:1;
/** lp_gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_wpd:1;
/** lp_gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_wpu:1;
/** lp_gpio0_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_ie:1;
/** lp_gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_drv:2;
/** lp_gpio0_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio0_fun_wpd:1;
/** lp_gpio0_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio0_fun_wpu:1;
/** lp_gpio0_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio0_fun_ie:1;
/** lp_gpio0_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio0_fun_drv:2;
/** lp_gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio0_reg_t;
/** Type of gpio1 register
* need des
*/
typedef union {
struct {
/** lp_gpio1_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_oe:1;
/** lp_gpio1_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio1_slp_sel:1;
/** lp_gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_wpd:1;
/** lp_gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_wpu:1;
/** lp_gpio1_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_ie:1;
/** lp_gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_drv:2;
/** lp_gpio1_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio1_fun_wpd:1;
/** lp_gpio1_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio1_fun_wpu:1;
/** lp_gpio1_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio1_fun_ie:1;
/** lp_gpio1_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio1_fun_drv:2;
/** lp_gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio1_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio1_reg_t;
/** Type of gpio2 register
* need des
*/
typedef union {
struct {
/** lp_gpio2_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_oe:1;
/** lp_gpio2_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio2_slp_sel:1;
/** lp_gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_wpd:1;
/** lp_gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_wpu:1;
/** lp_gpio2_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_ie:1;
/** lp_gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_drv:2;
/** lp_gpio2_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio2_fun_wpd:1;
/** lp_gpio2_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio2_fun_wpu:1;
/** lp_gpio2_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio2_fun_ie:1;
/** lp_gpio2_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio2_fun_drv:2;
/** lp_gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio2_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio2_reg_t;
/** Type of gpio3 register
* need des
*/
typedef union {
struct {
/** lp_gpio3_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_oe:1;
/** lp_gpio3_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio3_slp_sel:1;
/** lp_gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_wpd:1;
/** lp_gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_wpu:1;
/** lp_gpio3_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_ie:1;
/** lp_gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_drv:2;
/** lp_gpio3_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio3_fun_wpd:1;
/** lp_gpio3_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio3_fun_wpu:1;
/** lp_gpio3_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio3_fun_ie:1;
/** lp_gpio3_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio3_fun_drv:2;
/** lp_gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio3_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio3_reg_t;
/** Type of gpio4 register
* need des
*/
typedef union {
struct {
/** lp_gpio4_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_oe:1;
/** lp_gpio4_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio4_slp_sel:1;
/** lp_gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_wpd:1;
/** lp_gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_wpu:1;
/** lp_gpio4_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_ie:1;
/** lp_gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_drv:2;
/** lp_gpio4_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio4_fun_wpd:1;
/** lp_gpio4_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio4_fun_wpu:1;
/** lp_gpio4_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio4_fun_ie:1;
/** lp_gpio4_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio4_fun_drv:2;
/** lp_gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio4_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio4_reg_t;
/** Type of gpio5 register
* need des
*/
typedef union {
struct {
/** lp_gpio5_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_oe:1;
/** lp_gpio5_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio5_slp_sel:1;
/** lp_gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_wpd:1;
/** lp_gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_wpu:1;
/** lp_gpio5_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_ie:1;
/** lp_gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_drv:2;
/** lp_gpio5_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio5_fun_wpd:1;
/** lp_gpio5_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio5_fun_wpu:1;
/** lp_gpio5_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio5_fun_ie:1;
/** lp_gpio5_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio5_fun_drv:2;
/** lp_gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio5_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio5_reg_t;
/** Type of gpio6 register
* need des
*/
typedef union {
struct {
/** lp_gpio6_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_oe:1;
/** lp_gpio6_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio6_slp_sel:1;
/** lp_gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_wpd:1;
/** lp_gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_wpu:1;
/** lp_gpio6_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_ie:1;
/** lp_gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_drv:2;
/** lp_gpio6_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio6_fun_wpd:1;
/** lp_gpio6_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio6_fun_wpu:1;
/** lp_gpio6_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio6_fun_ie:1;
/** lp_gpio6_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio6_fun_drv:2;
/** lp_gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio6_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio6_reg_t;
/** Type of gpio7 register
* need des
*/
typedef union {
struct {
/** lp_gpio7_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_oe:1;
/** lp_gpio7_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio7_slp_sel:1;
/** lp_gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_wpd:1;
/** lp_gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_wpu:1;
/** lp_gpio7_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_ie:1;
/** lp_gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_drv:2;
/** lp_gpio7_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio7_fun_wpd:1;
/** lp_gpio7_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio7_fun_wpu:1;
/** lp_gpio7_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio7_fun_ie:1;
/** lp_gpio7_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio7_fun_drv:2;
/** lp_gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio7_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio7_reg_t;
/** Type of status_interrupt register
* need des
*/
typedef union {
struct {
/** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
* need des
*/
uint32_t status_interrupt_next:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_io_status_interrupt_reg_t;
/** Type of debug_sel0 register
* need des
*/
typedef union {
struct {
/** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t lp_debug_sel0:7;
/** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0;
* need des
*/
uint32_t lp_debug_sel1:7;
/** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0;
* need des
*/
uint32_t lp_debug_sel2:7;
/** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0;
* need des
*/
uint32_t lp_debug_sel3:7;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_io_debug_sel0_reg_t;
/** Type of debug_sel1 register
* need des
*/
typedef union {
struct {
/** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0;
* need des
*/
uint32_t lp_debug_sel4:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lp_io_debug_sel1_reg_t;
/** Type of lpi2c register
* need des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1;
* need des
*/
uint32_t lp_i2c_sda_ie:1;
/** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1;
* need des
*/
uint32_t lp_i2c_scl_ie:1;
};
uint32_t val;
} lp_io_lpi2c_reg_t;
/** Type of date register
* need des
*/
typedef union {
struct {
/** lp_io_date : R/W; bitpos: [30:0]; default: 35660032;
* need des
*/
uint32_t lp_io_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_io_date_reg_t;
typedef struct {
volatile lp_io_out_data_reg_t out_data;
volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
volatile lp_io_out_enable_reg_t out_enable;
volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts;
volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc;
volatile lp_io_status_reg_t status;
volatile lp_io_status_w1ts_reg_t status_w1ts;
volatile lp_io_status_w1tc_reg_t status_w1tc;
volatile lp_io_in_reg_t in;
volatile lp_io_pin0_reg_t pin0;
volatile lp_io_pin1_reg_t pin1;
volatile lp_io_pin2_reg_t pin2;
volatile lp_io_pin3_reg_t pin3;
volatile lp_io_pin4_reg_t pin4;
volatile lp_io_pin5_reg_t pin5;
volatile lp_io_pin6_reg_t pin6;
volatile lp_io_pin7_reg_t pin7;
volatile lp_io_gpio0_reg_t gpio0;
volatile lp_io_gpio1_reg_t gpio1;
volatile lp_io_gpio2_reg_t gpio2;
volatile lp_io_gpio3_reg_t gpio3;
volatile lp_io_gpio4_reg_t gpio4;
volatile lp_io_gpio5_reg_t gpio5;
volatile lp_io_gpio6_reg_t gpio6;
volatile lp_io_gpio7_reg_t gpio7;
volatile lp_io_status_interrupt_reg_t status_interrupt;
volatile lp_io_debug_sel0_reg_t debug_sel0;
volatile lp_io_debug_sel1_reg_t debug_sel1;
volatile lp_io_lpi2c_reg_t lpi2c;
uint32_t reserved_078[225];
volatile lp_io_date_reg_t date;
} lp_io_dev_t;
extern lp_io_dev_t LP_IO;
#ifndef __cplusplus
_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

72
components/soc/esp32c5/include/soc/lp_tee_reg.h Normal file
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@ -0,0 +1,72 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TEE_M0_MODE_CTRL_REG register
* Tee mode control register
*/
#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define LP_TEE_M0_MODE 0x00000003U
#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
#define LP_TEE_M0_MODE_V 0x00000003U
#define LP_TEE_M0_MODE_S 0
/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
*/
#define LP_TEE_M0_LOCK (BIT(2))
#define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S)
#define LP_TEE_M0_LOCK_V 0x00000001U
#define LP_TEE_M0_LOCK_S 2
/** LP_TEE_CLOCK_GATE_REG register
* Clock gating register
*/
#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define LP_TEE_CLK_EN (BIT(0))
#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
#define LP_TEE_CLK_EN_V 0x00000001U
#define LP_TEE_CLK_EN_S 0
/** LP_TEE_FORCE_ACC_HP_REG register
* need_des
*/
#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0))
#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U
#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0
/** LP_TEE_DATE_REG register
* Version register
*/
#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
* reg_tee_date
*/
#define LP_TEE_DATE_REG 0x0FFFFFFFU
#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
#define LP_TEE_DATE_REG_V 0x0FFFFFFFU
#define LP_TEE_DATE_REG_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 3;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m0_mode:2;
/** m0_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
*/
uint32_t m0_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} lp_tee_m0_mode_ctrl_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_clock_gate_reg_t;
/** Group: configure_register */
/** Type of force_acc_hp register
* need_des
*/
typedef union {
struct {
/** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
* need_des
*/
uint32_t force_acc_hpmem_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_force_acc_hp_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date_reg : R/W; bitpos: [27:0]; default: 35725664;
* reg_tee_date
*/
uint32_t date_reg:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_tee_date_reg_t;
typedef struct {
volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile lp_tee_clock_gate_reg_t clock_gate;
uint32_t reserved_008[34];
volatile lp_tee_force_acc_hp_reg_t force_acc_hp;
uint32_t reserved_094[26];
volatile lp_tee_date_reg_t date;
} lp_tee_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TIMER_TAR0_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0
/** LP_TIMER_TAR0_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31
/** LP_TIMER_TAR1_LOW_REG register
* need_des
*/
#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0
/** LP_TIMER_TAR1_HIGH_REG register
* need_des
*/
#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31
/** LP_TIMER_UPDATE_REG register
* need_des
*/
#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28))
#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_UPDATE_S 28
/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29
/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30
/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31
/** LP_TIMER_MAIN_BUF0_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0
/** LP_TIMER_MAIN_BUF0_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
/** LP_TIMER_MAIN_BUF1_LOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0
/** LP_TIMER_MAIN_BUF1_HIGH_REG register
* need_des
*/
#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
/** LP_TIMER_MAIN_OVERFLOW_REG register
* need_des
*/
#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31))
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31
/** LP_TIMER_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_RAW (BIT(30))
#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U
#define LP_TIMER_OVERFLOW_RAW_S 30
/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31
/** LP_TIMER_INT_ST_REG register
* need_des
*/
#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ST (BIT(30))
#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
#define LP_TIMER_OVERFLOW_ST_V 0x00000001U
#define LP_TIMER_OVERFLOW_ST_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31
/** LP_TIMER_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_ENA (BIT(30))
#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U
#define LP_TIMER_OVERFLOW_ENA_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31
/** LP_TIMER_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_OVERFLOW_CLR (BIT(30))
#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U
#define LP_TIMER_OVERFLOW_CLR_S 30
/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31
/** LP_TIMER_LP_INT_RAW_REG register
* need_des
*/
#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
/** LP_TIMER_LP_INT_ST_REG register
* need_des
*/
#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31
/** LP_TIMER_LP_INT_ENA_REG register
* need_des
*/
#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
/** LP_TIMER_LP_INT_CLR_REG register
* need_des
*/
#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
/** LP_TIMER_DATE_REG register
* need_des
*/
#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
#define LP_TIMER_DATE 0x7FFFFFFFU
#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
#define LP_TIMER_DATE_V 0x7FFFFFFFU
#define LP_TIMER_DATE_S 0
/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_TIMER_CLK_EN (BIT(31))
#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
#define LP_TIMER_CLK_EN_V 0x00000001U
#define LP_TIMER_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of tar0_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low0:32;
};
uint32_t val;
} lp_timer_tar0_low_reg_t;
/** Type of tar0_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high0:16;
uint32_t reserved_16:15;
/** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en0:1;
};
uint32_t val;
} lp_timer_tar0_high_reg_t;
/** Type of tar1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low1:32;
};
uint32_t val;
} lp_timer_tar1_low_reg_t;
/** Type of tar1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high1:16;
uint32_t reserved_16:15;
/** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en1:1;
};
uint32_t val;
} lp_timer_tar1_high_reg_t;
/** Type of update register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** main_timer_update : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t main_timer_update:1;
/** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t main_timer_xtal_off:1;
/** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_sys_stall:1;
/** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_sys_rst:1;
};
uint32_t val;
} lp_timer_update_reg_t;
/** Type of main_buf0_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_low:32;
};
uint32_t val;
} lp_timer_main_buf0_low_reg_t;
/** Type of main_buf0_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf0_high_reg_t;
/** Type of main_buf1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_low:32;
};
uint32_t val;
} lp_timer_main_buf1_low_reg_t;
/** Type of main_buf1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf1_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf1_high_reg_t;
/** Type of main_overflow register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_alarm_load:1;
};
uint32_t val;
} lp_timer_main_overflow_reg_t;
/** Type of int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_raw:1;
/** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_raw:1;
};
uint32_t val;
} lp_timer_int_raw_reg_t;
/** Type of int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_st:1;
/** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_st:1;
};
uint32_t val;
} lp_timer_int_st_reg_t;
/** Type of int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_ena:1;
/** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_ena:1;
};
uint32_t val;
} lp_timer_int_ena_reg_t;
/** Type of int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** overflow_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t overflow_clr:1;
/** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t soc_wakeup_int_clr:1;
};
uint32_t val;
} lp_timer_int_clr_reg_t;
/** Type of lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_raw:1;
/** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_raw:1;
};
uint32_t val;
} lp_timer_lp_int_raw_reg_t;
/** Type of lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_st:1;
/** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_st:1;
};
uint32_t val;
} lp_timer_lp_int_st_reg_t;
/** Type of lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_ena:1;
/** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_ena:1;
};
uint32_t val;
} lp_timer_lp_int_ena_reg_t;
/** Type of lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t main_timer_overflow_lp_int_clr:1;
/** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_lp_int_clr:1;
};
uint32_t val;
} lp_timer_lp_int_clr_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 34672976;
* need_des
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_timer_date_reg_t;
typedef struct {
volatile lp_timer_tar0_low_reg_t tar0_low;
volatile lp_timer_tar0_high_reg_t tar0_high;
volatile lp_timer_tar1_low_reg_t tar1_low;
volatile lp_timer_tar1_high_reg_t tar1_high;
volatile lp_timer_update_reg_t update;
volatile lp_timer_main_buf0_low_reg_t main_buf0_low;
volatile lp_timer_main_buf0_high_reg_t main_buf0_high;
volatile lp_timer_main_buf1_low_reg_t main_buf1_low;
volatile lp_timer_main_buf1_high_reg_t main_buf1_high;
volatile lp_timer_main_overflow_reg_t main_overflow;
volatile lp_timer_int_raw_reg_t int_raw;
volatile lp_timer_int_st_reg_t int_st;
volatile lp_timer_int_ena_reg_t int_ena;
volatile lp_timer_int_clr_reg_t int_clr;
volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
volatile lp_timer_lp_int_st_reg_t lp_int_st;
volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
uint32_t reserved_048[237];
volatile lp_timer_date_reg_t date;
} lp_timer_dev_t;
extern lp_timer_dev_t LP_TIMER;
#ifndef __cplusplus
_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPPERI_CLK_EN_REG register
* need_des
*/
#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
* need_des
*/
#define LPPERI_RNG_CK_EN (BIT(24))
#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
#define LPPERI_RNG_CK_EN_V 0x00000001U
#define LPPERI_RNG_CK_EN_S 24
/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
* need_des
*/
#define LPPERI_OTP_DBG_CK_EN (BIT(25))
#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U
#define LPPERI_OTP_DBG_CK_EN_S 25
/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1;
* need_des
*/
#define LPPERI_LP_UART_CK_EN (BIT(26))
#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S)
#define LPPERI_LP_UART_CK_EN_V 0x00000001U
#define LPPERI_LP_UART_CK_EN_S 26
/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
* need_des
*/
#define LPPERI_LP_IO_CK_EN (BIT(27))
#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
#define LPPERI_LP_IO_CK_EN_V 0x00000001U
#define LPPERI_LP_IO_CK_EN_S 27
/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1;
* need_des
*/
#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S)
#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_CK_EN_S 28
/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1;
* need_des
*/
#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S)
#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_CK_EN_S 29
/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
* need_des
*/
#define LPPERI_EFUSE_CK_EN (BIT(30))
#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
#define LPPERI_EFUSE_CK_EN_V 0x00000001U
#define LPPERI_EFUSE_CK_EN_S 30
/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_LP_CPU_CK_EN (BIT(31))
#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S)
#define LPPERI_LP_CPU_CK_EN_V 0x00000001U
#define LPPERI_LP_CPU_CK_EN_S 31
/** LPPERI_RESET_EN_REG register
* need_des
*/
#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
* need_des
*/
#define LPPERI_BUS_RESET_EN (BIT(23))
#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
#define LPPERI_BUS_RESET_EN_V 0x00000001U
#define LPPERI_BUS_RESET_EN_S 23
/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
* need_des
*/
#define LPPERI_OTP_DBG_RESET_EN (BIT(25))
#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U
#define LPPERI_OTP_DBG_RESET_EN_S 25
/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define LPPERI_LP_UART_RESET_EN (BIT(26))
#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S)
#define LPPERI_LP_UART_RESET_EN_V 0x00000001U
#define LPPERI_LP_UART_RESET_EN_S 26
/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LPPERI_LP_IO_RESET_EN (BIT(27))
#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
#define LPPERI_LP_IO_RESET_EN_V 0x00000001U
#define LPPERI_LP_IO_RESET_EN_S 27
/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28))
#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S)
#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_EXT_I2C_RESET_EN_S 28
/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29))
#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S)
#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U
#define LPPERI_LP_ANA_I2C_RESET_EN_S 29
/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_EFUSE_RESET_EN (BIT(30))
#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
#define LPPERI_EFUSE_RESET_EN_V 0x00000001U
#define LPPERI_EFUSE_RESET_EN_S 30
/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_LP_CPU_RESET_EN (BIT(31))
#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S)
#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U
#define LPPERI_LP_CPU_RESET_EN_S 31
/** LPPERI_RNG_DATA_REG register
* need_des
*/
#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LPPERI_RND_DATA 0xFFFFFFFFU
#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S)
#define LPPERI_RND_DATA_V 0xFFFFFFFFU
#define LPPERI_RND_DATA_S 0
/** LPPERI_CPU_REG register
* need_des
*/
#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31))
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S)
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U
#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31
/** LPPERI_BUS_TIMEOUT_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S)
#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14
/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30))
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S)
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30
/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31))
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S)
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31
/** LPPERI_BUS_TIMEOUT_ADDR_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S)
#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0
/** LPPERI_BUS_TIMEOUT_UID_REG register
* need_des
*/
#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* need_des
*/
#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S)
#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU
#define LPPERI_LP_PERI_TIMEOUT_UID_S 0
/** LPPERI_MEM_CTRL_REG register
* need_des
*/
#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0))
#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S)
#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0
/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_FLAG (BIT(1))
#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S)
#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U
#define LPPERI_UART_WAKEUP_FLAG_S 1
/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LPPERI_UART_WAKEUP_EN (BIT(29))
#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S)
#define LPPERI_UART_WAKEUP_EN_V 0x00000001U
#define LPPERI_UART_WAKEUP_EN_S 29
/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LPPERI_UART_MEM_FORCE_PD (BIT(30))
#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S)
#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PD_S 30
/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
* need_des
*/
#define LPPERI_UART_MEM_FORCE_PU (BIT(31))
#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S)
#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U
#define LPPERI_UART_MEM_FORCE_PU_S 31
/** LPPERI_INTERRUPT_SOURCE_REG register
* need_des
*/
#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU
#define LPPERI_LP_INTERRUPT_SOURCE_S 0
/** LPPERI_RNG_CFG_REG register
* need_des
*/
#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x24)
/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
* need des
*/
#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0))
#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S)
#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U
#define LPPERI_RNG_SAMPLE_ENABLE_S 0
/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
* need des
*/
#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU
#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S)
#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU
#define LPPERI_RNG_TIMER_PSCALE_S 1
/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
* need des
*/
#define LPPERI_RNG_TIMER_EN (BIT(9))
#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S)
#define LPPERI_RNG_TIMER_EN_V 0x00000001U
#define LPPERI_RNG_TIMER_EN_S 9
/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
* need des
*/
#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU
#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S)
#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU
#define LPPERI_RNG_SAMPLE_CNT_S 24
/** LPPERI_DATE_REG register
* need_des
*/
#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36720720;
* need_des
*/
#define LPPERI_LPPERI_DATE 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_S 0
/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LPPERI_CLK_EN (BIT(31))
#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
#define LPPERI_CLK_EN_V 0x00000001U
#define LPPERI_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
* need_des
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1;
* need_des
*/
uint32_t otp_dbg_ck_en:1;
/** lp_uart_ck_en : R/W; bitpos: [26]; default: 1;
* need_des
*/
uint32_t lp_uart_ck_en:1;
/** lp_io_ck_en : R/W; bitpos: [27]; default: 1;
* need_des
*/
uint32_t lp_io_ck_en:1;
/** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1;
* need_des
*/
uint32_t lp_ext_i2c_ck_en:1;
/** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1;
* need_des
*/
uint32_t lp_ana_i2c_ck_en:1;
/** efuse_ck_en : R/W; bitpos: [30]; default: 1;
* need_des
*/
uint32_t efuse_ck_en:1;
/** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cpu_ck_en:1;
};
uint32_t val;
} lpperi_clk_en_reg_t;
/** Type of reset_en register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** bus_reset_en : WT; bitpos: [23]; default: 0;
* need_des
*/
uint32_t bus_reset_en:1;
uint32_t reserved_24:1;
/** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0;
* need_des
*/
uint32_t otp_dbg_reset_en:1;
/** lp_uart_reset_en : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t lp_uart_reset_en:1;
/** lp_io_reset_en : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t lp_io_reset_en:1;
/** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t lp_ext_i2c_reset_en:1;
/** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_ana_i2c_reset_en:1;
/** efuse_reset_en : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t efuse_reset_en:1;
/** lp_cpu_reset_en : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cpu_reset_en:1;
};
uint32_t val;
} lpperi_reset_en_reg_t;
/** Type of rng_data register
* need_des
*/
typedef union {
struct {
/** rnd_data : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t rnd_data:32;
};
uint32_t val;
} lpperi_rng_data_reg_t;
/** Type of cpu register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lpcore_dbgm_unavaliable:1;
};
uint32_t val;
} lpperi_cpu_reg_t;
/** Type of bus_timeout register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:14;
/** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535;
* need_des
*/
uint32_t lp_peri_timeout_thres:16;
/** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_int_clear:1;
/** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t lp_peri_timeout_protect_en:1;
};
uint32_t val;
} lpperi_bus_timeout_reg_t;
/** Type of bus_timeout_addr register
* need_des
*/
typedef union {
struct {
/** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_addr:32;
};
uint32_t val;
} lpperi_bus_timeout_addr_reg_t;
/** Type of bus_timeout_uid register
* need_des
*/
typedef union {
struct {
/** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* need_des
*/
uint32_t lp_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} lpperi_bus_timeout_uid_reg_t;
/** Type of mem_ctrl register
* need_des
*/
typedef union {
struct {
/** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
* need_des
*/
uint32_t uart_wakeup_flag_clr:1;
/** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
* need_des
*/
uint32_t uart_wakeup_flag:1;
uint32_t reserved_2:27;
/** uart_wakeup_en : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t uart_wakeup_en:1;
/** uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t uart_mem_force_pd:1;
/** uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
* need_des
*/
uint32_t uart_mem_force_pu:1;
};
uint32_t val;
} lpperi_mem_ctrl_reg_t;
/** Type of interrupt_source register
* need_des
*/
typedef union {
struct {
/** lp_interrupt_source : RO; bitpos: [5:0]; default: 0;
* BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
* lp_io_int
*/
uint32_t lp_interrupt_source:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lpperi_interrupt_source_reg_t;
/** Type of rng_cfg register
* need_des
*/
typedef union {
struct {
/** rng_sample_enable : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t rng_sample_enable:1;
/** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255;
* need des
*/
uint32_t rng_timer_pscale:8;
/** rng_timer_en : R/W; bitpos: [9]; default: 1;
* need des
*/
uint32_t rng_timer_en:1;
uint32_t reserved_10:14;
/** rng_sample_cnt : RO; bitpos: [31:24]; default: 0;
* need des
*/
uint32_t rng_sample_cnt:8;
};
uint32_t val;
} lpperi_rng_cfg_reg_t;
/** Group: Version register */
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lpperi_date : R/W; bitpos: [30:0]; default: 36720720;
* need_des
*/
uint32_t lpperi_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t clk_en:1;
};
uint32_t val;
} lpperi_date_reg_t;
typedef struct {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_reset_en_reg_t reset_en;
volatile lpperi_rng_data_reg_t rng_data;
volatile lpperi_cpu_reg_t cpu;
volatile lpperi_bus_timeout_reg_t bus_timeout;
volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr;
volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid;
volatile lpperi_mem_ctrl_reg_t mem_ctrl;
volatile lpperi_interrupt_source_reg_t interrupt_source;
volatile lpperi_rng_cfg_reg_t rng_cfg;
uint32_t reserved_028[245];
volatile lpperi_date_reg_t date;
} lpperi_dev_t;
extern lpperi_dev_t LPPERI;
#ifndef __cplusplus
_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** MEM_MONITOR_LOG_SETTING_REG register
* log config regsiter
*/
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
* enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA
*/
#define MEM_MONITOR_LOG_ENA 0x00000007U
#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
#define MEM_MONITOR_LOG_ENA_V 0x00000007U
#define MEM_MONITOR_LOG_ENA_S 0
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
* Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE
* monitor
*/
#define MEM_MONITOR_LOG_MODE 0x0000000FU
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
#define MEM_MONITOR_LOG_MODE_S 3
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7))
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
* check data regsiter
*/
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
/** MEM_MONITOR_LOG_DATA_MASK_REG register
* check data mask register
*/
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
#define MEM_MONITOR_LOG_DATA_MASK_S 0
/** MEM_MONITOR_LOG_MIN_REG register
* log boundary regsiter
*/
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MIN_S 0
/** MEM_MONITOR_LOG_MAX_REG register
* log boundary regsiter
*/
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MAX_S 0
/** MEM_MONITOR_LOG_MEM_START_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_START_S 0
/** MEM_MONITOR_LOG_MEM_END_REG register
* log message store range register
*/
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_END_S 0
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
* current writing address.
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
* writing address update
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
* full flag status register
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
/** MEM_MONITOR_CLOCK_GATE_REG register
* clock gate force on register
*/
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
#define MEM_MONITOR_CLK_EN (BIT(0))
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
#define MEM_MONITOR_CLK_EN_V 0x00000001U
#define MEM_MONITOR_CLK_EN_S 0
/** MEM_MONITOR_DATE_REG register
* version register
*/
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34632336;
* version register
*/
#define MEM_MONITOR_DATE 0x0FFFFFFFU
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
#define MEM_MONITOR_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configuration registers */
/** Type of log_setting register
* log config regsiter
*/
typedef union {
struct {
/** log_ena : R/W; bitpos: [2:0]; default: 0;
* enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA
*/
uint32_t log_ena:3;
/** log_mode : R/W; bitpos: [6:3]; default: 0;
* Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE
* monitor
*/
uint32_t log_mode:4;
/** log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
*/
uint32_t log_mem_loop_enable:1;
uint32_t reserved_8:24;
};
uint32_t val;
} mem_monitor_log_setting_reg_t;
/** Type of log_check_data register
* check data regsiter
*/
typedef union {
struct {
/** log_check_data : R/W; bitpos: [31:0]; default: 0;
* The special check data, when write this special data, it will trigger logging.
*/
uint32_t log_check_data:32;
};
uint32_t val;
} mem_monitor_log_check_data_reg_t;
/** Type of log_data_mask register
* check data mask register
*/
typedef union {
struct {
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
* mask second byte, and so on.
*/
uint32_t log_data_mask:4;
uint32_t reserved_4:28;
};
uint32_t val;
} mem_monitor_log_data_mask_reg_t;
/** Type of log_min register
* log boundary regsiter
*/
typedef union {
struct {
/** log_min : R/W; bitpos: [31:0]; default: 0;
* the min address of log range
*/
uint32_t log_min:32;
};
uint32_t val;
} mem_monitor_log_min_reg_t;
/** Type of log_max register
* log boundary regsiter
*/
typedef union {
struct {
/** log_max : R/W; bitpos: [31:0]; default: 0;
* the max address of log range
*/
uint32_t log_max:32;
};
uint32_t val;
} mem_monitor_log_max_reg_t;
/** Type of log_mem_start register
* log message store range register
*/
typedef union {
struct {
/** log_mem_start : R/W; bitpos: [31:0]; default: 0;
* the start address of writing logging message
*/
uint32_t log_mem_start:32;
};
uint32_t val;
} mem_monitor_log_mem_start_reg_t;
/** Type of log_mem_end register
* log message store range register
*/
typedef union {
struct {
/** log_mem_end : R/W; bitpos: [31:0]; default: 0;
* the end address of writing logging message
*/
uint32_t log_mem_end:32;
};
uint32_t val;
} mem_monitor_log_mem_end_reg_t;
/** Type of log_mem_current_addr register
* current writing address.
*/
typedef union {
struct {
/** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
* means next writing address
*/
uint32_t log_mem_current_addr:32;
};
uint32_t val;
} mem_monitor_log_mem_current_addr_reg_t;
/** Type of log_mem_addr_update register
* writing address update
*/
typedef union {
struct {
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
*/
uint32_t log_mem_addr_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_log_mem_addr_update_reg_t;
/** Type of log_mem_full_flag register
* full flag status register
*/
typedef union {
struct {
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
*/
uint32_t log_mem_full_flag:1;
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
*/
uint32_t clr_log_mem_full_flag:1;
uint32_t reserved_2:30;
};
uint32_t val;
} mem_monitor_log_mem_full_flag_reg_t;
/** Group: clk register */
/** Type of clock_gate register
* clock gate force on register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set 1 to force on the clk of mem_monitor register
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} mem_monitor_clock_gate_reg_t;
/** Group: version register */
/** Type of date register
* version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 34632336;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} mem_monitor_date_reg_t;
typedef struct {
volatile mem_monitor_log_setting_reg_t log_setting;
volatile mem_monitor_log_check_data_reg_t log_check_data;
volatile mem_monitor_log_data_mask_reg_t log_data_mask;
volatile mem_monitor_log_min_reg_t log_min;
volatile mem_monitor_log_max_reg_t log_max;
volatile mem_monitor_log_mem_start_reg_t log_mem_start;
volatile mem_monitor_log_mem_end_reg_t log_mem_end;
volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
volatile mem_monitor_clock_gate_reg_t clock_gate;
uint32_t reserved_02c[244];
volatile mem_monitor_date_reg_t date;
} mem_monitor_dev_t;
extern mem_monitor_dev_t MEM_MONITOR;
#ifndef __cplusplus
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** PAU_REGDMA_CONF_REG register
* Peri backup control register
*/
#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
#define PAU_FLOW_ERR 0x00000007U
#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
#define PAU_FLOW_ERR_V 0x00000007U
#define PAU_FLOW_ERR_S 0
/** PAU_START : WT; bitpos: [3]; default: 0;
* backup start signal
*/
#define PAU_START (BIT(3))
#define PAU_START_M (PAU_START_V << PAU_START_S)
#define PAU_START_V 0x00000001U
#define PAU_START_S 3
/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM (BIT(4))
#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
#define PAU_TO_MEM_V 0x00000001U
#define PAU_TO_MEM_S 4
/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0;
* Link select
*/
#define PAU_LINK_SEL 0x00000003U
#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
#define PAU_LINK_SEL_V 0x00000003U
#define PAU_LINK_SEL_S 5
/** PAU_START_MAC : WT; bitpos: [7]; default: 0;
* mac sw backup start signal
*/
#define PAU_START_MAC (BIT(7))
#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S)
#define PAU_START_MAC_V 0x00000001U
#define PAU_START_MAC_S 7
/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
#define PAU_TO_MEM_MAC (BIT(8))
#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
#define PAU_TO_MEM_MAC_V 0x00000001U
#define PAU_TO_MEM_MAC_S 8
/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0;
* mac hw/sw select
*/
#define PAU_SEL_MAC (BIT(9))
#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
#define PAU_SEL_MAC_V 0x00000001U
#define PAU_SEL_MAC_S 9
/** PAU_REGDMA_CLK_CONF_REG register
* Clock control register
*/
#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
* clock enable
*/
#define PAU_CLK_EN (BIT(0))
#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
#define PAU_CLK_EN_V 0x00000001U
#define PAU_CLK_EN_S 0
/** PAU_REGDMA_ETM_CTRL_REG register
* ETM start ctrl reg
*/
#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
#define PAU_ETM_START_0 (BIT(0))
#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
#define PAU_ETM_START_0_V 0x00000001U
#define PAU_ETM_START_0_S 0
/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
#define PAU_ETM_START_1 (BIT(1))
#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
#define PAU_ETM_START_1_V 0x00000001U
#define PAU_ETM_START_1_S 1
/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
#define PAU_ETM_START_2 (BIT(2))
#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
#define PAU_ETM_START_2_V 0x00000001U
#define PAU_ETM_START_2_S 2
/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
#define PAU_ETM_START_3 (BIT(3))
#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
#define PAU_ETM_START_3_V 0x00000001U
#define PAU_ETM_START_3_S 3
/** PAU_REGDMA_LINK_0_ADDR_REG register
* link_0_addr
*/
#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0;
* link_0_addr reg
*/
#define PAU_LINK_ADDR_0 0xFFFFFFFFU
#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S)
#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_0_S 0
/** PAU_REGDMA_LINK_1_ADDR_REG register
* Link_1_addr
*/
#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0;
* Link_1_addr reg
*/
#define PAU_LINK_ADDR_1 0xFFFFFFFFU
#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S)
#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_1_S 0
/** PAU_REGDMA_LINK_2_ADDR_REG register
* Link_2_addr
*/
#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0;
* Link_2_addr reg
*/
#define PAU_LINK_ADDR_2 0xFFFFFFFFU
#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S)
#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_2_S 0
/** PAU_REGDMA_LINK_3_ADDR_REG register
* Link_3_addr
*/
#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0;
* Link_3_addr reg
*/
#define PAU_LINK_ADDR_3 0xFFFFFFFFU
#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S)
#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_3_S 0
/** PAU_REGDMA_LINK_MAC_ADDR_REG register
* Link_mac_addr
*/
#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0;
* Link_mac_addr reg
*/
#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU
#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S)
#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU
#define PAU_LINK_ADDR_MAC_S 0
/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
* current link addr
*/
#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU
#define PAU_CURRENT_LINK_ADDR_S 0
/** PAU_REGDMA_BACKUP_ADDR_REG register
* Backup addr
*/
#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0;
* backup addr reg
*/
#define PAU_BACKUP_ADDR 0xFFFFFFFFU
#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S)
#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU
#define PAU_BACKUP_ADDR_S 0
/** PAU_REGDMA_MEM_ADDR_REG register
* mem addr
*/
#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28)
/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
#define PAU_MEM_ADDR 0xFFFFFFFFU
#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
#define PAU_MEM_ADDR_V 0xFFFFFFFFU
#define PAU_MEM_ADDR_S 0
/** PAU_REGDMA_BKP_CONF_REG register
* backup config
*/
#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c)
/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32;
* Link read_interval
*/
#define PAU_READ_INTERVAL 0x0000007FU
#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S)
#define PAU_READ_INTERVAL_V 0x0000007FU
#define PAU_READ_INTERVAL_S 0
/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50;
* link wait timeout threshold
*/
#define PAU_LINK_TOUT_THRES 0x000003FFU
#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S)
#define PAU_LINK_TOUT_THRES_V 0x000003FFU
#define PAU_LINK_TOUT_THRES_S 7
/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8;
* burst limit
*/
#define PAU_BURST_LIMIT 0x0000001FU
#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S)
#define PAU_BURST_LIMIT_V 0x0000001FU
#define PAU_BURST_LIMIT_S 17
/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500;
* Backup timeout threshold
*/
#define PAU_BACKUP_TOUT_THRES 0x000003FFU
#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S)
#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU
#define PAU_BACKUP_TOUT_THRES_S 22
/** PAU_INT_ENA_REG register
* Read only register for error and done
*/
#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30)
/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ENA (BIT(0))
#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
#define PAU_DONE_INT_ENA_V 0x00000001U
#define PAU_DONE_INT_ENA_S 0
/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ENA (BIT(1))
#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
#define PAU_ERROR_INT_ENA_V 0x00000001U
#define PAU_ERROR_INT_ENA_S 1
/** PAU_INT_RAW_REG register
* Read only register for error and done
*/
#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34)
/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_RAW (BIT(0))
#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
#define PAU_DONE_INT_RAW_V 0x00000001U
#define PAU_DONE_INT_RAW_S 0
/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_RAW (BIT(1))
#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
#define PAU_ERROR_INT_RAW_V 0x00000001U
#define PAU_ERROR_INT_RAW_S 1
/** PAU_INT_CLR_REG register
* Read only register for error and done
*/
#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38)
/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_CLR (BIT(0))
#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
#define PAU_DONE_INT_CLR_V 0x00000001U
#define PAU_DONE_INT_CLR_S 0
/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_CLR (BIT(1))
#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
#define PAU_ERROR_INT_CLR_V 0x00000001U
#define PAU_ERROR_INT_CLR_S 1
/** PAU_INT_ST_REG register
* Read only register for error and done
*/
#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c)
/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* backup done flag
*/
#define PAU_DONE_INT_ST (BIT(0))
#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
#define PAU_DONE_INT_ST_V 0x00000001U
#define PAU_DONE_INT_ST_S 0
/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
* error flag
*/
#define PAU_ERROR_INT_ST (BIT(1))
#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
#define PAU_ERROR_INT_ST_V 0x00000001U
#define PAU_ERROR_INT_ST_S 1
/** PAU_DATE_REG register
* Date register.
*/
#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
/** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608;
* REGDMA date information/ REGDMA version information.
*/
#define PAU_DATE 0x0FFFFFFFU
#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
#define PAU_DATE_V 0x0FFFFFFFU
#define PAU_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of regdma_conf register
* Peri backup control register
*/
typedef union {
struct {
/** flow_err : RO; bitpos: [2:0]; default: 0;
* backup error type
*/
uint32_t flow_err:3;
/** start : WT; bitpos: [3]; default: 0;
* backup start signal
*/
uint32_t start:1;
/** to_mem : R/W; bitpos: [4]; default: 0;
* backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem:1;
/** link_sel : R/W; bitpos: [6:5]; default: 0;
* Link select
*/
uint32_t link_sel:2;
/** start_mac : WT; bitpos: [7]; default: 0;
* mac sw backup start signal
*/
uint32_t start_mac:1;
/** to_mem_mac : R/W; bitpos: [8]; default: 0;
* mac sw backup direction(reg to mem / mem to reg)
*/
uint32_t to_mem_mac:1;
/** sel_mac : R/W; bitpos: [9]; default: 0;
* mac hw/sw select
*/
uint32_t sel_mac:1;
uint32_t reserved_10:22;
};
uint32_t val;
} pau_regdma_conf_reg_t;
/** Type of regdma_clk_conf register
* Clock control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* clock enable
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} pau_regdma_clk_conf_reg_t;
/** Type of regdma_etm_ctrl register
* ETM start ctrl reg
*/
typedef union {
struct {
/** etm_start_0 : WT; bitpos: [0]; default: 0;
* etm_start_0 reg
*/
uint32_t etm_start_0:1;
/** etm_start_1 : WT; bitpos: [1]; default: 0;
* etm_start_1 reg
*/
uint32_t etm_start_1:1;
/** etm_start_2 : WT; bitpos: [2]; default: 0;
* etm_start_2 reg
*/
uint32_t etm_start_2:1;
/** etm_start_3 : WT; bitpos: [3]; default: 0;
* etm_start_3 reg
*/
uint32_t etm_start_3:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pau_regdma_etm_ctrl_reg_t;
/** Type of regdma_link_0_addr register
* link_0_addr
*/
typedef union {
struct {
/** link_addr_0 : R/W; bitpos: [31:0]; default: 0;
* link_0_addr reg
*/
uint32_t link_addr_0:32;
};
uint32_t val;
} pau_regdma_link_0_addr_reg_t;
/** Type of regdma_link_1_addr register
* Link_1_addr
*/
typedef union {
struct {
/** link_addr_1 : R/W; bitpos: [31:0]; default: 0;
* Link_1_addr reg
*/
uint32_t link_addr_1:32;
};
uint32_t val;
} pau_regdma_link_1_addr_reg_t;
/** Type of regdma_link_2_addr register
* Link_2_addr
*/
typedef union {
struct {
/** link_addr_2 : R/W; bitpos: [31:0]; default: 0;
* Link_2_addr reg
*/
uint32_t link_addr_2:32;
};
uint32_t val;
} pau_regdma_link_2_addr_reg_t;
/** Type of regdma_link_3_addr register
* Link_3_addr
*/
typedef union {
struct {
/** link_addr_3 : R/W; bitpos: [31:0]; default: 0;
* Link_3_addr reg
*/
uint32_t link_addr_3:32;
};
uint32_t val;
} pau_regdma_link_3_addr_reg_t;
/** Type of regdma_link_mac_addr register
* Link_mac_addr
*/
typedef union {
struct {
/** link_addr_mac : R/W; bitpos: [31:0]; default: 0;
* Link_mac_addr reg
*/
uint32_t link_addr_mac:32;
};
uint32_t val;
} pau_regdma_link_mac_addr_reg_t;
/** Type of regdma_current_link_addr register
* current link addr
*/
typedef union {
struct {
/** current_link_addr : RO; bitpos: [31:0]; default: 0;
* current link addr reg
*/
uint32_t current_link_addr:32;
};
uint32_t val;
} pau_regdma_current_link_addr_reg_t;
/** Type of regdma_backup_addr register
* Backup addr
*/
typedef union {
struct {
/** backup_addr : RO; bitpos: [31:0]; default: 0;
* backup addr reg
*/
uint32_t backup_addr:32;
};
uint32_t val;
} pau_regdma_backup_addr_reg_t;
/** Type of regdma_mem_addr register
* mem addr
*/
typedef union {
struct {
/** mem_addr : RO; bitpos: [31:0]; default: 0;
* mem addr reg
*/
uint32_t mem_addr:32;
};
uint32_t val;
} pau_regdma_mem_addr_reg_t;
/** Type of regdma_bkp_conf register
* backup config
*/
typedef union {
struct {
/** read_interval : R/W; bitpos: [6:0]; default: 32;
* Link read_interval
*/
uint32_t read_interval:7;
/** link_tout_thres : R/W; bitpos: [16:7]; default: 50;
* link wait timeout threshold
*/
uint32_t link_tout_thres:10;
/** burst_limit : R/W; bitpos: [21:17]; default: 8;
* burst limit
*/
uint32_t burst_limit:5;
/** backup_tout_thres : R/W; bitpos: [31:22]; default: 500;
* Backup timeout threshold
*/
uint32_t backup_tout_thres:10;
};
uint32_t val;
} pau_regdma_bkp_conf_reg_t;
/** Type of int_ena register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_ena : R/W; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_ena:1;
/** error_int_ena : R/W; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_ena_reg_t;
/** Type of int_raw register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_raw:1;
/** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_raw_reg_t;
/** Type of int_clr register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_clr : WT; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_clr:1;
/** error_int_clr : WT; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_clr_reg_t;
/** Type of int_st register
* Read only register for error and done
*/
typedef union {
struct {
/** done_int_st : RO; bitpos: [0]; default: 0;
* backup done flag
*/
uint32_t done_int_st:1;
/** error_int_st : RO; bitpos: [1]; default: 0;
* error flag
*/
uint32_t error_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} pau_int_st_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36708608;
* REGDMA date information/ REGDMA version information.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} pau_date_reg_t;
typedef struct {
volatile pau_regdma_conf_reg_t regdma_conf;
volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr;
volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr;
volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr;
volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr;
volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr;
volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
volatile pau_regdma_backup_addr_reg_t regdma_backup_addr;
volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf;
volatile pau_int_ena_reg_t int_ena;
volatile pau_int_raw_reg_t int_raw;
volatile pau_int_clr_reg_t int_clr;
volatile pau_int_st_reg_t int_st;
uint32_t reserved_040[239];
volatile pau_date_reg_t date;
} pau_dev_t;
extern pau_dev_t PAU;
#ifndef __cplusplus
_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Register */
/** Type of un_conf0 register
* Configuration register 0 for unit n
*/
typedef union {
struct {
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
* This sets the maximum threshold, in APB_CLK cycles, for the filter.
*
* Any pulses with width less than this will be ignored when the filter is enabled.
*/
uint32_t filter_thres_un:10;
/** filter_en_un : R/W; bitpos: [10]; default: 1;
* This is the enable bit for unit n's input filter.
*/
uint32_t filter_en_un:1;
/** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
* This is the enable bit for unit n's zero comparator.
*/
uint32_t thr_zero_en_un:1;
/** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
* This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
* the high limit interrupt.
*/
uint32_t thr_h_lim_en_un:1;
/** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
* This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
* the low limit interrupt.
*/
uint32_t thr_l_lim_en_un:1;
/** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
* This is the enable bit for unit n's thres0 comparator.
*/
uint32_t thr_thres0_en_un:1;
/** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
* This is the enable bit for unit n's thres1 comparator.
*/
uint32_t thr_thres1_en_un:1;
/** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
* This register sets the behavior when the signal input of channel 0 detects a
* negative edge.
*
* 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
*/
uint32_t ch0_neg_mode_un:2;
/** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
* This register sets the behavior when the signal input of channel 0 detects a
* positive edge.
*
* 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
*/
uint32_t ch0_pos_mode_un:2;
/** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is high.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch0_hctrl_mode_un:2;
/** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is low.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch0_lctrl_mode_un:2;
/** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
* This register sets the behavior when the signal input of channel 1 detects a
* negative edge.
*
* 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
*/
uint32_t ch1_neg_mode_un:2;
/** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
* This register sets the behavior when the signal input of channel 1 detects a
* positive edge.
*
* 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
*/
uint32_t ch1_pos_mode_un:2;
/** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is high.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch1_hctrl_mode_un:2;
/** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
* modified when the control signal is low.
*
* 0: No modification.1: Invert behavior (increase -> decrease, decrease ->
* increase).2, 3: Inhibit counter modification
*/
uint32_t ch1_lctrl_mode_un:2;
};
uint32_t val;
} pcnt_un_conf0_reg_t;
/** Type of un_conf1 register
* Configuration register 1 for unit n
*/
typedef union {
struct {
/** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
* This register is used to configure the thres0 value for unit n.
*/
uint32_t cnt_thres0_un:16;
/** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
* This register is used to configure the thres1 value for unit n.
*/
uint32_t cnt_thres1_un:16;
};
uint32_t val;
} pcnt_un_conf1_reg_t;
/** Type of un_conf2 register
* Configuration register 2 for unit n
*/
typedef union {
struct {
/** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
* This register is used to configure the thr_h_lim value for unit n. When pcnt
* reaches this value, the counter will be cleared to 0.
*/
uint32_t cnt_h_lim_un:16;
/** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
* This register is used to configure the thr_l_lim value for unit n. When pcnt
* reaches this value, the counter will be cleared to 0.
*/
uint32_t cnt_l_lim_un:16;
};
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of ctrl register
* Control register for all counters
*/
typedef union {
struct {
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
* Set this bit to clear unit 0's counter.
*/
uint32_t pulse_cnt_rst_u0:1;
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
* Set this bit to freeze unit 0's counter.
*/
uint32_t cnt_pause_u0:1;
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
* Set this bit to clear unit 1's counter.
*/
uint32_t pulse_cnt_rst_u1:1;
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
* Set this bit to freeze unit 1's counter.
*/
uint32_t cnt_pause_u1:1;
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
* Set this bit to clear unit 2's counter.
*/
uint32_t pulse_cnt_rst_u2:1;
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
* Set this bit to freeze unit 2's counter.
*/
uint32_t cnt_pause_u2:1;
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
* Set this bit to clear unit 3's counter.
*/
uint32_t pulse_cnt_rst_u3:1;
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
* Set this bit to freeze unit 3's counter.
*/
uint32_t cnt_pause_u3:1;
/** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
* Configures this bit to enable unit 0's step comparator.
*/
uint32_t dalta_change_en_u0:1;
/** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
* Configures this bit to enable unit 1's step comparator.
*/
uint32_t dalta_change_en_u1:1;
/** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
* Configures this bit to enable unit 2's step comparator.
*/
uint32_t dalta_change_en_u2:1;
/** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
* Configures this bit to enable unit 3's step comparator.
*/
uint32_t dalta_change_en_u3:1;
uint32_t reserved_12:4;
/** clk_en : R/W; bitpos: [16]; default: 0;
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
* and written by application. 0: the registers can not be read or written by
* application
*/
uint32_t clk_en:1;
uint32_t reserved_17:15;
};
uint32_t val;
} pcnt_ctrl_reg_t;
/** Type of u3_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 3.
*/
uint32_t cnt_step_u3:16;
/** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 3.
*/
uint32_t cnt_step_lim_u3:16;
};
uint32_t val;
} pcnt_u3_change_conf_reg_t;
/** Type of u2_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 2.
*/
uint32_t cnt_step_u2:16;
/** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 2.
*/
uint32_t cnt_step_lim_u2:16;
};
uint32_t val;
} pcnt_u2_change_conf_reg_t;
/** Type of u1_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 1.
*/
uint32_t cnt_step_u1:16;
/** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 1.
*/
uint32_t cnt_step_lim_u1:16;
};
uint32_t val;
} pcnt_u1_change_conf_reg_t;
/** Type of u0_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 0.
*/
uint32_t cnt_step_u0:16;
/** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 0.
*/
uint32_t cnt_step_lim_u0:16;
};
uint32_t val;
} pcnt_u0_change_conf_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
* Counter value for unit n
*/
typedef union {
struct {
/** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
* This register stores the current pulse count value for unit n.
*/
uint32_t pulse_cnt_un:16;
uint32_t reserved_16:16;
};
uint32_t val;
} pcnt_un_cnt_reg_t;
/** Type of un_status register
* PNCT UNITn status register
*/
typedef union {
struct {
/** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
* The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
* from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
* is negative. 3: pulse counter is positive.
*/
uint32_t cnt_thr_zero_mode_un:2;
/** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
* The latched value of thres1 event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
* others
*/
uint32_t cnt_thr_thres1_lat_un:1;
/** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
* The latched value of thres0 event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
* others
*/
uint32_t cnt_thr_thres0_lat_un:1;
/** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
* The latched value of low limit event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
* valid. 0: others
*/
uint32_t cnt_thr_l_lim_lat_un:1;
/** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
* The latched value of high limit event of PCNT_Un when threshold event interrupt is
* valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
* valid. 0: others
*/
uint32_t cnt_thr_h_lim_lat_un:1;
/** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
* The latched value of zero threshold event of PCNT_Un when threshold event interrupt
* is valid. 1: the current pulse counter equals to 0 and zero threshold event is
* valid. 0: others
*/
uint32_t cnt_thr_zero_lat_un:1;
uint32_t reserved_7:25;
};
uint32_t val;
} pcnt_un_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* Interrupt raw status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_raw:1;
/** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_raw:1;
/** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_raw:1;
/** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_st:1;
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_st:1;
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_st:1;
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_ena:1;
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_ena:1;
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_ena:1;
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear register
*/
typedef union {
struct {
/** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
*/
uint32_t cnt_thr_event_u0_int_clr:1;
/** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
*/
uint32_t cnt_thr_event_u1_int_clr:1;
/** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
*/
uint32_t cnt_thr_event_u2_int_clr:1;
/** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
*/
uint32_t cnt_thr_event_u3_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} pcnt_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* PCNT version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 571021568;
* This is the PCNT version control register.
*/
uint32_t date:32;
};
uint32_t val;
} pcnt_date_reg_t;
typedef struct {
volatile pcnt_un_conf0_reg_t u0_conf0;
volatile pcnt_un_conf1_reg_t u0_conf1;
volatile pcnt_un_conf2_reg_t u0_conf2;
volatile pcnt_un_conf0_reg_t u1_conf0;
volatile pcnt_un_conf1_reg_t u1_conf1;
volatile pcnt_un_conf2_reg_t u1_conf2;
volatile pcnt_un_conf0_reg_t u2_conf0;
volatile pcnt_un_conf1_reg_t u2_conf1;
volatile pcnt_un_conf2_reg_t u2_conf2;
volatile pcnt_un_conf0_reg_t u3_conf0;
volatile pcnt_un_conf1_reg_t u3_conf1;
volatile pcnt_un_conf2_reg_t u3_conf2;
volatile pcnt_un_cnt_reg_t un_cnt[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t un_status[4];
volatile pcnt_ctrl_reg_t ctrl;
volatile pcnt_u3_change_conf_reg_t u3_change_conf;
volatile pcnt_u2_change_conf_reg_t u2_change_conf;
volatile pcnt_u1_change_conf_reg_t u1_change_conf;
volatile pcnt_u0_change_conf_reg_t u0_change_conf;
uint32_t reserved_074[34];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifndef __cplusplus
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: FIFO R/W registers */
/** Type of chndata register
* The read and write data register for CHANNELn by apb fifo access.
*/
typedef union {
struct {
/** chndata : HRO; bitpos: [31:0]; default: 0;
* Read and write data for channel n via APB FIFO.
*/
uint32_t chndata:32;
};
uint32_t val;
} rmt_chndata_reg_t;
/** Group: Configuration registers */
/** Type of chnconf0 register
* Channel n configure register 0
*/
typedef union {
struct {
/** tx_start_chn : WT; bitpos: [0]; default: 0;
* Set this bit to start sending data on CHANNELn.
*/
uint32_t tx_start_chn:1;
/** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
* Set this bit to reset read ram address for CHANNELn by accessing transmitter.
*/
uint32_t mem_rd_rst_chn:1;
/** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo.
*/
uint32_t apb_mem_rst_chn:1;
/** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
* Set this bit to restart transmission from the first data to the last data in
* CHANNELn.
*/
uint32_t tx_conti_mode_chn:1;
/** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
* This is the channel n enable bit for wraparound mode: it will resume sending at the
* start when the data to be sent is more than its memory size.
*/
uint32_t mem_tx_wrap_en_chn:1;
/** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
* This bit configures the level of output signal in CHANNELn when the latter is in
* IDLE state.
*/
uint32_t idle_out_lv_chn:1;
/** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
* This is the output enable-control bit for CHANNELn in IDLE state.
*/
uint32_t idle_out_en_chn:1;
/** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
* Set this bit to stop the transmitter of CHANNELn sending data out.
*/
uint32_t tx_stop_chn:1;
/** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
* This register is used to configure the divider for clock of CHANNELn.
*/
uint32_t div_cnt_chn:8;
/** mem_size_chn : R/W; bitpos: [18:16]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELn.
*/
uint32_t mem_size_chn:3;
uint32_t reserved_19:1;
/** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
* 1: Add carrier modulation on the output signal only at the send data state for
* CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn.
* Only valid when RMT_CARRIER_EN_CHn is 1.
*/
uint32_t carrier_eff_en_chn:1;
/** carrier_en_chn : R/W; bitpos: [21]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_chn:1;
/** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELn.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_chn:1;
uint32_t reserved_23:1;
/** conf_update_chn : WT; bitpos: [24]; default: 0;
* synchronization bit for CHANNELn
*/
uint32_t conf_update_chn:1;
uint32_t reserved_25:7;
};
uint32_t val;
} rmt_chnconf0_reg_t;
/** Type of chmconf0 register
* Channel m configure register 0
*/
typedef union {
struct {
/** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
* This register is used to configure the divider for clock of CHANNELm.
*/
uint32_t div_cnt_chm:8;
/** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
* When no edge is detected on the input signal and continuous clock cycles is longer
* than this register value, received process is finished.
*/
uint32_t idle_thres_chm:15;
/** mem_size_chm : R/W; bitpos: [25:23]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELm.
*/
uint32_t mem_size_chm:3;
uint32_t reserved_26:2;
/** carrier_en_chm : R/W; bitpos: [28]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_chm:1;
/** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELm.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_chm:1;
uint32_t reserved_30:2;
};
uint32_t val;
} rmt_chmconf0_reg_t;
/** Type of chmconf1 register
* Channel m configure register 1
*/
typedef union {
struct {
/** rx_en_chm : R/W; bitpos: [0]; default: 0;
* Set this bit to enable receiver to receive data on CHANNELm.
*/
uint32_t rx_en_chm:1;
/** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
* Set this bit to reset write ram address for CHANNELm by accessing receiver.
*/
uint32_t mem_wr_rst_chm:1;
/** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo.
*/
uint32_t apb_mem_rst_chm:1;
/** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
* This register marks the ownership of CHANNELm's ram block.
*
* 1'h1: Receiver is using the ram.
*
* 1'h0: APB bus is using the ram.
*/
uint32_t mem_owner_chm:1;
/** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
* This is the receive filter's enable bit for CHANNELm.
*/
uint32_t rx_filter_en_chm:1;
/** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
* Ignores the input pulse when its width is smaller than this register value in APB
* clock periods (in receive mode).
*/
uint32_t rx_filter_thres_chm:8;
/** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
* This is the channel m enable bit for wraparound mode: it will resume receiving at
* the start when the data to be received is more than its memory size.
*/
uint32_t mem_rx_wrap_en_chm:1;
uint32_t reserved_14:1;
/** conf_update_chm : WT; bitpos: [15]; default: 0;
* synchronization bit for CHANNELm
*/
uint32_t conf_update_chm:1;
uint32_t reserved_16:16;
};
uint32_t val;
} rmt_chmconf1_reg_t;
/** Type of sys_conf register
* RMT apb configuration register
*/
typedef union {
struct {
/** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
* 1'h1: access memory directly. 1'h0: access memory by FIFO.
*/
uint32_t apb_fifo_mask:1;
/** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
* Set this bit to enable the clock for RMT memory.
*/
uint32_t mem_clk_force_on:1;
/** mem_force_pd : R/W; bitpos: [2]; default: 0;
* Set this bit to power down RMT memory.
*/
uint32_t mem_force_pd:1;
/** mem_force_pu : R/W; bitpos: [3]; default: 0;
* 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
* when RMT is in light sleep mode.
*/
uint32_t mem_force_pu:1;
/** sclk_div_num : R/W; bitpos: [11:4]; default: 1;
* the integral part of the fractional divisor
*/
uint32_t sclk_div_num:8;
/** sclk_div_a : R/W; bitpos: [17:12]; default: 0;
* the numerator of the fractional part of the fractional divisor
*/
uint32_t sclk_div_a:6;
/** sclk_div_b : R/W; bitpos: [23:18]; default: 0;
* the denominator of the fractional part of the fractional divisor
*/
uint32_t sclk_div_b:6;
/** sclk_sel : R/W; bitpos: [25:24]; default: 1;
* choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL
*/
uint32_t sclk_sel:2;
/** sclk_active : R/W; bitpos: [26]; default: 1;
* rmt_sclk switch
*/
uint32_t sclk_active:1;
uint32_t reserved_27:4;
/** clk_en : R/W; bitpos: [31]; default: 0;
* RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0:
* Power down the drive clock of registers
*/
uint32_t clk_en:1;
};
uint32_t val;
} rmt_sys_conf_reg_t;
/** Type of ref_cnt_rst register
* RMT clock divider reset register
*/
typedef union {
struct {
/** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0;
* This register is used to reset the clock divider of CHANNEL0.
*/
uint32_t ref_cnt_rst_ch0:1;
/** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0;
* This register is used to reset the clock divider of CHANNEL1.
*/
uint32_t ref_cnt_rst_ch1:1;
/** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0;
* This register is used to reset the clock divider of CHANNEL2.
*/
uint32_t ref_cnt_rst_ch2:1;
/** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0;
* This register is used to reset the clock divider of CHANNEL3.
*/
uint32_t ref_cnt_rst_ch3:1;
uint32_t reserved_4:28;
};
uint32_t val;
} rmt_ref_cnt_rst_reg_t;
/** Group: Status registers */
/** Type of chnstatus register
* Channel n status register
*/
typedef union {
struct {
/** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0;
* This register records the memory address offset when transmitter of CHANNELn is
* using the RAM.
*/
uint32_t mem_raddr_ex_chn:9;
/** state_chn : RO; bitpos: [11:9]; default: 0;
* This register records the FSM status of CHANNELn.
*/
uint32_t state_chn:3;
/** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0;
* This register records the memory address offset when writes RAM over APB bus.
*/
uint32_t apb_mem_waddr_chn:9;
/** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0;
* This status bit will be set if the offset address out of memory size when reading
* via APB bus.
*/
uint32_t apb_mem_rd_err_chn:1;
/** mem_empty_chn : RO; bitpos: [22]; default: 0;
* This status bit will be set when the data to be set is more than memory size and
* the wraparound mode is disabled.
*/
uint32_t mem_empty_chn:1;
/** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0;
* This status bit will be set if the offset address out of memory size when writes
* via APB bus.
*/
uint32_t apb_mem_wr_err_chn:1;
/** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0;
* This register records the memory address offset when reading RAM over APB bus.
*/
uint32_t apb_mem_raddr_chn:8;
};
uint32_t val;
} rmt_chnstatus_reg_t;
/** Type of chmstatus register
* Channel m status register
*/
typedef union {
struct {
/** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0;
* This register records the memory address offset when receiver of CHANNELm is using
* the RAM.
*/
uint32_t mem_waddr_ex_chm:9;
uint32_t reserved_9:3;
/** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0;
* This register records the memory address offset when reads RAM over APB bus.
*/
uint32_t apb_mem_raddr_chm:9;
uint32_t reserved_21:1;
/** state_chm : RO; bitpos: [24:22]; default: 0;
* This register records the FSM status of CHANNELm.
*/
uint32_t state_chm:3;
/** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
* This status bit will be set when the ownership of memory block is wrong.
*/
uint32_t mem_owner_err_chm:1;
/** mem_full_chm : RO; bitpos: [26]; default: 0;
* This status bit will be set if the receiver receives more data than the memory size.
*/
uint32_t mem_full_chm:1;
/** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
* This status bit will be set if the offset address out of memory size when reads via
* APB bus.
*/
uint32_t apb_mem_rd_err_chm:1;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_chmstatus_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmission done.
*/
uint32_t ch0_tx_end_int_raw:1;
/** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmission done.
*/
uint32_t ch1_tx_end_int_raw:1;
/** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when reception done.
*/
uint32_t ch2_rx_end_int_raw:1;
/** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when reception done.
*/
uint32_t ch3_rx_end_int_raw:1;
/** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch0_err_int_raw:1;
/** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch1_err_int_raw:1;
/** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch2_err_int_raw:1;
/** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
*/
uint32_t ch3_err_int_raw:1;
/** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch0_tx_thr_event_int_raw:1;
/** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
* configured value.
*/
uint32_t ch1_tx_thr_event_int_raw:1;
/** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch2_rx_thr_event_int_raw:1;
/** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than
* configured value.
*/
uint32_t ch3_rx_thr_event_int_raw:1;
/** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch0_tx_loop_int_raw:1;
/** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
* configured threshold value.
*/
uint32_t ch1_tx_loop_int_raw:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_raw_reg_t;
/** Type of int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_st:1;
/** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_st:1;
/** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_st:1;
/** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_st:1;
/** ch0_err_int_st : RO; bitpos: [4]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_st:1;
/** ch1_err_int_st : RO; bitpos: [5]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_st:1;
/** ch2_err_int_st : RO; bitpos: [6]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_st:1;
/** ch3_err_int_st : RO; bitpos: [7]; default: 0;
* The masked interrupt status bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_st:1;
/** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0;
* The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_st:1;
/** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0;
* The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_st:1;
/** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0;
* The masked interrupt status bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_st:1;
/** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0;
* The masked interrupt status bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_st:1;
/** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0;
* The masked interrupt status bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_st:1;
/** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0;
* The masked interrupt status bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_st:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for CH0_TX_END_INT.
*/
uint32_t ch0_tx_end_int_ena:1;
/** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for CH1_TX_END_INT.
*/
uint32_t ch1_tx_end_int_ena:1;
/** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for CH2_RX_END_INT.
*/
uint32_t ch2_rx_end_int_ena:1;
/** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for CH3_RX_END_INT.
*/
uint32_t ch3_rx_end_int_ena:1;
/** ch0_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch0_err_int_ena:1;
/** ch1_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch1_err_int_ena:1;
/** ch2_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch2_err_int_ena:1;
/** ch3_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for CH$n_ERR_INT.
*/
uint32_t ch3_err_int_ena:1;
/** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for CH0_TX_THR_EVENT_INT.
*/
uint32_t ch0_tx_thr_event_int_ena:1;
/** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for CH1_TX_THR_EVENT_INT.
*/
uint32_t ch1_tx_thr_event_int_ena:1;
/** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for CH2_RX_THR_EVENT_INT.
*/
uint32_t ch2_rx_thr_event_int_ena:1;
/** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for CH3_RX_THR_EVENT_INT.
*/
uint32_t ch3_rx_thr_event_int_ena:1;
/** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0;
* The interrupt enable bit for CH0_TX_LOOP_INT.
*/
uint32_t ch0_tx_loop_int_ena:1;
/** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0;
* The interrupt enable bit for CH1_TX_LOOP_INT.
*/
uint32_t ch1_tx_loop_int_ena:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear theCH0_TX_END_INT interrupt.
*/
uint32_t ch0_tx_end_int_clr:1;
/** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear theCH1_TX_END_INT interrupt.
*/
uint32_t ch1_tx_end_int_clr:1;
/** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear theCH2_RX_END_INT interrupt.
*/
uint32_t ch2_rx_end_int_clr:1;
/** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear theCH3_RX_END_INT interrupt.
*/
uint32_t ch3_rx_end_int_clr:1;
/** ch0_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch0_err_int_clr:1;
/** ch1_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch1_err_int_clr:1;
/** ch2_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch2_err_int_clr:1;
/** ch3_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear theCH$n_ERR_INT interrupt.
*/
uint32_t ch3_err_int_clr:1;
/** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch0_tx_thr_event_int_clr:1;
/** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
*/
uint32_t ch1_tx_thr_event_int_clr:1;
/** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch2_rx_thr_event_int_clr:1;
/** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.
*/
uint32_t ch3_rx_thr_event_int_clr:1;
/** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0;
* Set this bit to clear theCH0_TX_LOOP_INT interrupt.
*/
uint32_t ch0_tx_loop_int_clr:1;
/** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0;
* Set this bit to clear theCH1_TX_LOOP_INT interrupt.
*/
uint32_t ch1_tx_loop_int_clr:1;
uint32_t reserved_14:18;
};
uint32_t val;
} rmt_int_clr_reg_t;
/** Group: Carrier wave duty cycle registers */
/** Type of chncarrier_duty register
* Channel n duty cycle configuration register
*/
typedef union {
struct {
/** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
* This register is used to configure carrier wave 's low level clock period for
* CHANNELn.
*/
uint32_t carrier_low_chn:16;
/** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
* This register is used to configure carrier wave 's high level clock period for
* CHANNELn.
*/
uint32_t carrier_high_chn:16;
};
uint32_t val;
} rmt_chncarrier_duty_reg_t;
/** Type of chm_rx_carrier_rm register
* Channel m carrier remove register
*/
typedef union {
struct {
/** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0;
* The low level period in a carrier modulation mode is
* (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m.
*/
uint32_t carrier_low_thres_chm:16;
/** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0;
* The high level period in a carrier modulation mode is
* (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m.
*/
uint32_t carrier_high_thres_chm:16;
};
uint32_t val;
} rmt_chm_rx_carrier_rm_reg_t;
/** Group: Tx event configuration registers */
/** Type of chn_tx_lim register
* Channel n Tx event configuration register
*/
typedef union {
struct {
/** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELn can send out.
*/
uint32_t tx_lim_chn:9;
/** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
* This register is used to configure the maximum loop count when tx_conti_mode is
* valid.
*/
uint32_t tx_loop_num_chn:10;
/** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
* This register is the enabled bit for loop count.
*/
uint32_t tx_loop_cnt_en_chn:1;
/** loop_count_reset_chn : WT; bitpos: [20]; default: 0;
* This register is used to reset the loop count when tx_conti_mode is valid.
*/
uint32_t loop_count_reset_chn:1;
/** loop_stop_en_chn : R/W; bitpos: [21]; default: 0;
* This bit is used to enable the loop send stop function after the loop counter
* counts to loop number for CHANNELn.
*/
uint32_t loop_stop_en_chn:1;
uint32_t reserved_22:10;
};
uint32_t val;
} rmt_chn_tx_lim_reg_t;
/** Type of tx_sim register
* RMT TX synchronous register
*/
typedef union {
struct {
/** tx_sim_ch0 : R/W; bitpos: [0]; default: 0;
* Set this bit to enable CHANNEL0 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch0:1;
/** tx_sim_ch1 : R/W; bitpos: [1]; default: 0;
* Set this bit to enable CHANNEL1 to start sending data synchronously with other
* enabled channels.
*/
uint32_t tx_sim_ch1:1;
/** tx_sim_en : R/W; bitpos: [2]; default: 0;
* This register is used to enable multiple of channels to start sending data
* synchronously.
*/
uint32_t tx_sim_en:1;
uint32_t reserved_3:29;
};
uint32_t val;
} rmt_tx_sim_reg_t;
/** Group: Rx event configuration registers */
/** Type of chm_rx_lim register
* Channel m Rx event configuration register
*/
typedef union {
struct {
/** rx_lim_chm : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELm can receive.
*/
uint32_t rx_lim_chm:9;
uint32_t reserved_9:23;
};
uint32_t val;
} rmt_chm_rx_lim_reg_t;
/** Group: Version register */
/** Type of date register
* RMT version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 34636307;
* This is the version register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} rmt_date_reg_t;
typedef struct {
volatile rmt_chndata_reg_t chndata[4];
volatile rmt_chnconf0_reg_t chnconf0[2];
volatile rmt_chmconf0_reg_t ch2conf0;
volatile rmt_chmconf1_reg_t ch2conf1;
volatile rmt_chmconf0_reg_t ch3conf0;
volatile rmt_chmconf1_reg_t ch3conf1;
volatile rmt_chnstatus_reg_t chnstatus[2];
volatile rmt_chmstatus_reg_t chmstatus[2];
volatile rmt_int_raw_reg_t int_raw;
volatile rmt_int_st_reg_t int_st;
volatile rmt_int_ena_reg_t int_ena;
volatile rmt_int_clr_reg_t int_clr;
volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2];
volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2];
volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2];
volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2];
volatile rmt_sys_conf_reg_t sys_conf;
volatile rmt_tx_sim_reg_t tx_sim;
volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
uint32_t reserved_074[22];
volatile rmt_date_reg_t date;
} rmt_dev_t;
extern rmt_dev_t RMT;
#ifndef __cplusplus
_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HINF_CFG_DATA0_REG register
* Configure sdio cis content
*/
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
#define HINF_DEVICE_ID_FN1 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_S 0
/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
#define HINF_USER_ID_FN1 0x0000FFFFU
#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
#define HINF_USER_ID_FN1_V 0x0000FFFFU
#define HINF_USER_ID_FN1_S 16
/** HINF_CFG_DATA1_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
#define HINF_SDIO_ENABLE (BIT(0))
#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
#define HINF_SDIO_ENABLE_V 0x00000001U
#define HINF_SDIO_ENABLE_S 0
/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY1 (BIT(1))
#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
#define HINF_SDIO_IOREADY1_V 0x00000001U
#define HINF_SDIO_IOREADY1_S 1
/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
#define HINF_HIGHSPEED_ENABLE (BIT(2))
#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
#define HINF_HIGHSPEED_ENABLE_V 0x00000001U
#define HINF_HIGHSPEED_ENABLE_S 2
/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
#define HINF_HIGHSPEED_MODE (BIT(3))
#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
#define HINF_HIGHSPEED_MODE_V 0x00000001U
#define HINF_HIGHSPEED_MODE_S 3
/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
#define HINF_SDIO_CD_ENABLE (BIT(4))
#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
#define HINF_SDIO_CD_ENABLE_V 0x00000001U
#define HINF_SDIO_CD_ENABLE_S 4
/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY2 (BIT(5))
#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
#define HINF_SDIO_IOREADY2_V 0x00000001U
#define HINF_SDIO_IOREADY2_S 5
/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
#define HINF_SDIO_INT_MASK (BIT(6))
#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
#define HINF_SDIO_INT_MASK_V 0x00000001U
#define HINF_SDIO_INT_MASK_S 6
/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
#define HINF_IOENABLE2 (BIT(7))
#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
#define HINF_IOENABLE2_V 0x00000001U
#define HINF_IOENABLE2_S 7
/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
#define HINF_CD_DISABLE (BIT(8))
#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
#define HINF_CD_DISABLE_V 0x00000001U
#define HINF_CD_DISABLE_S 8
/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
#define HINF_FUNC1_EPS (BIT(9))
#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
#define HINF_FUNC1_EPS_V 0x00000001U
#define HINF_FUNC1_EPS_S 9
/** HINF_EMP : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
#define HINF_EMP (BIT(10))
#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S)
#define HINF_EMP_V 0x00000001U
#define HINF_EMP_S 10
/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
#define HINF_IOENABLE1 (BIT(11))
#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
#define HINF_IOENABLE1_V 0x00000001U
#define HINF_IOENABLE1_S 11
/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
#define HINF_SDIO_VER 0x00000FFFU
#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
#define HINF_SDIO_VER_V 0x00000FFFU
#define HINF_SDIO_VER_S 12
/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
#define HINF_FUNC2_EPS (BIT(24))
#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
#define HINF_FUNC2_EPS_V 0x00000001U
#define HINF_FUNC2_EPS_S 24
/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
#define HINF_SDIO20_CONF 0x0000007FU
#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
#define HINF_SDIO20_CONF_V 0x0000007FU
#define HINF_SDIO20_CONF_S 25
/** HINF_CFG_TIMING_REG register
* Timing configuration registers
*/
#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
#define HINF_NCRC 0x00000007U
#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S)
#define HINF_NCRC_V 0x00000007U
#define HINF_NCRC_S 0
/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_S 3
/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_S 10
/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
#define HINF_SDCLK_STOP_THRES 0x000007FFU
#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
#define HINF_SDCLK_STOP_THRES_V 0x000007FFU
#define HINF_SDCLK_STOP_THRES_S 16
/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_S 28
/** HINF_CFG_UPDATE_REG register
* update sdio configurations
*/
#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
#define HINF_CONF_UPDATE (BIT(0))
#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
#define HINF_CONF_UPDATE_V 0x00000001U
#define HINF_CONF_UPDATE_S 0
/** HINF_CFG_DATA7_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
#define HINF_PIN_STATE 0x000000FFU
#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
#define HINF_PIN_STATE_V 0x000000FFU
#define HINF_PIN_STATE_S 0
/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
#define HINF_CHIP_STATE 0x000000FFU
#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
#define HINF_CHIP_STATE_V 0x000000FFU
#define HINF_CHIP_STATE_S 8
/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
#define HINF_SDIO_RST (BIT(16))
#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
#define HINF_SDIO_RST_V 0x00000001U
#define HINF_SDIO_RST_S 16
/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
#define HINF_SDIO_IOREADY0 (BIT(17))
#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
#define HINF_SDIO_IOREADY0_V 0x00000001U
#define HINF_SDIO_IOREADY0_S 17
/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
#define HINF_SDIO_MEM_PD (BIT(18))
#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
#define HINF_SDIO_MEM_PD_V 0x00000001U
#define HINF_SDIO_MEM_PD_S 18
/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
#define HINF_ESDIO_DATA1_INT_EN (BIT(19))
#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U
#define HINF_ESDIO_DATA1_INT_EN_S 19
/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20))
#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_SW_S 20
/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21))
#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U
#define HINF_DDR50_BLK_LEN_FIX_EN_S 21
/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
#define HINF_CLK_EN (BIT(22))
#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S)
#define HINF_CLK_EN_V 0x00000001U
#define HINF_CLK_EN_S 22
/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
#define HINF_SDDR50 (BIT(23))
#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S)
#define HINF_SDDR50_V 0x00000001U
#define HINF_SDDR50_S 23
/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
#define HINF_SSDR104 (BIT(24))
#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S)
#define HINF_SSDR104_V 0x00000001U
#define HINF_SSDR104_S 24
/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
#define HINF_SSDR50 (BIT(25))
#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S)
#define HINF_SSDR50_V 0x00000001U
#define HINF_SSDR50_S 25
/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
#define HINF_SDTD (BIT(26))
#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S)
#define HINF_SDTD_V 0x00000001U
#define HINF_SDTD_S 26
/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
#define HINF_SDTA (BIT(27))
#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S)
#define HINF_SDTA_V 0x00000001U
#define HINF_SDTA_S 27
/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
#define HINF_SDTC (BIT(28))
#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S)
#define HINF_SDTC_V 0x00000001U
#define HINF_SDTC_S 28
/** HINF_SAI : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
#define HINF_SAI (BIT(29))
#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S)
#define HINF_SAI_V 0x00000001U
#define HINF_SAI_S 29
/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
#define HINF_SDIO_WAKEUP_CLR (BIT(30))
#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U
#define HINF_SDIO_WAKEUP_CLR_S 30
/** HINF_CIS_CONF_W0_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
#define HINF_CIS_CONF_W0 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_S 0
/** HINF_CIS_CONF_W1_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
#define HINF_CIS_CONF_W1 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_S 0
/** HINF_CIS_CONF_W2_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
#define HINF_CIS_CONF_W2 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_S 0
/** HINF_CIS_CONF_W3_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
#define HINF_CIS_CONF_W3 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_S 0
/** HINF_CIS_CONF_W4_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
#define HINF_CIS_CONF_W4 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_S 0
/** HINF_CIS_CONF_W5_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
#define HINF_CIS_CONF_W5 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_S 0
/** HINF_CIS_CONF_W6_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
#define HINF_CIS_CONF_W6 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_S 0
/** HINF_CIS_CONF_W7_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
#define HINF_CIS_CONF_W7 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_S 0
/** HINF_CFG_DATA16_REG register
* SDIO cis configuration register
*/
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
#define HINF_DEVICE_ID_FN2 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_S 0
/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
#define HINF_USER_ID_FN2 0x0000FFFFU
#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
#define HINF_USER_ID_FN2_V 0x0000FFFFU
#define HINF_USER_ID_FN2_S 16
/** HINF_CFG_UHS1_INT_MODE_REG register
* configure int to start and end ahead of time in uhs1 mode
*/
#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_END_AHEAD_MODE 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_S 0
/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_END_AHEAD_MODE 0x00000003U
#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
#define HINF_INT_END_AHEAD_MODE_V 0x00000003U
#define HINF_INT_END_AHEAD_MODE_S 2
/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_S 4
/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_ST_AHEAD_MODE 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_S 6
/** HINF_CONF_STATUS_REG register
* func0 config0 status
*/
#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
#define HINF_FUNC0_CONFIG0 0x000000FFU
#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
#define HINF_FUNC0_CONFIG0_V 0x000000FFU
#define HINF_FUNC0_CONFIG0_S 0
/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
#define HINF_SDR25_ST (BIT(8))
#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
#define HINF_SDR25_ST_V 0x00000001U
#define HINF_SDR25_ST_S 8
/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
#define HINF_SDR50_ST (BIT(9))
#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
#define HINF_SDR50_ST_V 0x00000001U
#define HINF_SDR50_ST_S 9
/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
#define HINF_SDR104_ST (BIT(10))
#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
#define HINF_SDR104_ST_V 0x00000001U
#define HINF_SDR104_ST_S 10
/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
#define HINF_DDR50_ST (BIT(11))
#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
#define HINF_DDR50_ST_V 0x00000001U
#define HINF_DDR50_ST_S 11
/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
#define HINF_TUNE_ST 0x00000007U
#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
#define HINF_TUNE_ST_V 0x00000007U
#define HINF_TUNE_ST_S 12
/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15))
#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_ST_S 15
/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
#define HINF_SDIO_SWITCH_END (BIT(16))
#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
#define HINF_SDIO_SWITCH_END_V 0x00000001U
#define HINF_SDIO_SWITCH_END_S 16
/** HINF_SDIO_SLAVE_LDO_CONF_REG register
* sdio slave ldo control register
*/
#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
#define HINF_LDO_READY_CTL_IN_EN (BIT(0))
#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U
#define HINF_LDO_READY_CTL_IN_EN_S 0
/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
#define HINF_LDO_READY_THRES 0x0000001FU
#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
#define HINF_LDO_READY_THRES_V 0x0000001FU
#define HINF_LDO_READY_THRES_S 1
/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
#define HINF_LDO_READY_IGNORE_EN (BIT(6))
#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U
#define HINF_LDO_READY_IGNORE_EN_S 6
/** HINF_SDIO_DATE_REG register
* ******* Description ***********
*/
#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208;
* sdio version date.
*/
#define HINF_SDIO_DATE 0xFFFFFFFFU
#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
#define HINF_SDIO_DATE_V 0xFFFFFFFFU
#define HINF_SDIO_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration registers */
/** Type of cfg_data0 register
* Configure sdio cis content
*/
typedef union {
struct {
/** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
uint32_t device_id_fn1:16;
/** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
uint32_t user_id_fn1:16;
};
uint32_t val;
} hinf_cfg_data0_reg_t;
/** Type of cfg_data1 register
* SDIO configuration register
*/
typedef union {
struct {
/** sdio_enable : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
uint32_t sdio_enable:1;
/** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready1:1;
/** highspeed_enable : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
uint32_t highspeed_enable:1;
/** highspeed_mode : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
uint32_t highspeed_mode:1;
/** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
uint32_t sdio_cd_enable:1;
/** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready2:1;
/** sdio_int_mask : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
uint32_t sdio_int_mask:1;
/** ioenable2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
uint32_t ioenable2:1;
/** cd_disable : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
uint32_t cd_disable:1;
/** func1_eps : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
uint32_t func1_eps:1;
/** emp : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
uint32_t emp:1;
/** ioenable1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
uint32_t ioenable1:1;
/** sdio_ver : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
uint32_t sdio_ver:12;
/** func2_eps : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
uint32_t func2_eps:1;
/** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
uint32_t sdio20_conf:7;
};
uint32_t val;
} hinf_cfg_data1_reg_t;
/** Type of cfg_timing register
* Timing configuration registers
*/
typedef union {
struct {
/** ncrc : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
uint32_t ncrc:3;
/** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
uint32_t pst_end_cmd_low_value:7;
/** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
uint32_t pst_end_data_low_value:6;
/** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
uint32_t sdclk_stop_thres:11;
uint32_t reserved_27:1;
/** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
uint32_t sample_clk_divider:4;
};
uint32_t val;
} hinf_cfg_timing_reg_t;
/** Type of cfg_update register
* update sdio configurations
*/
typedef union {
struct {
/** conf_update : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
uint32_t conf_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hinf_cfg_update_reg_t;
/** Type of cfg_data7 register
* SDIO configuration register
*/
typedef union {
struct {
/** pin_state : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
uint32_t pin_state:8;
/** chip_state : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
uint32_t chip_state:8;
/** sdio_rst : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
uint32_t sdio_rst:1;
/** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
uint32_t sdio_ioready0:1;
/** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
uint32_t sdio_mem_pd:1;
/** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
uint32_t esdio_data1_int_en:1;
/** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
uint32_t sdio_switch_volt_sw:1;
/** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
uint32_t ddr50_blk_len_fix_en:1;
/** clk_en : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
uint32_t clk_en:1;
/** sddr50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
uint32_t sddr50:1;
/** ssdr104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
uint32_t ssdr104:1;
/** ssdr50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
uint32_t ssdr50:1;
/** sdtd : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
uint32_t sdtd:1;
/** sdta : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
uint32_t sdta:1;
/** sdtc : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
uint32_t sdtc:1;
/** sai : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
uint32_t sai:1;
/** sdio_wakeup_clr : WT; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
uint32_t sdio_wakeup_clr:1;
uint32_t reserved_31:1;
};
uint32_t val;
} hinf_cfg_data7_reg_t;
/** Type of cis_conf_w0 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
uint32_t cis_conf_w0:32;
};
uint32_t val;
} hinf_cis_conf_w0_reg_t;
/** Type of cis_conf_w1 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
uint32_t cis_conf_w1:32;
};
uint32_t val;
} hinf_cis_conf_w1_reg_t;
/** Type of cis_conf_w2 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
uint32_t cis_conf_w2:32;
};
uint32_t val;
} hinf_cis_conf_w2_reg_t;
/** Type of cis_conf_w3 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
uint32_t cis_conf_w3:32;
};
uint32_t val;
} hinf_cis_conf_w3_reg_t;
/** Type of cis_conf_w4 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
uint32_t cis_conf_w4:32;
};
uint32_t val;
} hinf_cis_conf_w4_reg_t;
/** Type of cis_conf_w5 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
uint32_t cis_conf_w5:32;
};
uint32_t val;
} hinf_cis_conf_w5_reg_t;
/** Type of cis_conf_w6 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
uint32_t cis_conf_w6:32;
};
uint32_t val;
} hinf_cis_conf_w6_reg_t;
/** Type of cis_conf_w7 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
uint32_t cis_conf_w7:32;
};
uint32_t val;
} hinf_cis_conf_w7_reg_t;
/** Type of cfg_data16 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
uint32_t device_id_fn2:16;
/** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
uint32_t user_id_fn2:16;
};
uint32_t val;
} hinf_cfg_data16_reg_t;
/** Type of cfg_uhs1_int_mode register
* configure int to start and end ahead of time in uhs1 mode
*/
typedef union {
struct {
/** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_end_ahead_mode:2;
/** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_end_ahead_mode:2;
/** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_st_ahead_mode:2;
/** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_st_ahead_mode:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hinf_cfg_uhs1_int_mode_reg_t;
/** Type of sdio_slave_ldo_conf register
* sdio slave ldo control register
*/
typedef union {
struct {
/** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
uint32_t ldo_ready_ctl_in_en:1;
/** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
uint32_t ldo_ready_thres:5;
/** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
uint32_t ldo_ready_ignore_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hinf_sdio_slave_ldo_conf_reg_t;
/** Group: Status registers */
/** Type of conf_status register
* func0 config0 status
*/
typedef union {
struct {
/** func0_config0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
uint32_t func0_config0:8;
/** sdr25_st : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
uint32_t sdr25_st:1;
/** sdr50_st : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
uint32_t sdr50_st:1;
/** sdr104_st : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
uint32_t sdr104_st:1;
/** ddr50_st : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
uint32_t ddr50_st:1;
/** tune_st : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
uint32_t tune_st:3;
/** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
uint32_t sdio_switch_volt_st:1;
/** sdio_switch_end : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
uint32_t sdio_switch_end:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hinf_conf_status_reg_t;
/** Group: Version register */
/** Type of sdio_date register
* ******* Description ***********
*/
typedef union {
struct {
/** sdio_date : R/W; bitpos: [31:0]; default: 35664208;
* sdio version date.
*/
uint32_t sdio_date:32;
};
uint32_t val;
} hinf_sdio_date_reg_t;
typedef struct {
volatile hinf_cfg_data0_reg_t cfg_data0;
volatile hinf_cfg_data1_reg_t cfg_data1;
volatile hinf_cfg_timing_reg_t cfg_timing;
volatile hinf_cfg_update_reg_t cfg_update;
uint32_t reserved_010[3];
volatile hinf_cfg_data7_reg_t cfg_data7;
volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
volatile hinf_cfg_data16_reg_t cfg_data16;
volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
uint32_t reserved_048[3];
volatile hinf_conf_status_reg_t conf_status;
uint32_t reserved_058[22];
volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
uint32_t reserved_0b4[18];
volatile hinf_sdio_date_reg_t sdio_date;
} hinf_dev_t;
extern hinf_dev_t HINF;
#ifndef __cplusplus
_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_M0_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M0_MODE 0x00000003U
#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S)
#define TEE_M0_MODE_V 0x00000003U
#define TEE_M0_MODE_S 0
/** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
*/
#define TEE_M0_LOCK (BIT(2))
#define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S)
#define TEE_M0_LOCK_V 0x00000001U
#define TEE_M0_LOCK_S 2
/** TEE_M1_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3;
* M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M1_MODE 0x00000003U
#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S)
#define TEE_M1_MODE_V 0x00000003U
#define TEE_M1_MODE_S 0
/** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m1 tee configuration
*/
#define TEE_M1_LOCK (BIT(2))
#define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S)
#define TEE_M1_LOCK_V 0x00000001U
#define TEE_M1_LOCK_S 2
/** TEE_M2_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0;
* M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M2_MODE 0x00000003U
#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S)
#define TEE_M2_MODE_V 0x00000003U
#define TEE_M2_MODE_S 0
/** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m2 tee configuration
*/
#define TEE_M2_LOCK (BIT(2))
#define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S)
#define TEE_M2_LOCK_V 0x00000001U
#define TEE_M2_LOCK_S 2
/** TEE_M3_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc)
/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3;
* M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M3_MODE 0x00000003U
#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S)
#define TEE_M3_MODE_V 0x00000003U
#define TEE_M3_MODE_S 0
/** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m3 tee configuration
*/
#define TEE_M3_LOCK (BIT(2))
#define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S)
#define TEE_M3_LOCK_V 0x00000001U
#define TEE_M3_LOCK_S 2
/** TEE_M4_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10)
/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3;
* M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M4_MODE 0x00000003U
#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S)
#define TEE_M4_MODE_V 0x00000003U
#define TEE_M4_MODE_S 0
/** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m4 tee configuration
*/
#define TEE_M4_LOCK (BIT(2))
#define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S)
#define TEE_M4_LOCK_V 0x00000001U
#define TEE_M4_LOCK_S 2
/** TEE_M5_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14)
/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3;
* M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M5_MODE 0x00000003U
#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S)
#define TEE_M5_MODE_V 0x00000003U
#define TEE_M5_MODE_S 0
/** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m5 tee configuration
*/
#define TEE_M5_LOCK (BIT(2))
#define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S)
#define TEE_M5_LOCK_V 0x00000001U
#define TEE_M5_LOCK_S 2
/** TEE_M6_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18)
/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3;
* M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M6_MODE 0x00000003U
#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S)
#define TEE_M6_MODE_V 0x00000003U
#define TEE_M6_MODE_S 0
/** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m6 tee configuration
*/
#define TEE_M6_LOCK (BIT(2))
#define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S)
#define TEE_M6_LOCK_V 0x00000001U
#define TEE_M6_LOCK_S 2
/** TEE_M7_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c)
/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3;
* M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M7_MODE 0x00000003U
#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S)
#define TEE_M7_MODE_V 0x00000003U
#define TEE_M7_MODE_S 0
/** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m7 tee configuration
*/
#define TEE_M7_LOCK (BIT(2))
#define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S)
#define TEE_M7_LOCK_V 0x00000001U
#define TEE_M7_LOCK_S 2
/** TEE_M8_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20)
/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3;
* M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M8_MODE 0x00000003U
#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S)
#define TEE_M8_MODE_V 0x00000003U
#define TEE_M8_MODE_S 0
/** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m8 tee configuration
*/
#define TEE_M8_LOCK (BIT(2))
#define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S)
#define TEE_M8_LOCK_V 0x00000001U
#define TEE_M8_LOCK_S 2
/** TEE_M9_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24)
/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3;
* M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M9_MODE 0x00000003U
#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S)
#define TEE_M9_MODE_V 0x00000003U
#define TEE_M9_MODE_S 0
/** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m9 tee configuration
*/
#define TEE_M9_LOCK (BIT(2))
#define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S)
#define TEE_M9_LOCK_V 0x00000001U
#define TEE_M9_LOCK_S 2
/** TEE_M10_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28)
/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3;
* M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M10_MODE 0x00000003U
#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S)
#define TEE_M10_MODE_V 0x00000003U
#define TEE_M10_MODE_S 0
/** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m10 tee configuration
*/
#define TEE_M10_LOCK (BIT(2))
#define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S)
#define TEE_M10_LOCK_V 0x00000001U
#define TEE_M10_LOCK_S 2
/** TEE_M11_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c)
/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3;
* M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M11_MODE 0x00000003U
#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S)
#define TEE_M11_MODE_V 0x00000003U
#define TEE_M11_MODE_S 0
/** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m11 tee configuration
*/
#define TEE_M11_LOCK (BIT(2))
#define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S)
#define TEE_M11_LOCK_V 0x00000001U
#define TEE_M11_LOCK_S 2
/** TEE_M12_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30)
/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3;
* M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M12_MODE 0x00000003U
#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S)
#define TEE_M12_MODE_V 0x00000003U
#define TEE_M12_MODE_S 0
/** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m12 tee configuration
*/
#define TEE_M12_LOCK (BIT(2))
#define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S)
#define TEE_M12_LOCK_V 0x00000001U
#define TEE_M12_LOCK_S 2
/** TEE_M13_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34)
/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3;
* M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M13_MODE 0x00000003U
#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S)
#define TEE_M13_MODE_V 0x00000003U
#define TEE_M13_MODE_S 0
/** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m13 tee configuration
*/
#define TEE_M13_LOCK (BIT(2))
#define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S)
#define TEE_M13_LOCK_V 0x00000001U
#define TEE_M13_LOCK_S 2
/** TEE_M14_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38)
/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3;
* M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M14_MODE 0x00000003U
#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S)
#define TEE_M14_MODE_V 0x00000003U
#define TEE_M14_MODE_S 0
/** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m14 tee configuration
*/
#define TEE_M14_LOCK (BIT(2))
#define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S)
#define TEE_M14_LOCK_V 0x00000001U
#define TEE_M14_LOCK_S 2
/** TEE_M15_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c)
/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3;
* M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M15_MODE 0x00000003U
#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S)
#define TEE_M15_MODE_V 0x00000003U
#define TEE_M15_MODE_S 0
/** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m15 tee configuration
*/
#define TEE_M15_LOCK (BIT(2))
#define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S)
#define TEE_M15_LOCK_V 0x00000001U
#define TEE_M15_LOCK_S 2
/** TEE_M16_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40)
/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3;
* M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M16_MODE 0x00000003U
#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S)
#define TEE_M16_MODE_V 0x00000003U
#define TEE_M16_MODE_S 0
/** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m16 tee configuration
*/
#define TEE_M16_LOCK (BIT(2))
#define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S)
#define TEE_M16_LOCK_V 0x00000001U
#define TEE_M16_LOCK_S 2
/** TEE_M17_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44)
/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3;
* M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M17_MODE 0x00000003U
#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S)
#define TEE_M17_MODE_V 0x00000003U
#define TEE_M17_MODE_S 0
/** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m17 tee configuration
*/
#define TEE_M17_LOCK (BIT(2))
#define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S)
#define TEE_M17_LOCK_V 0x00000001U
#define TEE_M17_LOCK_S 2
/** TEE_M18_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48)
/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3;
* M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M18_MODE 0x00000003U
#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S)
#define TEE_M18_MODE_V 0x00000003U
#define TEE_M18_MODE_S 0
/** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m18 tee configuration
*/
#define TEE_M18_LOCK (BIT(2))
#define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S)
#define TEE_M18_LOCK_V 0x00000001U
#define TEE_M18_LOCK_S 2
/** TEE_M19_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c)
/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3;
* M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M19_MODE 0x00000003U
#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S)
#define TEE_M19_MODE_V 0x00000003U
#define TEE_M19_MODE_S 0
/** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m19 tee configuration
*/
#define TEE_M19_LOCK (BIT(2))
#define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S)
#define TEE_M19_LOCK_V 0x00000001U
#define TEE_M19_LOCK_S 2
/** TEE_M20_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50)
/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3;
* M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M20_MODE 0x00000003U
#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S)
#define TEE_M20_MODE_V 0x00000003U
#define TEE_M20_MODE_S 0
/** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m20 tee configuration
*/
#define TEE_M20_LOCK (BIT(2))
#define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S)
#define TEE_M20_LOCK_V 0x00000001U
#define TEE_M20_LOCK_S 2
/** TEE_M21_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54)
/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3;
* M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M21_MODE 0x00000003U
#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S)
#define TEE_M21_MODE_V 0x00000003U
#define TEE_M21_MODE_S 0
/** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m21 tee configuration
*/
#define TEE_M21_LOCK (BIT(2))
#define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S)
#define TEE_M21_LOCK_V 0x00000001U
#define TEE_M21_LOCK_S 2
/** TEE_M22_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58)
/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3;
* M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M22_MODE 0x00000003U
#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S)
#define TEE_M22_MODE_V 0x00000003U
#define TEE_M22_MODE_S 0
/** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m22 tee configuration
*/
#define TEE_M22_LOCK (BIT(2))
#define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S)
#define TEE_M22_LOCK_V 0x00000001U
#define TEE_M22_LOCK_S 2
/** TEE_M23_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c)
/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3;
* M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M23_MODE 0x00000003U
#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S)
#define TEE_M23_MODE_V 0x00000003U
#define TEE_M23_MODE_S 0
/** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m23 tee configuration
*/
#define TEE_M23_LOCK (BIT(2))
#define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S)
#define TEE_M23_LOCK_V 0x00000001U
#define TEE_M23_LOCK_S 2
/** TEE_M24_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60)
/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3;
* M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M24_MODE 0x00000003U
#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S)
#define TEE_M24_MODE_V 0x00000003U
#define TEE_M24_MODE_S 0
/** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m24 tee configuration
*/
#define TEE_M24_LOCK (BIT(2))
#define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S)
#define TEE_M24_LOCK_V 0x00000001U
#define TEE_M24_LOCK_S 2
/** TEE_M25_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64)
/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3;
* M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M25_MODE 0x00000003U
#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S)
#define TEE_M25_MODE_V 0x00000003U
#define TEE_M25_MODE_S 0
/** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m25 tee configuration
*/
#define TEE_M25_LOCK (BIT(2))
#define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S)
#define TEE_M25_LOCK_V 0x00000001U
#define TEE_M25_LOCK_S 2
/** TEE_M26_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68)
/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3;
* M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M26_MODE 0x00000003U
#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S)
#define TEE_M26_MODE_V 0x00000003U
#define TEE_M26_MODE_S 0
/** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m26 tee configuration
*/
#define TEE_M26_LOCK (BIT(2))
#define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S)
#define TEE_M26_LOCK_V 0x00000001U
#define TEE_M26_LOCK_S 2
/** TEE_M27_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c)
/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3;
* M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M27_MODE 0x00000003U
#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S)
#define TEE_M27_MODE_V 0x00000003U
#define TEE_M27_MODE_S 0
/** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m27 tee configuration
*/
#define TEE_M27_LOCK (BIT(2))
#define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S)
#define TEE_M27_LOCK_V 0x00000001U
#define TEE_M27_LOCK_S 2
/** TEE_M28_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70)
/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3;
* M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M28_MODE 0x00000003U
#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S)
#define TEE_M28_MODE_V 0x00000003U
#define TEE_M28_MODE_S 0
/** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m28 tee configuration
*/
#define TEE_M28_LOCK (BIT(2))
#define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S)
#define TEE_M28_LOCK_V 0x00000001U
#define TEE_M28_LOCK_S 2
/** TEE_M29_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74)
/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3;
* M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M29_MODE 0x00000003U
#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S)
#define TEE_M29_MODE_V 0x00000003U
#define TEE_M29_MODE_S 0
/** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m29 tee configuration
*/
#define TEE_M29_LOCK (BIT(2))
#define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S)
#define TEE_M29_LOCK_V 0x00000001U
#define TEE_M29_LOCK_S 2
/** TEE_M30_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78)
/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3;
* M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M30_MODE 0x00000003U
#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S)
#define TEE_M30_MODE_V 0x00000003U
#define TEE_M30_MODE_S 0
/** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m30 tee configuration
*/
#define TEE_M30_LOCK (BIT(2))
#define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S)
#define TEE_M30_LOCK_V 0x00000001U
#define TEE_M30_LOCK_S 2
/** TEE_M31_MODE_CTRL_REG register
* Tee mode control register
*/
#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c)
/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3;
* M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
#define TEE_M31_MODE 0x00000003U
#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S)
#define TEE_M31_MODE_V 0x00000003U
#define TEE_M31_MODE_S 0
/** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m31 tee configuration
*/
#define TEE_M31_LOCK (BIT(2))
#define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S)
#define TEE_M31_LOCK_V 0x00000001U
#define TEE_M31_LOCK_S 2
/** TEE_CLOCK_GATE_REG register
* Clock gating register
*/
#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80)
/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
#define TEE_CLK_EN (BIT(0))
#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S)
#define TEE_CLK_EN_V 0x00000001U
#define TEE_CLK_EN_S 0
/** TEE_DATE_REG register
* Version register
*/
#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc)
/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
* reg_tee_date
*/
#define TEE_DATE_REG 0x0FFFFFFFU
#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S)
#define TEE_DATE_REG_V 0x0FFFFFFFU
#define TEE_DATE_REG_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Tee mode control register */
/** Type of m0_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m0_mode : R/W; bitpos: [1:0]; default: 0;
* M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m0_mode:2;
/** m0_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m0 tee configuration
*/
uint32_t m0_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m0_mode_ctrl_reg_t;
/** Type of m1_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m1_mode : R/W; bitpos: [1:0]; default: 3;
* M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m1_mode:2;
/** m1_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m1 tee configuration
*/
uint32_t m1_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m1_mode_ctrl_reg_t;
/** Type of m2_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m2_mode : R/W; bitpos: [1:0]; default: 0;
* M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m2_mode:2;
/** m2_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m2 tee configuration
*/
uint32_t m2_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m2_mode_ctrl_reg_t;
/** Type of m3_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m3_mode : R/W; bitpos: [1:0]; default: 3;
* M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m3_mode:2;
/** m3_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m3 tee configuration
*/
uint32_t m3_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m3_mode_ctrl_reg_t;
/** Type of m4_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m4_mode : R/W; bitpos: [1:0]; default: 3;
* M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m4_mode:2;
/** m4_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m4 tee configuration
*/
uint32_t m4_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m4_mode_ctrl_reg_t;
/** Type of m5_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m5_mode : R/W; bitpos: [1:0]; default: 3;
* M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m5_mode:2;
/** m5_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m5 tee configuration
*/
uint32_t m5_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m5_mode_ctrl_reg_t;
/** Type of m6_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m6_mode : R/W; bitpos: [1:0]; default: 3;
* M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m6_mode:2;
/** m6_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m6 tee configuration
*/
uint32_t m6_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m6_mode_ctrl_reg_t;
/** Type of m7_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m7_mode : R/W; bitpos: [1:0]; default: 3;
* M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m7_mode:2;
/** m7_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m7 tee configuration
*/
uint32_t m7_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m7_mode_ctrl_reg_t;
/** Type of m8_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m8_mode : R/W; bitpos: [1:0]; default: 3;
* M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m8_mode:2;
/** m8_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m8 tee configuration
*/
uint32_t m8_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m8_mode_ctrl_reg_t;
/** Type of m9_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m9_mode : R/W; bitpos: [1:0]; default: 3;
* M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m9_mode:2;
/** m9_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m9 tee configuration
*/
uint32_t m9_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m9_mode_ctrl_reg_t;
/** Type of m10_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m10_mode : R/W; bitpos: [1:0]; default: 3;
* M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m10_mode:2;
/** m10_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m10 tee configuration
*/
uint32_t m10_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m10_mode_ctrl_reg_t;
/** Type of m11_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m11_mode : R/W; bitpos: [1:0]; default: 3;
* M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m11_mode:2;
/** m11_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m11 tee configuration
*/
uint32_t m11_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m11_mode_ctrl_reg_t;
/** Type of m12_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m12_mode : R/W; bitpos: [1:0]; default: 3;
* M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m12_mode:2;
/** m12_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m12 tee configuration
*/
uint32_t m12_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m12_mode_ctrl_reg_t;
/** Type of m13_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m13_mode : R/W; bitpos: [1:0]; default: 3;
* M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m13_mode:2;
/** m13_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m13 tee configuration
*/
uint32_t m13_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m13_mode_ctrl_reg_t;
/** Type of m14_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m14_mode : R/W; bitpos: [1:0]; default: 3;
* M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m14_mode:2;
/** m14_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m14 tee configuration
*/
uint32_t m14_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m14_mode_ctrl_reg_t;
/** Type of m15_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m15_mode : R/W; bitpos: [1:0]; default: 3;
* M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m15_mode:2;
/** m15_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m15 tee configuration
*/
uint32_t m15_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m15_mode_ctrl_reg_t;
/** Type of m16_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m16_mode : R/W; bitpos: [1:0]; default: 3;
* M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m16_mode:2;
/** m16_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m16 tee configuration
*/
uint32_t m16_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m16_mode_ctrl_reg_t;
/** Type of m17_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m17_mode : R/W; bitpos: [1:0]; default: 3;
* M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m17_mode:2;
/** m17_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m17 tee configuration
*/
uint32_t m17_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m17_mode_ctrl_reg_t;
/** Type of m18_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m18_mode : R/W; bitpos: [1:0]; default: 3;
* M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m18_mode:2;
/** m18_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m18 tee configuration
*/
uint32_t m18_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m18_mode_ctrl_reg_t;
/** Type of m19_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m19_mode : R/W; bitpos: [1:0]; default: 3;
* M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m19_mode:2;
/** m19_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m19 tee configuration
*/
uint32_t m19_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m19_mode_ctrl_reg_t;
/** Type of m20_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m20_mode : R/W; bitpos: [1:0]; default: 3;
* M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m20_mode:2;
/** m20_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m20 tee configuration
*/
uint32_t m20_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m20_mode_ctrl_reg_t;
/** Type of m21_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m21_mode : R/W; bitpos: [1:0]; default: 3;
* M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m21_mode:2;
/** m21_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m21 tee configuration
*/
uint32_t m21_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m21_mode_ctrl_reg_t;
/** Type of m22_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m22_mode : R/W; bitpos: [1:0]; default: 3;
* M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m22_mode:2;
/** m22_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m22 tee configuration
*/
uint32_t m22_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m22_mode_ctrl_reg_t;
/** Type of m23_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m23_mode : R/W; bitpos: [1:0]; default: 3;
* M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m23_mode:2;
/** m23_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m23 tee configuration
*/
uint32_t m23_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m23_mode_ctrl_reg_t;
/** Type of m24_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m24_mode : R/W; bitpos: [1:0]; default: 3;
* M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m24_mode:2;
/** m24_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m24 tee configuration
*/
uint32_t m24_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m24_mode_ctrl_reg_t;
/** Type of m25_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m25_mode : R/W; bitpos: [1:0]; default: 3;
* M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m25_mode:2;
/** m25_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m25 tee configuration
*/
uint32_t m25_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m25_mode_ctrl_reg_t;
/** Type of m26_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m26_mode : R/W; bitpos: [1:0]; default: 3;
* M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m26_mode:2;
/** m26_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m26 tee configuration
*/
uint32_t m26_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m26_mode_ctrl_reg_t;
/** Type of m27_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m27_mode : R/W; bitpos: [1:0]; default: 3;
* M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m27_mode:2;
/** m27_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m27 tee configuration
*/
uint32_t m27_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m27_mode_ctrl_reg_t;
/** Type of m28_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m28_mode : R/W; bitpos: [1:0]; default: 3;
* M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m28_mode:2;
/** m28_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m28 tee configuration
*/
uint32_t m28_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m28_mode_ctrl_reg_t;
/** Type of m29_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m29_mode : R/W; bitpos: [1:0]; default: 3;
* M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m29_mode:2;
/** m29_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m29 tee configuration
*/
uint32_t m29_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m29_mode_ctrl_reg_t;
/** Type of m30_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m30_mode : R/W; bitpos: [1:0]; default: 3;
* M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m30_mode:2;
/** m30_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m30 tee configuration
*/
uint32_t m30_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m30_mode_ctrl_reg_t;
/** Type of m31_mode_ctrl register
* Tee mode control register
*/
typedef union {
struct {
/** m31_mode : R/W; bitpos: [1:0]; default: 3;
* M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
* tee_mode
*/
uint32_t m31_mode:2;
/** m31_lock : R/W; bitpos: [2]; default: 0;
* Set 1 to lock m31 tee configuration
*/
uint32_t m31_lock:1;
uint32_t reserved_3:29;
};
uint32_t val;
} tee_m31_mode_ctrl_reg_t;
/** Group: clock gating register */
/** Type of clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* reg_clk_en
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_clock_gate_reg_t;
/** Group: Version register */
/** Type of date register
* Version register
*/
typedef union {
struct {
/** date_reg : R/W; bitpos: [27:0]; default: 35725664;
* reg_tee_date
*/
uint32_t date_reg:28;
uint32_t reserved_28:4;
};
uint32_t val;
} tee_date_reg_t;
typedef struct {
volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl;
volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl;
volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl;
volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl;
volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl;
volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl;
volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl;
volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl;
volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl;
volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl;
volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl;
volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl;
volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl;
volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl;
volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl;
volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl;
volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl;
volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl;
volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl;
volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl;
volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl;
volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl;
volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl;
volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl;
volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl;
volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl;
volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl;
volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl;
volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl;
volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl;
volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl;
volatile tee_clock_gate_reg_t clock_gate;
uint32_t reserved_084[990];
volatile tee_date_reg_t date;
} tee_dev_t;
extern tee_dev_t TEE;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/include/soc/twai_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TWAI_MODE_REG register
* TWAI mode register.
*/
#define TWAI_MODE_REG (DR_REG_TWAI_BASE + 0x0)
/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1;
* 1: reset, detection of a set reset mode bit results in aborting the current
* transmission/reception of a message and entering the reset mode. 0: normal, on the
* '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
* operating mode.
*/
#define TWAI_RESET_MODE (BIT(0))
#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S)
#define TWAI_RESET_MODE_V 0x00000001U
#define TWAI_RESET_MODE_S 0
/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0;
* 1: listen only, in this mode the TWAI controller would give no acknowledge to the
* TWAI-bus, even if a message is received successfully. The error counters are
* stopped at the current value. 0: normal.
*/
#define TWAI_LISTEN_ONLY_MODE (BIT(1))
#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S)
#define TWAI_LISTEN_ONLY_MODE_V 0x00000001U
#define TWAI_LISTEN_ONLY_MODE_S 1
/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0;
* 1: self test, in this mode a full node test is possible without any other active
* node on the bus using the self reception request command. The TWAI controller will
* perform a successful transmission, even if there is no acknowledge received. 0:
* normal, an acknowledge is required for successful transmission.
*/
#define TWAI_SELF_TEST_MODE (BIT(2))
#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S)
#define TWAI_SELF_TEST_MODE_V 0x00000001U
#define TWAI_SELF_TEST_MODE_S 2
/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0;
* 1:single, the single acceptance filter option is enabled (one filter with the
* length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
* (two filters, each with the length of 16 bit are active).
*/
#define TWAI_ACCEPTANCE_FILTER_MODE (BIT(3))
#define TWAI_ACCEPTANCE_FILTER_MODE_M (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S)
#define TWAI_ACCEPTANCE_FILTER_MODE_V 0x00000001U
#define TWAI_ACCEPTANCE_FILTER_MODE_S 3
/** TWAI_CMD_REG register
* TWAI command register.
*/
#define TWAI_CMD_REG (DR_REG_TWAI_BASE + 0x4)
/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0;
* 1: present, a message shall be transmitted. 0: absent
*/
#define TWAI_TX_REQUEST (BIT(0))
#define TWAI_TX_REQUEST_M (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S)
#define TWAI_TX_REQUEST_V 0x00000001U
#define TWAI_TX_REQUEST_S 0
/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0;
* 1: present, if not already in progress, a pending transmission request is
* cancelled. 0: absent
*/
#define TWAI_ABORT_TX (BIT(1))
#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S)
#define TWAI_ABORT_TX_V 0x00000001U
#define TWAI_ABORT_TX_S 1
/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0;
* 1: released, the receive buffer, representing the message memory space in the
* RXFIFO is released. 0: no action
*/
#define TWAI_RELEASE_BUFFER (BIT(2))
#define TWAI_RELEASE_BUFFER_M (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S)
#define TWAI_RELEASE_BUFFER_V 0x00000001U
#define TWAI_RELEASE_BUFFER_S 2
/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0;
* 1: clear, the data overrun status bit is cleared. 0: no action.
*/
#define TWAI_CLEAR_DATA_OVERRUN (BIT(3))
#define TWAI_CLEAR_DATA_OVERRUN_M (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S)
#define TWAI_CLEAR_DATA_OVERRUN_V 0x00000001U
#define TWAI_CLEAR_DATA_OVERRUN_S 3
/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0;
* 1: present, a message shall be transmitted and received simultaneously. 0: absent.
*/
#define TWAI_SELF_RX_REQUEST (BIT(4))
#define TWAI_SELF_RX_REQUEST_M (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S)
#define TWAI_SELF_RX_REQUEST_V 0x00000001U
#define TWAI_SELF_RX_REQUEST_S 4
/** TWAI_STATUS_REG register
* TWAI status register.
*/
#define TWAI_STATUS_REG (DR_REG_TWAI_BASE + 0x8)
/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0;
* 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
* message is available
*/
#define TWAI_STATUS_RECEIVE_BUFFER (BIT(0))
#define TWAI_STATUS_RECEIVE_BUFFER_M (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S)
#define TWAI_STATUS_RECEIVE_BUFFER_V 0x00000001U
#define TWAI_STATUS_RECEIVE_BUFFER_S 0
/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0;
* 1: overrun, a message was lost because there was not enough space for that message
* in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
* overrun command was given
*/
#define TWAI_STATUS_OVERRUN (BIT(1))
#define TWAI_STATUS_OVERRUN_M (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S)
#define TWAI_STATUS_OVERRUN_V 0x00000001U
#define TWAI_STATUS_OVERRUN_S 1
/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0;
* 1: released, the CPU may write a message into the transmit buffer. 0: locked, the
* CPU cannot access the transmit buffer, a message is either waiting for transmission
* or is in the process of being transmitted
*/
#define TWAI_STATUS_TRANSMIT_BUFFER (BIT(2))
#define TWAI_STATUS_TRANSMIT_BUFFER_M (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S)
#define TWAI_STATUS_TRANSMIT_BUFFER_V 0x00000001U
#define TWAI_STATUS_TRANSMIT_BUFFER_S 2
/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0;
* 1: complete, last requested transmission has been successfully completed. 0:
* incomplete, previously requested transmission is not yet completed
*/
#define TWAI_STATUS_TRANSMISSION_COMPLETE (BIT(3))
#define TWAI_STATUS_TRANSMISSION_COMPLETE_M (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S)
#define TWAI_STATUS_TRANSMISSION_COMPLETE_V 0x00000001U
#define TWAI_STATUS_TRANSMISSION_COMPLETE_S 3
/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0;
* 1: receive, the TWAI controller is receiving a message. 0: idle
*/
#define TWAI_STATUS_RECEIVE (BIT(4))
#define TWAI_STATUS_RECEIVE_M (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S)
#define TWAI_STATUS_RECEIVE_V 0x00000001U
#define TWAI_STATUS_RECEIVE_S 4
/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0;
* 1: transmit, the TWAI controller is transmitting a message. 0: idle
*/
#define TWAI_STATUS_TRANSMIT (BIT(5))
#define TWAI_STATUS_TRANSMIT_M (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S)
#define TWAI_STATUS_TRANSMIT_V 0x00000001U
#define TWAI_STATUS_TRANSMIT_S 5
/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0;
* 1: error, at least one of the error counters has reached or exceeded the CPU
* warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
* counters are below the warning limit
*/
#define TWAI_STATUS_ERR (BIT(6))
#define TWAI_STATUS_ERR_M (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S)
#define TWAI_STATUS_ERR_V 0x00000001U
#define TWAI_STATUS_ERR_S 6
/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0;
* 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
* TWAI controller is involved in bus activities
*/
#define TWAI_STATUS_NODE_BUS_OFF (BIT(7))
#define TWAI_STATUS_NODE_BUS_OFF_M (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S)
#define TWAI_STATUS_NODE_BUS_OFF_V 0x00000001U
#define TWAI_STATUS_NODE_BUS_OFF_S 7
/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0;
* 1: current message is destroyed because of FIFO overflow.
*/
#define TWAI_STATUS_MISS (BIT(8))
#define TWAI_STATUS_MISS_M (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S)
#define TWAI_STATUS_MISS_V 0x00000001U
#define TWAI_STATUS_MISS_S 8
/** TWAI_INTERRUPT_REG register
* Interrupt signals' register.
*/
#define TWAI_INTERRUPT_REG (DR_REG_TWAI_BASE + 0xc)
/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0;
* 1: this bit is set while the receive FIFO is not empty and the RIE bit is set
* within the interrupt enable register. 0: reset
*/
#define TWAI_RECEIVE_INT_ST (BIT(0))
#define TWAI_RECEIVE_INT_ST_M (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S)
#define TWAI_RECEIVE_INT_ST_V 0x00000001U
#define TWAI_RECEIVE_INT_ST_S 0
/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0;
* 1: this bit is set whenever the transmit buffer status changes from '0-to-1'
* (released) and the TIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_TRANSMIT_INT_ST (BIT(1))
#define TWAI_TRANSMIT_INT_ST_M (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S)
#define TWAI_TRANSMIT_INT_ST_V 0x00000001U
#define TWAI_TRANSMIT_INT_ST_S 1
/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0;
* 1: this bit is set on every change (set and clear) of either the error status or
* bus status bits and the EIE bit is set within the interrupt enable register. 0:
* reset
*/
#define TWAI_ERR_WARNING_INT_ST (BIT(2))
#define TWAI_ERR_WARNING_INT_ST_M (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S)
#define TWAI_ERR_WARNING_INT_ST_V 0x00000001U
#define TWAI_ERR_WARNING_INT_ST_S 2
/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
* 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
* DOIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_DATA_OVERRUN_INT_ST (BIT(3))
#define TWAI_DATA_OVERRUN_INT_ST_M (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S)
#define TWAI_DATA_OVERRUN_INT_ST_V 0x00000001U
#define TWAI_DATA_OVERRUN_INT_ST_S 3
/** TWAI_TS_COUNTER_OVFL_INT_ST : RO; bitpos: [4]; default: 0;
* 1: this bit is set then the timestamp counter reaches the maximum value and
* overflow.
*/
#define TWAI_TS_COUNTER_OVFL_INT_ST (BIT(4))
#define TWAI_TS_COUNTER_OVFL_INT_ST_M (TWAI_TS_COUNTER_OVFL_INT_ST_V << TWAI_TS_COUNTER_OVFL_INT_ST_S)
#define TWAI_TS_COUNTER_OVFL_INT_ST_V 0x00000001U
#define TWAI_TS_COUNTER_OVFL_INT_ST_S 4
/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0;
* 1: this bit is set whenever the TWAI controller has reached the error passive
* status (at least one error counter exceeds the protocol-defined level of 127) or if
* the TWAI controller is in the error passive status and enters the error active
* status again and the EPIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_ERR_PASSIVE_INT_ST (BIT(5))
#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S)
#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001U
#define TWAI_ERR_PASSIVE_INT_ST_S 5
/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0;
* 1: this bit is set when the TWAI controller lost the arbitration and becomes a
* receiver and the ALIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_ARBITRATION_LOST_INT_ST (BIT(6))
#define TWAI_ARBITRATION_LOST_INT_ST_M (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S)
#define TWAI_ARBITRATION_LOST_INT_ST_V 0x00000001U
#define TWAI_ARBITRATION_LOST_INT_ST_S 6
/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0;
* 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
* the BEIE bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_BUS_ERR_INT_ST (BIT(7))
#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S)
#define TWAI_BUS_ERR_INT_ST_V 0x00000001U
#define TWAI_BUS_ERR_INT_ST_S 7
/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0;
* 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
* this interrupt enable bit is set within the interrupt enable register. 0: reset
*/
#define TWAI_IDLE_INT_ST (BIT(8))
#define TWAI_IDLE_INT_ST_M (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S)
#define TWAI_IDLE_INT_ST_V 0x00000001U
#define TWAI_IDLE_INT_ST_S 8
/** TWAI_INTERRUPT_ENABLE_REG register
* Interrupt enable register.
*/
#define TWAI_INTERRUPT_ENABLE_REG (DR_REG_TWAI_BASE + 0x10)
/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0;
* 1: enabled, when the receive buffer status is 'full' the TWAI controller requests
* the respective interrupt. 0: disable
*/
#define TWAI_EXT_RECEIVE_INT_ENA (BIT(0))
#define TWAI_EXT_RECEIVE_INT_ENA_M (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S)
#define TWAI_EXT_RECEIVE_INT_ENA_V 0x00000001U
#define TWAI_EXT_RECEIVE_INT_ENA_S 0
/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
* 1: enabled, when a message has been successfully transmitted or the transmit buffer
* is accessible again (e.g. after an abort transmission command), the TWAI controller
* requests the respective interrupt. 0: disable
*/
#define TWAI_EXT_TRANSMIT_INT_ENA (BIT(1))
#define TWAI_EXT_TRANSMIT_INT_ENA_M (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S)
#define TWAI_EXT_TRANSMIT_INT_ENA_V 0x00000001U
#define TWAI_EXT_TRANSMIT_INT_ENA_S 1
/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0;
* 1: enabled, if the error or bus status change (see status register. Table 14), the
* TWAI controllerrequests the respective interrupt. 0: disable
*/
#define TWAI_EXT_ERR_WARNING_INT_ENA (BIT(2))
#define TWAI_EXT_ERR_WARNING_INT_ENA_M (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S)
#define TWAI_EXT_ERR_WARNING_INT_ENA_V 0x00000001U
#define TWAI_EXT_ERR_WARNING_INT_ENA_S 2
/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
* 1: enabled, if the data overrun status bit is set (see status register. Table 14),
* the TWAI controllerrequests the respective interrupt. 0: disable
*/
#define TWAI_EXT_DATA_OVERRUN_INT_ENA (BIT(3))
#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S)
#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V 0x00000001U
#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S 3
/** TWAI_TS_COUNTER_OVFL_INT_ENA : R/W; bitpos: [4]; default: 0;
* enable the timestamp counter overflow interrupt request.
*/
#define TWAI_TS_COUNTER_OVFL_INT_ENA (BIT(4))
#define TWAI_TS_COUNTER_OVFL_INT_ENA_M (TWAI_TS_COUNTER_OVFL_INT_ENA_V << TWAI_TS_COUNTER_OVFL_INT_ENA_S)
#define TWAI_TS_COUNTER_OVFL_INT_ENA_V 0x00000001U
#define TWAI_TS_COUNTER_OVFL_INT_ENA_S 4
/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0;
* 1: enabled, if the error status of the TWAI controller changes from error active to
* error passive or vice versa, the respective interrupt is requested. 0: disable
*/
#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5))
#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S)
#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001U
#define TWAI_ERR_PASSIVE_INT_ENA_S 5
/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0;
* 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
* is requested. 0: disable
*/
#define TWAI_ARBITRATION_LOST_INT_ENA (BIT(6))
#define TWAI_ARBITRATION_LOST_INT_ENA_M (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S)
#define TWAI_ARBITRATION_LOST_INT_ENA_V 0x00000001U
#define TWAI_ARBITRATION_LOST_INT_ENA_S 6
/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
* 1: enabled, if an bus error has been detected, the TWAI controller requests the
* respective interrupt. 0: disable
*/
#define TWAI_BUS_ERR_INT_ENA (BIT(7))
#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S)
#define TWAI_BUS_ERR_INT_ENA_V 0x00000001U
#define TWAI_BUS_ERR_INT_ENA_S 7
/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0;
* 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
* respective interrupt. 0: disable
*/
#define TWAI_IDLE_INT_ENA (BIT(8))
#define TWAI_IDLE_INT_ENA_M (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S)
#define TWAI_IDLE_INT_ENA_V 0x00000001U
#define TWAI_IDLE_INT_ENA_S 8
/** TWAI_BUS_TIMING_0_REG register
* Bit timing configuration register 0.
*/
#define TWAI_BUS_TIMING_0_REG (DR_REG_TWAI_BASE + 0x18)
/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0;
* The period of the TWAI system clock is programmable and determines the individual
* bit timing. Software has R/W permission in reset mode and RO permission in
* operation mode.
*/
#define TWAI_BAUD_PRESC 0x00003FFFU
#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S)
#define TWAI_BAUD_PRESC_V 0x00003FFFU
#define TWAI_BAUD_PRESC_S 0
/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0;
* The synchronization jump width defines the maximum number of clock cycles a bit
* period may be shortened or lengthened. Software has R/W permission in reset mode
* and RO in operation mode.
*/
#define TWAI_SYNC_JUMP_WIDTH 0x00000003U
#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S)
#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003U
#define TWAI_SYNC_JUMP_WIDTH_S 14
/** TWAI_BUS_TIMING_1_REG register
* Bit timing configuration register 1.
*/
#define TWAI_BUS_TIMING_1_REG (DR_REG_TWAI_BASE + 0x1c)
/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0;
* The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
*/
#define TWAI_TIME_SEGMENT1 0x0000000FU
#define TWAI_TIME_SEGMENT1_M (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S)
#define TWAI_TIME_SEGMENT1_V 0x0000000FU
#define TWAI_TIME_SEGMENT1_S 0
/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0;
* The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
*/
#define TWAI_TIME_SEGMENT2 0x00000007U
#define TWAI_TIME_SEGMENT2_M (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S)
#define TWAI_TIME_SEGMENT2_V 0x00000007U
#define TWAI_TIME_SEGMENT2_S 4
/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0;
* 1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
* Software has R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_TIME_SAMPLING (BIT(7))
#define TWAI_TIME_SAMPLING_M (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S)
#define TWAI_TIME_SAMPLING_V 0x00000001U
#define TWAI_TIME_SAMPLING_S 7
/** TWAI_ARB_LOST_CAP_REG register
* TWAI arbiter lost capture register.
*/
#define TWAI_ARB_LOST_CAP_REG (DR_REG_TWAI_BASE + 0x2c)
/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0;
* This register contains information about the bit position of losing arbitration.
*/
#define TWAI_ARBITRATION_LOST_CAPTURE 0x0000001FU
#define TWAI_ARBITRATION_LOST_CAPTURE_M (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S)
#define TWAI_ARBITRATION_LOST_CAPTURE_V 0x0000001FU
#define TWAI_ARBITRATION_LOST_CAPTURE_S 0
/** TWAI_ERR_CODE_CAP_REG register
* TWAI error info capture register.
*/
#define TWAI_ERR_CODE_CAP_REG (DR_REG_TWAI_BASE + 0x30)
/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0;
* This register contains information about the location of errors on the bus.
*/
#define TWAI_ERR_CAPTURE_CODE_SEGMENT 0x0000001FU
#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S)
#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V 0x0000001FU
#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S 0
/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0;
* 1: RX, error occurred during reception. 0: TX, error occurred during transmission.
*/
#define TWAI_ERR_CAPTURE_CODE_DIRECTION (BIT(5))
#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S)
#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V 0x00000001U
#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S 5
/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0;
* 00: bit error. 01: form error. 10:stuff error. 11:other type of error.
*/
#define TWAI_ERR_CAPTURE_CODE_TYPE 0x00000003U
#define TWAI_ERR_CAPTURE_CODE_TYPE_M (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S)
#define TWAI_ERR_CAPTURE_CODE_TYPE_V 0x00000003U
#define TWAI_ERR_CAPTURE_CODE_TYPE_S 6
/** TWAI_ERR_WARNING_LIMIT_REG register
* TWAI error threshold configuration register.
*/
#define TWAI_ERR_WARNING_LIMIT_REG (DR_REG_TWAI_BASE + 0x34)
/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96;
* The threshold that trigger error warning interrupt when this interrupt is enabled.
* Software has R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_ERR_WARNING_LIMIT 0x000000FFU
#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S)
#define TWAI_ERR_WARNING_LIMIT_V 0x000000FFU
#define TWAI_ERR_WARNING_LIMIT_S 0
/** TWAI_RX_ERR_CNT_REG register
* Rx error counter register.
*/
#define TWAI_RX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x38)
/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
* The RX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_RX_ERR_CNT 0x000000FFU
#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S)
#define TWAI_RX_ERR_CNT_V 0x000000FFU
#define TWAI_RX_ERR_CNT_S 0
/** TWAI_TX_ERR_CNT_REG register
* Tx error counter register.
*/
#define TWAI_TX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x3c)
/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
* The TX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_TX_ERR_CNT 0x000000FFU
#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S)
#define TWAI_TX_ERR_CNT_V 0x000000FFU
#define TWAI_TX_ERR_CNT_S 0
/** TWAI_DATA_0_REG register
* Data register 0.
*/
#define TWAI_DATA_0_REG (DR_REG_TWAI_BASE + 0x40)
/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 0 and when
* software initiate read operation, it is rx data register 0.
*/
#define TWAI_DATA_0 0x000000FFU
#define TWAI_DATA_0_M (TWAI_DATA_0_V << TWAI_DATA_0_S)
#define TWAI_DATA_0_V 0x000000FFU
#define TWAI_DATA_0_S 0
/** TWAI_DATA_1_REG register
* Data register 1.
*/
#define TWAI_DATA_1_REG (DR_REG_TWAI_BASE + 0x44)
/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 1 and when
* software initiate read operation, it is rx data register 1.
*/
#define TWAI_DATA_1 0x000000FFU
#define TWAI_DATA_1_M (TWAI_DATA_1_V << TWAI_DATA_1_S)
#define TWAI_DATA_1_V 0x000000FFU
#define TWAI_DATA_1_S 0
/** TWAI_DATA_2_REG register
* Data register 2.
*/
#define TWAI_DATA_2_REG (DR_REG_TWAI_BASE + 0x48)
/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 2 and when
* software initiate read operation, it is rx data register 2.
*/
#define TWAI_DATA_2 0x000000FFU
#define TWAI_DATA_2_M (TWAI_DATA_2_V << TWAI_DATA_2_S)
#define TWAI_DATA_2_V 0x000000FFU
#define TWAI_DATA_2_S 0
/** TWAI_DATA_3_REG register
* Data register 3.
*/
#define TWAI_DATA_3_REG (DR_REG_TWAI_BASE + 0x4c)
/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 3 and when
* software initiate read operation, it is rx data register 3.
*/
#define TWAI_DATA_3 0x000000FFU
#define TWAI_DATA_3_M (TWAI_DATA_3_V << TWAI_DATA_3_S)
#define TWAI_DATA_3_V 0x000000FFU
#define TWAI_DATA_3_S 0
/** TWAI_DATA_4_REG register
* Data register 4.
*/
#define TWAI_DATA_4_REG (DR_REG_TWAI_BASE + 0x50)
/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 4 and when
* software initiate read operation, it is rx data register 4.
*/
#define TWAI_DATA_4 0x000000FFU
#define TWAI_DATA_4_M (TWAI_DATA_4_V << TWAI_DATA_4_S)
#define TWAI_DATA_4_V 0x000000FFU
#define TWAI_DATA_4_S 0
/** TWAI_DATA_5_REG register
* Data register 5.
*/
#define TWAI_DATA_5_REG (DR_REG_TWAI_BASE + 0x54)
/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 5 and when
* software initiate read operation, it is rx data register 5.
*/
#define TWAI_DATA_5 0x000000FFU
#define TWAI_DATA_5_M (TWAI_DATA_5_V << TWAI_DATA_5_S)
#define TWAI_DATA_5_V 0x000000FFU
#define TWAI_DATA_5_S 0
/** TWAI_DATA_6_REG register
* Data register 6.
*/
#define TWAI_DATA_6_REG (DR_REG_TWAI_BASE + 0x58)
/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 6 and when
* software initiate read operation, it is rx data register 6.
*/
#define TWAI_DATA_6 0x000000FFU
#define TWAI_DATA_6_M (TWAI_DATA_6_V << TWAI_DATA_6_S)
#define TWAI_DATA_6_V 0x000000FFU
#define TWAI_DATA_6_S 0
/** TWAI_DATA_7_REG register
* Data register 7.
*/
#define TWAI_DATA_7_REG (DR_REG_TWAI_BASE + 0x5c)
/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 7 and when
* software initiate read operation, it is rx data register 7.
*/
#define TWAI_DATA_7 0x000000FFU
#define TWAI_DATA_7_M (TWAI_DATA_7_V << TWAI_DATA_7_S)
#define TWAI_DATA_7_V 0x000000FFU
#define TWAI_DATA_7_S 0
/** TWAI_DATA_8_REG register
* Data register 8.
*/
#define TWAI_DATA_8_REG (DR_REG_TWAI_BASE + 0x60)
/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 8 and when software initiate read operation, it
* is rx data register 8.
*/
#define TWAI_DATA_8 0x000000FFU
#define TWAI_DATA_8_M (TWAI_DATA_8_V << TWAI_DATA_8_S)
#define TWAI_DATA_8_V 0x000000FFU
#define TWAI_DATA_8_S 0
/** TWAI_DATA_9_REG register
* Data register 9.
*/
#define TWAI_DATA_9_REG (DR_REG_TWAI_BASE + 0x64)
/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 9 and when software initiate read operation, it
* is rx data register 9.
*/
#define TWAI_DATA_9 0x000000FFU
#define TWAI_DATA_9_M (TWAI_DATA_9_V << TWAI_DATA_9_S)
#define TWAI_DATA_9_V 0x000000FFU
#define TWAI_DATA_9_S 0
/** TWAI_DATA_10_REG register
* Data register 10.
*/
#define TWAI_DATA_10_REG (DR_REG_TWAI_BASE + 0x68)
/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 10 and when software initiate read operation, it
* is rx data register 10.
*/
#define TWAI_DATA_10 0x000000FFU
#define TWAI_DATA_10_M (TWAI_DATA_10_V << TWAI_DATA_10_S)
#define TWAI_DATA_10_V 0x000000FFU
#define TWAI_DATA_10_S 0
/** TWAI_DATA_11_REG register
* Data register 11.
*/
#define TWAI_DATA_11_REG (DR_REG_TWAI_BASE + 0x6c)
/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 11 and when software initiate read operation, it
* is rx data register 11.
*/
#define TWAI_DATA_11 0x000000FFU
#define TWAI_DATA_11_M (TWAI_DATA_11_V << TWAI_DATA_11_S)
#define TWAI_DATA_11_V 0x000000FFU
#define TWAI_DATA_11_S 0
/** TWAI_DATA_12_REG register
* Data register 12.
*/
#define TWAI_DATA_12_REG (DR_REG_TWAI_BASE + 0x70)
/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 12 and when software initiate read operation, it
* is rx data register 12.
*/
#define TWAI_DATA_12 0x000000FFU
#define TWAI_DATA_12_M (TWAI_DATA_12_V << TWAI_DATA_12_S)
#define TWAI_DATA_12_V 0x000000FFU
#define TWAI_DATA_12_S 0
/** TWAI_RX_MESSAGE_COUNTER_REG register
* Received message counter register.
*/
#define TWAI_RX_MESSAGE_COUNTER_REG (DR_REG_TWAI_BASE + 0x74)
/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0;
* Reflects the number of messages available within the RXFIFO. The value is
* incremented with each receive event and decremented by the release receive buffer
* command.
*/
#define TWAI_RX_MESSAGE_COUNTER 0x0000007FU
#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S)
#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007FU
#define TWAI_RX_MESSAGE_COUNTER_S 0
/** TWAI_CLOCK_DIVIDER_REG register
* Clock divider register.
*/
#define TWAI_CLOCK_DIVIDER_REG (DR_REG_TWAI_BASE + 0x7c)
/** TWAI_CD : R/W; bitpos: [7:0]; default: 0;
* These bits are used to define the frequency at the external CLKOUT pin.
*/
#define TWAI_CD 0x000000FFU
#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S)
#define TWAI_CD_V 0x000000FFU
#define TWAI_CD_S 0
/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0;
* 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
* R/W permission in reset mode and RO in operation mode.
*/
#define TWAI_CLOCK_OFF (BIT(8))
#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S)
#define TWAI_CLOCK_OFF_V 0x00000001U
#define TWAI_CLOCK_OFF_S 8
/** TWAI_SW_STANDBY_CFG_REG register
* Software configure standby pin directly.
*/
#define TWAI_SW_STANDBY_CFG_REG (DR_REG_TWAI_BASE + 0x80)
/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
* Enable standby pin.
*/
#define TWAI_SW_STANDBY_EN (BIT(0))
#define TWAI_SW_STANDBY_EN_M (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S)
#define TWAI_SW_STANDBY_EN_V 0x00000001U
#define TWAI_SW_STANDBY_EN_S 0
/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1;
* Clear standby pin.
*/
#define TWAI_SW_STANDBY_CLR (BIT(1))
#define TWAI_SW_STANDBY_CLR_M (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S)
#define TWAI_SW_STANDBY_CLR_V 0x00000001U
#define TWAI_SW_STANDBY_CLR_S 1
/** TWAI_HW_CFG_REG register
* Hardware configure standby pin.
*/
#define TWAI_HW_CFG_REG (DR_REG_TWAI_BASE + 0x84)
/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
* Enable function that hardware control standby pin.
*/
#define TWAI_HW_STANDBY_EN (BIT(0))
#define TWAI_HW_STANDBY_EN_M (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S)
#define TWAI_HW_STANDBY_EN_V 0x00000001U
#define TWAI_HW_STANDBY_EN_S 0
/** TWAI_HW_STANDBY_CNT_REG register
* Configure standby counter.
*/
#define TWAI_HW_STANDBY_CNT_REG (DR_REG_TWAI_BASE + 0x88)
/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
* is enabled.
*/
#define TWAI_STANDBY_WAIT_CNT 0xFFFFFFFFU
#define TWAI_STANDBY_WAIT_CNT_M (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S)
#define TWAI_STANDBY_WAIT_CNT_V 0xFFFFFFFFU
#define TWAI_STANDBY_WAIT_CNT_S 0
/** TWAI_IDLE_INTR_CNT_REG register
* Configure idle interrupt counter.
*/
#define TWAI_IDLE_INTR_CNT_REG (DR_REG_TWAI_BASE + 0x8c)
/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before triggering idle interrupt.
*/
#define TWAI_IDLE_INTR_CNT 0xFFFFFFFFU
#define TWAI_IDLE_INTR_CNT_M (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S)
#define TWAI_IDLE_INTR_CNT_V 0xFFFFFFFFU
#define TWAI_IDLE_INTR_CNT_S 0
/** TWAI_ECO_CFG_REG register
* ECO configuration register.
*/
#define TWAI_ECO_CFG_REG (DR_REG_TWAI_BASE + 0x90)
/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0;
* Enable eco module.
*/
#define TWAI_RDN_ENA (BIT(0))
#define TWAI_RDN_ENA_M (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S)
#define TWAI_RDN_ENA_V 0x00000001U
#define TWAI_RDN_ENA_S 0
/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1;
* Output of eco module.
*/
#define TWAI_RDN_RESULT (BIT(1))
#define TWAI_RDN_RESULT_M (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S)
#define TWAI_RDN_RESULT_V 0x00000001U
#define TWAI_RDN_RESULT_S 1
/** TWAI_TIMESTAMP_DATA_REG register
* Timestamp data register
*/
#define TWAI_TIMESTAMP_DATA_REG (DR_REG_TWAI_BASE + 0x94)
/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0;
* Data of timestamp of a CAN frame.
*/
#define TWAI_TIMESTAMP_DATA 0xFFFFFFFFU
#define TWAI_TIMESTAMP_DATA_M (TWAI_TIMESTAMP_DATA_V << TWAI_TIMESTAMP_DATA_S)
#define TWAI_TIMESTAMP_DATA_V 0xFFFFFFFFU
#define TWAI_TIMESTAMP_DATA_S 0
/** TWAI_TIMESTAMP_PRESCALER_REG register
* Timestamp configuration register
*/
#define TWAI_TIMESTAMP_PRESCALER_REG (DR_REG_TWAI_BASE + 0x98)
/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31;
* Configures the clock division number of timestamp counter.
*/
#define TWAI_TS_DIV_NUM 0x0000FFFFU
#define TWAI_TS_DIV_NUM_M (TWAI_TS_DIV_NUM_V << TWAI_TS_DIV_NUM_S)
#define TWAI_TS_DIV_NUM_V 0x0000FFFFU
#define TWAI_TS_DIV_NUM_S 0
/** TWAI_TIMESTAMP_CFG_REG register
* Timestamp configuration register
*/
#define TWAI_TIMESTAMP_CFG_REG (DR_REG_TWAI_BASE + 0x9c)
/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0;
* enable the timestamp collection function.
*/
#define TWAI_TS_ENABLE (BIT(0))
#define TWAI_TS_ENABLE_M (TWAI_TS_ENABLE_V << TWAI_TS_ENABLE_S)
#define TWAI_TS_ENABLE_V 0x00000001U
#define TWAI_TS_ENABLE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/include/soc/twai_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of mode register
* TWAI mode register.
*/
typedef union {
struct {
/** reset_mode : R/W; bitpos: [0]; default: 1;
* 1: reset, detection of a set reset mode bit results in aborting the current
* transmission/reception of a message and entering the reset mode. 0: normal, on the
* '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
* operating mode.
*/
uint32_t reset_mode:1;
/** listen_only_mode : R/W; bitpos: [1]; default: 0;
* 1: listen only, in this mode the TWAI controller would give no acknowledge to the
* TWAI-bus, even if a message is received successfully. The error counters are
* stopped at the current value. 0: normal.
*/
uint32_t listen_only_mode:1;
/** self_test_mode : R/W; bitpos: [2]; default: 0;
* 1: self test, in this mode a full node test is possible without any other active
* node on the bus using the self reception request command. The TWAI controller will
* perform a successful transmission, even if there is no acknowledge received. 0:
* normal, an acknowledge is required for successful transmission.
*/
uint32_t self_test_mode:1;
/** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
* 1:single, the single acceptance filter option is enabled (one filter with the
* length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
* (two filters, each with the length of 16 bit are active).
*/
uint32_t acceptance_filter_mode:1;
uint32_t reserved_4:28;
};
uint32_t val;
} twai_mode_reg_t;
/** Type of cmd register
* TWAI command register.
*/
typedef union {
struct {
/** tx_request : WO; bitpos: [0]; default: 0;
* 1: present, a message shall be transmitted. 0: absent
*/
uint32_t tx_request:1;
/** abort_tx : WO; bitpos: [1]; default: 0;
* 1: present, if not already in progress, a pending transmission request is
* cancelled. 0: absent
*/
uint32_t abort_tx:1;
/** release_buffer : WO; bitpos: [2]; default: 0;
* 1: released, the receive buffer, representing the message memory space in the
* RXFIFO is released. 0: no action
*/
uint32_t release_buffer:1;
/** clear_data_overrun : WO; bitpos: [3]; default: 0;
* 1: clear, the data overrun status bit is cleared. 0: no action.
*/
uint32_t clear_data_overrun:1;
/** self_rx_request : WO; bitpos: [4]; default: 0;
* 1: present, a message shall be transmitted and received simultaneously. 0: absent.
*/
uint32_t self_rx_request:1;
uint32_t reserved_5:27;
};
uint32_t val;
} twai_cmd_reg_t;
/** Type of bus_timing_0 register
* Bit timing configuration register 0.
*/
typedef union {
struct {
/** baud_presc : R/W; bitpos: [13:0]; default: 0;
* The period of the TWAI system clock is programmable and determines the individual
* bit timing. Software has R/W permission in reset mode and RO permission in
* operation mode.
*/
uint32_t baud_presc:14;
/** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
* The synchronization jump width defines the maximum number of clock cycles a bit
* period may be shortened or lengthened. Software has R/W permission in reset mode
* and RO in operation mode.
*/
uint32_t sync_jump_width:2;
uint32_t reserved_16:16;
};
uint32_t val;
} twai_bus_timing_0_reg_t;
/** Type of bus_timing_1 register
* Bit timing configuration register 1.
*/
typedef union {
struct {
/** time_segment1 : R/W; bitpos: [3:0]; default: 0;
* The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
*/
uint32_t time_segment1:4;
/** time_segment2 : R/W; bitpos: [6:4]; default: 0;
* The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
*/
uint32_t time_segment2:3;
/** time_sampling : R/W; bitpos: [7]; default: 0;
* 1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
* Software has R/W permission in reset mode and RO in operation mode.
*/
uint32_t time_sampling:1;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_bus_timing_1_reg_t;
/** Type of err_warning_limit register
* TWAI error threshold configuration register.
*/
typedef union {
struct {
/** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
* The threshold that trigger error warning interrupt when this interrupt is enabled.
* Software has R/W permission in reset mode and RO in operation mode.
*/
uint32_t err_warning_limit:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_err_warning_limit_reg_t;
/** Type of clock_divider register
* Clock divider register.
*/
typedef union {
struct {
/** cd : R/W; bitpos: [7:0]; default: 0;
* These bits are used to define the frequency at the external CLKOUT pin.
*/
uint32_t cd:8;
/** clock_off : R/W; bitpos: [8]; default: 0;
* 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
* R/W permission in reset mode and RO in operation mode.
*/
uint32_t clock_off:1;
uint32_t reserved_9:23;
};
uint32_t val;
} twai_clock_divider_reg_t;
/** Type of sw_standby_cfg register
* Software configure standby pin directly.
*/
typedef union {
struct {
/** sw_standby_en : R/W; bitpos: [0]; default: 0;
* Enable standby pin.
*/
uint32_t sw_standby_en:1;
/** sw_standby_clr : R/W; bitpos: [1]; default: 1;
* Clear standby pin.
*/
uint32_t sw_standby_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} twai_sw_standby_cfg_reg_t;
/** Type of hw_cfg register
* Hardware configure standby pin.
*/
typedef union {
struct {
/** hw_standby_en : R/W; bitpos: [0]; default: 0;
* Enable function that hardware control standby pin.
*/
uint32_t hw_standby_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} twai_hw_cfg_reg_t;
/** Type of hw_standby_cnt register
* Configure standby counter.
*/
typedef union {
struct {
/** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
* is enabled.
*/
uint32_t standby_wait_cnt:32;
};
uint32_t val;
} twai_hw_standby_cnt_reg_t;
/** Type of idle_intr_cnt register
* Configure idle interrupt counter.
*/
typedef union {
struct {
/** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before triggering idle interrupt.
*/
uint32_t idle_intr_cnt:32;
};
uint32_t val;
} twai_idle_intr_cnt_reg_t;
/** Type of eco_cfg register
* ECO configuration register.
*/
typedef union {
struct {
/** rdn_ena : R/W; bitpos: [0]; default: 0;
* Enable eco module.
*/
uint32_t rdn_ena:1;
/** rdn_result : RO; bitpos: [1]; default: 1;
* Output of eco module.
*/
uint32_t rdn_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} twai_eco_cfg_reg_t;
/** Group: Status Registers */
/** Type of status register
* TWAI status register.
*/
typedef union {
struct {
/** status_receive_buffer : RO; bitpos: [0]; default: 0;
* 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
* message is available
*/
uint32_t status_receive_buffer:1;
/** status_overrun : RO; bitpos: [1]; default: 0;
* 1: overrun, a message was lost because there was not enough space for that message
* in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
* overrun command was given
*/
uint32_t status_overrun:1;
/** status_transmit_buffer : RO; bitpos: [2]; default: 0;
* 1: released, the CPU may write a message into the transmit buffer. 0: locked, the
* CPU cannot access the transmit buffer, a message is either waiting for transmission
* or is in the process of being transmitted
*/
uint32_t status_transmit_buffer:1;
/** status_transmission_complete : RO; bitpos: [3]; default: 0;
* 1: complete, last requested transmission has been successfully completed. 0:
* incomplete, previously requested transmission is not yet completed
*/
uint32_t status_transmission_complete:1;
/** status_receive : RO; bitpos: [4]; default: 0;
* 1: receive, the TWAI controller is receiving a message. 0: idle
*/
uint32_t status_receive:1;
/** status_transmit : RO; bitpos: [5]; default: 0;
* 1: transmit, the TWAI controller is transmitting a message. 0: idle
*/
uint32_t status_transmit:1;
/** status_err : RO; bitpos: [6]; default: 0;
* 1: error, at least one of the error counters has reached or exceeded the CPU
* warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
* counters are below the warning limit
*/
uint32_t status_err:1;
/** status_node_bus_off : RO; bitpos: [7]; default: 0;
* 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
* TWAI controller is involved in bus activities
*/
uint32_t status_node_bus_off:1;
/** status_miss : RO; bitpos: [8]; default: 0;
* 1: current message is destroyed because of FIFO overflow.
*/
uint32_t status_miss:1;
uint32_t reserved_9:23;
};
uint32_t val;
} twai_status_reg_t;
/** Type of arb_lost_cap register
* TWAI arbiter lost capture register.
*/
typedef union {
struct {
/** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
* This register contains information about the bit position of losing arbitration.
*/
uint32_t arbitration_lost_capture:5;
uint32_t reserved_5:27;
};
uint32_t val;
} twai_arb_lost_cap_reg_t;
/** Type of err_code_cap register
* TWAI error info capture register.
*/
typedef union {
struct {
/** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
* This register contains information about the location of errors on the bus.
*/
uint32_t err_capture_code_segment:5;
/** err_capture_code_direction : RO; bitpos: [5]; default: 0;
* 1: RX, error occurred during reception. 0: TX, error occurred during transmission.
*/
uint32_t err_capture_code_direction:1;
/** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
* 00: bit error. 01: form error. 10:stuff error. 11:other type of error.
*/
uint32_t err_capture_code_type:2;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_err_code_cap_reg_t;
/** Type of rx_err_cnt register
* Rx error counter register.
*/
typedef union {
struct {
/** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
* The RX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
*/
uint32_t rx_err_cnt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_rx_err_cnt_reg_t;
/** Type of tx_err_cnt register
* Tx error counter register.
*/
typedef union {
struct {
/** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
* The TX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
*/
uint32_t tx_err_cnt:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_tx_err_cnt_reg_t;
/** Type of rx_message_counter register
* Received message counter register.
*/
typedef union {
struct {
/** rx_message_counter : RO; bitpos: [6:0]; default: 0;
* Reflects the number of messages available within the RXFIFO. The value is
* incremented with each receive event and decremented by the release receive buffer
* command.
*/
uint32_t rx_message_counter:7;
uint32_t reserved_7:25;
};
uint32_t val;
} twai_rx_message_counter_reg_t;
/** Group: Interrupt Registers */
/** Type of interrupt register
* Interrupt signals' register.
*/
typedef union {
struct {
/** receive_int_st : RO; bitpos: [0]; default: 0;
* 1: this bit is set while the receive FIFO is not empty and the RIE bit is set
* within the interrupt enable register. 0: reset
*/
uint32_t receive_int_st:1;
/** transmit_int_st : RO; bitpos: [1]; default: 0;
* 1: this bit is set whenever the transmit buffer status changes from '0-to-1'
* (released) and the TIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t transmit_int_st:1;
/** err_warning_int_st : RO; bitpos: [2]; default: 0;
* 1: this bit is set on every change (set and clear) of either the error status or
* bus status bits and the EIE bit is set within the interrupt enable register. 0:
* reset
*/
uint32_t err_warning_int_st:1;
/** data_overrun_int_st : RO; bitpos: [3]; default: 0;
* 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
* DOIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t data_overrun_int_st:1;
/** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
* 1: this bit is set then the timestamp counter reaches the maximum value and
* overflow.
*/
uint32_t ts_counter_ovfl_int_st:1;
/** err_passive_int_st : RO; bitpos: [5]; default: 0;
* 1: this bit is set whenever the TWAI controller has reached the error passive
* status (at least one error counter exceeds the protocol-defined level of 127) or if
* the TWAI controller is in the error passive status and enters the error active
* status again and the EPIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t err_passive_int_st:1;
/** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
* 1: this bit is set when the TWAI controller lost the arbitration and becomes a
* receiver and the ALIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t arbitration_lost_int_st:1;
/** bus_err_int_st : RO; bitpos: [7]; default: 0;
* 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
* the BEIE bit is set within the interrupt enable register. 0: reset
*/
uint32_t bus_err_int_st:1;
/** idle_int_st : RO; bitpos: [8]; default: 0;
* 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
* this interrupt enable bit is set within the interrupt enable register. 0: reset
*/
uint32_t idle_int_st:1;
uint32_t reserved_9:23;
};
uint32_t val;
} twai_interrupt_reg_t;
/** Type of interrupt_enable register
* Interrupt enable register.
*/
typedef union {
struct {
/** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
* 1: enabled, when the receive buffer status is 'full' the TWAI controller requests
* the respective interrupt. 0: disable
*/
uint32_t ext_receive_int_ena:1;
/** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
* 1: enabled, when a message has been successfully transmitted or the transmit buffer
* is accessible again (e.g. after an abort transmission command), the TWAI controller
* requests the respective interrupt. 0: disable
*/
uint32_t ext_transmit_int_ena:1;
/** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
* 1: enabled, if the error or bus status change (see status register. Table 14), the
* TWAI controllerrequests the respective interrupt. 0: disable
*/
uint32_t ext_err_warning_int_ena:1;
/** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
* 1: enabled, if the data overrun status bit is set (see status register. Table 14),
* the TWAI controllerrequests the respective interrupt. 0: disable
*/
uint32_t ext_data_overrun_int_ena:1;
/** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
* enable the timestamp counter overflow interrupt request.
*/
uint32_t ts_counter_ovfl_int_ena:1;
/** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
* 1: enabled, if the error status of the TWAI controller changes from error active to
* error passive or vice versa, the respective interrupt is requested. 0: disable
*/
uint32_t err_passive_int_ena:1;
/** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
* 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
* is requested. 0: disable
*/
uint32_t arbitration_lost_int_ena:1;
/** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
* 1: enabled, if an bus error has been detected, the TWAI controller requests the
* respective interrupt. 0: disable
*/
uint32_t bus_err_int_ena:1;
/** idle_int_ena : RO; bitpos: [8]; default: 0;
* 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
* respective interrupt. 0: disable
*/
uint32_t idle_int_ena:1;
uint32_t reserved_9:23;
};
uint32_t val;
} twai_interrupt_enable_reg_t;
/** Group: Data Registers */
/** Type of data_0 register
* Data register 0.
*/
typedef union {
struct {
/** data_0 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 0 and when
* software initiate read operation, it is rx data register 0.
*/
uint32_t data_0:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_0_reg_t;
/** Type of data_1 register
* Data register 1.
*/
typedef union {
struct {
/** data_1 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 1 and when
* software initiate read operation, it is rx data register 1.
*/
uint32_t data_1:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_1_reg_t;
/** Type of data_2 register
* Data register 2.
*/
typedef union {
struct {
/** data_2 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 2 and when
* software initiate read operation, it is rx data register 2.
*/
uint32_t data_2:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_2_reg_t;
/** Type of data_3 register
* Data register 3.
*/
typedef union {
struct {
/** data_3 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 3 and when
* software initiate read operation, it is rx data register 3.
*/
uint32_t data_3:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_3_reg_t;
/** Type of data_4 register
* Data register 4.
*/
typedef union {
struct {
/** data_4 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 4 and when
* software initiate read operation, it is rx data register 4.
*/
uint32_t data_4:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_4_reg_t;
/** Type of data_5 register
* Data register 5.
*/
typedef union {
struct {
/** data_5 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 5 and when
* software initiate read operation, it is rx data register 5.
*/
uint32_t data_5:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_5_reg_t;
/** Type of data_6 register
* Data register 6.
*/
typedef union {
struct {
/** data_6 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 6 and when
* software initiate read operation, it is rx data register 6.
*/
uint32_t data_6:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_6_reg_t;
/** Type of data_7 register
* Data register 7.
*/
typedef union {
struct {
/** data_7 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 7 and when
* software initiate read operation, it is rx data register 7.
*/
uint32_t data_7:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_7_reg_t;
/** Type of data_8 register
* Data register 8.
*/
typedef union {
struct {
/** data_8 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 8 and when software initiate read operation, it
* is rx data register 8.
*/
uint32_t data_8:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_8_reg_t;
/** Type of data_9 register
* Data register 9.
*/
typedef union {
struct {
/** data_9 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 9 and when software initiate read operation, it
* is rx data register 9.
*/
uint32_t data_9:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_9_reg_t;
/** Type of data_10 register
* Data register 10.
*/
typedef union {
struct {
/** data_10 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 10 and when software initiate read operation, it
* is rx data register 10.
*/
uint32_t data_10:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_10_reg_t;
/** Type of data_11 register
* Data register 11.
*/
typedef union {
struct {
/** data_11 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 11 and when software initiate read operation, it
* is rx data register 11.
*/
uint32_t data_11:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_11_reg_t;
/** Type of data_12 register
* Data register 12.
*/
typedef union {
struct {
/** data_12 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 12 and when software initiate read operation, it
* is rx data register 12.
*/
uint32_t data_12:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_12_reg_t;
/** Group: Timestamp Register */
/** Type of timestamp_data register
* Timestamp data register
*/
typedef union {
struct {
/** timestamp_data : RO; bitpos: [31:0]; default: 0;
* Data of timestamp of a CAN frame.
*/
uint32_t timestamp_data:32;
};
uint32_t val;
} twai_timestamp_data_reg_t;
/** Type of timestamp_prescaler register
* Timestamp configuration register
*/
typedef union {
struct {
/** ts_div_num : R/W; bitpos: [15:0]; default: 31;
* Configures the clock division number of timestamp counter.
*/
uint32_t ts_div_num:16;
uint32_t reserved_16:16;
};
uint32_t val;
} twai_timestamp_prescaler_reg_t;
/** Type of timestamp_cfg register
* Timestamp configuration register
*/
typedef union {
struct {
/** ts_enable : R/W; bitpos: [0]; default: 0;
* enable the timestamp collection function.
*/
uint32_t ts_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} twai_timestamp_cfg_reg_t;
typedef struct {
volatile twai_mode_reg_t mode;
volatile twai_cmd_reg_t cmd;
volatile twai_status_reg_t status;
volatile twai_interrupt_reg_t interrupt;
volatile twai_interrupt_enable_reg_t interrupt_enable;
uint32_t reserved_014;
volatile twai_bus_timing_0_reg_t bus_timing_0;
volatile twai_bus_timing_1_reg_t bus_timing_1;
uint32_t reserved_020[3];
volatile twai_arb_lost_cap_reg_t arb_lost_cap;
volatile twai_err_code_cap_reg_t err_code_cap;
volatile twai_err_warning_limit_reg_t err_warning_limit;
volatile twai_rx_err_cnt_reg_t rx_err_cnt;
volatile twai_tx_err_cnt_reg_t tx_err_cnt;
volatile twai_data_0_reg_t data_0;
volatile twai_data_1_reg_t data_1;
volatile twai_data_2_reg_t data_2;
volatile twai_data_3_reg_t data_3;
volatile twai_data_4_reg_t data_4;
volatile twai_data_5_reg_t data_5;
volatile twai_data_6_reg_t data_6;
volatile twai_data_7_reg_t data_7;
volatile twai_data_8_reg_t data_8;
volatile twai_data_9_reg_t data_9;
volatile twai_data_10_reg_t data_10;
volatile twai_data_11_reg_t data_11;
volatile twai_data_12_reg_t data_12;
volatile twai_rx_message_counter_reg_t rx_message_counter;
uint32_t reserved_078;
volatile twai_clock_divider_reg_t clock_divider;
volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
volatile twai_hw_cfg_reg_t hw_cfg;
volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
volatile twai_eco_cfg_reg_t eco_cfg;
volatile twai_timestamp_data_reg_t timestamp_data;
volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
volatile twai_timestamp_cfg_reg_t timestamp_cfg;
} twai_dev_t;
extern twai_dev_t TWAI0;
extern twai_dev_t TWAI1;
#ifndef __cplusplus
_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** USB_OTG_MISC_CLK_EN0_REG register
* Reserved
*/
#define USB_OTG_MISC_CLK_EN0_REG (DR_REG_USB_OTG_MISC_BASE + 0x0)
/** USB_OTG_MISC_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* Reserved
*/
#define USB_OTG_MISC_REG_CLK_EN (BIT(0))
#define USB_OTG_MISC_REG_CLK_EN_M (USB_OTG_MISC_REG_CLK_EN_V << USB_OTG_MISC_REG_CLK_EN_S)
#define USB_OTG_MISC_REG_CLK_EN_V 0x00000001U
#define USB_OTG_MISC_REG_CLK_EN_S 0
/** USB_OTG_MISC_DATE0_REG register
* Reserved
*/
#define USB_OTG_MISC_DATE0_REG (DR_REG_USB_OTG_MISC_BASE + 0x4)
/** USB_OTG_MISC_REG_DATE : R/W; bitpos: [31:0]; default: 23050900;
* Reserved
*/
#define USB_OTG_MISC_REG_DATE 0xFFFFFFFFU
#define USB_OTG_MISC_REG_DATE_M (USB_OTG_MISC_REG_DATE_V << USB_OTG_MISC_REG_DATE_S)
#define USB_OTG_MISC_REG_DATE_V 0xFFFFFFFFU
#define USB_OTG_MISC_REG_DATE_S 0
/** USB_OTG_MISC_CORE_AHB_CTRL0_REG register
* USB OTG core AHB bus control.
*/
#define USB_OTG_MISC_CORE_AHB_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x8)
/** USB_OTG_MISC_REG_CORE_S_HBIGENDIAN : R/W; bitpos: [0]; default: 0;
* USB OTG core AHB slave big endian mode. 1'b0: Little, 1'b1: Big.
*/
#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN (BIT(0))
#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_M (USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_V << USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_S)
#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_V 0x00000001U
#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_S 0
/** USB_OTG_MISC_REG_CORE_M_HBIGENDIAN : R/W; bitpos: [1]; default: 0;
* USB OTG core AHB master big endian mode. 1'b0: Little, 1'b1: Big.
*/
#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN (BIT(1))
#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_M (USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_V << USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_S)
#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_V 0x00000001U
#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_S 1
/** USB_OTG_MISC_DFIFO_CTRL0_REG register
* dfifo control.
*/
#define USB_OTG_MISC_DFIFO_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0xc)
/** USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
* enable dfifo hclk always on.
*/
#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON (BIT(0))
#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_M (USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_V << USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_S)
#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_V 0x00000001U
#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_S 0
/** USB_OTG_MISC_CORE_SS_CTRL0_REG register
* USB OTG core simulation scale control.
*/
#define USB_OTG_MISC_CORE_SS_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x10)
/** USB_OTG_MISC_REG_SS_SCALEDOWN_MODE : R/W; bitpos: [1:0]; default: 0;
* USB OTG 2.0 Core Simulation Scale Down Mode, Scale-down timing values, resulting in
* <faster> simulations.
*/
#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE 0x00000003U
#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_M (USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_V << USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_S)
#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_V 0x00000003U
#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_S 0
/** USB_OTG_MISC_PHY_CTRL0_REG register
* USB PHY auxiliary control.
*/
#define USB_OTG_MISC_PHY_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x14)
/** USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE : R/W; bitpos: [0]; default: 0;
* Use software to override phy_pll_en.
*/
#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE (BIT(0))
#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_M (USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_V << USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_S)
#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_S 0
/** USB_OTG_MISC_REG_PHY_PLL_EN : R/W; bitpos: [1]; default: 0;
* Software phy_pll_en.
*/
#define USB_OTG_MISC_REG_PHY_PLL_EN (BIT(1))
#define USB_OTG_MISC_REG_PHY_PLL_EN_M (USB_OTG_MISC_REG_PHY_PLL_EN_V << USB_OTG_MISC_REG_PHY_PLL_EN_S)
#define USB_OTG_MISC_REG_PHY_PLL_EN_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_PLL_EN_S 1
/** USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE : R/W; bitpos: [2]; default: 0;
* Use software to override phy_suspendm.
*/
#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE (BIT(2))
#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_M (USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_V << USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_S)
#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_S 2
/** USB_OTG_MISC_REG_PHY_SUSPENDM : R/W; bitpos: [3]; default: 0;
* Software phy_suspendm.
*/
#define USB_OTG_MISC_REG_PHY_SUSPENDM (BIT(3))
#define USB_OTG_MISC_REG_PHY_SUSPENDM_M (USB_OTG_MISC_REG_PHY_SUSPENDM_V << USB_OTG_MISC_REG_PHY_SUSPENDM_S)
#define USB_OTG_MISC_REG_PHY_SUSPENDM_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_SUSPENDM_S 3
/** USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE : R/W; bitpos: [4]; default: 0;
* Use software to override phy_reset_n.
*/
#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE (BIT(4))
#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_M (USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_V << USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_S)
#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_S 4
/** USB_OTG_MISC_REG_PHY_RESET_N : R/W; bitpos: [5]; default: 0;
* Software phy_reset_n.
*/
#define USB_OTG_MISC_REG_PHY_RESET_N (BIT(5))
#define USB_OTG_MISC_REG_PHY_RESET_N_M (USB_OTG_MISC_REG_PHY_RESET_N_V << USB_OTG_MISC_REG_PHY_RESET_N_S)
#define USB_OTG_MISC_REG_PHY_RESET_N_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_RESET_N_S 5
/** USB_OTG_MISC_REG_PHY_BIST_OK : RO; bitpos: [6]; default: 0;
* USB PHY self test done.
*/
#define USB_OTG_MISC_REG_PHY_BIST_OK (BIT(6))
#define USB_OTG_MISC_REG_PHY_BIST_OK_M (USB_OTG_MISC_REG_PHY_BIST_OK_V << USB_OTG_MISC_REG_PHY_BIST_OK_S)
#define USB_OTG_MISC_REG_PHY_BIST_OK_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_BIST_OK_S 6
/** USB_OTG_MISC_REG_PHY_OTG_SUSPENDM : R/W; bitpos: [7]; default: 0;
* USB PHY otg_suspendm.
*/
#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM (BIT(7))
#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_M (USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_V << USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_S)
#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_S 7
/** USB_OTG_MISC_REG_PHY_REFCLK_MODE : R/W; bitpos: [8]; default: 1;
* Select USB PHY refclk mode. 0: refclk is 25MHz, 1: refclk is 12MHz.
*/
#define USB_OTG_MISC_REG_PHY_REFCLK_MODE (BIT(8))
#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_M (USB_OTG_MISC_REG_PHY_REFCLK_MODE_V << USB_OTG_MISC_REG_PHY_REFCLK_MODE_S)
#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_S 8
/** USB_OTG_MISC_REG_PHY_SELF_TEST : R/W; bitpos: [9]; default: 0;
* USB PHY self test enable.
*/
#define USB_OTG_MISC_REG_PHY_SELF_TEST (BIT(9))
#define USB_OTG_MISC_REG_PHY_SELF_TEST_M (USB_OTG_MISC_REG_PHY_SELF_TEST_V << USB_OTG_MISC_REG_PHY_SELF_TEST_S)
#define USB_OTG_MISC_REG_PHY_SELF_TEST_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_SELF_TEST_S 9
/** USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE : R/W; bitpos: [10]; default: 0;
* USB PHY tx bitstuff enable.
*/
#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE (BIT(10))
#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_M (USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_V << USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_S)
#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_S 10
/** USB_OTG_MISC_PHY_DBG_PROBE0_REG register
* USB PHY debug probe register.
*/
#define USB_OTG_MISC_PHY_DBG_PROBE0_REG (DR_REG_USB_OTG_MISC_BASE + 0x18)
/** USB_OTG_MISC_REG_PHY_DBG_LINE_STATE : RO; bitpos: [1:0]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE 0x00000003U
#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_M (USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_V << USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_S)
#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_V 0x00000003U
#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_S 0
/** USB_OTG_MISC_REG_PHY_DBG_RX_VALID : RO; bitpos: [2]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID (BIT(2))
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_M (USB_OTG_MISC_REG_PHY_DBG_RX_VALID_V << USB_OTG_MISC_REG_PHY_DBG_RX_VALID_S)
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_S 2
/** USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH : RO; bitpos: [3]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH (BIT(3))
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_M (USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_V << USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_S)
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_S 3
/** USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE : RO; bitpos: [4]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE (BIT(4))
#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_M (USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_V << USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_S)
#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_S 4
/** USB_OTG_MISC_REG_PHY_DBG_RX_ERROR : RO; bitpos: [5]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR (BIT(5))
#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_M (USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_V << USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_S)
#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_S 5
/** USB_OTG_MISC_REG_PHY_DBG_TX_READY : RO; bitpos: [6]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_TX_READY (BIT(6))
#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_M (USB_OTG_MISC_REG_PHY_DBG_TX_READY_V << USB_OTG_MISC_REG_PHY_DBG_TX_READY_S)
#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_S 6
/** USB_OTG_MISC_PHY_INT_RAW_REG register
* Interrupt raw of USB PHY interrupt register.
*/
#define USB_OTG_MISC_PHY_INT_RAW_REG (DR_REG_USB_OTG_MISC_BASE + 0x1c)
/** USB_OTG_MISC_REG_IDDIG_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* Interrupt raw of reg_iddig_int_st
*/
#define USB_OTG_MISC_REG_IDDIG_INT_RAW (BIT(0))
#define USB_OTG_MISC_REG_IDDIG_INT_RAW_M (USB_OTG_MISC_REG_IDDIG_INT_RAW_V << USB_OTG_MISC_REG_IDDIG_INT_RAW_S)
#define USB_OTG_MISC_REG_IDDIG_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_IDDIG_INT_RAW_S 0
/** USB_OTG_MISC_REG_VBUS_VALID_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* Interrupt raw of reg_vbus_valid_int_st
*/
#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW (BIT(1))
#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_M (USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_V << USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_S)
#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_S 1
/** USB_OTG_MISC_REG_SESSVALID_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* Interrupt raw of reg_sessvalid_int_st
*/
#define USB_OTG_MISC_REG_SESSVALID_INT_RAW (BIT(2))
#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_M (USB_OTG_MISC_REG_SESSVALID_INT_RAW_V << USB_OTG_MISC_REG_SESSVALID_INT_RAW_S)
#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_S 2
/** USB_OTG_MISC_REG_SESSEND_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
* Interrupt raw of reg_sessend_int_st
*/
#define USB_OTG_MISC_REG_SESSEND_INT_RAW (BIT(3))
#define USB_OTG_MISC_REG_SESSEND_INT_RAW_M (USB_OTG_MISC_REG_SESSEND_INT_RAW_V << USB_OTG_MISC_REG_SESSEND_INT_RAW_S)
#define USB_OTG_MISC_REG_SESSEND_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_SESSEND_INT_RAW_S 3
/** USB_OTG_MISC_REG_BVALID_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
* Interrupt raw of reg_bvalid_int_st
*/
#define USB_OTG_MISC_REG_BVALID_INT_RAW (BIT(4))
#define USB_OTG_MISC_REG_BVALID_INT_RAW_M (USB_OTG_MISC_REG_BVALID_INT_RAW_V << USB_OTG_MISC_REG_BVALID_INT_RAW_S)
#define USB_OTG_MISC_REG_BVALID_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_BVALID_INT_RAW_S 4
/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
* Interrupt raw of reg_host_disconnect_int_st
*/
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW (BIT(5))
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_S)
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_S 5
/** USB_OTG_MISC_PHY_INT_CLR_REG register
* Interrupt clear of USB PHY interrupt register.
*/
#define USB_OTG_MISC_PHY_INT_CLR_REG (DR_REG_USB_OTG_MISC_BASE + 0x20)
/** USB_OTG_MISC_REG_IDDIG_INT_CLR : WT; bitpos: [0]; default: 0;
* Interrupt clear of reg_iddig_int_st
*/
#define USB_OTG_MISC_REG_IDDIG_INT_CLR (BIT(0))
#define USB_OTG_MISC_REG_IDDIG_INT_CLR_M (USB_OTG_MISC_REG_IDDIG_INT_CLR_V << USB_OTG_MISC_REG_IDDIG_INT_CLR_S)
#define USB_OTG_MISC_REG_IDDIG_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_IDDIG_INT_CLR_S 0
/** USB_OTG_MISC_REG_VBUS_VALID_INT_CLR : WT; bitpos: [1]; default: 0;
* Interrupt clear of reg_vbus_valid_int_st
*/
#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR (BIT(1))
#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_M (USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_V << USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_S)
#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_S 1
/** USB_OTG_MISC_REG_SESSVALID_INT_CLR : WT; bitpos: [2]; default: 0;
* Interrupt clear of reg_sessvalid_int_st
*/
#define USB_OTG_MISC_REG_SESSVALID_INT_CLR (BIT(2))
#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_M (USB_OTG_MISC_REG_SESSVALID_INT_CLR_V << USB_OTG_MISC_REG_SESSVALID_INT_CLR_S)
#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_S 2
/** USB_OTG_MISC_REG_SESSEND_INT_CLR : WT; bitpos: [3]; default: 0;
* Interrupt clear of reg_sessend_int_st
*/
#define USB_OTG_MISC_REG_SESSEND_INT_CLR (BIT(3))
#define USB_OTG_MISC_REG_SESSEND_INT_CLR_M (USB_OTG_MISC_REG_SESSEND_INT_CLR_V << USB_OTG_MISC_REG_SESSEND_INT_CLR_S)
#define USB_OTG_MISC_REG_SESSEND_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_SESSEND_INT_CLR_S 3
/** USB_OTG_MISC_REG_BVALID_INT_CLR : WT; bitpos: [4]; default: 0;
* Interrupt clear of reg_bvalid_int_st
*/
#define USB_OTG_MISC_REG_BVALID_INT_CLR (BIT(4))
#define USB_OTG_MISC_REG_BVALID_INT_CLR_M (USB_OTG_MISC_REG_BVALID_INT_CLR_V << USB_OTG_MISC_REG_BVALID_INT_CLR_S)
#define USB_OTG_MISC_REG_BVALID_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_BVALID_INT_CLR_S 4
/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR : WT; bitpos: [5]; default: 0;
* Interrupt clear of reg_host_disconnect_int_st
*/
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR (BIT(5))
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_S)
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_S 5
/** USB_OTG_MISC_PHY_INT_ENA_REG register
* Interrupt enable of USB PHY interrupt register.
*/
#define USB_OTG_MISC_PHY_INT_ENA_REG (DR_REG_USB_OTG_MISC_BASE + 0x24)
/** USB_OTG_MISC_REG_IDDIG_INT_ENA : R/W; bitpos: [0]; default: 0;
* Interrupt enable of reg_iddig_int_st
*/
#define USB_OTG_MISC_REG_IDDIG_INT_ENA (BIT(0))
#define USB_OTG_MISC_REG_IDDIG_INT_ENA_M (USB_OTG_MISC_REG_IDDIG_INT_ENA_V << USB_OTG_MISC_REG_IDDIG_INT_ENA_S)
#define USB_OTG_MISC_REG_IDDIG_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_IDDIG_INT_ENA_S 0
/** USB_OTG_MISC_REG_VBUS_VALID_INT_ENA : R/W; bitpos: [1]; default: 0;
* Interrupt enable of reg_vbus_valid_int_st
*/
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA (BIT(1))
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_M (USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_V << USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_S)
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_S 1
/** USB_OTG_MISC_REG_SESSVALID_INT_ENA : R/W; bitpos: [2]; default: 0;
* Interrupt enable of reg_sessvalid_int_st
*/
#define USB_OTG_MISC_REG_SESSVALID_INT_ENA (BIT(2))
#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_M (USB_OTG_MISC_REG_SESSVALID_INT_ENA_V << USB_OTG_MISC_REG_SESSVALID_INT_ENA_S)
#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_S 2
/** USB_OTG_MISC_REG_SESSEND_INT_ENA : R/W; bitpos: [3]; default: 0;
* Interrupt enable of reg_sessend_int_st
*/
#define USB_OTG_MISC_REG_SESSEND_INT_ENA (BIT(3))
#define USB_OTG_MISC_REG_SESSEND_INT_ENA_M (USB_OTG_MISC_REG_SESSEND_INT_ENA_V << USB_OTG_MISC_REG_SESSEND_INT_ENA_S)
#define USB_OTG_MISC_REG_SESSEND_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_SESSEND_INT_ENA_S 3
/** USB_OTG_MISC_REG_BVALID_INT_ENA : R/W; bitpos: [4]; default: 0;
* Interrupt enable of reg_bvalid_int_st
*/
#define USB_OTG_MISC_REG_BVALID_INT_ENA (BIT(4))
#define USB_OTG_MISC_REG_BVALID_INT_ENA_M (USB_OTG_MISC_REG_BVALID_INT_ENA_V << USB_OTG_MISC_REG_BVALID_INT_ENA_S)
#define USB_OTG_MISC_REG_BVALID_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_BVALID_INT_ENA_S 4
/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA : R/W; bitpos: [5]; default: 0;
* Interrupt enable of reg_host_disconnect_int_st
*/
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA (BIT(5))
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_S)
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_S 5
/** USB_OTG_MISC_PHY_INT_ST_REG register
* USB PHY interrupt register.
*/
#define USB_OTG_MISC_PHY_INT_ST_REG (DR_REG_USB_OTG_MISC_BASE + 0x28)
/** USB_OTG_MISC_REG_IDDIG_INT_ST : RO; bitpos: [0]; default: 0;
* indicates connected plug is a mini-A or mini-B.
*/
#define USB_OTG_MISC_REG_IDDIG_INT_ST (BIT(0))
#define USB_OTG_MISC_REG_IDDIG_INT_ST_M (USB_OTG_MISC_REG_IDDIG_INT_ST_V << USB_OTG_MISC_REG_IDDIG_INT_ST_S)
#define USB_OTG_MISC_REG_IDDIG_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_IDDIG_INT_ST_S 0
/** USB_OTG_MISC_REG_VBUS_VALID_INT_ST : RO; bitpos: [1]; default: 0;
* indicates if the voltage on VBUS is at a valid level for operation, 0: VBUS < 4.4V,
* 1: VBUS > 4.75V.
*/
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST (BIT(1))
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_M (USB_OTG_MISC_REG_VBUS_VALID_INT_ST_V << USB_OTG_MISC_REG_VBUS_VALID_INT_ST_S)
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_S 1
/** USB_OTG_MISC_REG_SESSVALID_INT_ST : RO; bitpos: [2]; default: 0;
* indicates if the session for an peripheral is valid, 0: VBUS < 0.8V, 1: VBUS > 2.0V.
*/
#define USB_OTG_MISC_REG_SESSVALID_INT_ST (BIT(2))
#define USB_OTG_MISC_REG_SESSVALID_INT_ST_M (USB_OTG_MISC_REG_SESSVALID_INT_ST_V << USB_OTG_MISC_REG_SESSVALID_INT_ST_S)
#define USB_OTG_MISC_REG_SESSVALID_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_SESSVALID_INT_ST_S 2
/** USB_OTG_MISC_REG_SESSEND_INT_ST : RO; bitpos: [3]; default: 0;
* indicates the voltage on VBUS, 1: VBUS < 0.2V, 0: VBUS > 0.8V.
*/
#define USB_OTG_MISC_REG_SESSEND_INT_ST (BIT(3))
#define USB_OTG_MISC_REG_SESSEND_INT_ST_M (USB_OTG_MISC_REG_SESSEND_INT_ST_V << USB_OTG_MISC_REG_SESSEND_INT_ST_S)
#define USB_OTG_MISC_REG_SESSEND_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_SESSEND_INT_ST_S 3
/** USB_OTG_MISC_REG_BVALID_INT_ST : RO; bitpos: [4]; default: 0;
* indicates the voltage on VBUS, 0: VBUS < 0.8V, 1: VBUS > 4.0V.
*/
#define USB_OTG_MISC_REG_BVALID_INT_ST (BIT(4))
#define USB_OTG_MISC_REG_BVALID_INT_ST_M (USB_OTG_MISC_REG_BVALID_INT_ST_V << USB_OTG_MISC_REG_BVALID_INT_ST_S)
#define USB_OTG_MISC_REG_BVALID_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_BVALID_INT_ST_S 4
/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST : RO; bitpos: [5]; default: 0;
* host disconnect.
*/
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST (BIT(5))
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_S)
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_S 5
/** USB_OTG_MISC_WAKEUP_CTRL0_REG register
* USB wakeup control.
*/
#define USB_OTG_MISC_WAKEUP_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x2c)
/** USB_OTG_MISC_REG_USB_IN_SUSPEND : R/W; bitpos: [0]; default: 0;
* indicate usb is in suspend state
*/
#define USB_OTG_MISC_REG_USB_IN_SUSPEND (BIT(0))
#define USB_OTG_MISC_REG_USB_IN_SUSPEND_M (USB_OTG_MISC_REG_USB_IN_SUSPEND_V << USB_OTG_MISC_REG_USB_IN_SUSPEND_S)
#define USB_OTG_MISC_REG_USB_IN_SUSPEND_V 0x00000001U
#define USB_OTG_MISC_REG_USB_IN_SUSPEND_S 0
/** USB_OTG_MISC_REG_USB_WKUP_CLR : WT; bitpos: [1]; default: 0;
* clear usb wakeup signals.
*/
#define USB_OTG_MISC_REG_USB_WKUP_CLR (BIT(1))
#define USB_OTG_MISC_REG_USB_WKUP_CLR_M (USB_OTG_MISC_REG_USB_WKUP_CLR_V << USB_OTG_MISC_REG_USB_WKUP_CLR_S)
#define USB_OTG_MISC_REG_USB_WKUP_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_USB_WKUP_CLR_S 1
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: clk_en */
/** Type of clk_en0 register
* Reserved
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_otg_misc_clk_en0_reg_t;
/** Group: date */
/** Type of date0 register
* Reserved
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [31:0]; default: 23050900;
* Reserved
*/
uint32_t reg_date:32;
};
uint32_t val;
} usb_otg_misc_date0_reg_t;
/** Group: core_ahb_ctrl */
/** Type of core_ahb_ctrl0 register
* USB OTG core AHB bus control.
*/
typedef union {
struct {
/** reg_core_s_hbigendian : R/W; bitpos: [0]; default: 0;
* USB OTG core AHB slave big endian mode. 1'b0: Little, 1'b1: Big.
*/
uint32_t reg_core_s_hbigendian:1;
/** reg_core_m_hbigendian : R/W; bitpos: [1]; default: 0;
* USB OTG core AHB master big endian mode. 1'b0: Little, 1'b1: Big.
*/
uint32_t reg_core_m_hbigendian:1;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_otg_misc_core_ahb_ctrl0_reg_t;
/** Group: dfifo_ctrl */
/** Type of dfifo_ctrl0 register
* dfifo control.
*/
typedef union {
struct {
/** reg_dfifo_hclk_force_on : R/W; bitpos: [0]; default: 0;
* enable dfifo hclk always on.
*/
uint32_t reg_dfifo_hclk_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_otg_misc_dfifo_ctrl0_reg_t;
/** Group: core_ss_ctrl */
/** Type of core_ss_ctrl0 register
* USB OTG core simulation scale control.
*/
typedef union {
struct {
/** reg_ss_scaledown_mode : R/W; bitpos: [1:0]; default: 0;
* USB OTG 2.0 Core Simulation Scale Down Mode, Scale-down timing values, resulting in
* <faster> simulations.
*/
uint32_t reg_ss_scaledown_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_otg_misc_core_ss_ctrl0_reg_t;
/** Group: phy_ctrl */
/** Type of phy_ctrl0 register
* USB PHY auxiliary control.
*/
typedef union {
struct {
/** reg_phy_pll_en_override : R/W; bitpos: [0]; default: 0;
* Use software to override phy_pll_en.
*/
uint32_t reg_phy_pll_en_override:1;
/** reg_phy_pll_en : R/W; bitpos: [1]; default: 0;
* Software phy_pll_en.
*/
uint32_t reg_phy_pll_en:1;
/** reg_phy_suspendm_override : R/W; bitpos: [2]; default: 0;
* Use software to override phy_suspendm.
*/
uint32_t reg_phy_suspendm_override:1;
/** reg_phy_suspendm : R/W; bitpos: [3]; default: 0;
* Software phy_suspendm.
*/
uint32_t reg_phy_suspendm:1;
/** reg_phy_reset_n_override : R/W; bitpos: [4]; default: 0;
* Use software to override phy_reset_n.
*/
uint32_t reg_phy_reset_n_override:1;
/** reg_phy_reset_n : R/W; bitpos: [5]; default: 0;
* Software phy_reset_n.
*/
uint32_t reg_phy_reset_n:1;
/** reg_phy_bist_ok : RO; bitpos: [6]; default: 0;
* USB PHY self test done.
*/
uint32_t reg_phy_bist_ok:1;
/** reg_phy_otg_suspendm : R/W; bitpos: [7]; default: 0;
* USB PHY otg_suspendm.
*/
uint32_t reg_phy_otg_suspendm:1;
/** reg_phy_refclk_mode : R/W; bitpos: [8]; default: 1;
* Select USB PHY refclk mode. 0: refclk is 25MHz, 1: refclk is 12MHz.
*/
uint32_t reg_phy_refclk_mode:1;
/** reg_phy_self_test : R/W; bitpos: [9]; default: 0;
* USB PHY self test enable.
*/
uint32_t reg_phy_self_test:1;
/** reg_phy_txbitstuff_enable : R/W; bitpos: [10]; default: 0;
* USB PHY tx bitstuff enable.
*/
uint32_t reg_phy_txbitstuff_enable:1;
uint32_t reserved_11:21;
};
uint32_t val;
} usb_otg_misc_phy_ctrl0_reg_t;
/** Group: phy_dbg_probe */
/** Type of phy_dbg_probe0 register
* USB PHY debug probe register.
*/
typedef union {
struct {
/** reg_phy_dbg_line_state : RO; bitpos: [1:0]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_line_state:2;
/** reg_phy_dbg_rx_valid : RO; bitpos: [2]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_rx_valid:1;
/** reg_phy_dbg_rx_validh : RO; bitpos: [3]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_rx_validh:1;
/** reg_phy_dbg_rx_active : RO; bitpos: [4]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_rx_active:1;
/** reg_phy_dbg_rx_error : RO; bitpos: [5]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_rx_error:1;
/** reg_phy_dbg_tx_ready : RO; bitpos: [6]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_tx_ready:1;
uint32_t reserved_7:25;
};
uint32_t val;
} usb_otg_misc_phy_dbg_probe0_reg_t;
/** Group: Interrupt */
/** Type of phy_int_raw register
* Interrupt raw of USB PHY interrupt register.
*/
typedef union {
struct {
/** reg_iddig_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* Interrupt raw of reg_iddig_int_st
*/
uint32_t reg_iddig_int_raw:1;
/** reg_vbus_valid_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* Interrupt raw of reg_vbus_valid_int_st
*/
uint32_t reg_vbus_valid_int_raw:1;
/** reg_sessvalid_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* Interrupt raw of reg_sessvalid_int_st
*/
uint32_t reg_sessvalid_int_raw:1;
/** reg_sessend_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
* Interrupt raw of reg_sessend_int_st
*/
uint32_t reg_sessend_int_raw:1;
/** reg_bvalid_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
* Interrupt raw of reg_bvalid_int_st
*/
uint32_t reg_bvalid_int_raw:1;
/** reg_host_disconnect_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
* Interrupt raw of reg_host_disconnect_int_st
*/
uint32_t reg_host_disconnect_int_raw:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_otg_misc_phy_int_raw_reg_t;
/** Type of phy_int_clr register
* Interrupt clear of USB PHY interrupt register.
*/
typedef union {
struct {
/** reg_iddig_int_clr : WT; bitpos: [0]; default: 0;
* Interrupt clear of reg_iddig_int_st
*/
uint32_t reg_iddig_int_clr:1;
/** reg_vbus_valid_int_clr : WT; bitpos: [1]; default: 0;
* Interrupt clear of reg_vbus_valid_int_st
*/
uint32_t reg_vbus_valid_int_clr:1;
/** reg_sessvalid_int_clr : WT; bitpos: [2]; default: 0;
* Interrupt clear of reg_sessvalid_int_st
*/
uint32_t reg_sessvalid_int_clr:1;
/** reg_sessend_int_clr : WT; bitpos: [3]; default: 0;
* Interrupt clear of reg_sessend_int_st
*/
uint32_t reg_sessend_int_clr:1;
/** reg_bvalid_int_clr : WT; bitpos: [4]; default: 0;
* Interrupt clear of reg_bvalid_int_st
*/
uint32_t reg_bvalid_int_clr:1;
/** reg_host_disconnect_int_clr : WT; bitpos: [5]; default: 0;
* Interrupt clear of reg_host_disconnect_int_st
*/
uint32_t reg_host_disconnect_int_clr:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_otg_misc_phy_int_clr_reg_t;
/** Type of phy_int_ena register
* Interrupt enable of USB PHY interrupt register.
*/
typedef union {
struct {
/** reg_iddig_int_ena : R/W; bitpos: [0]; default: 0;
* Interrupt enable of reg_iddig_int_st
*/
uint32_t reg_iddig_int_ena:1;
/** reg_vbus_valid_int_ena : R/W; bitpos: [1]; default: 0;
* Interrupt enable of reg_vbus_valid_int_st
*/
uint32_t reg_vbus_valid_int_ena:1;
/** reg_sessvalid_int_ena : R/W; bitpos: [2]; default: 0;
* Interrupt enable of reg_sessvalid_int_st
*/
uint32_t reg_sessvalid_int_ena:1;
/** reg_sessend_int_ena : R/W; bitpos: [3]; default: 0;
* Interrupt enable of reg_sessend_int_st
*/
uint32_t reg_sessend_int_ena:1;
/** reg_bvalid_int_ena : R/W; bitpos: [4]; default: 0;
* Interrupt enable of reg_bvalid_int_st
*/
uint32_t reg_bvalid_int_ena:1;
/** reg_host_disconnect_int_ena : R/W; bitpos: [5]; default: 0;
* Interrupt enable of reg_host_disconnect_int_st
*/
uint32_t reg_host_disconnect_int_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_otg_misc_phy_int_ena_reg_t;
/** Type of phy_int_st register
* USB PHY interrupt register.
*/
typedef union {
struct {
/** reg_iddig_int_st : RO; bitpos: [0]; default: 0;
* indicates connected plug is a mini-A or mini-B.
*/
uint32_t reg_iddig_int_st:1;
/** reg_vbus_valid_int_st : RO; bitpos: [1]; default: 0;
* indicates if the voltage on VBUS is at a valid level for operation, 0: VBUS < 4.4V,
* 1: VBUS > 4.75V.
*/
uint32_t reg_vbus_valid_int_st:1;
/** reg_sessvalid_int_st : RO; bitpos: [2]; default: 0;
* indicates if the session for an peripheral is valid, 0: VBUS < 0.8V, 1: VBUS > 2.0V.
*/
uint32_t reg_sessvalid_int_st:1;
/** reg_sessend_int_st : RO; bitpos: [3]; default: 0;
* indicates the voltage on VBUS, 1: VBUS < 0.2V, 0: VBUS > 0.8V.
*/
uint32_t reg_sessend_int_st:1;
/** reg_bvalid_int_st : RO; bitpos: [4]; default: 0;
* indicates the voltage on VBUS, 0: VBUS < 0.8V, 1: VBUS > 4.0V.
*/
uint32_t reg_bvalid_int_st:1;
/** reg_host_disconnect_int_st : RO; bitpos: [5]; default: 0;
* host disconnect.
*/
uint32_t reg_host_disconnect_int_st:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_otg_misc_phy_int_st_reg_t;
/** Group: wakeup_ctrl */
/** Type of wakeup_ctrl0 register
* USB wakeup control.
*/
typedef union {
struct {
/** reg_usb_in_suspend : R/W; bitpos: [0]; default: 0;
* indicate usb is in suspend state
*/
uint32_t reg_usb_in_suspend:1;
/** reg_usb_wkup_clr : WT; bitpos: [1]; default: 0;
* clear usb wakeup signals.
*/
uint32_t reg_usb_wkup_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_otg_misc_wakeup_ctrl0_reg_t;
typedef struct {
volatile usb_otg_misc_clk_en0_reg_t clk_en0;
volatile usb_otg_misc_date0_reg_t date0;
volatile usb_otg_misc_core_ahb_ctrl0_reg_t core_ahb_ctrl0;
volatile usb_otg_misc_dfifo_ctrl0_reg_t dfifo_ctrl0;
volatile usb_otg_misc_core_ss_ctrl0_reg_t core_ss_ctrl0;
volatile usb_otg_misc_phy_ctrl0_reg_t phy_ctrl0;
volatile usb_otg_misc_phy_dbg_probe0_reg_t phy_dbg_probe0;
volatile usb_otg_misc_phy_int_raw_reg_t phy_int_raw;
volatile usb_otg_misc_phy_int_clr_reg_t phy_int_clr;
volatile usb_otg_misc_phy_int_ena_reg_t phy_int_ena;
volatile usb_otg_misc_phy_int_st_reg_t phy_int_st;
volatile usb_otg_misc_wakeup_ctrl0_reg_t wakeup_ctrl0;
} usb_otg_misc_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(usb_otg_misc_dev_t) == 0x30, "Invalid size of usb_otg_misc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of ep1 register
* FIFO access for the CDC-ACM data IN and OUT endpoints.
*/
typedef union {
struct {
/** rdwr_byte : R/W; bitpos: [7:0]; default: 0;
* Write and read byte data to/from UART Tx/Rx FIFO through this field. When
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
* bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
uint32_t rdwr_byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
/** Type of ep1_conf register
* Configuration and control registers for the CDC-ACM FIFOs.
*/
typedef union {
struct {
/** wr_done : WT; bitpos: [0]; default: 0;
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
*/
uint32_t wr_done:1;
/** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
* 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
* USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
* USB Host.
*/
uint32_t serial_in_ep_data_free:1;
/** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
* 1'b1: Indicate there is data in UART Rx FIFO.
*/
uint32_t serial_out_ep_data_avail:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_ep1_conf_reg_t;
/** Type of conf0 register
* PHY hardware configuration.
*/
typedef union {
struct {
/** phy_sel : R/W; bitpos: [0]; default: 0;
* Select internal/external PHY
*/
uint32_t phy_sel:1;
/** exchg_pins_override : R/W; bitpos: [1]; default: 0;
* Enable software control USB D+ D- exchange
*/
uint32_t exchg_pins_override:1;
/** exchg_pins : R/W; bitpos: [2]; default: 0;
* USB D+ D- exchange
*/
uint32_t exchg_pins:1;
/** vrefh : R/W; bitpos: [4:3]; default: 0;
* Control single-end input high threshold,1.76V to 2V, step 80mV
*/
uint32_t vrefh:2;
/** vrefl : R/W; bitpos: [6:5]; default: 0;
* Control single-end input low threshold,0.8V to 1.04V, step 80mV
*/
uint32_t vrefl:2;
/** vref_override : R/W; bitpos: [7]; default: 0;
* Enable software control input threshold
*/
uint32_t vref_override:1;
/** pad_pull_override : R/W; bitpos: [8]; default: 0;
* Enable software control USB D+ D- pullup pulldown
*/
uint32_t pad_pull_override:1;
/** dp_pullup : R/W; bitpos: [9]; default: 1;
* Control USB D+ pull up.
*/
uint32_t dp_pullup:1;
/** dp_pulldown : R/W; bitpos: [10]; default: 0;
* Control USB D+ pull down.
*/
uint32_t dp_pulldown:1;
/** dm_pullup : R/W; bitpos: [11]; default: 0;
* Control USB D- pull up.
*/
uint32_t dm_pullup:1;
/** dm_pulldown : R/W; bitpos: [12]; default: 0;
* Control USB D- pull down.
*/
uint32_t dm_pulldown:1;
/** pullup_value : R/W; bitpos: [13]; default: 0;
* Control pull up value.
*/
uint32_t pullup_value:1;
/** usb_pad_enable : R/W; bitpos: [14]; default: 1;
* Enable USB pad function.
*/
uint32_t usb_pad_enable:1;
/** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
* Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
* disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
* through GPIO Matrix.
*/
uint32_t usb_jtag_bridge_en:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_conf0_reg_t;
/** Type of test register
* Registers used for debugging the PHY.
*/
typedef union {
struct {
/** test_enable : R/W; bitpos: [0]; default: 0;
* Enable test of the USB pad
*/
uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test
*/
uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in test
*/
uint32_t test_tx_dp:1;
/** test_tx_dm : R/W; bitpos: [3]; default: 0;
* USB D- tx value in test
*/
uint32_t test_tx_dm:1;
/** test_rx_rcv : RO; bitpos: [4]; default: 1;
* USB RCV value in test
*/
uint32_t test_rx_rcv:1;
/** test_rx_dp : RO; bitpos: [5]; default: 1;
* USB D+ rx value in test
*/
uint32_t test_rx_dp:1;
/** test_rx_dm : RO; bitpos: [6]; default: 0;
* USB D- rx value in test
*/
uint32_t test_rx_dm:1;
uint32_t reserved_7:25;
};
uint32_t val;
} usb_serial_jtag_test_reg_t;
/** Type of misc_conf register
* Clock enable control
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when application writes
* registers.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_misc_conf_reg_t;
/** Type of mem_conf register
* Memory power control
*/
typedef union {
struct {
/** usb_mem_pd : R/W; bitpos: [0]; default: 0;
* 1: power down usb memory.
*/
uint32_t usb_mem_pd:1;
/** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
* 1: Force clock on for usb memory.
*/
uint32_t usb_mem_clk_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_serial_jtag_mem_conf_reg_t;
/** Type of chip_rst register
* CDC-ACM chip reset control.
*/
typedef union {
struct {
/** rts : RO; bitpos: [0]; default: 0;
* 1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
*/
uint32_t rts:1;
/** dtr : RO; bitpos: [1]; default: 0;
* 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
*/
uint32_t dtr:1;
/** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
* Set this bit to disable chip reset from usb serial channel to reset chip.
*/
uint32_t usb_uart_chip_rst_dis:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_chip_rst_reg_t;
/** Type of get_line_code_w0 register
* W0 of GET_LINE_CODING command.
*/
typedef union {
struct {
/** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
* The value of dwDTERate set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t get_dw_dte_rate:32;
};
uint32_t val;
} usb_serial_jtag_get_line_code_w0_reg_t;
/** Type of get_line_code_w1 register
* W1 of GET_LINE_CODING command.
*/
typedef union {
struct {
/** get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
* The value of bCharFormat set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t get_bdata_bits:8;
/** get_bparity_type : R/W; bitpos: [15:8]; default: 0;
* The value of bParityTpye set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t get_bparity_type:8;
/** get_bchar_format : R/W; bitpos: [23:16]; default: 0;
* The value of bDataBits set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t get_bchar_format:8;
uint32_t reserved_24:8;
};
uint32_t val;
} usb_serial_jtag_get_line_code_w1_reg_t;
/** Type of config_update register
* Configuration registers' value update
*/
typedef union {
struct {
/** config_update : WT; bitpos: [0]; default: 0;
* Write 1 to this register would update the value of configure registers from APB
* clock domain to 48MHz clock domain.
*/
uint32_t config_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_config_update_reg_t;
/** Type of ser_afifo_config register
* Serial AFIFO configure register
*/
typedef union {
struct {
/** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
* Write 1 to reset CDC_ACM IN async FIFO write clock domain.
*/
uint32_t serial_in_afifo_reset_wr:1;
/** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
* Write 1 to reset CDC_ACM IN async FIFO read clock domain.
*/
uint32_t serial_in_afifo_reset_rd:1;
/** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
* Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
*/
uint32_t serial_out_afifo_reset_wr:1;
/** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
* Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
*/
uint32_t serial_out_afifo_reset_rd:1;
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
*/
uint32_t serial_out_afifo_rempty:1;
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
* CDC_ACM OUT IN async FIFO empty signal in write clock domain.
*/
uint32_t serial_in_afifo_wfull:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_serial_jtag_ser_afifo_config_reg_t;
/** Group: Interrupt Registers */
/** Type of int_raw register
* Interrupt raw status register.
*/
typedef union {
struct {
/** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when flush cmd is received for IN
* endpoint 2 of JTAG.
*/
uint32_t jtag_in_flush_int_raw:1;
/** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when SOF frame is received.
*/
uint32_t sof_int_raw:1;
/** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
* one packet.
*/
uint32_t serial_out_recv_pkt_int_raw:1;
/** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
* The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
*/
uint32_t serial_in_empty_int_raw:1;
/** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt bit turns to high level when pid error is detected.
*/
uint32_t pid_err_int_raw:1;
/** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt bit turns to high level when CRC5 error is detected.
*/
uint32_t crc5_err_int_raw:1;
/** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt bit turns to high level when CRC16 error is detected.
*/
uint32_t crc16_err_int_raw:1;
/** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The raw interrupt bit turns to high level when stuff error is detected.
*/
uint32_t stuff_err_int_raw:1;
/** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
* received.
*/
uint32_t in_token_rec_in_ep1_int_raw:1;
/** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The raw interrupt bit turns to high level when usb bus reset is detected.
*/
uint32_t usb_bus_reset_int_raw:1;
/** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
* zero palyload.
*/
uint32_t out_ep1_zero_payload_int_raw:1;
/** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
* zero palyload.
*/
uint32_t out_ep2_zero_payload_int_raw:1;
/** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The raw interrupt bit turns to high level when level of RTS from usb serial channel
* is changed.
*/
uint32_t rts_chg_int_raw:1;
/** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The raw interrupt bit turns to high level when level of DTR from usb serial channel
* is changed.
*/
uint32_t dtr_chg_int_raw:1;
/** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
* The raw interrupt bit turns to high level when level of GET LINE CODING request is
* received.
*/
uint32_t get_line_code_int_raw:1;
/** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
* The raw interrupt bit turns to high level when level of SET LINE CODING request is
* received.
*/
uint32_t set_line_code_int_raw:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_raw_reg_t;
/** Type of int_st register
* Interrupt status register.
*/
typedef union {
struct {
/** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t jtag_in_flush_int_st:1;
/** sof_int_st : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
uint32_t sof_int_st:1;
/** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
uint32_t serial_out_recv_pkt_int_st:1;
/** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_in_empty_int_st:1;
/** pid_err_int_st : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t pid_err_int_st:1;
/** crc5_err_int_st : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t crc5_err_int_st:1;
/** crc16_err_int_st : RO; bitpos: [6]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t crc16_err_int_st:1;
/** stuff_err_int_st : RO; bitpos: [7]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t stuff_err_int_st:1;
/** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
uint32_t in_token_rec_in_ep1_int_st:1;
/** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t usb_bus_reset_int_st:1;
/** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
uint32_t out_ep1_zero_payload_int_st:1;
/** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
uint32_t out_ep2_zero_payload_int_st:1;
/** rts_chg_int_st : RO; bitpos: [12]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t rts_chg_int_st:1;
/** dtr_chg_int_st : RO; bitpos: [13]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t dtr_chg_int_st:1;
/** get_line_code_int_st : RO; bitpos: [14]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t get_line_code_int_st:1;
/** set_line_code_int_st : RO; bitpos: [15]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t set_line_code_int_st:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_st_reg_t;
/** Type of int_ena register
* Interrupt enable status register.
*/
typedef union {
struct {
/** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t jtag_in_flush_int_ena:1;
/** sof_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
uint32_t sof_int_ena:1;
/** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
uint32_t serial_out_recv_pkt_int_ena:1;
/** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_in_empty_int_ena:1;
/** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t pid_err_int_ena:1;
/** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t crc5_err_int_ena:1;
/** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t crc16_err_int_ena:1;
/** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t stuff_err_int_ena:1;
/** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
*/
uint32_t in_token_rec_in_ep1_int_ena:1;
/** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t usb_bus_reset_int_ena:1;
/** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t out_ep1_zero_payload_int_ena:1;
/** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t out_ep2_zero_payload_int_ena:1;
/** rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t rts_chg_int_ena:1;
/** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t dtr_chg_int_ena:1;
/** get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t get_line_code_int_ena:1;
/** set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t set_line_code_int_ena:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_ena_reg_t;
/** Type of int_clr register
* Interrupt clear status register.
*/
typedef union {
struct {
/** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t jtag_in_flush_int_clr:1;
/** sof_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
*/
uint32_t sof_int_clr:1;
/** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
uint32_t serial_out_recv_pkt_int_clr:1;
/** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_in_empty_int_clr:1;
/** pid_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t pid_err_int_clr:1;
/** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t crc5_err_int_clr:1;
/** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t crc16_err_int_clr:1;
/** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t stuff_err_int_clr:1;
/** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
*/
uint32_t in_token_rec_in_ep1_int_clr:1;
/** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t usb_bus_reset_int_clr:1;
/** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t out_ep1_zero_payload_int_clr:1;
/** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t out_ep2_zero_payload_int_clr:1;
/** rts_chg_int_clr : WT; bitpos: [12]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t rts_chg_int_clr:1;
/** dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t dtr_chg_int_clr:1;
/** get_line_code_int_clr : WT; bitpos: [14]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t get_line_code_int_clr:1;
/** set_line_code_int_clr : WT; bitpos: [15]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t set_line_code_int_clr:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_clr_reg_t;
/** Group: Status Registers */
/** Type of jfifo_st register
* JTAG FIFO status and control registers.
*/
typedef union {
struct {
/** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
* JTAT in fifo counter.
*/
uint32_t in_fifo_cnt:2;
/** in_fifo_empty : RO; bitpos: [2]; default: 1;
* 1: JTAG in fifo is empty.
*/
uint32_t in_fifo_empty:1;
/** in_fifo_full : RO; bitpos: [3]; default: 0;
* 1: JTAG in fifo is full.
*/
uint32_t in_fifo_full:1;
/** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
* JTAT out fifo counter.
*/
uint32_t out_fifo_cnt:2;
/** out_fifo_empty : RO; bitpos: [6]; default: 1;
* 1: JTAG out fifo is empty.
*/
uint32_t out_fifo_empty:1;
/** out_fifo_full : RO; bitpos: [7]; default: 0;
* 1: JTAG out fifo is full.
*/
uint32_t out_fifo_full:1;
/** in_fifo_reset : R/W; bitpos: [8]; default: 0;
* Write 1 to reset JTAG in fifo.
*/
uint32_t in_fifo_reset:1;
/** out_fifo_reset : R/W; bitpos: [9]; default: 0;
* Write 1 to reset JTAG out fifo.
*/
uint32_t out_fifo_reset:1;
uint32_t reserved_10:22;
};
uint32_t val;
} usb_serial_jtag_jfifo_st_reg_t;
/** Type of fram_num register
* Last received SOF frame index register.
*/
typedef union {
struct {
/** sof_frame_index : RO; bitpos: [10:0]; default: 0;
* Frame index of received SOF frame.
*/
uint32_t sof_frame_index:11;
uint32_t reserved_11:21;
};
uint32_t val;
} usb_serial_jtag_fram_num_reg_t;
/** Type of in_ep0_st register
* Control IN endpoint status information.
*/
typedef union {
struct {
/** in_ep0_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 0.
*/
uint32_t in_ep0_state:2;
/** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 0.
*/
uint32_t in_ep0_wr_addr:7;
/** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 0.
*/
uint32_t in_ep0_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep0_st_reg_t;
/** Type of in_ep1_st register
* CDC-ACM IN endpoint status information.
*/
typedef union {
struct {
/** in_ep1_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 1.
*/
uint32_t in_ep1_state:2;
/** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 1.
*/
uint32_t in_ep1_wr_addr:7;
/** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 1.
*/
uint32_t in_ep1_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep1_st_reg_t;
/** Type of in_ep2_st register
* CDC-ACM interrupt IN endpoint status information.
*/
typedef union {
struct {
/** in_ep2_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 2.
*/
uint32_t in_ep2_state:2;
/** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 2.
*/
uint32_t in_ep2_wr_addr:7;
/** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 2.
*/
uint32_t in_ep2_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep2_st_reg_t;
/** Type of in_ep3_st register
* JTAG IN endpoint status information.
*/
typedef union {
struct {
/** in_ep3_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 3.
*/
uint32_t in_ep3_state:2;
/** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 3.
*/
uint32_t in_ep3_wr_addr:7;
/** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 3.
*/
uint32_t in_ep3_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep3_st_reg_t;
/** Type of out_ep0_st register
* Control OUT endpoint status information.
*/
typedef union {
struct {
/** out_ep0_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 0.
*/
uint32_t out_ep0_state:2;
/** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
*/
uint32_t out_ep0_wr_addr:7;
/** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 0.
*/
uint32_t out_ep0_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_out_ep0_st_reg_t;
/** Type of out_ep1_st register
* CDC-ACM OUT endpoint status information.
*/
typedef union {
struct {
/** out_ep1_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 1.
*/
uint32_t out_ep1_state:2;
/** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
*/
uint32_t out_ep1_wr_addr:7;
/** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 1.
*/
uint32_t out_ep1_rd_addr:7;
/** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
* Data count in OUT endpoint 1 when one packet is received.
*/
uint32_t out_ep1_rec_data_cnt:7;
uint32_t reserved_23:9;
};
uint32_t val;
} usb_serial_jtag_out_ep1_st_reg_t;
/** Type of out_ep2_st register
* JTAG OUT endpoint status information.
*/
typedef union {
struct {
/** out_ep2_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 2.
*/
uint32_t out_ep2_state:2;
/** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
*/
uint32_t out_ep2_wr_addr:7;
/** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 2.
*/
uint32_t out_ep2_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_out_ep2_st_reg_t;
/** Type of set_line_code_w0 register
* W0 of SET_LINE_CODING command.
*/
typedef union {
struct {
/** dw_dte_rate : RO; bitpos: [31:0]; default: 0;
* The value of dwDTERate set by host through SET_LINE_CODING command.
*/
uint32_t dw_dte_rate:32;
};
uint32_t val;
} usb_serial_jtag_set_line_code_w0_reg_t;
/** Type of set_line_code_w1 register
* W1 of SET_LINE_CODING command.
*/
typedef union {
struct {
/** bchar_format : RO; bitpos: [7:0]; default: 0;
* The value of bCharFormat set by host through SET_LINE_CODING command.
*/
uint32_t bchar_format:8;
/** bparity_type : RO; bitpos: [15:8]; default: 0;
* The value of bParityTpye set by host through SET_LINE_CODING command.
*/
uint32_t bparity_type:8;
/** bdata_bits : RO; bitpos: [23:16]; default: 0;
* The value of bDataBits set by host through SET_LINE_CODING command.
*/
uint32_t bdata_bits:8;
uint32_t reserved_24:8;
};
uint32_t val;
} usb_serial_jtag_set_line_code_w1_reg_t;
/** Type of bus_reset_st register
* USB Bus reset status register
*/
typedef union {
struct {
/** usb_bus_reset_st : RO; bitpos: [0]; default: 1;
* USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
* reset is released.
*/
uint32_t usb_bus_reset_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_bus_reset_st_reg_t;
/** Group: Version Registers */
/** Type of date register
* Date register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 34640416;
* register version.
*/
uint32_t date:32;
};
uint32_t val;
} usb_serial_jtag_date_reg_t;
typedef struct {
volatile usb_serial_jtag_ep1_reg_t ep1;
volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
volatile usb_serial_jtag_int_raw_reg_t int_raw;
volatile usb_serial_jtag_int_st_reg_t int_st;
volatile usb_serial_jtag_int_ena_reg_t int_ena;
volatile usb_serial_jtag_int_clr_reg_t int_clr;
volatile usb_serial_jtag_conf0_reg_t conf0;
volatile usb_serial_jtag_test_reg_t test;
volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
volatile usb_serial_jtag_fram_num_reg_t fram_num;
volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
volatile usb_serial_jtag_config_update_reg_t config_update;
volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
uint32_t reserved_06c[5];
volatile usb_serial_jtag_date_reg_t date;
} usb_serial_jtag_dev_t;
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
#ifndef __cplusplus
_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif