diff --git a/components/soc/esp32c5/include/soc/aes_reg.h b/components/soc/esp32c5/include/soc/aes_reg.h new file mode 100644 index 0000000000..fbf892dae7 --- /dev/null +++ b/components/soc/esp32c5/include/soc/aes_reg.h @@ -0,0 +1,368 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** AES_KEY_0_REG register + * Key material key_0 configure register + */ +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) +/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ +#define AES_KEY_0 0xFFFFFFFFU +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFFU +#define AES_KEY_0_S 0 + +/** AES_KEY_1_REG register + * Key material key_1 configure register + */ +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) +/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_1 that is a part of key material. + */ +#define AES_KEY_1 0xFFFFFFFFU +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFFU +#define AES_KEY_1_S 0 + +/** AES_KEY_2_REG register + * Key material key_2 configure register + */ +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) +/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_2 that is a part of key material. + */ +#define AES_KEY_2 0xFFFFFFFFU +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFFU +#define AES_KEY_2_S 0 + +/** AES_KEY_3_REG register + * Key material key_3 configure register + */ +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) +/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_3 that is a part of key material. + */ +#define AES_KEY_3 0xFFFFFFFFU +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFFU +#define AES_KEY_3_S 0 + +/** AES_KEY_4_REG register + * Key material key_4 configure register + */ +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) +/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_4 that is a part of key material. + */ +#define AES_KEY_4 0xFFFFFFFFU +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFFU +#define AES_KEY_4_S 0 + +/** AES_KEY_5_REG register + * Key material key_5 configure register + */ +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) +/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_5 that is a part of key material. + */ +#define AES_KEY_5 0xFFFFFFFFU +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFFU +#define AES_KEY_5_S 0 + +/** AES_KEY_6_REG register + * Key material key_6 configure register + */ +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) +/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_6 that is a part of key material. + */ +#define AES_KEY_6 0xFFFFFFFFU +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFFU +#define AES_KEY_6_S 0 + +/** AES_KEY_7_REG register + * Key material key_7 configure register + */ +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) +/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_7 that is a part of key material. + */ +#define AES_KEY_7 0xFFFFFFFFU +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFFU +#define AES_KEY_7_S 0 + +/** AES_TEXT_IN_0_REG register + * source text material text_in_0 configure register + */ +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) +/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ +#define AES_TEXT_IN_0 0xFFFFFFFFU +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFFU +#define AES_TEXT_IN_0_S 0 + +/** AES_TEXT_IN_1_REG register + * source text material text_in_1 configure register + */ +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) +/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_1 that is a part of source text material. + */ +#define AES_TEXT_IN_1 0xFFFFFFFFU +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFFU +#define AES_TEXT_IN_1_S 0 + +/** AES_TEXT_IN_2_REG register + * source text material text_in_2 configure register + */ +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) +/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_2 that is a part of source text material. + */ +#define AES_TEXT_IN_2 0xFFFFFFFFU +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFFU +#define AES_TEXT_IN_2_S 0 + +/** AES_TEXT_IN_3_REG register + * source text material text_in_3 configure register + */ +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) +/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_3 that is a part of source text material. + */ +#define AES_TEXT_IN_3 0xFFFFFFFFU +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFFU +#define AES_TEXT_IN_3_S 0 + +/** AES_TEXT_OUT_0_REG register + * result text material text_out_0 configure register + */ +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) +/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ +#define AES_TEXT_OUT_0 0xFFFFFFFFU +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFFU +#define AES_TEXT_OUT_0_S 0 + +/** AES_TEXT_OUT_1_REG register + * result text material text_out_1 configure register + */ +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) +/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_1 that is a part of result text material. + */ +#define AES_TEXT_OUT_1 0xFFFFFFFFU +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFFU +#define AES_TEXT_OUT_1_S 0 + +/** AES_TEXT_OUT_2_REG register + * result text material text_out_2 configure register + */ +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) +/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_2 that is a part of result text material. + */ +#define AES_TEXT_OUT_2 0xFFFFFFFFU +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFFU +#define AES_TEXT_OUT_2_S 0 + +/** AES_TEXT_OUT_3_REG register + * result text material text_out_3 configure register + */ +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) +/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_3 that is a part of result text material. + */ +#define AES_TEXT_OUT_3 0xFFFFFFFFU +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFFU +#define AES_TEXT_OUT_3_S 0 + +/** AES_MODE_REG register + * AES Mode register + */ +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) +/** AES_MODE : R/W; bitpos: [2:0]; default: 0; + * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: + * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + */ +#define AES_MODE 0x00000007U +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007U +#define AES_MODE_S 0 + +/** AES_TRIGGER_REG register + * AES trigger register + */ +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) +/** AES_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to start AES calculation. + */ +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001U +#define AES_TRIGGER_S 0 + +/** AES_STATE_REG register + * AES state register + */ +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) +/** AES_STATE : RO; bitpos: [1:0]; default: 0; + * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: + * idle, 1: busy, 2: calculation_done. + */ +#define AES_STATE 0x00000003U +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003U +#define AES_STATE_S 0 + +/** AES_IV_MEM register + * The memory that stores initialization vector + */ +#define AES_IV_MEM (DR_REG_AES_BASE + 0x50) +#define AES_IV_MEM_SIZE_BYTES 16 + +/** AES_H_MEM register + * The memory that stores GCM hash subkey + */ +#define AES_H_MEM (DR_REG_AES_BASE + 0x60) +#define AES_H_MEM_SIZE_BYTES 16 + +/** AES_J0_MEM register + * The memory that stores J0 + */ +#define AES_J0_MEM (DR_REG_AES_BASE + 0x70) +#define AES_J0_MEM_SIZE_BYTES 16 + +/** AES_T0_MEM register + * The memory that stores T0 + */ +#define AES_T0_MEM (DR_REG_AES_BASE + 0x80) +#define AES_T0_MEM_SIZE_BYTES 16 + +/** AES_DMA_ENABLE_REG register + * DMA-AES working mode register + */ +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) +/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + */ +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001U +#define AES_DMA_ENABLE_S 0 + +/** AES_BLOCK_MODE_REG register + * AES cipher block mode register + */ +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) +/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, + * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + */ +#define AES_BLOCK_MODE 0x00000007U +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007U +#define AES_BLOCK_MODE_S 0 + +/** AES_BLOCK_NUM_REG register + * AES block number register + */ +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) +/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of Plaintext/ciphertext block. + */ +#define AES_BLOCK_NUM 0xFFFFFFFFU +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFFU +#define AES_BLOCK_NUM_S 0 + +/** AES_INC_SEL_REG register + * Standard incrementing function configure register + */ +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) +/** AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * This bit decides the standard incrementing function. 0: INC32. 1: INC128. + */ +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001U +#define AES_INC_SEL_S 0 + +/** AES_INT_CLEAR_REG register + * AES Interrupt clear register + */ +#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac) +/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the AES interrupt. + */ +#define AES_INT_CLEAR (BIT(0)) +#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S) +#define AES_INT_CLEAR_V 0x00000001U +#define AES_INT_CLEAR_S 0 + +/** AES_INT_ENA_REG register + * AES Interrupt enable register + */ +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) +/** AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + */ +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001U +#define AES_INT_ENA_S 0 + +/** AES_DATE_REG register + * AES version control register + */ +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) +/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936; + * This bits stores the version information of AES. + */ +#define AES_DATE 0x3FFFFFFFU +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFFU +#define AES_DATE_S 0 + +/** AES_DMA_EXIT_REG register + * AES-DMA exit config + */ +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) +/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0; + * Set this register to leave calculation done stage. Recommend to use it after + * software finishes reading DMA's output buffer. + */ +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001U +#define AES_DMA_EXIT_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/aes_struct.h b/components/soc/esp32c5/include/soc/aes_struct.h new file mode 100644 index 0000000000..04f89f619b --- /dev/null +++ b/components/soc/esp32c5/include/soc/aes_struct.h @@ -0,0 +1,438 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: key register */ +/** Type of key_0 register + * Key material key_0 configure register + */ +typedef union { + struct { + /** key_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_0 that is a part of key material. + */ + uint32_t key_0:32; + }; + uint32_t val; +} aes_key_0_reg_t; + +/** Type of key_1 register + * Key material key_1 configure register + */ +typedef union { + struct { + /** key_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_1 that is a part of key material. + */ + uint32_t key_1:32; + }; + uint32_t val; +} aes_key_1_reg_t; + +/** Type of key_2 register + * Key material key_2 configure register + */ +typedef union { + struct { + /** key_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_2 that is a part of key material. + */ + uint32_t key_2:32; + }; + uint32_t val; +} aes_key_2_reg_t; + +/** Type of key_3 register + * Key material key_3 configure register + */ +typedef union { + struct { + /** key_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_3 that is a part of key material. + */ + uint32_t key_3:32; + }; + uint32_t val; +} aes_key_3_reg_t; + +/** Type of key_4 register + * Key material key_4 configure register + */ +typedef union { + struct { + /** key_4 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_4 that is a part of key material. + */ + uint32_t key_4:32; + }; + uint32_t val; +} aes_key_4_reg_t; + +/** Type of key_5 register + * Key material key_5 configure register + */ +typedef union { + struct { + /** key_5 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_5 that is a part of key material. + */ + uint32_t key_5:32; + }; + uint32_t val; +} aes_key_5_reg_t; + +/** Type of key_6 register + * Key material key_6 configure register + */ +typedef union { + struct { + /** key_6 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_6 that is a part of key material. + */ + uint32_t key_6:32; + }; + uint32_t val; +} aes_key_6_reg_t; + +/** Type of key_7 register + * Key material key_7 configure register + */ +typedef union { + struct { + /** key_7 : R/W; bitpos: [31:0]; default: 0; + * This bits stores key_7 that is a part of key material. + */ + uint32_t key_7:32; + }; + uint32_t val; +} aes_key_7_reg_t; + + +/** Group: text in register */ +/** Type of text_in_0 register + * source text material text_in_0 configure register + */ +typedef union { + struct { + /** text_in_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_0 that is a part of source text material. + */ + uint32_t text_in_0:32; + }; + uint32_t val; +} aes_text_in_0_reg_t; + +/** Type of text_in_1 register + * source text material text_in_1 configure register + */ +typedef union { + struct { + /** text_in_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_1 that is a part of source text material. + */ + uint32_t text_in_1:32; + }; + uint32_t val; +} aes_text_in_1_reg_t; + +/** Type of text_in_2 register + * source text material text_in_2 configure register + */ +typedef union { + struct { + /** text_in_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_2 that is a part of source text material. + */ + uint32_t text_in_2:32; + }; + uint32_t val; +} aes_text_in_2_reg_t; + +/** Type of text_in_3 register + * source text material text_in_3 configure register + */ +typedef union { + struct { + /** text_in_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_in_3 that is a part of source text material. + */ + uint32_t text_in_3:32; + }; + uint32_t val; +} aes_text_in_3_reg_t; + + +/** Group: text out register */ +/** Type of text_out_0 register + * result text material text_out_0 configure register + */ +typedef union { + struct { + /** text_out_0 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_0 that is a part of result text material. + */ + uint32_t text_out_0:32; + }; + uint32_t val; +} aes_text_out_0_reg_t; + +/** Type of text_out_1 register + * result text material text_out_1 configure register + */ +typedef union { + struct { + /** text_out_1 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_1 that is a part of result text material. + */ + uint32_t text_out_1:32; + }; + uint32_t val; +} aes_text_out_1_reg_t; + +/** Type of text_out_2 register + * result text material text_out_2 configure register + */ +typedef union { + struct { + /** text_out_2 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_2 that is a part of result text material. + */ + uint32_t text_out_2:32; + }; + uint32_t val; +} aes_text_out_2_reg_t; + +/** Type of text_out_3 register + * result text material text_out_3 configure register + */ +typedef union { + struct { + /** text_out_3 : R/W; bitpos: [31:0]; default: 0; + * This bits stores text_out_3 that is a part of result text material. + */ + uint32_t text_out_3:32; + }; + uint32_t val; +} aes_text_out_3_reg_t; + + +/** Group: Configuration register */ +/** Type of mode register + * AES Mode register + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: + * AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_mode_reg_t; + +/** Type of block_mode register + * AES cipher block mode register + */ +typedef union { + struct { + /** block_mode : R/W; bitpos: [2:0]; default: 0; + * Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, + * 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + */ + uint32_t block_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} aes_block_mode_reg_t; + +/** Type of block_num register + * AES block number register + */ +typedef union { + struct { + /** block_num : R/W; bitpos: [31:0]; default: 0; + * Those bits stores the number of Plaintext/ciphertext block. + */ + uint32_t block_num:32; + }; + uint32_t val; +} aes_block_num_reg_t; + +/** Type of inc_sel register + * Standard incrementing function configure register + */ +typedef union { + struct { + /** inc_sel : R/W; bitpos: [0]; default: 0; + * This bit decides the standard incrementing function. 0: INC32. 1: INC128. + */ + uint32_t inc_sel:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_inc_sel_reg_t; + + +/** Group: Control/Status register */ +/** Type of trigger register + * AES trigger register + */ +typedef union { + struct { + /** trigger : WT; bitpos: [0]; default: 0; + * Set this bit to start AES calculation. + */ + uint32_t trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_trigger_reg_t; + +/** Type of state register + * AES state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: + * idle, 1: busy, 2: calculation_done. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} aes_state_reg_t; + +/** Type of dma_enable register + * DMA-AES working mode register + */ +typedef union { + struct { + /** dma_enable : R/W; bitpos: [0]; default: 0; + * 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + */ + uint32_t dma_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_enable_reg_t; + +/** Type of dma_exit register + * AES-DMA exit config + */ +typedef union { + struct { + /** dma_exit : WT; bitpos: [0]; default: 0; + * Set this register to leave calculation done stage. Recommend to use it after + * software finishes reading DMA's output buffer. + */ + uint32_t dma_exit:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_dma_exit_reg_t; + + +/** Group: memory type */ + +/** Group: interrupt register */ +/** Type of int_clear register + * AES Interrupt clear register + */ +typedef union { + struct { + /** int_clear : WT; bitpos: [0]; default: 0; + * Set this bit to clear the AES interrupt. + */ + uint32_t int_clear:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_clear_reg_t; + +/** Type of int_ena register + * AES Interrupt enable register + */ +typedef union { + struct { + /** int_ena : R/W; bitpos: [0]; default: 0; + * Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + */ + uint32_t int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} aes_int_ena_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * AES version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538513936; + * This bits stores the version information of AES. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} aes_date_reg_t; + + +typedef struct { + volatile aes_key_0_reg_t key_0; + volatile aes_key_1_reg_t key_1; + volatile aes_key_2_reg_t key_2; + volatile aes_key_3_reg_t key_3; + volatile aes_key_4_reg_t key_4; + volatile aes_key_5_reg_t key_5; + volatile aes_key_6_reg_t key_6; + volatile aes_key_7_reg_t key_7; + volatile aes_text_in_0_reg_t text_in_0; + volatile aes_text_in_1_reg_t text_in_1; + volatile aes_text_in_2_reg_t text_in_2; + volatile aes_text_in_3_reg_t text_in_3; + volatile aes_text_out_0_reg_t text_out_0; + volatile aes_text_out_1_reg_t text_out_1; + volatile aes_text_out_2_reg_t text_out_2; + volatile aes_text_out_3_reg_t text_out_3; + volatile aes_mode_reg_t mode; + uint32_t reserved_044; + volatile aes_trigger_reg_t trigger; + volatile aes_state_reg_t state; + volatile uint32_t iv[4]; + volatile uint32_t h[4]; + volatile uint32_t j0[4]; + volatile uint32_t t0[4]; + volatile aes_dma_enable_reg_t dma_enable; + volatile aes_block_mode_reg_t block_mode; + volatile aes_block_num_reg_t block_num; + volatile aes_inc_sel_reg_t inc_sel; + uint32_t reserved_0a0[3]; + volatile aes_int_clear_reg_t int_clear; + volatile aes_int_ena_reg_t int_ena; + volatile aes_date_reg_t date; + volatile aes_dma_exit_reg_t dma_exit; +} aes_dev_t; + +extern aes_dev_t AES; + +#ifndef __cplusplus +_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/cache_reg.h b/components/soc/esp32c5/include/soc/cache_reg.h new file mode 100644 index 0000000000..34bacbb706 --- /dev/null +++ b/components/soc/esp32c5/include/soc/cache_reg.h @@ -0,0 +1,1289 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CACHE_L1_CACHE_CTRL_REG register + * L1 data Cache(L1-Cache) control register + */ +#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4) +/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_BUS0 (BIT(0)) +#define CACHE_L1_CACHE_SHUT_BUS0_M (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S) +#define CACHE_L1_CACHE_SHUT_BUS0_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_BUS0_S 0 +/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + */ +#define CACHE_L1_CACHE_SHUT_BUS1 (BIT(1)) +#define CACHE_L1_CACHE_SHUT_BUS1_M (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S) +#define CACHE_L1_CACHE_SHUT_BUS1_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_BUS1_S 1 +/** CACHE_L1_CACHE_SHUT_DBUS2 : R/W; bitpos: [2]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_SHUT_DBUS2 (BIT(2)) +#define CACHE_L1_CACHE_SHUT_DBUS2_M (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S) +#define CACHE_L1_CACHE_SHUT_DBUS2_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DBUS2_S 2 +/** CACHE_L1_CACHE_SHUT_DBUS3 : R/W; bitpos: [3]; default: 0; + * Reserved + */ +#define CACHE_L1_CACHE_SHUT_DBUS3 (BIT(3)) +#define CACHE_L1_CACHE_SHUT_DBUS3_M (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S) +#define CACHE_L1_CACHE_SHUT_DBUS3_V 0x00000001U +#define CACHE_L1_CACHE_SHUT_DBUS3_S 3 + +/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register + * Cache wrap around control register + */ +#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20) +/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ +#define CACHE_L1_CACHE_WRAP (BIT(4)) +#define CACHE_L1_CACHE_WRAP_M (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S) +#define CACHE_L1_CACHE_WRAP_V 0x00000001U +#define CACHE_L1_CACHE_WRAP_S 4 + +/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register + * Cache tag memory power control register + */ +#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24) +/** CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M (CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S 16 +/** CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M (CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S 17 +/** CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU (BIT(18)) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M (CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S) +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S 18 + +/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register + * Cache data memory power control register + */ +#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28) +/** CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: + * open clock gating. + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M (CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S 16 +/** CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M (CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S 17 +/** CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU (BIT(18)) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M (CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S) +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S 18 + +/** CACHE_L1_CACHE_FREEZE_CTRL_REG register + * Cache Freeze control register + */ +#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c) +/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ +#define CACHE_L1_CACHE_FREEZE_EN (BIT(16)) +#define CACHE_L1_CACHE_FREEZE_EN_M (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S) +#define CACHE_L1_CACHE_FREEZE_EN_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_EN_S 16 +/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ +#define CACHE_L1_CACHE_FREEZE_MODE (BIT(17)) +#define CACHE_L1_CACHE_FREEZE_MODE_M (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S) +#define CACHE_L1_CACHE_FREEZE_MODE_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_MODE_S 17 +/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_CACHE_FREEZE_DONE (BIT(18)) +#define CACHE_L1_CACHE_FREEZE_DONE_M (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S) +#define CACHE_L1_CACHE_FREEZE_DONE_V 0x00000001U +#define CACHE_L1_CACHE_FREEZE_DONE_S 18 + +/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register + * Cache data memory access configure register + */ +#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30) +/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S) +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S 16 +/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S) +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S 17 + +/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register + * Cache tag memory access configure register + */ +#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34) +/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S) +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S 16 +/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ +#define CACHE_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S) +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V 0x00000001U +#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S 17 + +/** CACHE_L1_CACHE_PRELOCK_CONF_REG register + * L1 Cache prelock configure register + */ +#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78) +/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V 0x00000001U +#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S 0 +/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V 0x00000001U +#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S 1 +/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ +#define CACHE_L1_CACHE_PRELOCK_RGID 0x0000000FU +#define CACHE_L1_CACHE_PRELOCK_RGID_M (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S) +#define CACHE_L1_CACHE_PRELOCK_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_PRELOCK_RGID_S 2 + +/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register + * L1 Cache prelock section0 address configure register + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c) +/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register + * L1 Cache prelock section1 address configure register + */ +#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80) +/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register + * L1 Cache prelock section size configure register + */ +#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84) +/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S) +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 +/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S) +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 + +/** CACHE_LOCK_CTRL_REG register + * Lock-class (manual lock) operation control register + */ +#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88) +/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ +#define CACHE_LOCK_ENA (BIT(0)) +#define CACHE_LOCK_ENA_M (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S) +#define CACHE_LOCK_ENA_V 0x00000001U +#define CACHE_LOCK_ENA_S 0 +/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ +#define CACHE_UNLOCK_ENA (BIT(1)) +#define CACHE_UNLOCK_ENA_M (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S) +#define CACHE_UNLOCK_ENA_V 0x00000001U +#define CACHE_UNLOCK_ENA_S 1 +/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ +#define CACHE_LOCK_DONE (BIT(2)) +#define CACHE_LOCK_DONE_M (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S) +#define CACHE_LOCK_DONE_V 0x00000001U +#define CACHE_LOCK_DONE_S 2 +/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ +#define CACHE_LOCK_RGID 0x0000000FU +#define CACHE_LOCK_RGID_M (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S) +#define CACHE_LOCK_RGID_V 0x0000000FU +#define CACHE_LOCK_RGID_S 3 + +/** CACHE_LOCK_MAP_REG register + * Lock (manual lock) map configure register + */ +#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c) +/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ +#define CACHE_LOCK_MAP 0x0000003FU +#define CACHE_LOCK_MAP_M (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S) +#define CACHE_LOCK_MAP_V 0x0000003FU +#define CACHE_LOCK_MAP_S 0 + +/** CACHE_LOCK_ADDR_REG register + * Lock (manual lock) address configure register + */ +#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90) +/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the lock/unlock + * operation, which should be used together with CACHE_LOCK_SIZE_REG + */ +#define CACHE_LOCK_ADDR 0xFFFFFFFFU +#define CACHE_LOCK_ADDR_M (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S) +#define CACHE_LOCK_ADDR_V 0xFFFFFFFFU +#define CACHE_LOCK_ADDR_S 0 + +/** CACHE_LOCK_SIZE_REG register + * Lock (manual lock) size configure register + */ +#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94) +/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ +#define CACHE_LOCK_SIZE 0x0000FFFFU +#define CACHE_LOCK_SIZE_M (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S) +#define CACHE_LOCK_SIZE_V 0x0000FFFFU +#define CACHE_LOCK_SIZE_S 0 + +/** CACHE_SYNC_CTRL_REG register + * Sync-class operation control register + */ +#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98) +/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ +#define CACHE_INVALIDATE_ENA (BIT(0)) +#define CACHE_INVALIDATE_ENA_M (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S) +#define CACHE_INVALIDATE_ENA_V 0x00000001U +#define CACHE_INVALIDATE_ENA_S 0 +/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ +#define CACHE_CLEAN_ENA (BIT(1)) +#define CACHE_CLEAN_ENA_M (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S) +#define CACHE_CLEAN_ENA_V 0x00000001U +#define CACHE_CLEAN_ENA_S 1 +/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ +#define CACHE_WRITEBACK_ENA (BIT(2)) +#define CACHE_WRITEBACK_ENA_M (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S) +#define CACHE_WRITEBACK_ENA_V 0x00000001U +#define CACHE_WRITEBACK_ENA_S 2 +/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ +#define CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) +#define CACHE_WRITEBACK_INVALIDATE_ENA_M (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S) +#define CACHE_WRITEBACK_INVALIDATE_ENA_V 0x00000001U +#define CACHE_WRITEBACK_INVALIDATE_ENA_S 3 +/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ +#define CACHE_SYNC_DONE (BIT(4)) +#define CACHE_SYNC_DONE_M (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S) +#define CACHE_SYNC_DONE_V 0x00000001U +#define CACHE_SYNC_DONE_S 4 +/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ +#define CACHE_SYNC_RGID 0x0000000FU +#define CACHE_SYNC_RGID_M (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S) +#define CACHE_SYNC_RGID_V 0x0000000FU +#define CACHE_SYNC_RGID_S 5 + +/** CACHE_SYNC_MAP_REG register + * Sync map configure register + */ +#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c) +/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ +#define CACHE_SYNC_MAP 0x0000003FU +#define CACHE_SYNC_MAP_M (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S) +#define CACHE_SYNC_MAP_V 0x0000003FU +#define CACHE_SYNC_MAP_S 0 + +/** CACHE_SYNC_ADDR_REG register + * Sync address configure register + */ +#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0) +/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the sync operation, + * which should be used together with CACHE_SYNC_SIZE_REG + */ +#define CACHE_SYNC_ADDR 0xFFFFFFFFU +#define CACHE_SYNC_ADDR_M (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S) +#define CACHE_SYNC_ADDR_V 0xFFFFFFFFU +#define CACHE_SYNC_ADDR_S 0 + +/** CACHE_SYNC_SIZE_REG register + * Sync size configure register + */ +#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4) +/** CACHE_SYNC_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ +#define CACHE_SYNC_SIZE 0x00FFFFFFU +#define CACHE_SYNC_SIZE_M (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S) +#define CACHE_SYNC_SIZE_V 0x00FFFFFFU +#define CACHE_SYNC_SIZE_S 0 + +/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register + * L1 Cache preload-operation control register + */ +#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8) +/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ +#define CACHE_L1_CACHE_PRELOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_PRELOAD_ENA_M (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S) +#define CACHE_L1_CACHE_PRELOAD_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_ENA_S 0 +/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ +#define CACHE_L1_CACHE_PRELOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_PRELOAD_DONE_M (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S) +#define CACHE_L1_CACHE_PRELOAD_DONE_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_DONE_S 1 +/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ +#define CACHE_L1_CACHE_PRELOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_PRELOAD_ORDER_M (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S) +#define CACHE_L1_CACHE_PRELOAD_ORDER_V 0x00000001U +#define CACHE_L1_CACHE_PRELOAD_ORDER_S 2 +/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ +#define CACHE_L1_CACHE_PRELOAD_RGID 0x0000000FU +#define CACHE_L1_CACHE_PRELOAD_RGID_M (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S) +#define CACHE_L1_CACHE_PRELOAD_RGID_V 0x0000000FU +#define CACHE_L1_CACHE_PRELOAD_RGID_S 3 + +/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register + * L1 Cache preload address configure register + */ +#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc) +/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L1-Cache, + * which should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ +#define CACHE_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOAD_ADDR_M (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S) +#define CACHE_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_PRELOAD_ADDR_S 0 + +/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register + * L1 Cache preload size configure register + */ +#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0) +/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ +#define CACHE_L1_CACHE_PRELOAD_SIZE 0x00003FFFU +#define CACHE_L1_CACHE_PRELOAD_SIZE_M (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S) +#define CACHE_L1_CACHE_PRELOAD_SIZE_V 0x00003FFFU +#define CACHE_L1_CACHE_PRELOAD_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register + * L1 Cache autoload-operation control register + */ +#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134) +/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ +#define CACHE_L1_CACHE_AUTOLOAD_ENA (BIT(0)) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_M (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_ENA_S 0 +/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ +#define CACHE_L1_CACHE_AUTOLOAD_DONE (BIT(1)) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_M (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S) +#define CACHE_L1_CACHE_AUTOLOAD_DONE_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_DONE_S 1 +/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ +#define CACHE_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S) +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S 2 +/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S) +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U +#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register + * L1 Cache autoload section 0 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138) +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register + * L1 Cache autoload section 0 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c) +/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register + * L1 Cache autoload section 1 address configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140) +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 + +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register + * L1 Cache autoload section 1 size configure register + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144) +/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S) +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0x00FFFFFFU +#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 + +/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register + * Cache Access Counter Interrupt enable register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158) +/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_ENA (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ENA_M (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S) +#define CACHE_L1_BUS0_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_ENA_S 4 +/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_ENA (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ENA_M (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S) +#define CACHE_L1_BUS1_OVF_INT_ENA_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_ENA_S 5 + +/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register + * Cache Access Counter Interrupt clear register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c) +/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_CLR_M (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S) +#define CACHE_L1_BUS0_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_CLR_S 4 +/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_CLR (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_CLR_M (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S) +#define CACHE_L1_BUS1_OVF_INT_CLR_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_CLR_S 5 + +/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register + * Cache Access Counter Interrupt raw register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160) +/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_RAW (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_RAW_M (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S) +#define CACHE_L1_BUS0_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_RAW_S 4 +/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_RAW (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_RAW_M (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S) +#define CACHE_L1_BUS1_OVF_INT_RAW_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_RAW_S 5 + +/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register + * Cache Access Counter Interrupt status register + */ +#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164) +/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ +#define CACHE_L1_BUS0_OVF_INT_ST (BIT(4)) +#define CACHE_L1_BUS0_OVF_INT_ST_M (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S) +#define CACHE_L1_BUS0_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_BUS0_OVF_INT_ST_S 4 +/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ +#define CACHE_L1_BUS1_OVF_INT_ST (BIT(5)) +#define CACHE_L1_BUS1_OVF_INT_ST_M (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S) +#define CACHE_L1_BUS1_OVF_INT_ST_V 0x00000001U +#define CACHE_L1_BUS1_OVF_INT_ST_S 5 + +/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register + * Cache Access Fail Configuration register + */ +#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x168) +/** CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0; + * The bit is used to configure l1 cache access fail check mode. 0: the access fail is + * not propagated to the request, 1: the access fail is propagated to the request + */ +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE (BIT(4)) +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_M (CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S) +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V 0x00000001U +#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register + * Cache Access Fail Interrupt enable register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x16c) +/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ENA_M (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S) +#define CACHE_L1_CACHE_FAIL_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_ENA_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register + * L1-Cache Access Fail Interrupt clear register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x170) +/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_CLR_M (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S) +#define CACHE_L1_CACHE_FAIL_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_CLR_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register + * Cache Access Fail Interrupt raw register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x174) +/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_RAW_M (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S) +#define CACHE_L1_CACHE_FAIL_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_RAW_S 4 + +/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register + * Cache Access Fail Interrupt status register + */ +#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x178) +/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ +#define CACHE_L1_CACHE_FAIL_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_FAIL_INT_ST_M (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S) +#define CACHE_L1_CACHE_FAIL_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_FAIL_INT_ST_S 4 + +/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register + * Cache Access Counter enable and clear register + */ +#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x17c) +/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ +#define CACHE_L1_BUS0_CNT_ENA (BIT(4)) +#define CACHE_L1_BUS0_CNT_ENA_M (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S) +#define CACHE_L1_BUS0_CNT_ENA_V 0x00000001U +#define CACHE_L1_BUS0_CNT_ENA_S 4 +/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ +#define CACHE_L1_BUS1_CNT_ENA (BIT(5)) +#define CACHE_L1_BUS1_CNT_ENA_M (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S) +#define CACHE_L1_BUS1_CNT_ENA_V 0x00000001U +#define CACHE_L1_BUS1_CNT_ENA_S 5 +/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ +#define CACHE_L1_BUS0_CNT_CLR (BIT(20)) +#define CACHE_L1_BUS0_CNT_CLR_M (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S) +#define CACHE_L1_BUS0_CNT_CLR_V 0x00000001U +#define CACHE_L1_BUS0_CNT_CLR_S 20 +/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ +#define CACHE_L1_BUS1_CNT_CLR (BIT(21)) +#define CACHE_L1_BUS1_CNT_CLR_M (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S) +#define CACHE_L1_BUS1_CNT_CLR_V 0x00000001U +#define CACHE_L1_BUS1_CNT_CLR_S 21 + +/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register + * L1-Cache bus0 Hit-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1c0) +/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_HIT_CNT_M (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S) +#define CACHE_L1_BUS0_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_HIT_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register + * L1-Cache bus0 Miss-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c4) +/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_MISS_CNT_M (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S) +#define CACHE_L1_BUS0_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_MISS_CNT_S 0 + +/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register + * L1-Cache bus0 Conflict-Access Counter register + */ +#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c8) +/** CACHE_L1_BUS0_CONFLICT_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_CONFLICT_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_M (CACHE_L1_BUS0_CONFLICT_RD_CNT_V << CACHE_L1_BUS0_CONFLICT_RD_CNT_S) +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_RD_CNT_S 0 + +/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register + * L1-Cache bus0 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1cc) +/** CACHE_L1_BUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ +#define CACHE_L1_BUS0_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_M (CACHE_L1_BUS0_NXTLVL_RD_CNT_V << CACHE_L1_BUS0_NXTLVL_RD_CNT_S) +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register + * L1-DCache bus0 WB-Access Counter register + */ +#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1d0) +/** CACHE_L1_BUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus0 accesses L1-Cache. + */ +#define CACHE_L1_BUS0_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_M (CACHE_L1_BUS0_NXTLVL_WR_CNT_V << CACHE_L1_BUS0_NXTLVL_WR_CNT_S) +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_NXTLVL_WR_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register + * L1-Cache bus1 Hit-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4) +/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_HIT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_HIT_CNT_M (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S) +#define CACHE_L1_BUS1_HIT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_HIT_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register + * L1-Cache bus1 Miss-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d8) +/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_MISS_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_MISS_CNT_M (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S) +#define CACHE_L1_BUS1_MISS_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_MISS_CNT_S 0 + +/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register + * L1-Cache bus1 Conflict-Access Counter register + */ +#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc) +/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ +#define CACHE_L1_BUS1_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_CONFLICT_CNT_M (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S) +#define CACHE_L1_BUS1_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_CONFLICT_CNT_S 0 + +/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register + * L1-DCache bus1 Next-Level-Access Counter register + */ +#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1e0) +/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S) +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S 0 + +/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register + * L1-DCache bus1 WB-Access Counter register + */ +#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e4) +/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus1 accesses L1-Cache. + */ +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S) +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S 0 + +/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x210) +/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ID_M (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S) +#define CACHE_L1_ICACHE0_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ID_S 0 +/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ATTR_M (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S) +#define CACHE_L1_ICACHE0_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE0_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x214) +/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE0_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_FAIL_ADDR_M (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S) +#define CACHE_L1_ICACHE0_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE0_FAIL_ADDR_S 0 + +/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register + * L1-ICache0 Access Fail ID/attribution information register + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x218) +/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ID 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ID_M (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S) +#define CACHE_L1_ICACHE1_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ID_S 0 +/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ATTR_M (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S) +#define CACHE_L1_ICACHE1_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_ICACHE1_FAIL_ATTR_S 16 + +/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register + * L1-ICache0 Access Fail Address information register + */ +#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x21c) +/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ +#define CACHE_L1_ICACHE1_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_FAIL_ADDR_M (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S) +#define CACHE_L1_ICACHE1_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_ICACHE1_FAIL_ADDR_S 0 + +/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register + * L1-Cache Access Fail ID/attribution information register + */ +#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x230) +/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ID 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ID_M (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S) +#define CACHE_L1_CACHE_FAIL_ID_V 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ID_S 0 +/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ATTR 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ATTR_M (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S) +#define CACHE_L1_CACHE_FAIL_ATTR_V 0x0000FFFFU +#define CACHE_L1_CACHE_FAIL_ATTR_S 16 + +/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register + * L1-Cache Access Fail Address information register + */ +#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x234) +/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ +#define CACHE_L1_CACHE_FAIL_ADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_FAIL_ADDR_M (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S) +#define CACHE_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_FAIL_ADDR_S 0 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG register + * L1-Cache Access Fail Interrupt enable register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x238) +/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S 4 +/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ +#define CACHE_SYNC_DONE_INT_ENA (BIT(6)) +#define CACHE_SYNC_DONE_INT_ENA_M (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S) +#define CACHE_SYNC_DONE_INT_ENA_V 0x00000001U +#define CACHE_SYNC_DONE_INT_ENA_S 6 +/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S 11 +/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_ENA (BIT(13)) +#define CACHE_SYNC_ERR_INT_ENA_M (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S) +#define CACHE_SYNC_ERR_INT_ENA_V 0x00000001U +#define CACHE_SYNC_ERR_INT_ENA_S 13 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG register + * Sync Preload operation Interrupt clear register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x23c) +/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S 4 +/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ +#define CACHE_SYNC_DONE_INT_CLR (BIT(6)) +#define CACHE_SYNC_DONE_INT_CLR_M (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S) +#define CACHE_SYNC_DONE_INT_CLR_V 0x00000001U +#define CACHE_SYNC_DONE_INT_CLR_S 6 +/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S 11 +/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_CLR (BIT(13)) +#define CACHE_SYNC_ERR_INT_CLR_M (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S) +#define CACHE_SYNC_ERR_INT_CLR_V 0x00000001U +#define CACHE_SYNC_ERR_INT_CLR_S 13 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG register + * Sync Preload operation Interrupt raw register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x240) +/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S 4 +/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ +#define CACHE_SYNC_DONE_INT_RAW (BIT(6)) +#define CACHE_SYNC_DONE_INT_RAW_M (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S) +#define CACHE_SYNC_DONE_INT_RAW_V 0x00000001U +#define CACHE_SYNC_DONE_INT_RAW_S 6 +/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S 11 +/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ +#define CACHE_SYNC_ERR_INT_RAW (BIT(13)) +#define CACHE_SYNC_ERR_INT_RAW_M (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S) +#define CACHE_SYNC_ERR_INT_RAW_V 0x00000001U +#define CACHE_SYNC_ERR_INT_RAW_S 13 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG register + * L1-Cache Access Fail Interrupt status register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x244) +/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ +#define CACHE_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S) +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S 4 +/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ +#define CACHE_SYNC_DONE_INT_ST (BIT(6)) +#define CACHE_SYNC_DONE_INT_ST_M (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S) +#define CACHE_SYNC_DONE_INT_ST_V 0x00000001U +#define CACHE_SYNC_DONE_INT_ST_S 6 +/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ +#define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S) +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S 11 +/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ +#define CACHE_SYNC_ERR_INT_ST (BIT(13)) +#define CACHE_SYNC_ERR_INT_ST_M (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S) +#define CACHE_SYNC_ERR_INT_ST_V 0x00000001U +#define CACHE_SYNC_ERR_INT_ST_S 13 + +/** CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG register + * Cache Sync/Preload Operation exception register + */ +#define CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x248) +/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ +#define CACHE_L1_CACHE_PLD_ERR_CODE 0x00000003U +#define CACHE_L1_CACHE_PLD_ERR_CODE_M (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S) +#define CACHE_L1_CACHE_PLD_ERR_CODE_V 0x00000003U +#define CACHE_L1_CACHE_PLD_ERR_CODE_S 8 +/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ +#define CACHE_SYNC_ERR_CODE 0x00000003U +#define CACHE_SYNC_ERR_CODE_M (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S) +#define CACHE_SYNC_ERR_CODE_V 0x00000003U +#define CACHE_SYNC_ERR_CODE_S 12 + +/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register + * Cache Sync Reset control register + */ +#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c) +/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ +#define CACHE_L1_CACHE_SYNC_RST (BIT(4)) +#define CACHE_L1_CACHE_SYNC_RST_M (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S) +#define CACHE_L1_CACHE_SYNC_RST_V 0x00000001U +#define CACHE_L1_CACHE_SYNC_RST_S 4 + +/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register + * Cache Preload Reset control register + */ +#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x250) +/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ +#define CACHE_L1_CACHE_PLD_RST (BIT(4)) +#define CACHE_L1_CACHE_PLD_RST_M (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S) +#define CACHE_L1_CACHE_PLD_RST_V 0x00000001U +#define CACHE_L1_CACHE_PLD_RST_S 4 + +/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register + * Cache Autoload buffer clear control register + */ +#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x254) +/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ +#define CACHE_L1_CACHE_ALD_BUF_CLR (BIT(4)) +#define CACHE_L1_CACHE_ALD_BUF_CLR_M (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S) +#define CACHE_L1_CACHE_ALD_BUF_CLR_V 0x00000001U +#define CACHE_L1_CACHE_ALD_BUF_CLR_S 4 + +/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register + * Unallocate request buffer clear registers + */ +#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258) +/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ +#define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) +#define CACHE_L1_CACHE_UNALLOC_CLR_M (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S) +#define CACHE_L1_CACHE_UNALLOC_CLR_V 0x00000001U +#define CACHE_L1_CACHE_UNALLOC_CLR_S 4 + +/** CACHE_L1_CACHE_OBJECT_CTRL_REG register + * Cache Tag and Data memory Object control register + */ +#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x25c) +/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_CACHE_TAG_OBJECT (BIT(4)) +#define CACHE_L1_CACHE_TAG_OBJECT_M (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S) +#define CACHE_L1_CACHE_TAG_OBJECT_V 0x00000001U +#define CACHE_L1_CACHE_TAG_OBJECT_S 4 +/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ +#define CACHE_L1_CACHE_MEM_OBJECT (BIT(10)) +#define CACHE_L1_CACHE_MEM_OBJECT_M (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S) +#define CACHE_L1_CACHE_MEM_OBJECT_V 0x00000001U +#define CACHE_L1_CACHE_MEM_OBJECT_S 10 + +/** CACHE_L1_CACHE_WAY_OBJECT_REG register + * Cache Tag and Data memory way register + */ +#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x260) +/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ +#define CACHE_L1_CACHE_WAY_OBJECT 0x00000007U +#define CACHE_L1_CACHE_WAY_OBJECT_M (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S) +#define CACHE_L1_CACHE_WAY_OBJECT_V 0x00000007U +#define CACHE_L1_CACHE_WAY_OBJECT_S 0 + +/** CACHE_L1_CACHE_VADDR_REG register + * Cache Vaddr register + */ +#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x264) +/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ +#define CACHE_L1_CACHE_VADDR 0xFFFFFFFFU +#define CACHE_L1_CACHE_VADDR_M (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S) +#define CACHE_L1_CACHE_VADDR_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_VADDR_S 0 + +/** CACHE_L1_CACHE_DEBUG_BUS_REG register + * Cache Tag/data memory content register + */ +#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x268) +/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 616; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ +#define CACHE_L1_CACHE_DEBUG_BUS 0xFFFFFFFFU +#define CACHE_L1_CACHE_DEBUG_BUS_M (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S) +#define CACHE_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFFU +#define CACHE_L1_CACHE_DEBUG_BUS_S 0 + +/** CACHE_DATE_REG register + * Version control register + */ +#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc) +/** CACHE_DATE : R/W; bitpos: [27:0]; default: 36716800; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ +#define CACHE_DATE 0x0FFFFFFFU +#define CACHE_DATE_M (CACHE_DATE_V << CACHE_DATE_S) +#define CACHE_DATE_V 0x0FFFFFFFU +#define CACHE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/cache_struct.h b/components/soc/esp32c5/include/soc/cache_struct.h new file mode 100644 index 0000000000..b0e181fc17 --- /dev/null +++ b/components/soc/esp32c5/include/soc/cache_struct.h @@ -0,0 +1,1409 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control and configuration registers */ +/** Type of l1_cache_ctrl register + * L1 data Cache(L1-Cache) control register + */ +typedef union { + struct { + /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; + * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus0:1; + /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; + * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + */ + uint32_t l1_cache_shut_bus1:1; + /** l1_cache_shut_dbus2 : R/W; bitpos: [2]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus2:1; + /** l1_cache_shut_dbus3 : R/W; bitpos: [3]; default: 0; + * Reserved + */ + uint32_t l1_cache_shut_dbus3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} cache_l1_cache_ctrl_reg_t; + + +/** Group: Wrap Mode Control and configuration registers */ +/** Type of l1_cache_wrap_around_ctrl register + * Cache wrap around control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; + * Set this bit as 1 to enable L1-DCache wrap around mode. + */ + uint32_t l1_cache_wrap:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_wrap_around_ctrl_reg_t; + + +/** Group: Cache Tag Memory Power Control registers */ +/** Type of l1_cache_tag_mem_power_ctrl register + * Cache tag memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_tag_mem_force_on:1; + /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down + */ + uint32_t l1_cache_tag_mem_force_pd:1; + /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_tag_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_tag_mem_power_ctrl_reg_t; + + +/** Group: Cache Data Memory Power Control registers */ +/** Type of l1_cache_data_mem_power_ctrl register + * Cache data memory power control register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1; + * The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: + * open clock gating. + */ + uint32_t l1_cache_data_mem_force_on:1; + /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0; + * The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power + * down + */ + uint32_t l1_cache_data_mem_force_pd:1; + /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1; + * The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up + */ + uint32_t l1_cache_data_mem_force_pu:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_data_mem_power_ctrl_reg_t; + + +/** Group: Cache Freeze Control registers */ +/** Type of l1_cache_freeze_ctrl register + * Cache Freeze control register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; + * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * software. + */ + uint32_t l1_cache_freeze_en:1; + /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; + * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access + * will not stuck. 1: a miss-access will stuck. + */ + uint32_t l1_cache_freeze_mode:1; + /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; + * The bit is used to indicate whether freeze operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_freeze_done:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} cache_l1_cache_freeze_ctrl_reg_t; + + +/** Group: Cache Data Memory Access Control and Configuration registers */ +/** Type of l1_cache_data_mem_acs_conf register + * Cache data memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_rd_en:1; + /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_data_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} cache_l1_cache_data_mem_acs_conf_reg_t; + + +/** Group: Cache Tag Memory Access Control and Configuration registers */ +/** Type of l1_cache_tag_mem_acs_conf register + * Cache tag memory access configure register + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1; + * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_rd_en:1; + /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1; + * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: + * enable. + */ + uint32_t l1_cache_tag_mem_wr_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} cache_l1_cache_tag_mem_acs_conf_reg_t; + + +/** Group: Prelock Control and configuration registers */ +/** Type of l1_cache_prelock_conf register + * L1 Cache prelock configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; + * The bit is used to enable the first section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct0_en:1; + /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the second section of prelock function on L1-Cache. + */ + uint32_t l1_cache_prelock_sct1_en:1; + /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; + * The bit is used to set the gid of l1 cache prelock. + */ + uint32_t l1_cache_prelock_rgid:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_prelock_conf_reg_t; + +/** Type of l1_cache_prelock_sct0_addr register + * L1 Cache prelock section0 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT0_SIZE_REG + */ + uint32_t l1_cache_prelock_sct0_addr:32; + }; + uint32_t val; +} cache_l1_cache_prelock_sct0_addr_reg_t; + +/** Type of l1_dcache_prelock_sct1_addr register + * L1 Cache prelock section1 address configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section of + * prelock on L1-Cache, which should be used together with + * L1_CACHE_PRELOCK_SCT1_SIZE_REG + */ + uint32_t l1_cache_prelock_sct1_addr:32; + }; + uint32_t val; +} cache_l1_dcache_prelock_sct1_addr_reg_t; + +/** Type of l1_dcache_prelock_sct_size register + * L1 Cache prelock section size configure register + */ +typedef union { + struct { + /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + */ + uint32_t l1_cache_prelock_sct0_size:14; + uint32_t reserved_14:2; + /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; + * Those bits are used to configure the size of the second section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + */ + uint32_t l1_cache_prelock_sct1_size:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} cache_l1_dcache_prelock_sct_size_reg_t; + + +/** Group: Lock Control and configuration registers */ +/** Type of lock_ctrl register + * Lock-class (manual lock) operation control register + */ +typedef union { + struct { + /** lock_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware after lock + * operation done + */ + uint32_t lock_ena:1; + /** unlock_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by hardware after + * unlock operation done + */ + uint32_t unlock_ena:1; + /** lock_done : RO; bitpos: [2]; default: 1; + * The bit is used to indicate whether unlock/lock operation is finished or not. 0: + * not finished. 1: finished. + */ + uint32_t lock_done:1; + /** lock_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of cache lock/unlock. + */ + uint32_t lock_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_lock_ctrl_reg_t; + +/** Type of lock_map register + * Lock (manual lock) map configure register + */ +typedef union { + struct { + /** lock_map : R/W; bitpos: [5:0]; default: 0; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply this lock/unlock operation. [4]: L1-Cache + */ + uint32_t lock_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_lock_map_reg_t; + +/** Type of lock_addr register + * Lock (manual lock) address configure register + */ +typedef union { + struct { + /** lock_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the lock/unlock + * operation, which should be used together with CACHE_LOCK_SIZE_REG + */ + uint32_t lock_addr:32; + }; + uint32_t val; +} cache_lock_addr_reg_t; + +/** Type of lock_size register + * Lock (manual lock) size configure register + */ +typedef union { + struct { + /** lock_size : R/W; bitpos: [15:0]; default: 0; + * Those bits are used to configure the size of the lock/unlock operation, which + * should be used together with CACHE_LOCK_ADDR_REG + */ + uint32_t lock_size:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} cache_lock_size_reg_t; + + +/** Group: Sync Control and configuration registers */ +/** Type of sync_ctrl register + * Sync-class operation control register + */ +typedef union { + struct { + /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by hardware + * after invalidate operation done. Note that this bit and the other sync-bits + * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t invalidate_ena:1; + /** clean_ena : R/W/SC; bitpos: [1]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware after + * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, + * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those + * bits can not be set to 1 at the same time. + */ + uint32_t clean_ena:1; + /** writeback_ena : R/W/SC; bitpos: [2]; default: 0; + * The bit is used to enable writeback operation. It will be cleared by hardware after + * writeback operation done. Note that this bit and the other sync-bits + * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that + * is, those bits can not be set to 1 at the same time. + */ + uint32_t writeback_ena:1; + /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; + * The bit is used to enable writeback-invalidate operation. It will be cleared by + * hardware after writeback-invalidate operation done. Note that this bit and the + * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, + * that is, those bits can not be set to 1 at the same time. + */ + uint32_t writeback_invalidate_ena:1; + /** sync_done : RO; bitpos: [4]; default: 0; + * The bit is used to indicate whether sync operation (invalidate, clean, writeback, + * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + */ + uint32_t sync_done:1; + /** sync_rgid : HRO; bitpos: [8:5]; default: 0; + * The bit is used to set the gid of cache sync operation (invalidate, clean, + * writeback, writeback_invalidate) + */ + uint32_t sync_rgid:4; + uint32_t reserved_9:23; + }; + uint32_t val; +} cache_sync_ctrl_reg_t; + +/** Type of sync_map register + * Sync map configure register + */ +typedef union { + struct { + /** sync_map : R/W; bitpos: [5:0]; default: 63; + * Those bits are used to indicate which caches in the two-level cache structure will + * apply the sync operation. [4]: L1-Cache + */ + uint32_t sync_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_sync_map_reg_t; + +/** Type of sync_addr register + * Sync address configure register + */ +typedef union { + struct { + /** sync_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the sync operation, + * which should be used together with CACHE_SYNC_SIZE_REG + */ + uint32_t sync_addr:32; + }; + uint32_t val; +} cache_sync_addr_reg_t; + +/** Type of sync_size register + * Sync size configure register + */ +typedef union { + struct { + /** sync_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the sync operation, which should be + * used together with CACHE_SYNC_ADDR_REG + */ + uint32_t sync_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_sync_size_reg_t; + + +/** Group: Preload Control and configuration registers */ +/** Type of l1_cache_preload_ctrl register + * L1 Cache preload-operation control register + */ +typedef union { + struct { + /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; + * The bit is used to enable preload operation on L1-Cache. It will be cleared by + * hardware automatically after preload operation is done. + */ + uint32_t l1_cache_preload_ena:1; + /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether preload operation is finished or not. 0: not + * finished. 1: finished. + */ + uint32_t l1_cache_preload_done:1; + /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of preload operation. 0: ascending, 1: + * descending. + */ + uint32_t l1_cache_preload_order:1; + /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; + * The bit is used to set the gid of l1 cache preload. + */ + uint32_t l1_cache_preload_rgid:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} cache_l1_cache_preload_ctrl_reg_t; + +/** Type of l1_dcache_preload_addr register + * L1 Cache preload address configure register + */ +typedef union { + struct { + /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of preload on L1-Cache, + * which should be used together with L1_CACHE_PRELOAD_SIZE_REG + */ + uint32_t l1_cache_preload_addr:32; + }; + uint32_t val; +} cache_l1_dcache_preload_addr_reg_t; + +/** Type of l1_dcache_preload_size register + * L1 Cache preload size configure register + */ +typedef union { + struct { + /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; + * Those bits are used to configure the size of the first section of prelock on + * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + */ + uint32_t l1_cache_preload_size:14; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_l1_dcache_preload_size_reg_t; + + +/** Group: Autoload Control and configuration registers */ +/** Type of l1_cache_autoload_ctrl register + * L1 Cache autoload-operation control register + */ +typedef union { + struct { + /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; + * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, + * 0: disable. + */ + uint32_t l1_cache_autoload_ena:1; + /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; + * The bit is used to indicate whether autoload operation on L1-Cache is finished or + * not. 0: not finished. 1: finished. + */ + uint32_t l1_cache_autoload_done:1; + /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; + * The bit is used to configure the direction of autoload operation on L1-Cache. 0: + * ascending. 1: descending. + */ + uint32_t l1_cache_autoload_order:1; + /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; + * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: + * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + */ + uint32_t l1_cache_autoload_trigger_mode:2; + uint32_t reserved_5:3; + /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; + * The bit is used to enable the first section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct0_ena:1; + /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; + * The bit is used to enable the second section for autoload operation on L1-Cache. + */ + uint32_t l1_cache_autoload_sct1_ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} cache_l1_cache_autoload_ctrl_reg_t; + +/** Type of l1_cache_autoload_sct0_addr register + * L1 Cache autoload section 0 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the first section for + * autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct0_addr_reg_t; + +/** Type of l1_cache_autoload_sct0_size register + * L1 Cache autoload section 0 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct0_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the first section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + */ + uint32_t l1_cache_autoload_sct0_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_autoload_sct0_size_reg_t; + +/** Type of l1_cache_autoload_sct1_addr register + * L1 Cache autoload section 1 address configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; + * Those bits are used to configure the start virtual address of the second section + * for autoload operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_addr:32; + }; + uint32_t val; +} cache_l1_cache_autoload_sct1_addr_reg_t; + +/** Type of l1_cache_autoload_sct1_size register + * L1 Cache autoload section 1 size configure register + */ +typedef union { + struct { + /** l1_cache_autoload_sct1_size : R/W; bitpos: [23:0]; default: 0; + * Those bits are used to configure the size of the second section for autoload + * operation on L1-Cache. Note that it should be used together with + * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + */ + uint32_t l1_cache_autoload_sct1_size:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} cache_l1_cache_autoload_sct1_size_reg_t; + + +/** Group: Interrupt registers */ +/** Type of l1_cache_acs_cnt_int_ena register + * Cache Access Counter Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_ena:1; + /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_ena_reg_t; + +/** Type of l1_cache_acs_cnt_int_clr register + * Cache Access Counter Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_clr:1; + /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; + * The bit is used to clear counters overflow interrupt and counters in L1-DCache due + * to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_clr_reg_t; + +/** Type of l1_cache_acs_cnt_int_raw register + * Cache Access Counter Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_raw:1; + /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache + * due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_raw_reg_t; + +/** Type of l1_cache_acs_cnt_int_st register + * Cache Access Counter Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus0 accesses L1-DCache. + */ + uint32_t l1_bus0_ovf_int_st:1; + /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; + * The bit indicates the interrupt status of one of counters overflow that occurs in + * L1-DCache due to bus1 accesses L1-DCache. + */ + uint32_t l1_bus1_ovf_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_int_st_reg_t; + +/** Type of l1_cache_acs_fail_int_ena register + * Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_ena:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_ena_reg_t; + +/** Type of l1_cache_acs_fail_int_clr register + * L1-Cache Access Fail Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to + * cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_clr_reg_t; + +/** Type of l1_cache_acs_fail_int_raw register + * Cache Access Fail Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt of access fail that occurs in L1-DCache. + */ + uint32_t l1_cache_fail_int_raw:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_raw_reg_t; + +/** Type of l1_cache_acs_fail_int_st register + * Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the interrupt status of access fail that occurs in L1-DCache due + * to cpu accesses L1-DCache. + */ + uint32_t l1_cache_fail_int_st:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_int_st_reg_t; + +/** Type of sync_l1_cache_preload_int_ena register + * L1-Cache Access Fail Interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation. If preload + * operation is done, interrupt occurs. + */ + uint32_t l1_cache_pld_done_int_ena:1; + uint32_t reserved_5:1; + /** sync_done_int_ena : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation done. + */ + uint32_t sync_done_int_ena:1; + uint32_t reserved_7:4; + /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_ena:1; + uint32_t reserved_12:1; + /** sync_err_int_ena : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_int_ena_reg_t; + +/** Type of sync_l1_cache_preload_int_clr register + * Sync Preload operation Interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; + * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation + * is done. + */ + uint32_t l1_cache_pld_done_int_clr:1; + uint32_t reserved_5:1; + /** sync_done_int_clr : WT; bitpos: [6]; default: 0; + * The bit is used to clear interrupt that occurs only when Cache sync-operation is + * done. + */ + uint32_t sync_done_int_clr:1; + uint32_t reserved_7:4; + /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; + * The bit is used to clear interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_clr:1; + uint32_t reserved_12:1; + /** sync_err_int_clr : WT; bitpos: [13]; default: 0; + * The bit is used to clear interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_int_clr_reg_t; + +/** Type of sync_l1_cache_preload_int_raw register + * Sync Preload operation Interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is + * done. + */ + uint32_t l1_cache_pld_done_int_raw:1; + uint32_t reserved_5:1; + /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + */ + uint32_t sync_done_int_raw:1; + uint32_t reserved_7:4; + /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error + * occurs. + */ + uint32_t l1_cache_pld_err_int_raw:1; + uint32_t reserved_12:1; + /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit of the interrupt that occurs only when Cache sync-operation error + * occurs. + */ + uint32_t sync_err_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_int_raw_reg_t; + +/** Type of sync_l1_cache_preload_int_st register + * L1-Cache Access Fail Interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; + * The bit indicates the status of the interrupt that occurs only when L1-Cache + * preload-operation is done. + */ + uint32_t l1_cache_pld_done_int_st:1; + uint32_t reserved_5:1; + /** sync_done_int_st : RO; bitpos: [6]; default: 0; + * The bit indicates the status of the interrupt that occurs only when Cache + * sync-operation is done. + */ + uint32_t sync_done_int_st:1; + uint32_t reserved_7:4; + /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; + * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + */ + uint32_t l1_cache_pld_err_int_st:1; + uint32_t reserved_12:1; + /** sync_err_int_st : RO; bitpos: [13]; default: 0; + * The bit indicates the status of the interrupt of Cache sync-operation error. + */ + uint32_t sync_err_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_int_st_reg_t; + + +/** Group: Cache Access Fail Configuration register */ +/** Type of l1_cache_acs_fail_ctrl register + * Cache Access Fail Configuration register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0; + * The bit is used to configure l1 cache access fail check mode. 0: the access fail is + * not propagated to the request, 1: the access fail is propagated to the request + */ + uint32_t l1_cache_acs_fail_check_mode:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_ctrl_reg_t; + + +/** Group: Access Statistics registers */ +/** Type of l1_cache_acs_cnt_ctrl register + * Cache Access Counter enable and clear register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; + * The bit is used to enable dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_ena:1; + /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; + * The bit is used to enable dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_ena:1; + uint32_t reserved_6:14; + /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; + * The bit is used to clear dbus0 counter in L1-DCache. + */ + uint32_t l1_bus0_cnt_clr:1; + /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; + * The bit is used to clear dbus1 counter in L1-DCache. + */ + uint32_t l1_bus1_cnt_clr:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} cache_l1_cache_acs_cnt_ctrl_reg_t; + +/** Type of l1_bus0_acs_hit_cnt register + * L1-Cache bus0 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_hit_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_hit_cnt_reg_t; + +/** Type of l1_bus0_acs_miss_cnt register + * L1-Cache bus0 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_miss_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_miss_cnt_reg_t; + +/** Type of l1_bus0_acs_conflict_cnt register + * L1-Cache bus0 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_conflict_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_conflict_rd_cnt:32; + }; + uint32_t val; +} cache_l1_bus0_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register + * L1-Cache bus0 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus0 accessing L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register + * L1-DCache bus0 WB-Access Counter register + */ +typedef union { + struct { + /** l1_bus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus0 accesses L1-Cache. + */ + uint32_t l1_bus0_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t; + +/** Type of l1_bus1_acs_hit_cnt register + * L1-Cache bus1 Hit-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of hits when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_hit_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_hit_cnt_reg_t; + +/** Type of l1_bus1_acs_miss_cnt register + * L1-Cache bus1 Miss-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of missing when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_miss_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_miss_cnt_reg_t; + +/** Type of l1_bus1_acs_conflict_cnt register + * L1-Cache bus1 Conflict-Access Counter register + */ +typedef union { + struct { + /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of access-conflicts when bus1 accesses L1-Cache. + */ + uint32_t l1_bus1_conflict_cnt:32; + }; + uint32_t val; +} cache_l1_bus1_acs_conflict_cnt_reg_t; + +/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register + * L1-DCache bus1 Next-Level-Access Counter register + */ +typedef union { + struct { + /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of times that L1-Cache accesses L2-Cache due to + * bus1 accessing L1-Cache. + */ + uint32_t l1_dbus1_nxtlvl_rd_cnt:32; + }; + uint32_t val; +} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t; + +/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register + * L1-DCache bus1 WB-Access Counter register + */ +typedef union { + struct { + /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * The register records the number of write back when bus1 accesses L1-Cache. + */ + uint32_t l1_dbus1_nxtlvl_wr_cnt:32; + }; + uint32_t val; +} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t; + + +/** Group: Access Fail Debug registers */ +/** Type of l1_icache0_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_id:16; + /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache0_acs_fail_id_attr_reg_t; + +/** Type of l1_icache0_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache0 accesses L1-ICache. + */ + uint32_t l1_icache0_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache0_acs_fail_addr_reg_t; + +/** Type of l1_icache1_acs_fail_id_attr register + * L1-ICache0 Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_id:16; + /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_attr:16; + }; + uint32_t val; +} cache_l1_icache1_acs_fail_id_attr_reg_t; + +/** Type of l1_icache1_acs_fail_addr register + * L1-ICache0 Access Fail Address information register + */ +typedef union { + struct { + /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache1 accesses L1-ICache. + */ + uint32_t l1_icache1_fail_addr:32; + }; + uint32_t val; +} cache_l1_icache1_acs_fail_addr_reg_t; + +/** Type of l1_dcache_acs_fail_id_attr register + * L1-Cache Access Fail ID/attribution information register + */ +typedef union { + struct { + /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; + * The register records the ID of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_id:16; + /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; + * The register records the attribution of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_attr:16; + }; + uint32_t val; +} cache_l1_dcache_acs_fail_id_attr_reg_t; + +/** Type of l1_dcache_acs_fail_addr register + * L1-Cache Access Fail Address information register + */ +typedef union { + struct { + /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; + * The register records the address of fail-access when cache accesses L1-Cache. + */ + uint32_t l1_cache_fail_addr:32; + }; + uint32_t val; +} cache_l1_dcache_acs_fail_addr_reg_t; + + +/** Group: Operation Exception registers */ +/** Type of sync_l1_cache_preload_exception register + * Cache Sync/Preload Operation exception register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; + * The value 2 is Only available which means preload size is error in L1-Cache. + */ + uint32_t l1_cache_pld_err_code:2; + uint32_t reserved_10:2; + /** sync_err_code : RO; bitpos: [13:12]; default: 0; + * The values 0-2 are available which means sync map, command conflict and size are + * error in Cache System. + */ + uint32_t sync_err_code:2; + uint32_t reserved_14:18; + }; + uint32_t val; +} cache_sync_l1_cache_preload_exception_reg_t; + + +/** Group: Sync Reset control and configuration registers */ +/** Type of l1_cache_sync_rst_ctrl register + * Cache Sync Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only + * be used to initialize sync-logic when some fatal error of sync-logic occurs. + */ + uint32_t l1_cache_sync_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_sync_rst_ctrl_reg_t; + + +/** Group: Preload Reset control and configuration registers */ +/** Type of l1_cache_preload_rst_ctrl register + * Cache Preload Reset control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; + * set this bit to reset preload-logic inside L1-Cache. Recommend that this should + * only be used to initialize preload-logic when some fatal error of preload-logic + * occurs. + */ + uint32_t l1_cache_pld_rst:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_preload_rst_ctrl_reg_t; + + +/** Group: Autoload buffer clear control and configuration registers */ +/** Type of l1_cache_autoload_buf_clr_ctrl register + * Cache Autoload buffer clear control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; + * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, + * autoload will not work in L1-Cache. This bit should not be active when autoload + * works in L1-Cache. + */ + uint32_t l1_cache_ald_buf_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_autoload_buf_clr_ctrl_reg_t; + + +/** Group: Unallocate request buffer clear registers */ +/** Type of l1_unallocate_buffer_clear register + * Unallocate request buffer clear registers + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; + * The bit is used to clear the unallocate request buffer of l1 cache where the + * unallocate request is responsed but not completed. + */ + uint32_t l1_cache_unalloc_clr:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_unallocate_buffer_clear_reg_t; + + +/** Group: Tag and Data Memory Access Control and configuration register */ +/** Type of l1_cache_object_ctrl register + * Cache Tag and Data memory Object control register + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; + * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_tag_object:1; + uint32_t reserved_5:5; + /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; + * Set this bit to set L1-Cache data memory as object. This bit should be onehot with + * the others fields inside this register. + */ + uint32_t l1_cache_mem_object:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} cache_l1_cache_object_ctrl_reg_t; + +/** Type of l1_cache_way_object register + * Cache Tag and Data memory way register + */ +typedef union { + struct { + /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; + * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: + * way1, 2: way2, 3: way3, ?, 7: way7. + */ + uint32_t l1_cache_way_object:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} cache_l1_cache_way_object_reg_t; + +/** Type of l1_cache_vaddr register + * Cache Vaddr register + */ +typedef union { + struct { + /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824; + * Those bits stores the virtual address which will decide where inside the specified + * tag memory object will be accessed. + */ + uint32_t l1_cache_vaddr:32; + }; + uint32_t val; +} cache_l1_cache_vaddr_reg_t; + +/** Type of l1_cache_debug_bus register + * Cache Tag/data memory content register + */ +typedef union { + struct { + /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 616; + * This is a constant place where we can write data to or read data from the tag/data + * memory on the specified cache. + */ + uint32_t l1_cache_debug_bus:32; + }; + uint32_t val; +} cache_l1_cache_debug_bus_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36716800; + * version control register. Note that this default value stored is the latest date + * when the hardware logic was updated. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cache_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl; + uint32_t reserved_008[6]; + volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; + volatile cache_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl; + volatile cache_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl; + volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; + volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; + volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; + uint32_t reserved_038[16]; + volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; + volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; + volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; + volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; + volatile cache_lock_ctrl_reg_t lock_ctrl; + volatile cache_lock_map_reg_t lock_map; + volatile cache_lock_addr_reg_t lock_addr; + volatile cache_lock_size_reg_t lock_size; + volatile cache_sync_ctrl_reg_t sync_ctrl; + volatile cache_sync_map_reg_t sync_map; + volatile cache_sync_addr_reg_t sync_addr; + volatile cache_sync_size_reg_t sync_size; + uint32_t reserved_0a8[12]; + volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; + volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; + volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size; + uint32_t reserved_0e4[20]; + volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; + volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; + volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; + volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; + volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; + uint32_t reserved_148[4]; + volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; + volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; + volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; + volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st; + volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl; + volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena; + volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr; + volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; + volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; + volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; + uint32_t reserved_180[16]; + volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; + volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; + volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; + volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt; + volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt; + volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; + volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; + volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; + volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt; + volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt; + uint32_t reserved_1e8[10]; + volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; + volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; + volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; + volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; + uint32_t reserved_220[4]; + volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr; + volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; + volatile cache_sync_l1_cache_preload_int_ena_reg_t sync_l1_cache_preload_int_ena; + volatile cache_sync_l1_cache_preload_int_clr_reg_t sync_l1_cache_preload_int_clr; + volatile cache_sync_l1_cache_preload_int_raw_reg_t sync_l1_cache_preload_int_raw; + volatile cache_sync_l1_cache_preload_int_st_reg_t sync_l1_cache_preload_int_st; + volatile cache_sync_l1_cache_preload_exception_reg_t sync_l1_cache_preload_exception; + volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; + volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; + volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; + volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; + volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; + volatile cache_l1_cache_way_object_reg_t l1_cache_way_object; + volatile cache_l1_cache_vaddr_reg_t l1_cache_vaddr; + volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus; + uint32_t reserved_26c[100]; + volatile cache_date_reg_t date; +} cache_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ds_reg.h b/components/soc/esp32c5/include/soc/ds_reg.h new file mode 100644 index 0000000000..d164a12930 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ds_reg.h @@ -0,0 +1,149 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** DS_Y_MEM register + * memory that stores Y + */ +#define DS_Y_MEM (DR_REG_DS_BASE + 0x0) +#define DS_Y_MEM_SIZE_BYTES 512 + +/** DS_M_MEM register + * memory that stores M + */ +#define DS_M_MEM (DR_REG_DS_BASE + 0x200) +#define DS_M_MEM_SIZE_BYTES 512 + +/** DS_RB_MEM register + * memory that stores Rb + */ +#define DS_RB_MEM (DR_REG_DS_BASE + 0x400) +#define DS_RB_MEM_SIZE_BYTES 512 + +/** DS_BOX_MEM register + * memory that stores BOX + */ +#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600) +#define DS_BOX_MEM_SIZE_BYTES 48 + +/** DS_IV_MEM register + * memory that stores IV + */ +#define DS_IV_MEM (DR_REG_DS_BASE + 0x630) +#define DS_IV_MEM_SIZE_BYTES 16 + +/** DS_X_MEM register + * memory that stores X + */ +#define DS_X_MEM (DR_REG_DS_BASE + 0x800) +#define DS_X_MEM_SIZE_BYTES 512 + +/** DS_Z_MEM register + * memory that stores Z + */ +#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00) +#define DS_Z_MEM_SIZE_BYTES 512 + +/** DS_SET_START_REG register + * DS start control register + */ +#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00) +/** DS_SET_START : WT; bitpos: [0]; default: 0; + * set this bit to start DS operation. + */ +#define DS_SET_START (BIT(0)) +#define DS_SET_START_M (DS_SET_START_V << DS_SET_START_S) +#define DS_SET_START_V 0x00000001U +#define DS_SET_START_S 0 + +/** DS_SET_CONTINUE_REG register + * DS continue control register + */ +#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04) +/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0; + * set this bit to continue DS operation. + */ +#define DS_SET_CONTINUE (BIT(0)) +#define DS_SET_CONTINUE_M (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S) +#define DS_SET_CONTINUE_V 0x00000001U +#define DS_SET_CONTINUE_S 0 + +/** DS_SET_FINISH_REG register + * DS finish control register + */ +#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08) +/** DS_SET_FINISH : WT; bitpos: [0]; default: 0; + * Set this bit to finish DS process. + */ +#define DS_SET_FINISH (BIT(0)) +#define DS_SET_FINISH_M (DS_SET_FINISH_V << DS_SET_FINISH_S) +#define DS_SET_FINISH_V 0x00000001U +#define DS_SET_FINISH_S 0 + +/** DS_QUERY_BUSY_REG register + * DS query busy register + */ +#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c) +/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0; + * digital signature state. 1'b0: idle, 1'b1: busy + */ +#define DS_QUERY_BUSY (BIT(0)) +#define DS_QUERY_BUSY_M (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S) +#define DS_QUERY_BUSY_V 0x00000001U +#define DS_QUERY_BUSY_S 0 + +/** DS_QUERY_KEY_WRONG_REG register + * DS query key-wrong counter register + */ +#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10) +/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0; + * digital signature key wrong counter + */ +#define DS_QUERY_KEY_WRONG 0x0000000FU +#define DS_QUERY_KEY_WRONG_M (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S) +#define DS_QUERY_KEY_WRONG_V 0x0000000FU +#define DS_QUERY_KEY_WRONG_S 0 + +/** DS_QUERY_CHECK_REG register + * DS query check result register + */ +#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14) +/** DS_MD_ERROR : RO; bitpos: [0]; default: 0; + * MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + */ +#define DS_MD_ERROR (BIT(0)) +#define DS_MD_ERROR_M (DS_MD_ERROR_V << DS_MD_ERROR_S) +#define DS_MD_ERROR_V 0x00000001U +#define DS_MD_ERROR_S 0 +/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0; + * padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + */ +#define DS_PADDING_BAD (BIT(1)) +#define DS_PADDING_BAD_M (DS_PADDING_BAD_V << DS_PADDING_BAD_S) +#define DS_PADDING_BAD_V 0x00000001U +#define DS_PADDING_BAD_S 1 + +/** DS_DATE_REG register + * DS version control register + */ +#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20) +/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624; + * ds version information + */ +#define DS_DATE 0x3FFFFFFFU +#define DS_DATE_M (DS_DATE_V << DS_DATE_S) +#define DS_DATE_V 0x3FFFFFFFU +#define DS_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ds_struct.h b/components/soc/esp32c5/include/soc/ds_struct.h new file mode 100644 index 0000000000..3069fb58ed --- /dev/null +++ b/components/soc/esp32c5/include/soc/ds_struct.h @@ -0,0 +1,149 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: memory type */ + +/** Group: Control/Status registers */ +/** Type of set_start register + * DS start control register + */ +typedef union { + struct { + /** set_start : WT; bitpos: [0]; default: 0; + * set this bit to start DS operation. + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_start_reg_t; + +/** Type of set_continue register + * DS continue control register + */ +typedef union { + struct { + /** set_continue : WT; bitpos: [0]; default: 0; + * set this bit to continue DS operation. + */ + uint32_t set_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_continue_reg_t; + +/** Type of set_finish register + * DS finish control register + */ +typedef union { + struct { + /** set_finish : WT; bitpos: [0]; default: 0; + * Set this bit to finish DS process. + */ + uint32_t set_finish:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_set_finish_reg_t; + +/** Type of query_busy register + * DS query busy register + */ +typedef union { + struct { + /** query_busy : RO; bitpos: [0]; default: 0; + * digital signature state. 1'b0: idle, 1'b1: busy + */ + uint32_t query_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ds_query_busy_reg_t; + +/** Type of query_key_wrong register + * DS query key-wrong counter register + */ +typedef union { + struct { + /** query_key_wrong : RO; bitpos: [3:0]; default: 0; + * digital signature key wrong counter + */ + uint32_t query_key_wrong:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ds_query_key_wrong_reg_t; + +/** Type of query_check register + * DS query check result register + */ +typedef union { + struct { + /** md_error : RO; bitpos: [0]; default: 0; + * MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + */ + uint32_t md_error:1; + /** padding_bad : RO; bitpos: [1]; default: 0; + * padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + */ + uint32_t padding_bad:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ds_query_check_reg_t; + + +/** Group: version control register */ +/** Type of date register + * DS version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * ds version information + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} ds_date_reg_t; + + +typedef struct { + volatile uint32_t y[128]; + volatile uint32_t m[128]; + volatile uint32_t rb[128]; + volatile uint32_t box[12]; + volatile uint32_t iv[4]; + uint32_t reserved_640[112]; + volatile uint32_t x[128]; + volatile uint32_t z[128]; + uint32_t reserved_c00[128]; + volatile ds_set_start_reg_t set_start; + volatile ds_set_continue_reg_t set_continue; + volatile ds_set_finish_reg_t set_finish; + volatile ds_query_busy_reg_t query_busy; + volatile ds_query_key_wrong_reg_t query_key_wrong; + volatile ds_query_check_reg_t query_check; + uint32_t reserved_e18[2]; + volatile ds_date_reg_t date; +} ds_dev_t; + +extern ds_dev_t DS; + +#ifndef __cplusplus +_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/efuse_reg.h b/components/soc/esp32c5/include/soc/efuse_reg.h new file mode 100644 index 0000000000..0d9424909a --- /dev/null +++ b/components/soc/esp32c5/include/soc/efuse_reg.h @@ -0,0 +1,2365 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) +/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_0_S 0 + +/** EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) +/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_1_S 0 + +/** EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) +/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_2_S 0 + +/** EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) +/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_3 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_3_S 0 + +/** EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) +/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_4 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_4_S 0 + +/** EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) +/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_5 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_5_S 0 + +/** EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) +/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_6 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_6_S 0 + +/** EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) +/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ +#define EFUSE_PGM_DATA_7 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU +#define EFUSE_PGM_DATA_7_S 0 + +/** EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) +/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_0_S 0 + +/** EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) +/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_1_S 0 + +/** EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) +/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU +#define EFUSE_PGM_RS_DATA_2_S 0 + +/** EFUSE_RD_WR_DIS_REG register + * BLOCK0 data register 0. + */ +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ +#define EFUSE_WR_DIS 0xFFFFFFFFU +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFFU +#define EFUSE_WR_DIS_S 0 + +/** EFUSE_RD_REPEAT_DATA0_REG register + * BLOCK0 data register 1. + */ +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) +/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_RD_DIS 0x0000007FU +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007FU +#define EFUSE_RD_DIS_S 0 +/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001U +#define EFUSE_DIS_ICACHE_S 8 +/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_JTAG (BIT(9)) +#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) +#define EFUSE_DIS_USB_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 +/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_TWAI (BIT(14)) +#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) +#define EFUSE_DIS_TWAI_V 0x00000001U +#define EFUSE_DIS_TWAI_S 14 +/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_JTAG_SEL_ENABLE (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) +#define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_S 15 +/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ +#define EFUSE_SOFT_DIS_JTAG 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_S 16 +/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ +#define EFUSE_DIS_PAD_JTAG (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) +#define EFUSE_DIS_PAD_JTAG_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + */ +#define EFUSE_USB_EXCHG_PINS (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_S 25 +/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. + */ +#define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) +#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_S 26 +/** EFUSE_HUK_GEN_STATE_PART1 : RO; bitpos: [31:27]; default: 0; + * Represents the validation of HUK generate mode. + */ +#define EFUSE_HUK_GEN_STATE_PART1 0x0000001FU +#define EFUSE_HUK_GEN_STATE_PART1_M (EFUSE_HUK_GEN_STATE_PART1_V << EFUSE_HUK_GEN_STATE_PART1_S) +#define EFUSE_HUK_GEN_STATE_PART1_V 0x0000001FU +#define EFUSE_HUK_GEN_STATE_PART1_S 27 + +/** EFUSE_RD_REPEAT_DATA1_REG register + * BLOCK0 data register 2. + */ +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) +/** EFUSE_HUK_GEN_STATE_PART2 : RO; bitpos: [3:0]; default: 0; + * Represents the validation of HUK generate mode. + */ +#define EFUSE_HUK_GEN_STATE_PART2 0x0000000FU +#define EFUSE_HUK_GEN_STATE_PART2_M (EFUSE_HUK_GEN_STATE_PART2_V << EFUSE_HUK_GEN_STATE_PART2_S) +#define EFUSE_HUK_GEN_STATE_PART2_V 0x0000000FU +#define EFUSE_HUK_GEN_STATE_PART2_S 0 +/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0; + * Represents the key manager random number switch cycle. + */ +#define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) +#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_S 4 +/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0; + * Represents whether corresponding key can only be deployed once. + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_S 6 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0; + * Represents which corresponding key must come from key manager. + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 10 +/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0; + * Represents whether to disable software written init key and force use + * efuse_init_key. + */ +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(14)) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 14 +/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [15]; default: 0; + * TBD. + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE (BIT(15)) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x00000001U +#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 15 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ +#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 +/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ +#define EFUSE_KEY_PURPOSE_0 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_S 24 +/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ +#define EFUSE_KEY_PURPOSE_1 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_S 28 + +/** EFUSE_RD_REPEAT_DATA2_REG register + * BLOCK0 data register 3. + */ +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) +/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ +#define EFUSE_KEY_PURPOSE_2 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_S 0 +/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ +#define EFUSE_KEY_PURPOSE_3 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_S 4 +/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ +#define EFUSE_KEY_PURPOSE_4 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_S 8 +/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ +#define EFUSE_KEY_PURPOSE_5 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_S 12 +/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ +#define EFUSE_SEC_DPA_LEVEL 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) +#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_S 16 +/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0; + * TBD. + */ +#define EFUSE_ECDSA_ENABLE_SOFT_K (BIT(18)) +#define EFUSE_ECDSA_ENABLE_SOFT_K_M (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S) +#define EFUSE_ECDSA_ENABLE_SOFT_K_V 0x00000001U +#define EFUSE_ECDSA_ENABLE_SOFT_K_S 18 +/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ +#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) +#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_S 19 +/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ +#define EFUSE_FLASH_TPUW 0x0000000FU +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000FU +#define EFUSE_FLASH_TPUW_S 28 + +/** EFUSE_RD_REPEAT_DATA3_REG register + * BLOCK0 data register 4. + */ +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) +/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 +/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_DIRECT_BOOT (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) +#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_S 1 +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; + * TBD. + */ +#define EFUSE_LOCK_KM_KEY (BIT(3)) +#define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) +#define EFUSE_LOCK_KM_KEY_V 0x00000001U +#define EFUSE_LOCK_KM_KEY_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 +/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ +#define EFUSE_UART_PRINT_CONTROL 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_S 6 +/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ +#define EFUSE_FORCE_SEND_RESUME (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_S 8 +/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ +#define EFUSE_SECURE_VERSION 0x0000FFFFU +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 +/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ +#define EFUSE_HYS_EN_PAD (BIT(26)) +#define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) +#define EFUSE_HYS_EN_PAD_V 0x00000001U +#define EFUSE_HYS_EN_PAD_S 26 + +/** EFUSE_RD_REPEAT_DATA4_REG register + * BLOCK0 data register 5. + */ +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) +/** EFUSE_RESERVED_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RESERVED_0 0x000000FFU +#define EFUSE_RESERVED_0_M (EFUSE_RESERVED_0_V << EFUSE_RESERVED_0_S) +#define EFUSE_RESERVED_0_V 0x000000FFU +#define EFUSE_RESERVED_0_S 24 + +/** EFUSE_RD_MAC_SYS_0_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ +#define EFUSE_MAC_0 0xFFFFFFFFU +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFFU +#define EFUSE_MAC_0_S 0 + +/** EFUSE_RD_MAC_SYS_1_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ +#define EFUSE_MAC_1 0x0000FFFFU +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFFU +#define EFUSE_MAC_1_S 0 +/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ +#define EFUSE_MAC_EXT 0x0000FFFFU +#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) +#define EFUSE_MAC_EXT_V 0x0000FFFFU +#define EFUSE_MAC_EXT_S 16 + +/** EFUSE_RD_MAC_SYS_2_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_1 0x00003FFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_1_S 0 +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_0 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) +#define EFUSE_MAC_RESERVED_0_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0_S 14 + +/** EFUSE_RD_MAC_SYS_3_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/** EFUSE_RD_MAC_SYS_4_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/** EFUSE_RD_MAC_SYS_5_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA0_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) +/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/** EFUSE_RD_SYS_PART1_DATA1_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) +/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/** EFUSE_RD_SYS_PART1_DATA2_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) +/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/** EFUSE_RD_SYS_PART1_DATA3_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) +/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/** EFUSE_RD_SYS_PART1_DATA4_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/** EFUSE_RD_SYS_PART1_DATA5_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/** EFUSE_RD_SYS_PART1_DATA6_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/** EFUSE_RD_SYS_PART1_DATA7_REG register + * Register $n of BLOCK2 (system). + */ +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/** EFUSE_RD_USR_DATA0_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) +/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA0 0xFFFFFFFFU +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFFU +#define EFUSE_USR_DATA0_S 0 + +/** EFUSE_RD_USR_DATA1_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) +/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA1 0xFFFFFFFFU +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFFU +#define EFUSE_USR_DATA1_S 0 + +/** EFUSE_RD_USR_DATA2_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) +/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA2 0xFFFFFFFFU +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFFU +#define EFUSE_USR_DATA2_S 0 + +/** EFUSE_RD_USR_DATA3_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) +/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA3 0xFFFFFFFFU +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFFU +#define EFUSE_USR_DATA3_S 0 + +/** EFUSE_RD_USR_DATA4_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) +/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA4 0xFFFFFFFFU +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFFU +#define EFUSE_USR_DATA4_S 0 + +/** EFUSE_RD_USR_DATA5_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) +/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA5 0xFFFFFFFFU +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFFU +#define EFUSE_USR_DATA5_S 0 + +/** EFUSE_RD_USR_DATA6_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) +/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA6 0xFFFFFFFFU +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFFU +#define EFUSE_USR_DATA6_S 0 + +/** EFUSE_RD_USR_DATA7_REG register + * Register $n of BLOCK3 (user). + */ +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) +/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ +#define EFUSE_USR_DATA7 0xFFFFFFFFU +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFFU +#define EFUSE_USR_DATA7_S 0 + +/** EFUSE_RD_KEY0_DATA0_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) +/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA0 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA0_S 0 + +/** EFUSE_RD_KEY0_DATA1_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) +/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA1 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA1_S 0 + +/** EFUSE_RD_KEY0_DATA2_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) +/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA2 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA2_S 0 + +/** EFUSE_RD_KEY0_DATA3_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) +/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA3 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA3_S 0 + +/** EFUSE_RD_KEY0_DATA4_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) +/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA4 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA4_S 0 + +/** EFUSE_RD_KEY0_DATA5_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) +/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA5 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA5_S 0 + +/** EFUSE_RD_KEY0_DATA6_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) +/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA6 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA6_S 0 + +/** EFUSE_RD_KEY0_DATA7_REG register + * Register $n of BLOCK4 (KEY0). + */ +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) +/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ +#define EFUSE_KEY0_DATA7 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY0_DATA7_S 0 + +/** EFUSE_RD_KEY1_DATA0_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) +/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA0 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA0_S 0 + +/** EFUSE_RD_KEY1_DATA1_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) +/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA1 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA1_S 0 + +/** EFUSE_RD_KEY1_DATA2_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) +/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA2 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA2_S 0 + +/** EFUSE_RD_KEY1_DATA3_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) +/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA3 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA3_S 0 + +/** EFUSE_RD_KEY1_DATA4_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) +/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA4 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA4_S 0 + +/** EFUSE_RD_KEY1_DATA5_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) +/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA5 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA5_S 0 + +/** EFUSE_RD_KEY1_DATA6_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) +/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA6 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA6_S 0 + +/** EFUSE_RD_KEY1_DATA7_REG register + * Register $n of BLOCK5 (KEY1). + */ +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) +/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ +#define EFUSE_KEY1_DATA7 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY1_DATA7_S 0 + +/** EFUSE_RD_KEY2_DATA0_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) +/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA0 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA0_S 0 + +/** EFUSE_RD_KEY2_DATA1_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) +/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA1 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA1_S 0 + +/** EFUSE_RD_KEY2_DATA2_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) +/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA2 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA2_S 0 + +/** EFUSE_RD_KEY2_DATA3_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) +/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA3 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA3_S 0 + +/** EFUSE_RD_KEY2_DATA4_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) +/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA4 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA4_S 0 + +/** EFUSE_RD_KEY2_DATA5_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) +/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA5 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA5_S 0 + +/** EFUSE_RD_KEY2_DATA6_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) +/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA6 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA6_S 0 + +/** EFUSE_RD_KEY2_DATA7_REG register + * Register $n of BLOCK6 (KEY2). + */ +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) +/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ +#define EFUSE_KEY2_DATA7 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY2_DATA7_S 0 + +/** EFUSE_RD_KEY3_DATA0_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) +/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA0 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA0_S 0 + +/** EFUSE_RD_KEY3_DATA1_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) +/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA1 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA1_S 0 + +/** EFUSE_RD_KEY3_DATA2_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) +/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA2 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA2_S 0 + +/** EFUSE_RD_KEY3_DATA3_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) +/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA3 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA3_S 0 + +/** EFUSE_RD_KEY3_DATA4_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) +/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA4 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA4_S 0 + +/** EFUSE_RD_KEY3_DATA5_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) +/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA5 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA5_S 0 + +/** EFUSE_RD_KEY3_DATA6_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) +/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA6 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA6_S 0 + +/** EFUSE_RD_KEY3_DATA7_REG register + * Register $n of BLOCK7 (KEY3). + */ +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) +/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ +#define EFUSE_KEY3_DATA7 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY3_DATA7_S 0 + +/** EFUSE_RD_KEY4_DATA0_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) +/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA0 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA0_S 0 + +/** EFUSE_RD_KEY4_DATA1_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) +/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA1 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA1_S 0 + +/** EFUSE_RD_KEY4_DATA2_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) +/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA2 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA2_S 0 + +/** EFUSE_RD_KEY4_DATA3_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) +/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA3 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA3_S 0 + +/** EFUSE_RD_KEY4_DATA4_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) +/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA4 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA4_S 0 + +/** EFUSE_RD_KEY4_DATA5_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) +/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA5 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA5_S 0 + +/** EFUSE_RD_KEY4_DATA6_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) +/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA6 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA6_S 0 + +/** EFUSE_RD_KEY4_DATA7_REG register + * Register $n of BLOCK8 (KEY4). + */ +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) +/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ +#define EFUSE_KEY4_DATA7 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY4_DATA7_S 0 + +/** EFUSE_RD_KEY5_DATA0_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) +/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA0 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA0_S 0 + +/** EFUSE_RD_KEY5_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) +/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA1 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA1_S 0 + +/** EFUSE_RD_KEY5_DATA2_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) +/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA2 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA2_S 0 + +/** EFUSE_RD_KEY5_DATA3_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) +/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA3 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA3_S 0 + +/** EFUSE_RD_KEY5_DATA4_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) +/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA4 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA4_S 0 + +/** EFUSE_RD_KEY5_DATA5_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) +/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA5 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA5_S 0 + +/** EFUSE_RD_KEY5_DATA6_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) +/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA6 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA6_S 0 + +/** EFUSE_RD_KEY5_DATA7_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) +/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ +#define EFUSE_KEY5_DATA7 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU +#define EFUSE_KEY5_DATA7_S 0 + +/** EFUSE_RD_SYS_PART2_DATA0_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/** EFUSE_RD_SYS_PART2_DATA1_REG register + * Register $n of BLOCK9 (KEY5). + */ +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/** EFUSE_RD_SYS_PART2_DATA2_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/** EFUSE_RD_SYS_PART2_DATA3_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/** EFUSE_RD_SYS_PART2_DATA4_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/** EFUSE_RD_SYS_PART2_DATA5_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/** EFUSE_RD_SYS_PART2_DATA6_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/** EFUSE_RD_SYS_PART2_DATA7_REG register + * Register $n of BLOCK10 (system). + */ +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ +#define EFUSE_RD_DIS_ERR 0x0000007FU +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007FU +#define EFUSE_RD_DIS_ERR_S 0 +/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_ICACHE. + */ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001U +#define EFUSE_DIS_ICACHE_ERR_S 8 +/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ +#define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) +#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) +#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U +#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 +/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_CAN. + */ +#define EFUSE_DIS_TWAI_ERR (BIT(14)) +#define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) +#define EFUSE_DIS_TWAI_ERR_V 0x00000001U +#define EFUSE_DIS_TWAI_ERR_S 14 +/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ +#define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) +#define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) +#define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U +#define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 +/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ +#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U +#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 +/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ +#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) +#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) +#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_PAD_JTAG_ERR_S 19 +/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_EXCHG_PINS. + */ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U +#define EFUSE_USB_EXCHG_PINS_ERR_S 25 +/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; + * Indicates a programming error of VDD_SPI_AS_GPIO. + */ +#define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) +#define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U +#define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 +/** EFUSE_HUK_GEN_STATE_PART1_ERR : RO; bitpos: [31:27]; default: 0; + * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART1. + */ +#define EFUSE_HUK_GEN_STATE_PART1_ERR 0x0000001FU +#define EFUSE_HUK_GEN_STATE_PART1_ERR_M (EFUSE_HUK_GEN_STATE_PART1_ERR_V << EFUSE_HUK_GEN_STATE_PART1_ERR_S) +#define EFUSE_HUK_GEN_STATE_PART1_ERR_V 0x0000001FU +#define EFUSE_HUK_GEN_STATE_PART1_ERR_S 27 + +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_HUK_GEN_STATE_PART2_ERR : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART2. + */ +#define EFUSE_HUK_GEN_STATE_PART2_ERR 0x0000000FU +#define EFUSE_HUK_GEN_STATE_PART2_ERR_M (EFUSE_HUK_GEN_STATE_PART2_ERR_V << EFUSE_HUK_GEN_STATE_PART2_ERR_S) +#define EFUSE_HUK_GEN_STATE_PART2_ERR_V 0x0000000FU +#define EFUSE_HUK_GEN_STATE_PART2_ERR_S 0 +/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [5:4]; default: 0; + * Indicates a programming error of EFUSE_KM_RND_SWITCH_CYCLE. + */ +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S) +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000003U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 4 +/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [9:6]; default: 0; + * Indicates a programming error of EFUSE_KM_DEPLOY_ONLY_ONCE. + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0x0000000FU +#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 6 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [13:10]; default: 0; + * Indicates a programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY. + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0x0000000FU +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 10 +/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [14]; default: 0; + * Indicates a programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY. + */ +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(14)) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U +#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 14 +/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [15]; default: 0; + * Indicates a programming error of EFUSE_KM_DISABLE_DEPLOY_MODE. + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR (BIT(15)) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x00000001U +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 15 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 + +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 +/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ +#define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) +#define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U +#define EFUSE_SEC_DPA_LEVEL_ERR_S 16 +/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0; + * Reserved. + */ +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR (BIT(18)) +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S) +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V 0x00000001U +#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S 18 +/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ +#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) +#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U +#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 +/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ +#define EFUSE_FLASH_TPUW_ERR 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 +/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ +#define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) +#define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U +#define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 +/** EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ +#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) +#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) +#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U +#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0; + * TBD. + */ +#define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) +#define EFUSE_LOCK_KM_KEY_ERR_M (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S) +#define EFUSE_LOCK_KM_KEY_ERR_V 0x00000001U +#define EFUSE_LOCK_KM_KEY_ERR_S 3 +/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 +/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U +#define EFUSE_FORCE_SEND_RESUME_ERR_S 8 +/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; + * Indicates a programming error of SECURE VERSION. + */ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU +#define EFUSE_SECURE_VERSION_ERR_S 9 +/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + */ +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 +/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0; + * Indicates a programming error of HYS_EN_PAD. + */ +#define EFUSE_HYS_EN_PAD_ERR (BIT(26)) +#define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) +#define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U +#define EFUSE_HYS_EN_PAD_ERR_S 26 + +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +/** EFUSE_RESERVED_0_ERR : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RESERVED_0_ERR 0x000000FFU +#define EFUSE_RESERVED_0_ERR_M (EFUSE_RESERVED_0_ERR_V << EFUSE_RESERVED_0_ERR_S) +#define EFUSE_RESERVED_0_ERR_V 0x000000FFU +#define EFUSE_RESERVED_0_ERR_S 24 + +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SYS_ERR_NUM 0x00000007U +#define EFUSE_MAC_SYS_ERR_NUM_M (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S) +#define EFUSE_MAC_SYS_ERR_NUM_V 0x00000007U +#define EFUSE_MAC_SYS_ERR_NUM_S 0 +/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SYS is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SYS_FAIL (BIT(3)) +#define EFUSE_MAC_SYS_FAIL_M (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S) +#define EFUSE_MAC_SYS_FAIL_V 0x00000001U +#define EFUSE_MAC_SYS_FAIL_S 3 +/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART1_ERR_NUM_M (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S) +#define EFUSE_SYS_PART1_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_ERR_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 + +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U +#define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 + +/** EFUSE_CLK_REG register + * eFuse clcok configuration register. + */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) +#define EFUSE_MEM_FORCE_PD_V 0x00000001U +#define EFUSE_MEM_FORCE_PD_S 0 +/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) +#define EFUSE_MEM_FORCE_PU_V 0x00000001U +#define EFUSE_MEM_FORCE_PU_S 2 +/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001U +#define EFUSE_CLK_EN_S 16 + +/** EFUSE_CONF_REG register + * eFuse operation mode configuraiton register + */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ +#define EFUSE_OP_CODE 0x0000FFFFU +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFFU +#define EFUSE_OP_CODE_S 0 +/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ +#define EFUSE_CFG_ECDSA_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) +#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_S 16 + +/** EFUSE_STATUS_REG register + * eFuse status register. + */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ +#define EFUSE_STATE 0x0000000FU +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000FU +#define EFUSE_STATE_S 0 +/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ +#define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) +#define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU +#define EFUSE_BLK0_VALID_BIT_CNT_S 10 +/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ +#define EFUSE_CUR_ECDSA_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) +#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_S 20 + +/** EFUSE_CMD_REG register + * eFuse command register. + */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001U +#define EFUSE_READ_CMD_S 0 +/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001U +#define EFUSE_PGM_CMD_S 1 +/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ +#define EFUSE_BLK_NUM 0x0000000FU +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000FU +#define EFUSE_BLK_NUM_S 2 + +/** EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001U +#define EFUSE_READ_DONE_INT_RAW_S 0 +/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/** EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001U +#define EFUSE_READ_DONE_INT_ST_S 0 +/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/** EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001U +#define EFUSE_READ_DONE_INT_ENA_S 0 +/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/** EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001U +#define EFUSE_READ_DONE_INT_CLR_S 0 +/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/** EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ +#define EFUSE_DAC_CLK_DIV 0x000000FFU +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FFU +#define EFUSE_DAC_CLK_DIV_S 0 +/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ +#define EFUSE_DAC_NUM 0x000000FFU +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FFU +#define EFUSE_DAC_NUM_S 9 +/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001U +#define EFUSE_OE_CLR_S 17 + +/** EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ +#define EFUSE_THR_A 0x000000FFU +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FFU +#define EFUSE_THR_A_S 0 +/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ +#define EFUSE_TRD 0x000000FFU +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FFU +#define EFUSE_TRD_S 8 +/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ +#define EFUSE_TSUR_A 0x000000FFU +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FFU +#define EFUSE_TSUR_A_S 16 +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. + */ +#define EFUSE_READ_INIT_NUM 0x000000FFU +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FFU +#define EFUSE_READ_INIT_NUM_S 24 + +/** EFUSE_WR_TIM_CONF1_REG register + * Configurarion register 1 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) +/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ +#define EFUSE_TSUP_A 0x000000FFU +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FFU +#define EFUSE_TSUP_A_S 0 +/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. + */ +#define EFUSE_PWR_ON_NUM 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFFU +#define EFUSE_PWR_ON_NUM_S 8 +/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ +#define EFUSE_THP_A 0x000000FFU +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FFU +#define EFUSE_THP_A_S 24 + +/** EFUSE_WR_TIM_CONF2_REG register + * Configurarion register 2 of eFuse programming timing parameters. + */ +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) +/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. + */ +#define EFUSE_PWR_OFF_NUM 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU +#define EFUSE_PWR_OFF_NUM_S 0 +/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. + */ +#define EFUSE_TPGM 0x0000FFFFU +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFFU +#define EFUSE_TPGM_S 16 + +/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) +/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ +#define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) +#define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) +#define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U +#define EFUSE_BYPASS_RS_CORRECTION_S 0 +/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ +#define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) +#define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU +#define EFUSE_BYPASS_RS_BLK_NUM_S 1 +/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ +#define EFUSE_UPDATE (BIT(12)) +#define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) +#define EFUSE_UPDATE_V 0x00000001U +#define EFUSE_UPDATE_S 12 +/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ +#define EFUSE_TPGM_INACTIVE 0x000000FFU +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FFU +#define EFUSE_TPGM_INACTIVE_S 13 + +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/efuse_struct.h b/components/soc/esp32c5/include/soc/efuse_struct.h new file mode 100644 index 0000000000..f0fb593e5b --- /dev/null +++ b/components/soc/esp32c5/include/soc/efuse_struct.h @@ -0,0 +1,2243 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: ******** Registers */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Represents whether programming of individual eFuse memory bit is disabled or + * enabled. 1: Disabled. 0 Enabled. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Represents whether reading of individual eFuse block(block4~block10) is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t rd_dis:7; + uint32_t reserved_7:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_icache:1; + /** dis_usb_jtag : RO; bitpos: [9]; default: 0; + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_jtag:1; + uint32_t reserved_10:2; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_force_download:1; + /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. + */ + uint32_t spi_download_mspi_dis:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_twai:1; + /** jtag_sel_enable : RO; bitpos: [15]; default: 0; + * Represents whether the selection between usb_to_jtag and pad_to_jtag through + * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + * is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t jtag_sel_enable:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. + */ + uint32_t dis_download_manual_encrypt:1; + uint32_t reserved_21:4; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + */ + uint32_t usb_exchg_pins:1; + /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. + */ + uint32_t vdd_spi_as_gpio:1; + /** huk_gen_state_part1 : RO; bitpos: [31:27]; default: 0; + * Represents the validation of HUK generate mode. + */ + uint32_t huk_gen_state_part1:5; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** huk_gen_state_part2 : RO; bitpos: [3:0]; default: 0; + * Represents the validation of HUK generate mode. + */ + uint32_t huk_gen_state_part2:4; + /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0; + * Represents the key manager random number switch cycle. + */ + uint32_t km_rnd_switch_cycle:2; + /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0; + * Represents whether corresponding key can only be deployed once. + */ + uint32_t km_deploy_only_once:4; + /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0; + * Represents which corresponding key must come from key manager. + */ + uint32_t force_use_key_manager_key:4; + /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0; + * Represents whether to disable software written init key and force use + * efuse_init_key. + */ + uint32_t force_disable_sw_init_key:1; + /** km_disable_deploy_mode : RO; bitpos: [15]; default: 0; + * TBD. + */ + uint32_t km_disable_deploy_mode:1; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ + uint32_t sec_dpa_level:2; + /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0; + * TBD. + */ + uint32_t ecdsa_enable_soft_k:1; + /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ + uint32_t crypt_dpa_enable:1; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_aggressive_revoke:1; + uint32_t reserved_22:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. + * 0: enabled. + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** lock_km_key : RO; bitpos: [3]; default: 0; + * TBD. + */ + uint32_t lock_km_key:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ + uint32_t uart_print_control:2; + /** force_send_resume : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ + uint32_t secure_version:16; + /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ + uint32_t secure_boot_disable_fast_wake:1; + /** hys_en_pad : RO; bitpos: [26]; default: 0; + * Represents whether the hysteresis function of corresponding PAD is enabled. 1: + * enabled. 0:disabled. + */ + uint32_t hys_en_pad:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** reserved_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t reserved_0:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_sys_0 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_sys_0_reg_t; + +/** Type of rd_mac_sys_1 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** mac_ext : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ + uint32_t mac_ext:16; + }; + uint32_t val; +} efuse_rd_mac_sys_1_reg_t; + +/** Type of rd_mac_sys_2 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_1:14; + /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_0:18; + }; + uint32_t val; +} efuse_rd_mac_sys_2_reg_t; + +/** Type of rd_mac_sys_3 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_2:18; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the first 14 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_0:14; + }; + uint32_t val; +} efuse_rd_mac_sys_3_reg_t; + +/** Type of rd_mac_sys_4 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_1:32; + }; + uint32_t val; +} efuse_rd_mac_sys_4_reg_t; + +/** Type of rd_mac_sys_5 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_0:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_4:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of the first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data6:32; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of BLOCK3 (user). + */ + uint32_t usr_data7:32; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register $n of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * Indicates a programming error of RD_DIS. + */ + uint32_t rd_dis_err:7; + uint32_t reserved_7:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of DIS_ICACHE. + */ + uint32_t dis_icache_err:1; + /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; + * Indicates a programming error of DIS_USB_JTAG. + */ + uint32_t dis_usb_jtag_err:1; + uint32_t reserved_10:2; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * Indicates a programming error of DIS_FORCE_DOWNLOAD. + */ + uint32_t dis_force_download_err:1; + /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + */ + uint32_t spi_download_mspi_dis_err:1; + /** dis_twai_err : RO; bitpos: [14]; default: 0; + * Indicates a programming error of DIS_CAN. + */ + uint32_t dis_twai_err:1; + /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; + * Indicates a programming error of JTAG_SEL_ENABLE. + */ + uint32_t jtag_sel_enable_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * Indicates a programming error of SOFT_DIS_JTAG. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of DIS_PAD_JTAG. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + uint32_t dis_download_manual_encrypt_err:1; + uint32_t reserved_21:4; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of USB_EXCHG_PINS. + */ + uint32_t usb_exchg_pins_err:1; + /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; + * Indicates a programming error of VDD_SPI_AS_GPIO. + */ + uint32_t vdd_spi_as_gpio_err:1; + /** huk_gen_state_part1_err : RO; bitpos: [31:27]; default: 0; + * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART1. + */ + uint32_t huk_gen_state_part1_err:5; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** huk_gen_state_part2_err : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART2. + */ + uint32_t huk_gen_state_part2_err:4; + /** km_rnd_switch_cycle_err : RO; bitpos: [5:4]; default: 0; + * Indicates a programming error of EFUSE_KM_RND_SWITCH_CYCLE. + */ + uint32_t km_rnd_switch_cycle_err:2; + /** km_deploy_only_once_err : RO; bitpos: [9:6]; default: 0; + * Indicates a programming error of EFUSE_KM_DEPLOY_ONLY_ONCE. + */ + uint32_t km_deploy_only_once_err:4; + /** force_use_key_manager_key_err : RO; bitpos: [13:10]; default: 0; + * Indicates a programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY. + */ + uint32_t force_use_key_manager_key_err:4; + /** force_disable_sw_init_key_err : RO; bitpos: [14]; default: 0; + * Indicates a programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY. + */ + uint32_t force_disable_sw_init_key_err:1; + /** km_disable_deploy_mode_err : RO; bitpos: [15]; default: 0; + * Indicates a programming error of EFUSE_KM_DISABLE_DEPLOY_MODE. + */ + uint32_t km_disable_deploy_mode_err:1; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of WDT_DELAY_SEL. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * Indicates a programming error of KEY_PURPOSE_0. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of KEY_PURPOSE_1. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * Indicates a programming error of KEY_PURPOSE_2. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * Indicates a programming error of KEY_PURPOSE_3. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * Indicates a programming error of KEY_PURPOSE_4. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * Indicates a programming error of KEY_PURPOSE_5. + */ + uint32_t key_purpose_5_err:4; + /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; + * Indicates a programming error of SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_level_err:2; + /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0; + * Reserved. + */ + uint32_t ecdsa_enable_soft_k_err:1; + /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; + * Indicates a programming error of CRYPT_DPA_ENABLE. + */ + uint32_t crypt_dpa_enable_err:1; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * Indicates a programming error of SECURE_BOOT_EN. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + uint32_t reserved_22:6; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * Indicates a programming error of FLASH_TPUW. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * Indicates a programming error of DIS_DOWNLOAD_MODE. + */ + uint32_t dis_download_mode_err:1; + /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; + * Indicates a programming error of DIS_DIRECT_BOOT. + */ + uint32_t dis_direct_boot_err:1; + /** usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ + uint32_t usb_serial_jtag_rom_print_err:1; + /** lock_km_key_err : RO; bitpos: [3]; default: 0; + * TBD. + */ + uint32_t lock_km_key_err:1; + /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + */ + uint32_t dis_usb_serial_jtag_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * Indicates a programming error of UART_PRINT_CONTROL. + */ + uint32_t uart_print_control_err:2; + /** force_send_resume_err : RO; bitpos: [8]; default: 0; + * Indicates a programming error of FORCE_SEND_RESUME. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [24:9]; default: 0; + * Indicates a programming error of SECURE VERSION. + */ + uint32_t secure_version_err:16; + /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + */ + uint32_t secure_boot_disable_fast_wake_err:1; + /** hys_en_pad_err : RO; bitpos: [26]; default: 0; + * Indicates a programming error of HYS_EN_PAD. + */ + uint32_t hys_en_pad_err:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** reserved_0_err : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t reserved_0_err:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_sys_err_num:3; + /** mac_sys_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SYS is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_sys_fail:1; + /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_err_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit to force enable eFuse register configuration clock signal. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: programming operation command 0x5AA5: read operation command. + */ + uint32_t op_code:16; + /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. + */ + uint32_t cfg_ecdsa_blk:4; + uint32_t reserved_20:12; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + uint32_t reserved_4:6; + /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ + uint32_t blk0_valid_bit_cnt:10; + /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ + uint32_t cur_ecdsa_blk:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_status_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WT; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 160; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; + volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; + volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; + volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; + volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; + volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_190[12]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + volatile efuse_date_reg_t date; +} efuse_dev_t; + +extern efuse_dev_t EFUSE; + +#ifndef __cplusplus +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gdma_reg.h b/components/soc/esp32c5/include/soc/gdma_reg.h new file mode 100644 index 0000000000..bc014834e1 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gdma_reg.h @@ -0,0 +1,3213 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GDMA_IN_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) +/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_M (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S) +#define GDMA_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_M (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_M (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH0_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) +/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_M (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S) +#define GDMA_IN_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ST_M (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S) +#define GDMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ST_M (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S) +#define GDMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) +/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_M (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S) +#define GDMA_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_M (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_M (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) +/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_M (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S) +#define GDMA_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_M (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_M (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH1_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) +/** GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_M (GDMA_IN_DONE_CH1_INT_RAW_V << GDMA_IN_DONE_CH1_INT_RAW_S) +#define GDMA_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (GDMA_IN_SUC_EOF_CH1_INT_RAW_V << GDMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (GDMA_IN_ERR_EOF_CH1_INT_RAW_V << GDMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (GDMA_IN_DSCR_ERR_CH1_INT_RAW_V << GDMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_M (GDMA_INFIFO_OVF_CH1_INT_RAW_V << GDMA_INFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_M (GDMA_INFIFO_UDF_CH1_INT_RAW_V << GDMA_INFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH1_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) +/** GDMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_M (GDMA_IN_DONE_CH1_INT_ST_V << GDMA_IN_DONE_CH1_INT_ST_S) +#define GDMA_IN_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (GDMA_IN_SUC_EOF_CH1_INT_ST_V << GDMA_IN_SUC_EOF_CH1_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (GDMA_IN_ERR_EOF_CH1_INT_ST_V << GDMA_IN_ERR_EOF_CH1_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (GDMA_IN_DSCR_ERR_CH1_INT_ST_V << GDMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ST_M (GDMA_INFIFO_OVF_CH1_INT_ST_V << GDMA_INFIFO_OVF_CH1_INT_ST_S) +#define GDMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ST_M (GDMA_INFIFO_UDF_CH1_INT_ST_V << GDMA_INFIFO_UDF_CH1_INT_ST_S) +#define GDMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) +/** GDMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_M (GDMA_IN_DONE_CH1_INT_ENA_V << GDMA_IN_DONE_CH1_INT_ENA_S) +#define GDMA_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (GDMA_IN_SUC_EOF_CH1_INT_ENA_V << GDMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (GDMA_IN_ERR_EOF_CH1_INT_ENA_V << GDMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (GDMA_IN_DSCR_ERR_CH1_INT_ENA_V << GDMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_M (GDMA_INFIFO_OVF_CH1_INT_ENA_V << GDMA_INFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_M (GDMA_INFIFO_UDF_CH1_INT_ENA_V << GDMA_INFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) +/** GDMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_M (GDMA_IN_DONE_CH1_INT_CLR_V << GDMA_IN_DONE_CH1_INT_CLR_S) +#define GDMA_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (GDMA_IN_SUC_EOF_CH1_INT_CLR_V << GDMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (GDMA_IN_ERR_EOF_CH1_INT_CLR_V << GDMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (GDMA_IN_DSCR_ERR_CH1_INT_CLR_V << GDMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_M (GDMA_INFIFO_OVF_CH1_INT_CLR_V << GDMA_INFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_M (GDMA_INFIFO_UDF_CH1_INT_CLR_V << GDMA_INFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH2_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) +/** GDMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_RAW_M (GDMA_IN_DONE_CH2_INT_RAW_V << GDMA_IN_DONE_CH2_INT_RAW_S) +#define GDMA_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M (GDMA_IN_SUC_EOF_CH2_INT_RAW_V << GDMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (GDMA_IN_ERR_EOF_CH2_INT_RAW_V << GDMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (GDMA_IN_DSCR_ERR_CH2_INT_RAW_V << GDMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_M (GDMA_INFIFO_OVF_CH2_INT_RAW_V << GDMA_INFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_M (GDMA_INFIFO_UDF_CH2_INT_RAW_V << GDMA_INFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH2_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) +/** GDMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ST_M (GDMA_IN_DONE_CH2_INT_ST_V << GDMA_IN_DONE_CH2_INT_ST_S) +#define GDMA_IN_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (GDMA_IN_SUC_EOF_CH2_INT_ST_V << GDMA_IN_SUC_EOF_CH2_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_M (GDMA_IN_ERR_EOF_CH2_INT_ST_V << GDMA_IN_ERR_EOF_CH2_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M (GDMA_IN_DSCR_ERR_CH2_INT_ST_V << GDMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ST_M (GDMA_INFIFO_OVF_CH2_INT_ST_V << GDMA_INFIFO_OVF_CH2_INT_ST_S) +#define GDMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ST_M (GDMA_INFIFO_UDF_CH2_INT_ST_V << GDMA_INFIFO_UDF_CH2_INT_ST_S) +#define GDMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_IN_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) +/** GDMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ENA_M (GDMA_IN_DONE_CH2_INT_ENA_V << GDMA_IN_DONE_CH2_INT_ENA_S) +#define GDMA_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M (GDMA_IN_SUC_EOF_CH2_INT_ENA_V << GDMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (GDMA_IN_ERR_EOF_CH2_INT_ENA_V << GDMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M (GDMA_IN_DSCR_ERR_CH2_INT_ENA_V << GDMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_M (GDMA_INFIFO_OVF_CH2_INT_ENA_V << GDMA_INFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_M (GDMA_INFIFO_UDF_CH2_INT_ENA_V << GDMA_INFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_IN_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) +/** GDMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_CLR_M (GDMA_IN_DONE_CH2_INT_CLR_V << GDMA_IN_DONE_CH2_INT_CLR_S) +#define GDMA_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M (GDMA_IN_SUC_EOF_CH2_INT_CLR_V << GDMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M (GDMA_IN_ERR_EOF_CH2_INT_CLR_V << GDMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (GDMA_IN_DSCR_ERR_CH2_INT_CLR_V << GDMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_M (GDMA_INFIFO_OVF_CH2_INT_CLR_V << GDMA_INFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_M (GDMA_INFIFO_UDF_CH2_INT_CLR_V << GDMA_INFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_CLR_S 6 + +/** GDMA_OUT_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x30) +/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_M (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S) +#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_M (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH0_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x34) +/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_M (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S) +#define GDMA_OUT_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ST_S 0 +/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_M (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S) +#define GDMA_OUT_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x38) +/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_M (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S) +#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_M (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x3c) +/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_M (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S) +#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_M (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH1_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x40) +/** GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_M (GDMA_OUT_DONE_CH1_INT_RAW_V << GDMA_OUT_DONE_CH1_INT_RAW_S) +#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_M (GDMA_OUT_EOF_CH1_INT_RAW_V << GDMA_OUT_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_M (GDMA_OUTFIFO_OVF_CH1_INT_RAW_V << GDMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_M (GDMA_OUTFIFO_UDF_CH1_INT_RAW_V << GDMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH1_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x44) +/** GDMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_M (GDMA_OUT_DONE_CH1_INT_ST_V << GDMA_OUT_DONE_CH1_INT_ST_S) +#define GDMA_OUT_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ST_S 0 +/** GDMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_M (GDMA_OUT_EOF_CH1_INT_ST_V << GDMA_OUT_EOF_CH1_INT_ST_S) +#define GDMA_OUT_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (GDMA_OUT_DSCR_ERR_CH1_INT_ST_V << GDMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_M (GDMA_OUTFIFO_OVF_CH1_INT_ST_V << GDMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_M (GDMA_OUTFIFO_UDF_CH1_INT_ST_V << GDMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x48) +/** GDMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_M (GDMA_OUT_DONE_CH1_INT_ENA_V << GDMA_OUT_DONE_CH1_INT_ENA_S) +#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_M (GDMA_OUT_EOF_CH1_INT_ENA_V << GDMA_OUT_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_M (GDMA_OUTFIFO_OVF_CH1_INT_ENA_V << GDMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_M (GDMA_OUTFIFO_UDF_CH1_INT_ENA_V << GDMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x4c) +/** GDMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_M (GDMA_OUT_DONE_CH1_INT_CLR_V << GDMA_OUT_DONE_CH1_INT_CLR_S) +#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_M (GDMA_OUT_EOF_CH1_INT_CLR_V << GDMA_OUT_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_M (GDMA_OUTFIFO_OVF_CH1_INT_CLR_V << GDMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_M (GDMA_OUTFIFO_UDF_CH1_INT_CLR_V << GDMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH2_REG register + * Raw status interrupt of channel 0 + */ +#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x50) +/** GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_RAW_M (GDMA_OUT_DONE_CH2_INT_RAW_V << GDMA_OUT_DONE_CH2_INT_RAW_S) +#define GDMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_RAW_M (GDMA_OUT_EOF_CH2_INT_RAW_V << GDMA_OUT_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_M (GDMA_OUTFIFO_OVF_CH2_INT_RAW_V << GDMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_M (GDMA_OUTFIFO_UDF_CH2_INT_RAW_V << GDMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH2_REG register + * Masked interrupt of channel 0 + */ +#define GDMA_OUT_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x54) +/** GDMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ST_M (GDMA_OUT_DONE_CH2_INT_ST_V << GDMA_OUT_DONE_CH2_INT_ST_S) +#define GDMA_OUT_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ST_S 0 +/** GDMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ST_M (GDMA_OUT_EOF_CH2_INT_ST_V << GDMA_OUT_EOF_CH2_INT_ST_S) +#define GDMA_OUT_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M (GDMA_OUT_DSCR_ERR_CH2_INT_ST_V << GDMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_M (GDMA_OUTFIFO_OVF_CH2_INT_ST_V << GDMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_M (GDMA_OUTFIFO_UDF_CH2_INT_ST_V << GDMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 0 + */ +#define GDMA_OUT_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x58) +/** GDMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ENA_M (GDMA_OUT_DONE_CH2_INT_ENA_V << GDMA_OUT_DONE_CH2_INT_ENA_S) +#define GDMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ENA_M (GDMA_OUT_EOF_CH2_INT_ENA_V << GDMA_OUT_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_M (GDMA_OUTFIFO_OVF_CH2_INT_ENA_V << GDMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_M (GDMA_OUTFIFO_UDF_CH2_INT_ENA_V << GDMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 0 + */ +#define GDMA_OUT_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x5c) +/** GDMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_CLR_M (GDMA_OUT_DONE_CH2_INT_CLR_V << GDMA_OUT_DONE_CH2_INT_CLR_S) +#define GDMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_CLR_M (GDMA_OUT_EOF_CH2_INT_CLR_V << GDMA_OUT_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_M (GDMA_OUTFIFO_OVF_CH2_INT_CLR_V << GDMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_M (GDMA_OUTFIFO_UDF_CH2_INT_CLR_V << GDMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 + +/** GDMA_AHB_TEST_REG register + * reserved + */ +#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x60) +/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTMODE 0x00000007U +#define GDMA_AHB_TESTMODE_M (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S) +#define GDMA_AHB_TESTMODE_V 0x00000007U +#define GDMA_AHB_TESTMODE_S 0 +/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTADDR 0x00000003U +#define GDMA_AHB_TESTADDR_M (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S) +#define GDMA_AHB_TESTADDR_V 0x00000003U +#define GDMA_AHB_TESTADDR_S 4 + +/** GDMA_MISC_CONF_REG register + * MISC register + */ +#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x64) +/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ +#define GDMA_AHBM_RST_INTER (BIT(0)) +#define GDMA_AHBM_RST_INTER_M (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S) +#define GDMA_AHBM_RST_INTER_V 0x00000001U +#define GDMA_AHBM_RST_INTER_S 0 +/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ +#define GDMA_ARB_PRI_DIS (BIT(2)) +#define GDMA_ARB_PRI_DIS_M (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S) +#define GDMA_ARB_PRI_DIS_V 0x00000001U +#define GDMA_ARB_PRI_DIS_S 2 +/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define GDMA_CLK_EN (BIT(3)) +#define GDMA_CLK_EN_M (GDMA_CLK_EN_V << GDMA_CLK_EN_S) +#define GDMA_CLK_EN_V 0x00000001U +#define GDMA_CLK_EN_S 3 + +/** GDMA_DATE_REG register + * Version control register + */ +#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x68) +/** GDMA_DATE : R/W; bitpos: [31:0]; default: 36720912; + * register version. + */ +#define GDMA_DATE 0xFFFFFFFFU +#define GDMA_DATE_M (GDMA_DATE_V << GDMA_DATE_S) +#define GDMA_DATE_V 0xFFFFFFFFU +#define GDMA_DATE_S 0 + +/** GDMA_IN_CONF0_CH0_REG register + * Configure 0 register of Rx channel 0 + */ +#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) +/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH0 (BIT(0)) +#define GDMA_IN_RST_CH0_M (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S) +#define GDMA_IN_RST_CH0_V 0x00000001U +#define GDMA_IN_RST_CH0_S 0 +/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_M (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S) +#define GDMA_IN_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH0_S 1 +/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_M (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S) +#define GDMA_INDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH0_S 2 +/** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH0_M (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S) +#define GDMA_IN_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH0_S 3 +/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_M (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S) +#define GDMA_MEM_TRANS_EN_CH0_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH0_S 4 +/** GDMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH0 (BIT(5)) +#define GDMA_IN_ETM_EN_CH0_M (GDMA_IN_ETM_EN_CH0_V << GDMA_IN_ETM_EN_CH0_S) +#define GDMA_IN_ETM_EN_CH0_V 0x00000001U +#define GDMA_IN_ETM_EN_CH0_S 5 + +/** GDMA_IN_CONF1_CH0_REG register + * Configure 1 register of Rx channel 0 + */ +#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) +/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_M (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S) +#define GDMA_IN_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH0_S 12 + +/** GDMA_INFIFO_STATUS_CH0_REG register + * Receive FIFO status of Rx channel 0 + */ +#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) +/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ +#define GDMA_INFIFO_FULL_CH0 (BIT(0)) +#define GDMA_INFIFO_FULL_CH0_M (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S) +#define GDMA_INFIFO_FULL_CH0_V 0x00000001U +#define GDMA_INFIFO_FULL_CH0_S 0 +/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ +#define GDMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH0_M (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S) +#define GDMA_INFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH0_S 1 +/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ +#define GDMA_INFIFO_CNT_CH0 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_M (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S) +#define GDMA_INFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_M (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_M (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_M (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_M (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH0_M (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S) +#define GDMA_IN_BUF_HUNGRY_CH0_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH0_S 27 + +/** GDMA_IN_POP_CH0_REG register + * Pop control register of Rx channel 0 + */ +#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) +/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH0 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_M (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S) +#define GDMA_INFIFO_RDATA_CH0_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_S 0 +/** GDMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ +#define GDMA_INFIFO_POP_CH0 (BIT(12)) +#define GDMA_INFIFO_POP_CH0_M (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S) +#define GDMA_INFIFO_POP_CH0_V 0x00000001U +#define GDMA_INFIFO_POP_CH0_S 12 + +/** GDMA_IN_LINK_CH0_REG register + * Link descriptor configure and control register of Rx channel 0 + */ +#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) +/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_M (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S) +#define GDMA_INLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_S 0 +/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH0_M (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S) +#define GDMA_INLINK_AUTO_RET_CH0_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH0_S 20 +/** GDMA_INLINK_STOP_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH0 (BIT(21)) +#define GDMA_INLINK_STOP_CH0_M (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S) +#define GDMA_INLINK_STOP_CH0_V 0x00000001U +#define GDMA_INLINK_STOP_CH0_S 21 +/** GDMA_INLINK_START_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH0 (BIT(22)) +#define GDMA_INLINK_START_CH0_M (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S) +#define GDMA_INLINK_START_CH0_V 0x00000001U +#define GDMA_INLINK_START_CH0_S 22 +/** GDMA_INLINK_RESTART_CH0 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH0 (BIT(23)) +#define GDMA_INLINK_RESTART_CH0_M (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S) +#define GDMA_INLINK_RESTART_CH0_V 0x00000001U +#define GDMA_INLINK_RESTART_CH0_S 23 +/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH0 (BIT(24)) +#define GDMA_INLINK_PARK_CH0_M (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S) +#define GDMA_INLINK_PARK_CH0_V 0x00000001U +#define GDMA_INLINK_PARK_CH0_S 24 + +/** GDMA_IN_STATE_CH0_REG register + * Receive status of Rx channel 0 + */ +#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) +/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_M (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S) +#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH0 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_M (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S) +#define GDMA_IN_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_S 18 +/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH0 0x00000007U +#define GDMA_IN_STATE_CH0_M (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S) +#define GDMA_IN_STATE_CH0_V 0x00000007U +#define GDMA_IN_STATE_CH0_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_DSCR_CH0_REG register + * Current inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) +/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_M (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S) +#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_S 0 + +/** GDMA_IN_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) +/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_M (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S) +#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_IN_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) +/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_M (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S) +#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_IN_PRI_CH0_REG register + * Priority register of Rx channel 0 + */ +#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) +/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH0 0x0000000FU +#define GDMA_RX_PRI_CH0_M (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S) +#define GDMA_RX_PRI_CH0_V 0x0000000FU +#define GDMA_RX_PRI_CH0_S 0 + +/** GDMA_IN_PERI_SEL_CH0_REG register + * Peripheral selection of Rx channel 0 + */ +#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) +/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH0 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_M (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S) +#define GDMA_PERI_IN_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_S 0 + +/** GDMA_OUT_CONF0_CH0_REG register + * Configure 0 register of Tx channel 0 + */ +#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) +/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH0 (BIT(0)) +#define GDMA_OUT_RST_CH0_M (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S) +#define GDMA_OUT_RST_CH0_V 0x00000001U +#define GDMA_OUT_RST_CH0_S 0 +/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_M (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S) +#define GDMA_OUT_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH0_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_M (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S) +#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH0_S 2 +/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_M (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S) +#define GDMA_OUT_EOF_MODE_CH0_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH0_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_M (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S) +#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH0_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH0_M (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S) +#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH0_S 5 +/** GDMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH0 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH0_M (GDMA_OUT_ETM_EN_CH0_V << GDMA_OUT_ETM_EN_CH0_S) +#define GDMA_OUT_ETM_EN_CH0_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH0_S 6 + +/** GDMA_OUT_CONF1_CH0_REG register + * Configure 1 register of Tx channel 0 + */ +#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) +/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_M (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S) +#define GDMA_OUT_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH0_S 12 + +/** GDMA_OUTFIFO_STATUS_CH0_REG register + * Transmit FIFO status of Tx channel 0 + */ +#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) +/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH0_M (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S) +#define GDMA_OUTFIFO_FULL_CH0_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH0_S 0 +/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH0_M (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S) +#define GDMA_OUTFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH0_S 1 +/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH0 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_M (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S) +#define GDMA_OUTFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/** GDMA_OUT_PUSH_CH0_REG register + * Push control register of Rx channel 0 + */ +#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) +/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH0 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_M (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S) +#define GDMA_OUTFIFO_WDATA_CH0_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_S 0 +/** GDMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_M (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S) +#define GDMA_OUTFIFO_PUSH_CH0_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH0_S 9 + +/** GDMA_OUT_LINK_CH0_REG register + * Link descriptor configure and control register of Tx channel 0 + */ +#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) +/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_M (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S) +#define GDMA_OUTLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_S 0 +/** GDMA_OUTLINK_STOP_CH0 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH0 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH0_M (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S) +#define GDMA_OUTLINK_STOP_CH0_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH0_S 20 +/** GDMA_OUTLINK_START_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH0 (BIT(21)) +#define GDMA_OUTLINK_START_CH0_M (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S) +#define GDMA_OUTLINK_START_CH0_V 0x00000001U +#define GDMA_OUTLINK_START_CH0_S 21 +/** GDMA_OUTLINK_RESTART_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH0_M (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S) +#define GDMA_OUTLINK_RESTART_CH0_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH0_S 22 +/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH0 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH0_M (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S) +#define GDMA_OUTLINK_PARK_CH0_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH0_S 23 + +/** GDMA_OUT_STATE_CH0_REG register + * Transmit status of Tx channel 0 + */ +#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) +/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_M (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH0 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_M (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S) +#define GDMA_OUT_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_S 18 +/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH0 0x00000007U +#define GDMA_OUT_STATE_CH0_M (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S) +#define GDMA_OUT_STATE_CH0_V 0x00000007U +#define GDMA_OUT_STATE_CH0_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) +/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_M (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_DSCR_CH0_REG register + * Current inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) +/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_M (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S) +#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_S 0 + +/** GDMA_OUT_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) +/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_M (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S) +#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_OUT_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) +/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_M (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S) +#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_OUT_PRI_CH0_REG register + * Priority register of Tx channel 0. + */ +#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) +/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH0 0x0000000FU +#define GDMA_TX_PRI_CH0_M (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S) +#define GDMA_TX_PRI_CH0_V 0x0000000FU +#define GDMA_TX_PRI_CH0_S 0 + +/** GDMA_OUT_PERI_SEL_CH0_REG register + * Peripheral selection of Tx channel 0 + */ +#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) +/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH0 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_M (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S) +#define GDMA_PERI_OUT_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_S 0 + +/** GDMA_IN_CONF0_CH1_REG register + * Configure 0 register of Rx channel 1 + */ +#define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) +/** GDMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH1 (BIT(0)) +#define GDMA_IN_RST_CH1_M (GDMA_IN_RST_CH1_V << GDMA_IN_RST_CH1_S) +#define GDMA_IN_RST_CH1_V 0x00000001U +#define GDMA_IN_RST_CH1_S 0 +/** GDMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_M (GDMA_IN_LOOP_TEST_CH1_V << GDMA_IN_LOOP_TEST_CH1_S) +#define GDMA_IN_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH1_S 1 +/** GDMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_M (GDMA_INDSCR_BURST_EN_CH1_V << GDMA_INDSCR_BURST_EN_CH1_S) +#define GDMA_INDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH1_S 2 +/** GDMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH1_M (GDMA_IN_DATA_BURST_EN_CH1_V << GDMA_IN_DATA_BURST_EN_CH1_S) +#define GDMA_IN_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH1_S 3 +/** GDMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_M (GDMA_MEM_TRANS_EN_CH1_V << GDMA_MEM_TRANS_EN_CH1_S) +#define GDMA_MEM_TRANS_EN_CH1_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH1_S 4 +/** GDMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 1 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH1 (BIT(5)) +#define GDMA_IN_ETM_EN_CH1_M (GDMA_IN_ETM_EN_CH1_V << GDMA_IN_ETM_EN_CH1_S) +#define GDMA_IN_ETM_EN_CH1_V 0x00000001U +#define GDMA_IN_ETM_EN_CH1_S 5 + +/** GDMA_IN_CONF1_CH1_REG register + * Configure 1 register of Rx channel 1 + */ +#define GDMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) +/** GDMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_M (GDMA_IN_CHECK_OWNER_CH1_V << GDMA_IN_CHECK_OWNER_CH1_S) +#define GDMA_IN_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH1_S 12 + +/** GDMA_INFIFO_STATUS_CH1_REG register + * Receive FIFO status of Rx channel 1 + */ +#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) +/** GDMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ +#define GDMA_INFIFO_FULL_CH1 (BIT(0)) +#define GDMA_INFIFO_FULL_CH1_M (GDMA_INFIFO_FULL_CH1_V << GDMA_INFIFO_FULL_CH1_S) +#define GDMA_INFIFO_FULL_CH1_V 0x00000001U +#define GDMA_INFIFO_FULL_CH1_S 0 +/** GDMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ +#define GDMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH1_M (GDMA_INFIFO_EMPTY_CH1_V << GDMA_INFIFO_EMPTY_CH1_S) +#define GDMA_INFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH1_S 1 +/** GDMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. + */ +#define GDMA_INFIFO_CNT_CH1 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_M (GDMA_INFIFO_CNT_CH1_V << GDMA_INFIFO_CNT_CH1_S) +#define GDMA_INFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_M (GDMA_IN_REMAIN_UNDER_1B_CH1_V << GDMA_IN_REMAIN_UNDER_1B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_M (GDMA_IN_REMAIN_UNDER_2B_CH1_V << GDMA_IN_REMAIN_UNDER_2B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_M (GDMA_IN_REMAIN_UNDER_3B_CH1_V << GDMA_IN_REMAIN_UNDER_3B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_M (GDMA_IN_REMAIN_UNDER_4B_CH1_V << GDMA_IN_REMAIN_UNDER_4B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/** GDMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH1_M (GDMA_IN_BUF_HUNGRY_CH1_V << GDMA_IN_BUF_HUNGRY_CH1_S) +#define GDMA_IN_BUF_HUNGRY_CH1_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH1_S 27 + +/** GDMA_IN_POP_CH1_REG register + * Pop control register of Rx channel 1 + */ +#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) +/** GDMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH1 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_M (GDMA_INFIFO_RDATA_CH1_V << GDMA_INFIFO_RDATA_CH1_S) +#define GDMA_INFIFO_RDATA_CH1_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_S 0 +/** GDMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ +#define GDMA_INFIFO_POP_CH1 (BIT(12)) +#define GDMA_INFIFO_POP_CH1_M (GDMA_INFIFO_POP_CH1_V << GDMA_INFIFO_POP_CH1_S) +#define GDMA_INFIFO_POP_CH1_V 0x00000001U +#define GDMA_INFIFO_POP_CH1_S 12 + +/** GDMA_IN_LINK_CH1_REG register + * Link descriptor configure and control register of Rx channel 1 + */ +#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) +/** GDMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_M (GDMA_INLINK_ADDR_CH1_V << GDMA_INLINK_ADDR_CH1_S) +#define GDMA_INLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_S 0 +/** GDMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH1_M (GDMA_INLINK_AUTO_RET_CH1_V << GDMA_INLINK_AUTO_RET_CH1_S) +#define GDMA_INLINK_AUTO_RET_CH1_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH1_S 20 +/** GDMA_INLINK_STOP_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH1 (BIT(21)) +#define GDMA_INLINK_STOP_CH1_M (GDMA_INLINK_STOP_CH1_V << GDMA_INLINK_STOP_CH1_S) +#define GDMA_INLINK_STOP_CH1_V 0x00000001U +#define GDMA_INLINK_STOP_CH1_S 21 +/** GDMA_INLINK_START_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH1 (BIT(22)) +#define GDMA_INLINK_START_CH1_M (GDMA_INLINK_START_CH1_V << GDMA_INLINK_START_CH1_S) +#define GDMA_INLINK_START_CH1_V 0x00000001U +#define GDMA_INLINK_START_CH1_S 22 +/** GDMA_INLINK_RESTART_CH1 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH1 (BIT(23)) +#define GDMA_INLINK_RESTART_CH1_M (GDMA_INLINK_RESTART_CH1_V << GDMA_INLINK_RESTART_CH1_S) +#define GDMA_INLINK_RESTART_CH1_V 0x00000001U +#define GDMA_INLINK_RESTART_CH1_S 23 +/** GDMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH1 (BIT(24)) +#define GDMA_INLINK_PARK_CH1_M (GDMA_INLINK_PARK_CH1_V << GDMA_INLINK_PARK_CH1_S) +#define GDMA_INLINK_PARK_CH1_V 0x00000001U +#define GDMA_INLINK_PARK_CH1_S 24 + +/** GDMA_IN_STATE_CH1_REG register + * Receive status of Rx channel 1 + */ +#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) +/** GDMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_M (GDMA_INLINK_DSCR_ADDR_CH1_V << GDMA_INLINK_DSCR_ADDR_CH1_S) +#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH1 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_M (GDMA_IN_DSCR_STATE_CH1_V << GDMA_IN_DSCR_STATE_CH1_S) +#define GDMA_IN_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_S 18 +/** GDMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH1 0x00000007U +#define GDMA_IN_STATE_CH1_M (GDMA_IN_STATE_CH1_V << GDMA_IN_STATE_CH1_S) +#define GDMA_IN_STATE_CH1_V 0x00000007U +#define GDMA_IN_STATE_CH1_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when EOF occurs of Rx channel 1 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M (GDMA_IN_SUC_EOF_DES_ADDR_CH1_V << GDMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when errors occur of Rx channel 1 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M (GDMA_IN_ERR_EOF_DES_ADDR_CH1_V << GDMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_DSCR_CH1_REG register + * Current inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) +/** GDMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_M (GDMA_INLINK_DSCR_CH1_V << GDMA_INLINK_DSCR_CH1_S) +#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_S 0 + +/** GDMA_IN_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) +/** GDMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_M (GDMA_INLINK_DSCR_BF0_CH1_V << GDMA_INLINK_DSCR_BF0_CH1_S) +#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_IN_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Rx channel 1 + */ +#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) +/** GDMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_M (GDMA_INLINK_DSCR_BF1_CH1_V << GDMA_INLINK_DSCR_BF1_CH1_S) +#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_IN_PRI_CH1_REG register + * Priority register of Rx channel 1 + */ +#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) +/** GDMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH1 0x0000000FU +#define GDMA_RX_PRI_CH1_M (GDMA_RX_PRI_CH1_V << GDMA_RX_PRI_CH1_S) +#define GDMA_RX_PRI_CH1_V 0x0000000FU +#define GDMA_RX_PRI_CH1_S 0 + +/** GDMA_IN_PERI_SEL_CH1_REG register + * Peripheral selection of Rx channel 1 + */ +#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) +/** GDMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH1 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_M (GDMA_PERI_IN_SEL_CH1_V << GDMA_PERI_IN_SEL_CH1_S) +#define GDMA_PERI_IN_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_S 0 + +/** GDMA_OUT_CONF0_CH1_REG register + * Configure 0 register of Tx channel 1 + */ +#define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) +/** GDMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH1 (BIT(0)) +#define GDMA_OUT_RST_CH1_M (GDMA_OUT_RST_CH1_V << GDMA_OUT_RST_CH1_S) +#define GDMA_OUT_RST_CH1_V 0x00000001U +#define GDMA_OUT_RST_CH1_S 0 +/** GDMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_M (GDMA_OUT_LOOP_TEST_CH1_V << GDMA_OUT_LOOP_TEST_CH1_S) +#define GDMA_OUT_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH1_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_M (GDMA_OUT_AUTO_WRBACK_CH1_V << GDMA_OUT_AUTO_WRBACK_CH1_S) +#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH1_S 2 +/** GDMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_M (GDMA_OUT_EOF_MODE_CH1_V << GDMA_OUT_EOF_MODE_CH1_S) +#define GDMA_OUT_EOF_MODE_CH1_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH1_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_M (GDMA_OUTDSCR_BURST_EN_CH1_V << GDMA_OUTDSCR_BURST_EN_CH1_S) +#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH1_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH1_M (GDMA_OUT_DATA_BURST_EN_CH1_V << GDMA_OUT_DATA_BURST_EN_CH1_S) +#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH1_S 5 +/** GDMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH1 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH1_M (GDMA_OUT_ETM_EN_CH1_V << GDMA_OUT_ETM_EN_CH1_S) +#define GDMA_OUT_ETM_EN_CH1_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH1_S 6 + +/** GDMA_OUT_CONF1_CH1_REG register + * Configure 1 register of Tx channel 1 + */ +#define GDMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) +/** GDMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_M (GDMA_OUT_CHECK_OWNER_CH1_V << GDMA_OUT_CHECK_OWNER_CH1_S) +#define GDMA_OUT_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH1_S 12 + +/** GDMA_OUTFIFO_STATUS_CH1_REG register + * Transmit FIFO status of Tx channel 1 + */ +#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) +/** GDMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH1_M (GDMA_OUTFIFO_FULL_CH1_V << GDMA_OUTFIFO_FULL_CH1_S) +#define GDMA_OUTFIFO_FULL_CH1_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH1_S 0 +/** GDMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH1_M (GDMA_OUTFIFO_EMPTY_CH1_V << GDMA_OUTFIFO_EMPTY_CH1_S) +#define GDMA_OUTFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH1_S 1 +/** GDMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + */ +#define GDMA_OUTFIFO_CNT_CH1 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_M (GDMA_OUTFIFO_CNT_CH1_V << GDMA_OUTFIFO_CNT_CH1_S) +#define GDMA_OUTFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_M (GDMA_OUT_REMAIN_UNDER_1B_CH1_V << GDMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_M (GDMA_OUT_REMAIN_UNDER_2B_CH1_V << GDMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_M (GDMA_OUT_REMAIN_UNDER_3B_CH1_V << GDMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_M (GDMA_OUT_REMAIN_UNDER_4B_CH1_V << GDMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/** GDMA_OUT_PUSH_CH1_REG register + * Push control register of Rx channel 1 + */ +#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) +/** GDMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH1 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_M (GDMA_OUTFIFO_WDATA_CH1_V << GDMA_OUTFIFO_WDATA_CH1_S) +#define GDMA_OUTFIFO_WDATA_CH1_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_S 0 +/** GDMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_M (GDMA_OUTFIFO_PUSH_CH1_V << GDMA_OUTFIFO_PUSH_CH1_S) +#define GDMA_OUTFIFO_PUSH_CH1_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH1_S 9 + +/** GDMA_OUT_LINK_CH1_REG register + * Link descriptor configure and control register of Tx channel 1 + */ +#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) +/** GDMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_M (GDMA_OUTLINK_ADDR_CH1_V << GDMA_OUTLINK_ADDR_CH1_S) +#define GDMA_OUTLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_S 0 +/** GDMA_OUTLINK_STOP_CH1 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH1 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH1_M (GDMA_OUTLINK_STOP_CH1_V << GDMA_OUTLINK_STOP_CH1_S) +#define GDMA_OUTLINK_STOP_CH1_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH1_S 20 +/** GDMA_OUTLINK_START_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH1 (BIT(21)) +#define GDMA_OUTLINK_START_CH1_M (GDMA_OUTLINK_START_CH1_V << GDMA_OUTLINK_START_CH1_S) +#define GDMA_OUTLINK_START_CH1_V 0x00000001U +#define GDMA_OUTLINK_START_CH1_S 21 +/** GDMA_OUTLINK_RESTART_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH1_M (GDMA_OUTLINK_RESTART_CH1_V << GDMA_OUTLINK_RESTART_CH1_S) +#define GDMA_OUTLINK_RESTART_CH1_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH1_S 22 +/** GDMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH1 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH1_M (GDMA_OUTLINK_PARK_CH1_V << GDMA_OUTLINK_PARK_CH1_S) +#define GDMA_OUTLINK_PARK_CH1_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH1_S 23 + +/** GDMA_OUT_STATE_CH1_REG register + * Transmit status of Tx channel 1 + */ +#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) +/** GDMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_M (GDMA_OUTLINK_DSCR_ADDR_CH1_V << GDMA_OUTLINK_DSCR_ADDR_CH1_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH1 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_M (GDMA_OUT_DSCR_STATE_CH1_V << GDMA_OUT_DSCR_STATE_CH1_S) +#define GDMA_OUT_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_S 18 +/** GDMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH1 0x00000007U +#define GDMA_OUT_STATE_CH1_M (GDMA_OUT_STATE_CH1_V << GDMA_OUT_STATE_CH1_S) +#define GDMA_OUT_STATE_CH1_V 0x00000007U +#define GDMA_OUT_STATE_CH1_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH1_REG register + * Outlink descriptor address when EOF occurs of Tx channel 1 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) +/** GDMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_M (GDMA_OUT_EOF_DES_ADDR_CH1_V << GDMA_OUT_EOF_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 1 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_DSCR_CH1_REG register + * Current inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) +/** GDMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_M (GDMA_OUTLINK_DSCR_CH1_V << GDMA_OUTLINK_DSCR_CH1_S) +#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_S 0 + +/** GDMA_OUT_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) +/** GDMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_M (GDMA_OUTLINK_DSCR_BF0_CH1_V << GDMA_OUTLINK_DSCR_BF0_CH1_S) +#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_OUT_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Tx channel 1 + */ +#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) +/** GDMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_M (GDMA_OUTLINK_DSCR_BF1_CH1_V << GDMA_OUTLINK_DSCR_BF1_CH1_S) +#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_OUT_PRI_CH1_REG register + * Priority register of Tx channel 1 + */ +#define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) +/** GDMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH1 0x0000000FU +#define GDMA_TX_PRI_CH1_M (GDMA_TX_PRI_CH1_V << GDMA_TX_PRI_CH1_S) +#define GDMA_TX_PRI_CH1_V 0x0000000FU +#define GDMA_TX_PRI_CH1_S 0 + +/** GDMA_OUT_PERI_SEL_CH1_REG register + * Peripheral selection of Tx channel 1 + */ +#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) +/** GDMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH1 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_M (GDMA_PERI_OUT_SEL_CH1_V << GDMA_PERI_OUT_SEL_CH1_S) +#define GDMA_PERI_OUT_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_S 0 + +/** GDMA_IN_CONF0_CH2_REG register + * Configure 0 register of Rx channel 2 + */ +#define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) +/** GDMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH2 (BIT(0)) +#define GDMA_IN_RST_CH2_M (GDMA_IN_RST_CH2_V << GDMA_IN_RST_CH2_S) +#define GDMA_IN_RST_CH2_V 0x00000001U +#define GDMA_IN_RST_CH2_S 0 +/** GDMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH2_M (GDMA_IN_LOOP_TEST_CH2_V << GDMA_IN_LOOP_TEST_CH2_S) +#define GDMA_IN_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH2_S 1 +/** GDMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH2_M (GDMA_INDSCR_BURST_EN_CH2_V << GDMA_INDSCR_BURST_EN_CH2_S) +#define GDMA_INDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH2_S 2 +/** GDMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH2_M (GDMA_IN_DATA_BURST_EN_CH2_V << GDMA_IN_DATA_BURST_EN_CH2_S) +#define GDMA_IN_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH2_S 3 +/** GDMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH2_M (GDMA_MEM_TRANS_EN_CH2_V << GDMA_MEM_TRANS_EN_CH2_S) +#define GDMA_MEM_TRANS_EN_CH2_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH2_S 4 +/** GDMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 2 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH2 (BIT(5)) +#define GDMA_IN_ETM_EN_CH2_M (GDMA_IN_ETM_EN_CH2_V << GDMA_IN_ETM_EN_CH2_S) +#define GDMA_IN_ETM_EN_CH2_V 0x00000001U +#define GDMA_IN_ETM_EN_CH2_S 5 + +/** GDMA_IN_CONF1_CH2_REG register + * Configure 1 register of Rx channel 2 + */ +#define GDMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) +/** GDMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH2_M (GDMA_IN_CHECK_OWNER_CH2_V << GDMA_IN_CHECK_OWNER_CH2_S) +#define GDMA_IN_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH2_S 12 + +/** GDMA_INFIFO_STATUS_CH2_REG register + * Receive FIFO status of Rx channel 2 + */ +#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) +/** GDMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ +#define GDMA_INFIFO_FULL_CH2 (BIT(0)) +#define GDMA_INFIFO_FULL_CH2_M (GDMA_INFIFO_FULL_CH2_V << GDMA_INFIFO_FULL_CH2_S) +#define GDMA_INFIFO_FULL_CH2_V 0x00000001U +#define GDMA_INFIFO_FULL_CH2_S 0 +/** GDMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ +#define GDMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH2_M (GDMA_INFIFO_EMPTY_CH2_V << GDMA_INFIFO_EMPTY_CH2_S) +#define GDMA_INFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH2_S 1 +/** GDMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. + */ +#define GDMA_INFIFO_CNT_CH2 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_M (GDMA_INFIFO_CNT_CH2_V << GDMA_INFIFO_CNT_CH2_S) +#define GDMA_INFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_M (GDMA_IN_REMAIN_UNDER_1B_CH2_V << GDMA_IN_REMAIN_UNDER_1B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_M (GDMA_IN_REMAIN_UNDER_2B_CH2_V << GDMA_IN_REMAIN_UNDER_2B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_M (GDMA_IN_REMAIN_UNDER_3B_CH2_V << GDMA_IN_REMAIN_UNDER_3B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_M (GDMA_IN_REMAIN_UNDER_4B_CH2_V << GDMA_IN_REMAIN_UNDER_4B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH2_S 26 +/** GDMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH2_M (GDMA_IN_BUF_HUNGRY_CH2_V << GDMA_IN_BUF_HUNGRY_CH2_S) +#define GDMA_IN_BUF_HUNGRY_CH2_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH2_S 27 + +/** GDMA_IN_POP_CH2_REG register + * Pop control register of Rx channel 2 + */ +#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) +/** GDMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH2 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_M (GDMA_INFIFO_RDATA_CH2_V << GDMA_INFIFO_RDATA_CH2_S) +#define GDMA_INFIFO_RDATA_CH2_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_S 0 +/** GDMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ +#define GDMA_INFIFO_POP_CH2 (BIT(12)) +#define GDMA_INFIFO_POP_CH2_M (GDMA_INFIFO_POP_CH2_V << GDMA_INFIFO_POP_CH2_S) +#define GDMA_INFIFO_POP_CH2_V 0x00000001U +#define GDMA_INFIFO_POP_CH2_S 12 + +/** GDMA_IN_LINK_CH2_REG register + * Link descriptor configure and control register of Rx channel 2 + */ +#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) +/** GDMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_M (GDMA_INLINK_ADDR_CH2_V << GDMA_INLINK_ADDR_CH2_S) +#define GDMA_INLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_S 0 +/** GDMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH2_M (GDMA_INLINK_AUTO_RET_CH2_V << GDMA_INLINK_AUTO_RET_CH2_S) +#define GDMA_INLINK_AUTO_RET_CH2_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH2_S 20 +/** GDMA_INLINK_STOP_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH2 (BIT(21)) +#define GDMA_INLINK_STOP_CH2_M (GDMA_INLINK_STOP_CH2_V << GDMA_INLINK_STOP_CH2_S) +#define GDMA_INLINK_STOP_CH2_V 0x00000001U +#define GDMA_INLINK_STOP_CH2_S 21 +/** GDMA_INLINK_START_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH2 (BIT(22)) +#define GDMA_INLINK_START_CH2_M (GDMA_INLINK_START_CH2_V << GDMA_INLINK_START_CH2_S) +#define GDMA_INLINK_START_CH2_V 0x00000001U +#define GDMA_INLINK_START_CH2_S 22 +/** GDMA_INLINK_RESTART_CH2 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH2 (BIT(23)) +#define GDMA_INLINK_RESTART_CH2_M (GDMA_INLINK_RESTART_CH2_V << GDMA_INLINK_RESTART_CH2_S) +#define GDMA_INLINK_RESTART_CH2_V 0x00000001U +#define GDMA_INLINK_RESTART_CH2_S 23 +/** GDMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH2 (BIT(24)) +#define GDMA_INLINK_PARK_CH2_M (GDMA_INLINK_PARK_CH2_V << GDMA_INLINK_PARK_CH2_S) +#define GDMA_INLINK_PARK_CH2_V 0x00000001U +#define GDMA_INLINK_PARK_CH2_S 24 + +/** GDMA_IN_STATE_CH2_REG register + * Receive status of Rx channel 2 + */ +#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) +/** GDMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_M (GDMA_INLINK_DSCR_ADDR_CH2_V << GDMA_INLINK_DSCR_ADDR_CH2_S) +#define GDMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH2 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_M (GDMA_IN_DSCR_STATE_CH2_V << GDMA_IN_DSCR_STATE_CH2_S) +#define GDMA_IN_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_S 18 +/** GDMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH2 0x00000007U +#define GDMA_IN_STATE_CH2_M (GDMA_IN_STATE_CH2_V << GDMA_IN_STATE_CH2_S) +#define GDMA_IN_STATE_CH2_V 0x00000007U +#define GDMA_IN_STATE_CH2_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when EOF occurs of Rx channel 2 + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M (GDMA_IN_SUC_EOF_DES_ADDR_CH2_V << GDMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when errors occur of Rx channel 2 + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M (GDMA_IN_ERR_EOF_DES_ADDR_CH2_V << GDMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_DSCR_CH2_REG register + * Current inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) +/** GDMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_M (GDMA_INLINK_DSCR_CH2_V << GDMA_INLINK_DSCR_CH2_S) +#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_S 0 + +/** GDMA_IN_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) +/** GDMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_M (GDMA_INLINK_DSCR_BF0_CH2_V << GDMA_INLINK_DSCR_BF0_CH2_S) +#define GDMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_IN_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Rx channel 2 + */ +#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) +/** GDMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_M (GDMA_INLINK_DSCR_BF1_CH2_V << GDMA_INLINK_DSCR_BF1_CH2_S) +#define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_IN_PRI_CH2_REG register + * Priority register of Rx channel 2 + */ +#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) +/** GDMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH2 0x0000000FU +#define GDMA_RX_PRI_CH2_M (GDMA_RX_PRI_CH2_V << GDMA_RX_PRI_CH2_S) +#define GDMA_RX_PRI_CH2_V 0x0000000FU +#define GDMA_RX_PRI_CH2_S 0 + +/** GDMA_IN_PERI_SEL_CH2_REG register + * Peripheral selection of Rx channel 2 + */ +#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) +/** GDMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH2 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_M (GDMA_PERI_IN_SEL_CH2_V << GDMA_PERI_IN_SEL_CH2_S) +#define GDMA_PERI_IN_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_S 0 + +/** GDMA_OUT_CONF0_CH2_REG register + * Configure 0 register of Tx channel 2 + */ +#define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) +/** GDMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH2 (BIT(0)) +#define GDMA_OUT_RST_CH2_M (GDMA_OUT_RST_CH2_V << GDMA_OUT_RST_CH2_S) +#define GDMA_OUT_RST_CH2_V 0x00000001U +#define GDMA_OUT_RST_CH2_S 0 +/** GDMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH2_M (GDMA_OUT_LOOP_TEST_CH2_V << GDMA_OUT_LOOP_TEST_CH2_S) +#define GDMA_OUT_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH2_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH2_M (GDMA_OUT_AUTO_WRBACK_CH2_V << GDMA_OUT_AUTO_WRBACK_CH2_S) +#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH2_S 2 +/** GDMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH2_M (GDMA_OUT_EOF_MODE_CH2_V << GDMA_OUT_EOF_MODE_CH2_S) +#define GDMA_OUT_EOF_MODE_CH2_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH2_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH2_M (GDMA_OUTDSCR_BURST_EN_CH2_V << GDMA_OUTDSCR_BURST_EN_CH2_S) +#define GDMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH2_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH2_M (GDMA_OUT_DATA_BURST_EN_CH2_V << GDMA_OUT_DATA_BURST_EN_CH2_S) +#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH2_S 5 +/** GDMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 2 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH2 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH2_M (GDMA_OUT_ETM_EN_CH2_V << GDMA_OUT_ETM_EN_CH2_S) +#define GDMA_OUT_ETM_EN_CH2_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH2_S 6 + +/** GDMA_OUT_CONF1_CH2_REG register + * Configure 1 register of Tx channel 2 + */ +#define GDMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) +/** GDMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH2_M (GDMA_OUT_CHECK_OWNER_CH2_V << GDMA_OUT_CHECK_OWNER_CH2_S) +#define GDMA_OUT_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH2_S 12 + +/** GDMA_OUTFIFO_STATUS_CH2_REG register + * Transmit FIFO status of Tx channel 2 + */ +#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) +/** GDMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH2_M (GDMA_OUTFIFO_FULL_CH2_V << GDMA_OUTFIFO_FULL_CH2_S) +#define GDMA_OUTFIFO_FULL_CH2_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH2_S 0 +/** GDMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH2_M (GDMA_OUTFIFO_EMPTY_CH2_V << GDMA_OUTFIFO_EMPTY_CH2_S) +#define GDMA_OUTFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH2_S 1 +/** GDMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. + */ +#define GDMA_OUTFIFO_CNT_CH2 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_M (GDMA_OUTFIFO_CNT_CH2_V << GDMA_OUTFIFO_CNT_CH2_S) +#define GDMA_OUTFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_M (GDMA_OUT_REMAIN_UNDER_1B_CH2_V << GDMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_M (GDMA_OUT_REMAIN_UNDER_2B_CH2_V << GDMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_M (GDMA_OUT_REMAIN_UNDER_3B_CH2_V << GDMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_M (GDMA_OUT_REMAIN_UNDER_4B_CH2_V << GDMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/** GDMA_OUT_PUSH_CH2_REG register + * Push control register of Rx channel 2 + */ +#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) +/** GDMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH2 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_M (GDMA_OUTFIFO_WDATA_CH2_V << GDMA_OUTFIFO_WDATA_CH2_S) +#define GDMA_OUTFIFO_WDATA_CH2_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_S 0 +/** GDMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH2_M (GDMA_OUTFIFO_PUSH_CH2_V << GDMA_OUTFIFO_PUSH_CH2_S) +#define GDMA_OUTFIFO_PUSH_CH2_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH2_S 9 + +/** GDMA_OUT_LINK_CH2_REG register + * Link descriptor configure and control register of Tx channel 2 + */ +#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) +/** GDMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_M (GDMA_OUTLINK_ADDR_CH2_V << GDMA_OUTLINK_ADDR_CH2_S) +#define GDMA_OUTLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_S 0 +/** GDMA_OUTLINK_STOP_CH2 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH2 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH2_M (GDMA_OUTLINK_STOP_CH2_V << GDMA_OUTLINK_STOP_CH2_S) +#define GDMA_OUTLINK_STOP_CH2_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH2_S 20 +/** GDMA_OUTLINK_START_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH2 (BIT(21)) +#define GDMA_OUTLINK_START_CH2_M (GDMA_OUTLINK_START_CH2_V << GDMA_OUTLINK_START_CH2_S) +#define GDMA_OUTLINK_START_CH2_V 0x00000001U +#define GDMA_OUTLINK_START_CH2_S 21 +/** GDMA_OUTLINK_RESTART_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH2_M (GDMA_OUTLINK_RESTART_CH2_V << GDMA_OUTLINK_RESTART_CH2_S) +#define GDMA_OUTLINK_RESTART_CH2_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH2_S 22 +/** GDMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH2 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH2_M (GDMA_OUTLINK_PARK_CH2_V << GDMA_OUTLINK_PARK_CH2_S) +#define GDMA_OUTLINK_PARK_CH2_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH2_S 23 + +/** GDMA_OUT_STATE_CH2_REG register + * Transmit status of Tx channel 2 + */ +#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) +/** GDMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_M (GDMA_OUTLINK_DSCR_ADDR_CH2_V << GDMA_OUTLINK_DSCR_ADDR_CH2_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH2 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_M (GDMA_OUT_DSCR_STATE_CH2_V << GDMA_OUT_DSCR_STATE_CH2_S) +#define GDMA_OUT_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_S 18 +/** GDMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH2 0x00000007U +#define GDMA_OUT_STATE_CH2_M (GDMA_OUT_STATE_CH2_V << GDMA_OUT_STATE_CH2_S) +#define GDMA_OUT_STATE_CH2_V 0x00000007U +#define GDMA_OUT_STATE_CH2_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH2_REG register + * Outlink descriptor address when EOF occurs of Tx channel 2 + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) +/** GDMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_M (GDMA_OUT_EOF_DES_ADDR_CH2_V << GDMA_OUT_EOF_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 2 + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_DSCR_CH2_REG register + * Current inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) +/** GDMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_M (GDMA_OUTLINK_DSCR_CH2_V << GDMA_OUTLINK_DSCR_CH2_S) +#define GDMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_S 0 + +/** GDMA_OUT_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) +/** GDMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_M (GDMA_OUTLINK_DSCR_BF0_CH2_V << GDMA_OUTLINK_DSCR_BF0_CH2_S) +#define GDMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_OUT_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Tx channel 2 + */ +#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) +/** GDMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_M (GDMA_OUTLINK_DSCR_BF1_CH2_V << GDMA_OUTLINK_DSCR_BF1_CH2_S) +#define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_OUT_PRI_CH2_REG register + * Priority register of Tx channel 2 + */ +#define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) +/** GDMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH2 0x0000000FU +#define GDMA_TX_PRI_CH2_M (GDMA_TX_PRI_CH2_V << GDMA_TX_PRI_CH2_S) +#define GDMA_TX_PRI_CH2_V 0x0000000FU +#define GDMA_TX_PRI_CH2_S 0 + +/** GDMA_OUT_PERI_SEL_CH2_REG register + * Peripheral selection of Tx channel 2 + */ +#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) +/** GDMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH2 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_M (GDMA_PERI_OUT_SEL_CH2_V << GDMA_PERI_OUT_SEL_CH2_S) +#define GDMA_PERI_OUT_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_S 0 + +/** GDMA_BT_TX_SEL_REG register + * Bit scrambler selection + */ +#define GDMA_BT_TX_SEL_REG (DR_REG_GDMA_BASE + 0x284) +/** GDMA_BT_TX_SEL_CH0 : R/W; bitpos: [0]; default: 0; + * This register is used to select wiitch tx channel 0 across bit scrambler module + */ +#define GDMA_BT_TX_SEL_CH0 (BIT(0)) +#define GDMA_BT_TX_SEL_CH0_M (GDMA_BT_TX_SEL_CH0_V << GDMA_BT_TX_SEL_CH0_S) +#define GDMA_BT_TX_SEL_CH0_V 0x00000001U +#define GDMA_BT_TX_SEL_CH0_S 0 +/** GDMA_BT_TX_SEL_CH1 : R/W; bitpos: [1]; default: 0; + * This register is used to select wiitch tx channel 1 across bit scrambler module + */ +#define GDMA_BT_TX_SEL_CH1 (BIT(1)) +#define GDMA_BT_TX_SEL_CH1_M (GDMA_BT_TX_SEL_CH1_V << GDMA_BT_TX_SEL_CH1_S) +#define GDMA_BT_TX_SEL_CH1_V 0x00000001U +#define GDMA_BT_TX_SEL_CH1_S 1 +/** GDMA_BT_TX_SEL_CH2 : R/W; bitpos: [2]; default: 0; + * This register is used to select wiitch tx channel 2 across bit scrambler module + */ +#define GDMA_BT_TX_SEL_CH2 (BIT(2)) +#define GDMA_BT_TX_SEL_CH2_M (GDMA_BT_TX_SEL_CH2_V << GDMA_BT_TX_SEL_CH2_S) +#define GDMA_BT_TX_SEL_CH2_V 0x00000001U +#define GDMA_BT_TX_SEL_CH2_S 2 + +/** GDMA_BT_RX_SEL_REG register + * Bit scrambler selection + */ +#define GDMA_BT_RX_SEL_REG (DR_REG_GDMA_BASE + 0x288) +/** GDMA_BT_RX_SEL_CH0 : R/W; bitpos: [0]; default: 0; + * This register is used to select wiitch rx channel 0 across bit scrambler module + */ +#define GDMA_BT_RX_SEL_CH0 (BIT(0)) +#define GDMA_BT_RX_SEL_CH0_M (GDMA_BT_RX_SEL_CH0_V << GDMA_BT_RX_SEL_CH0_S) +#define GDMA_BT_RX_SEL_CH0_V 0x00000001U +#define GDMA_BT_RX_SEL_CH0_S 0 +/** GDMA_BT_RX_SEL_CH1 : R/W; bitpos: [1]; default: 0; + * This register is used to select wiitch rx channel 1 across bit scrambler module + */ +#define GDMA_BT_RX_SEL_CH1 (BIT(1)) +#define GDMA_BT_RX_SEL_CH1_M (GDMA_BT_RX_SEL_CH1_V << GDMA_BT_RX_SEL_CH1_S) +#define GDMA_BT_RX_SEL_CH1_V 0x00000001U +#define GDMA_BT_RX_SEL_CH1_S 1 +/** GDMA_BT_RX_SEL_CH2 : R/W; bitpos: [2]; default: 0; + * This register is used to select wiitch rx channel 2 across bit scrambler module + */ +#define GDMA_BT_RX_SEL_CH2 (BIT(2)) +#define GDMA_BT_RX_SEL_CH2_M (GDMA_BT_RX_SEL_CH2_V << GDMA_BT_RX_SEL_CH2_S) +#define GDMA_BT_RX_SEL_CH2_V 0x00000001U +#define GDMA_BT_RX_SEL_CH2_S 2 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gdma_struct.h b/components/soc/esp32c5/include/soc/gdma_struct.h new file mode 100644 index 0000000000..c06e41c011 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gdma_struct.h @@ -0,0 +1,2167 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers in */ +/** Type of in_int_raw_chn register + * Raw status interrupt of channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ + uint32_t in_done_chn_int_raw:1; + /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ + uint32_t in_suc_eof_chn_int_raw:1; + /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ + uint32_t in_err_eof_chn_int_raw:1; + /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ + uint32_t in_dscr_err_chn_int_raw:1; + /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ + uint32_t in_dscr_empty_chn_int_raw:1; + /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ + uint32_t infifo_ovf_chn_int_raw:1; + /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ + uint32_t infifo_udf_chn_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_raw_chn_reg_t; + +/** Type of in_int_st_chn register + * Masked interrupt of channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_st:1; + /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_st:1; + /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_st:1; + /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_st:1; + /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_st:1; + /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_st:1; + /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_st_chn_reg_t; + +/** Type of in_int_ena_chn register + * Interrupt enable bits of channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_ena:1; + /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_ena:1; + /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_ena:1; + /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_ena:1; + /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_ena:1; + /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_ena:1; + /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_ena_chn_reg_t; + +/** Type of in_int_clr_chn register + * Interrupt clear bits of channel 0 + */ +typedef union { + struct { + /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_clr:1; + /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_clr:1; + /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_clr:1; + /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_clr:1; + /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_clr:1; + /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_clr:1; + /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_clr_chn_reg_t; + + +/** Group: Interrupt Registers out */ +/** Type of out_int_raw_chn register + * Raw status interrupt of channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ + uint32_t out_done_chn_int_raw:1; + /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ + uint32_t out_eof_chn_int_raw:1; + /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ + uint32_t out_dscr_err_chn_int_raw:1; + /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ + uint32_t out_total_eof_chn_int_raw:1; + /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ + uint32_t outfifo_ovf_chn_int_raw:1; + /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ + uint32_t outfifo_udf_chn_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_raw_chn_reg_t; + +/** Type of out_int_st_chn register + * Masked interrupt of channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_st:1; + /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_st:1; + /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_st:1; + /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_st:1; + /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_st:1; + /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_st_chn_reg_t; + +/** Type of out_int_ena_chn register + * Interrupt enable bits of channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_ena:1; + /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_ena:1; + /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_ena:1; + /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_ena:1; + /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_ena:1; + /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_ena_chn_reg_t; + +/** Type of out_int_clr_chn register + * Interrupt clear bits of channel 0 + */ +typedef union { + struct { + /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_clr:1; + /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_clr:1; + /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_clr:1; + /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_clr:1; + /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_clr:1; + /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_clr_chn_reg_t; + + +/** Group: Debug Registers */ +/** Type of ahb_test register + * reserved + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_ahb_test_reg_t; + + +/** Group: Configuration Registers */ +/** Type of misc_conf register + * MISC register + */ +typedef union { + struct { + /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ + uint32_t ahbm_rst_inter:1; + uint32_t reserved_1:1; + /** arb_pri_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ + uint32_t arb_pri_dis:1; + /** clk_en : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_misc_conf_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 36720912; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} gdma_date_reg_t; + + +/** Group: Configuration Registers0 */ +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel 0 + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en_chn:1; + /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en_chn:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm + * task. + */ + uint32_t in_etm_en_chn:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel 0 + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ + uint32_t infifo_empty_chn:1; + /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ + uint32_t infifo_cnt_chn:6; + uint32_t reserved_8:15; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel 0 + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel 0 + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr_chn:20; + /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel 0 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel 0 + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of in_pri_chn register + * Priority register of Rx channel 0 + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel 0 + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_conf0_ch0 register + * Configure 0 register of Tx channel 0 + */ +typedef union { + struct { + /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_ch0:1; + /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_ch0:1; + /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_ch0:1; + /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_ch0:1; + /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_ch0:1; + /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_ch0:1; + /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + * task. + */ + uint32_t out_etm_en_ch0:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_ch0_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel 0 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel 0 + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ + uint32_t outfifo_empty_chn:1; + /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ + uint32_t outfifo_cnt_chn:6; + uint32_t reserved_8:15; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel 0 + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel 0 + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr_chn:20; + /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel 0 + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel 0 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel 0. + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel 0 + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +/** Group: Configuration Registers1 */ +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel 1 + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en_chn:1; + /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en_chn:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 1 is triggered by etm + * task. + */ + uint32_t in_etm_en_chn:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel 1 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel 1 + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ + uint32_t infifo_empty_chn:1; + /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. + */ + uint32_t infifo_cnt_chn:6; + uint32_t reserved_8:15; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel 1 + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel 1 + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr_chn:20; + /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel 1 + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel 1 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel 1 + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel 1 + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel 1 + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel 1 + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of in_pri_chn register + * Priority register of Rx channel 1 + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value the higher of the priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel 1 + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel 1 + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_chn:1; + /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_chn:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm + * task. + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel 1 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel 1 + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ + uint32_t outfifo_empty_chn:1; + /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + */ + uint32_t outfifo_cnt_chn:6; + uint32_t reserved_8:15; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel 1 + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel 1 + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr_chn:20; + /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel 1 + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel 1 + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel 1 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel 1 + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel 1 + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel 1 + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel 1 + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value the higher of the priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel 1 + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +/** Group: Configuration Registers2 */ +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel 2 + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en_chn:1; + /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en_chn:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel 2 is triggered by etm + * task. + */ + uint32_t in_etm_en_chn:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel 2 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel 2 + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ + uint32_t infifo_empty_chn:1; + /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. + */ + uint32_t infifo_cnt_chn:6; + uint32_t reserved_8:15; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel 2 + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel 2 + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr_chn:20; + /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel 2 + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel 2 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel 2 + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel 2 + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel 2 + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel 2 + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of in_pri_chn register + * Priority register of Rx channel 2 + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value the higher of the priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel 2 + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel 2 + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_chn:1; + /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_chn:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 2 is triggered by etm + * task. + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel 2 + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel 2 + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ + uint32_t outfifo_empty_chn:1; + /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. + */ + uint32_t outfifo_cnt_chn:6; + uint32_t reserved_8:15; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel 2 + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel 2 + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr_chn:20; + /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel 2 + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel 2 + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel 2 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel 2 + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel 2 + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel 2 + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel 2 + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value the higher of the priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel 2 + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +/** Group: Peripheral Select Registers */ +/** Type of bt_tx_sel register + * Bit scrambler selection + */ +typedef union { + struct { + /** bt_tx_sel_ch0 : R/W; bitpos: [0]; default: 0; + * This register is used to select wiitch tx channel 0 across bit scrambler module + */ + uint32_t bt_tx_sel_ch0:1; + /** bt_tx_sel_ch1 : R/W; bitpos: [1]; default: 0; + * This register is used to select wiitch tx channel 1 across bit scrambler module + */ + uint32_t bt_tx_sel_ch1:1; + /** bt_tx_sel_ch2 : R/W; bitpos: [2]; default: 0; + * This register is used to select wiitch tx channel 2 across bit scrambler module + */ + uint32_t bt_tx_sel_ch2:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gdma_bt_tx_sel_reg_t; + +/** Type of bt_rx_sel register + * Bit scrambler selection + */ +typedef union { + struct { + /** bt_rx_sel_ch0 : R/W; bitpos: [0]; default: 0; + * This register is used to select wiitch rx channel 0 across bit scrambler module + */ + uint32_t bt_rx_sel_ch0:1; + /** bt_rx_sel_ch1 : R/W; bitpos: [1]; default: 0; + * This register is used to select wiitch rx channel 1 across bit scrambler module + */ + uint32_t bt_rx_sel_ch1:1; + /** bt_rx_sel_ch2 : R/W; bitpos: [2]; default: 0; + * This register is used to select wiitch rx channel 2 across bit scrambler module + */ + uint32_t bt_rx_sel_ch2:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} gdma_bt_rx_sel_reg_t; + + +typedef struct { + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch0; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch1; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch2; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch2; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch2; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch2; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch0; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch1; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch2; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch2; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch2; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch2; + volatile gdma_ahb_test_reg_t ahb_test; + volatile gdma_misc_conf_reg_t misc_conf; + volatile gdma_date_reg_t date; + uint32_t reserved_06c; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch0; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch0; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch0; + volatile gdma_in_pop_chn_reg_t in_pop_ch0; + volatile gdma_in_link_chn_reg_t in_link_ch0; + volatile gdma_in_state_chn_reg_t in_state_ch0; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch0; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; + volatile gdma_in_pri_chn_reg_t in_pri_ch0; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; + uint32_t reserved_0a4[11]; + volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; + volatile gdma_out_push_chn_reg_t out_push_ch0; + volatile gdma_out_link_chn_reg_t out_link_ch0; + volatile gdma_out_state_chn_reg_t out_state_ch0; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch0; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; + volatile gdma_out_pri_chn_reg_t out_pri_ch0; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0; + uint32_t reserved_104[11]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch1; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch1; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch1; + volatile gdma_in_pop_chn_reg_t in_pop_ch1; + volatile gdma_in_link_chn_reg_t in_link_ch1; + volatile gdma_in_state_chn_reg_t in_state_ch1; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch1; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; + volatile gdma_in_pri_chn_reg_t in_pri_ch1; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1; + uint32_t reserved_164[11]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch1; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1; + volatile gdma_out_push_chn_reg_t out_push_ch1; + volatile gdma_out_link_chn_reg_t out_link_ch1; + volatile gdma_out_state_chn_reg_t out_state_ch1; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch1; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; + volatile gdma_out_pri_chn_reg_t out_pri_ch1; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1; + uint32_t reserved_1c4[11]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch2; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch2; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch2; + volatile gdma_in_pop_chn_reg_t in_pop_ch2; + volatile gdma_in_link_chn_reg_t in_link_ch2; + volatile gdma_in_state_chn_reg_t in_state_ch2; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch2; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; + volatile gdma_in_pri_chn_reg_t in_pri_ch2; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch2; + uint32_t reserved_224[11]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch2; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch2; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch2; + volatile gdma_out_push_chn_reg_t out_push_ch2; + volatile gdma_out_link_chn_reg_t out_link_ch2; + volatile gdma_out_state_chn_reg_t out_state_ch2; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch2; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; + volatile gdma_out_pri_chn_reg_t out_pri_ch2; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch2; + volatile gdma_bt_tx_sel_reg_t bt_tx_sel; + volatile gdma_bt_rx_sel_reg_t bt_rx_sel; +} gdma_dev_t; + +extern gdma_dev_t GDMA; + +#ifndef __cplusplus +_Static_assert(sizeof(gdma_dev_t) == 0x28c, "Invalid size of gdma_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_ext_reg.h b/components/soc/esp32c5/include/soc/gpio_ext_reg.h new file mode 100644 index 0000000000..0f28c35315 --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_ext_reg.h @@ -0,0 +1,1102 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GPIO_EXT_SIGMADELTA0_REG register + * Duty Cycle Configure Register of SDM0 + */ +#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0) +/** GPIO_EXT_SD0_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_EXT_SD0_IN 0x000000FFU +#define GPIO_EXT_SD0_IN_M (GPIO_EXT_SD0_IN_V << GPIO_EXT_SD0_IN_S) +#define GPIO_EXT_SD0_IN_V 0x000000FFU +#define GPIO_EXT_SD0_IN_S 0 +/** GPIO_EXT_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_EXT_SD0_PRESCALE 0x000000FFU +#define GPIO_EXT_SD0_PRESCALE_M (GPIO_EXT_SD0_PRESCALE_V << GPIO_EXT_SD0_PRESCALE_S) +#define GPIO_EXT_SD0_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD0_PRESCALE_S 8 + +/** GPIO_EXT_SIGMADELTA1_REG register + * Duty Cycle Configure Register of SDM1 + */ +#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4) +/** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_EXT_SD1_IN 0x000000FFU +#define GPIO_EXT_SD1_IN_M (GPIO_EXT_SD1_IN_V << GPIO_EXT_SD1_IN_S) +#define GPIO_EXT_SD1_IN_V 0x000000FFU +#define GPIO_EXT_SD1_IN_S 0 +/** GPIO_EXT_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_EXT_SD1_PRESCALE 0x000000FFU +#define GPIO_EXT_SD1_PRESCALE_M (GPIO_EXT_SD1_PRESCALE_V << GPIO_EXT_SD1_PRESCALE_S) +#define GPIO_EXT_SD1_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD1_PRESCALE_S 8 + +/** GPIO_EXT_SIGMADELTA2_REG register + * Duty Cycle Configure Register of SDM2 + */ +#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8) +/** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_EXT_SD2_IN 0x000000FFU +#define GPIO_EXT_SD2_IN_M (GPIO_EXT_SD2_IN_V << GPIO_EXT_SD2_IN_S) +#define GPIO_EXT_SD2_IN_V 0x000000FFU +#define GPIO_EXT_SD2_IN_S 0 +/** GPIO_EXT_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_EXT_SD2_PRESCALE 0x000000FFU +#define GPIO_EXT_SD2_PRESCALE_M (GPIO_EXT_SD2_PRESCALE_V << GPIO_EXT_SD2_PRESCALE_S) +#define GPIO_EXT_SD2_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD2_PRESCALE_S 8 + +/** GPIO_EXT_SIGMADELTA3_REG register + * Duty Cycle Configure Register of SDM3 + */ +#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc) +/** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0; + * This field is used to configure the duty cycle of sigma delta modulation output. + */ +#define GPIO_EXT_SD3_IN 0x000000FFU +#define GPIO_EXT_SD3_IN_M (GPIO_EXT_SD3_IN_V << GPIO_EXT_SD3_IN_S) +#define GPIO_EXT_SD3_IN_V 0x000000FFU +#define GPIO_EXT_SD3_IN_S 0 +/** GPIO_EXT_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255; + * This field is used to set a divider value to divide APB clock. + */ +#define GPIO_EXT_SD3_PRESCALE 0x000000FFU +#define GPIO_EXT_SD3_PRESCALE_M (GPIO_EXT_SD3_PRESCALE_V << GPIO_EXT_SD3_PRESCALE_S) +#define GPIO_EXT_SD3_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD3_PRESCALE_S 8 + +/** GPIO_EXT_SIGMADELTA_MISC_REG register + * MISC Register + */ +#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24) +/** GPIO_EXT_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; + * Clock enable bit of sigma delta modulation. + */ +#define GPIO_EXT_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_EXT_FUNCTION_CLK_EN_M (GPIO_EXT_FUNCTION_CLK_EN_V << GPIO_EXT_FUNCTION_CLK_EN_S) +#define GPIO_EXT_FUNCTION_CLK_EN_V 0x00000001U +#define GPIO_EXT_FUNCTION_CLK_EN_S 30 +/** GPIO_EXT_SPI_SWAP : R/W; bitpos: [31]; default: 0; + * Reserved. + */ +#define GPIO_EXT_SPI_SWAP (BIT(31)) +#define GPIO_EXT_SPI_SWAP_M (GPIO_EXT_SPI_SWAP_V << GPIO_EXT_SPI_SWAP_S) +#define GPIO_EXT_SPI_SWAP_V 0x00000001U +#define GPIO_EXT_SPI_SWAP_S 31 + +/** GPIO_EXT_PAD_COMP_CONFIG_REG register + * PAD Compare configure Register + */ +#define GPIO_EXT_PAD_COMP_CONFIG_REG (DR_REG_GPIO_EXT_BASE + 0x28) +/** GPIO_EXT_XPD_COMP : R/W; bitpos: [0]; default: 0; + * Pad compare enable bit. + */ +#define GPIO_EXT_XPD_COMP (BIT(0)) +#define GPIO_EXT_XPD_COMP_M (GPIO_EXT_XPD_COMP_V << GPIO_EXT_XPD_COMP_S) +#define GPIO_EXT_XPD_COMP_V 0x00000001U +#define GPIO_EXT_XPD_COMP_S 0 +/** GPIO_EXT_MODE_COMP : R/W; bitpos: [1]; default: 0; + * 1 to enable external reference from PAD[0]. 0 to enable internal reference, + * meanwhile PAD[0] can be used as a regular GPIO. + */ +#define GPIO_EXT_MODE_COMP (BIT(1)) +#define GPIO_EXT_MODE_COMP_M (GPIO_EXT_MODE_COMP_V << GPIO_EXT_MODE_COMP_S) +#define GPIO_EXT_MODE_COMP_V 0x00000001U +#define GPIO_EXT_MODE_COMP_S 1 +/** GPIO_EXT_DREF_COMP : R/W; bitpos: [4:2]; default: 0; + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + */ +#define GPIO_EXT_DREF_COMP 0x00000007U +#define GPIO_EXT_DREF_COMP_M (GPIO_EXT_DREF_COMP_V << GPIO_EXT_DREF_COMP_S) +#define GPIO_EXT_DREF_COMP_V 0x00000007U +#define GPIO_EXT_DREF_COMP_S 2 +/** GPIO_EXT_ZERO_DET_MODE : R/W; bitpos: [6:5]; default: 0; + * Zero Detect mode select. + */ +#define GPIO_EXT_ZERO_DET_MODE 0x00000003U +#define GPIO_EXT_ZERO_DET_MODE_M (GPIO_EXT_ZERO_DET_MODE_V << GPIO_EXT_ZERO_DET_MODE_S) +#define GPIO_EXT_ZERO_DET_MODE_V 0x00000003U +#define GPIO_EXT_ZERO_DET_MODE_S 5 + +/** GPIO_EXT_PAD_COMP_FILTER_REG register + * Zero Detect filter Register + */ +#define GPIO_EXT_PAD_COMP_FILTER_REG (DR_REG_GPIO_EXT_BASE + 0x2c) +/** GPIO_EXT_ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 0; + * Zero Detect filter cycle length + */ +#define GPIO_EXT_ZERO_DET_FILTER_CNT 0xFFFFFFFFU +#define GPIO_EXT_ZERO_DET_FILTER_CNT_M (GPIO_EXT_ZERO_DET_FILTER_CNT_V << GPIO_EXT_ZERO_DET_FILTER_CNT_S) +#define GPIO_EXT_ZERO_DET_FILTER_CNT_V 0xFFFFFFFFU +#define GPIO_EXT_ZERO_DET_FILTER_CNT_S 0 + +/** GPIO_EXT_GLITCH_FILTER_CH0_REG register + * Glitch Filter Configure Register of Channel0 + */ +#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH1_REG register + * Glitch Filter Configure Register of Channel1 + */ +#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH2_REG register + * Glitch Filter Configure Register of Channel2 + */ +#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH3_REG register + * Glitch Filter Configure Register of Channel3 + */ +#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH4_REG register + * Glitch Filter Configure Register of Channel4 + */ +#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH5_REG register + * Glitch Filter Configure Register of Channel5 + */ +#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH6_REG register + * Glitch Filter Configure Register of Channel6 + */ +#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_GLITCH_FILTER_CH7_REG register + * Glitch Filter Configure Register of Channel7 + */ +#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; + * Glitch Filter channel enable bit. + */ +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; + * Glitch Filter input io number. + */ +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; + * Glitch Filter window threshold. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; + * Glitch Filter window width. + */ +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 + +/** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register + * Etm Config register of Channel0 + */ +#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register + * Etm Config register of Channel1 + */ +#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register + * Etm Config register of Channel2 + */ +#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register + * Etm Config register of Channel3 + */ +#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register + * Etm Config register of Channel4 + */ +#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register + * Etm Config register of Channel5 + */ +#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register + * Etm Config register of Channel6 + */ +#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register + * Etm Config register of Channel7 + */ +#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; + * Etm event channel select gpio. + */ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. + */ +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 + +/** GPIO_EXT_ETM_TASK_P0_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0) +/** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO0_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO0_EN_M (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO0_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO0_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO0_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO1_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO1_EN_M (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO1_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO1_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO1_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO2_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO2_EN_M (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO2_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO2_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO2_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO3_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO3_EN_M (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO3_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO3_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO3_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P1_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4) +/** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO4_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO4_EN_M (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO4_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO4_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO4_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO5_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO5_EN_M (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO5_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO5_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO5_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO6_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO6_EN_M (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO6_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO6_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO6_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO7_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO7_EN_M (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO7_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO7_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO7_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P2_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8) +/** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO8_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO8_EN_M (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO8_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO8_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO8_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO9_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO9_EN_M (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO9_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO9_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO9_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO10_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO10_EN_M (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO10_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO10_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO10_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO11_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO11_EN_M (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO11_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO11_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO11_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P3_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac) +/** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO12_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO12_EN_M (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO12_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO12_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO12_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO13_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO13_EN_M (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO13_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO13_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO13_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO14_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO14_EN_M (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO14_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO14_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO14_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO15_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO15_EN_M (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO15_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO15_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO15_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P4_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0) +/** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO16_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO16_EN_M (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO16_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO16_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO16_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO17_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO17_EN_M (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO17_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO17_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO17_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO18_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO18_EN_M (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO18_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO18_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO18_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO19_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO19_EN_M (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO19_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO19_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO19_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P5_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4) +/** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO20_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO20_EN_M (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO20_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO20_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO20_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO21_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO21_EN_M (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO21_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO21_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO21_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO22_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO22_EN_M (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO22_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO22_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO22_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO23_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO23_EN_M (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO23_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO23_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO23_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S 25 + +/** GPIO_EXT_ETM_TASK_P6_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8) +/** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO24_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO24_EN_M (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO24_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO24_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO24_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO25_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_M (GPIO_EXT_ETM_TASK_GPIO25_EN_V << GPIO_EXT_ETM_TASK_GPIO25_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO25_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO25_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M (GPIO_EXT_ETM_TASK_GPIO25_SEL_V << GPIO_EXT_ETM_TASK_GPIO25_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO26_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_M (GPIO_EXT_ETM_TASK_GPIO26_EN_V << GPIO_EXT_ETM_TASK_GPIO26_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO26_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO26_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M (GPIO_EXT_ETM_TASK_GPIO26_SEL_V << GPIO_EXT_ETM_TASK_GPIO26_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S 17 + +/** GPIO_EXT_INT_RAW_REG register + * GPIOSD interrupt raw register + */ +#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0xe0) +/** GPIO_EXT_COMP0_NEG_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt raw + */ +#define GPIO_EXT_COMP0_NEG_INT_RAW (BIT(0)) +#define GPIO_EXT_COMP0_NEG_INT_RAW_M (GPIO_EXT_COMP0_NEG_INT_RAW_V << GPIO_EXT_COMP0_NEG_INT_RAW_S) +#define GPIO_EXT_COMP0_NEG_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP0_NEG_INT_RAW_S 0 +/** GPIO_EXT_COMP0_POS_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt raw + */ +#define GPIO_EXT_COMP0_POS_INT_RAW (BIT(1)) +#define GPIO_EXT_COMP0_POS_INT_RAW_M (GPIO_EXT_COMP0_POS_INT_RAW_V << GPIO_EXT_COMP0_POS_INT_RAW_S) +#define GPIO_EXT_COMP0_POS_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP0_POS_INT_RAW_S 1 +/** GPIO_EXT_COMP0_ALL_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt raw + */ +#define GPIO_EXT_COMP0_ALL_INT_RAW (BIT(2)) +#define GPIO_EXT_COMP0_ALL_INT_RAW_M (GPIO_EXT_COMP0_ALL_INT_RAW_V << GPIO_EXT_COMP0_ALL_INT_RAW_S) +#define GPIO_EXT_COMP0_ALL_INT_RAW_V 0x00000001U +#define GPIO_EXT_COMP0_ALL_INT_RAW_S 2 + +/** GPIO_EXT_INT_ST_REG register + * GPIOSD interrupt masked register + */ +#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0xe4) +/** GPIO_EXT_COMP0_NEG_INT_ST : RO; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt status + */ +#define GPIO_EXT_COMP0_NEG_INT_ST (BIT(0)) +#define GPIO_EXT_COMP0_NEG_INT_ST_M (GPIO_EXT_COMP0_NEG_INT_ST_V << GPIO_EXT_COMP0_NEG_INT_ST_S) +#define GPIO_EXT_COMP0_NEG_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP0_NEG_INT_ST_S 0 +/** GPIO_EXT_COMP0_POS_INT_ST : RO; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt status + */ +#define GPIO_EXT_COMP0_POS_INT_ST (BIT(1)) +#define GPIO_EXT_COMP0_POS_INT_ST_M (GPIO_EXT_COMP0_POS_INT_ST_V << GPIO_EXT_COMP0_POS_INT_ST_S) +#define GPIO_EXT_COMP0_POS_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP0_POS_INT_ST_S 1 +/** GPIO_EXT_COMP0_ALL_INT_ST : RO; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt status + */ +#define GPIO_EXT_COMP0_ALL_INT_ST (BIT(2)) +#define GPIO_EXT_COMP0_ALL_INT_ST_M (GPIO_EXT_COMP0_ALL_INT_ST_V << GPIO_EXT_COMP0_ALL_INT_ST_S) +#define GPIO_EXT_COMP0_ALL_INT_ST_V 0x00000001U +#define GPIO_EXT_COMP0_ALL_INT_ST_S 2 + +/** GPIO_EXT_INT_ENA_REG register + * GPIOSD interrupt enable register + */ +#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0xe8) +/** GPIO_EXT_COMP0_NEG_INT_ENA : R/W; bitpos: [0]; default: 1; + * analog comparator pos edge interrupt enable + */ +#define GPIO_EXT_COMP0_NEG_INT_ENA (BIT(0)) +#define GPIO_EXT_COMP0_NEG_INT_ENA_M (GPIO_EXT_COMP0_NEG_INT_ENA_V << GPIO_EXT_COMP0_NEG_INT_ENA_S) +#define GPIO_EXT_COMP0_NEG_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP0_NEG_INT_ENA_S 0 +/** GPIO_EXT_COMP0_POS_INT_ENA : R/W; bitpos: [1]; default: 1; + * analog comparator neg edge interrupt enable + */ +#define GPIO_EXT_COMP0_POS_INT_ENA (BIT(1)) +#define GPIO_EXT_COMP0_POS_INT_ENA_M (GPIO_EXT_COMP0_POS_INT_ENA_V << GPIO_EXT_COMP0_POS_INT_ENA_S) +#define GPIO_EXT_COMP0_POS_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP0_POS_INT_ENA_S 1 +/** GPIO_EXT_COMP0_ALL_INT_ENA : R/W; bitpos: [2]; default: 1; + * analog comparator neg or pos edge interrupt enable + */ +#define GPIO_EXT_COMP0_ALL_INT_ENA (BIT(2)) +#define GPIO_EXT_COMP0_ALL_INT_ENA_M (GPIO_EXT_COMP0_ALL_INT_ENA_V << GPIO_EXT_COMP0_ALL_INT_ENA_S) +#define GPIO_EXT_COMP0_ALL_INT_ENA_V 0x00000001U +#define GPIO_EXT_COMP0_ALL_INT_ENA_S 2 + +/** GPIO_EXT_INT_CLR_REG register + * GPIOSD interrupt clear register + */ +#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0xec) +/** GPIO_EXT_COMP0_NEG_INT_CLR : WT; bitpos: [0]; default: 0; + * analog comparator pos edge interrupt clear + */ +#define GPIO_EXT_COMP0_NEG_INT_CLR (BIT(0)) +#define GPIO_EXT_COMP0_NEG_INT_CLR_M (GPIO_EXT_COMP0_NEG_INT_CLR_V << GPIO_EXT_COMP0_NEG_INT_CLR_S) +#define GPIO_EXT_COMP0_NEG_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP0_NEG_INT_CLR_S 0 +/** GPIO_EXT_COMP0_POS_INT_CLR : WT; bitpos: [1]; default: 0; + * analog comparator neg edge interrupt clear + */ +#define GPIO_EXT_COMP0_POS_INT_CLR (BIT(1)) +#define GPIO_EXT_COMP0_POS_INT_CLR_M (GPIO_EXT_COMP0_POS_INT_CLR_V << GPIO_EXT_COMP0_POS_INT_CLR_S) +#define GPIO_EXT_COMP0_POS_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP0_POS_INT_CLR_S 1 +/** GPIO_EXT_COMP0_ALL_INT_CLR : WT; bitpos: [2]; default: 0; + * analog comparator neg or pos edge interrupt clear + */ +#define GPIO_EXT_COMP0_ALL_INT_CLR (BIT(2)) +#define GPIO_EXT_COMP0_ALL_INT_CLR_M (GPIO_EXT_COMP0_ALL_INT_CLR_V << GPIO_EXT_COMP0_ALL_INT_CLR_S) +#define GPIO_EXT_COMP0_ALL_INT_CLR_V 0x00000001U +#define GPIO_EXT_COMP0_ALL_INT_CLR_S 2 + +/** GPIO_EXT_VERSION_REG register + * Version Control Register + */ +#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc) +/** GPIO_EXT_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 36704513; + * Version control register. + */ +#define GPIO_EXT_GPIO_SD_DATE 0x0FFFFFFFU +#define GPIO_EXT_GPIO_SD_DATE_M (GPIO_EXT_GPIO_SD_DATE_V << GPIO_EXT_GPIO_SD_DATE_S) +#define GPIO_EXT_GPIO_SD_DATE_V 0x0FFFFFFFU +#define GPIO_EXT_GPIO_SD_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/gpio_struct.h b/components/soc/esp32c5/include/soc/gpio_struct.h new file mode 100644 index 0000000000..afccace39d --- /dev/null +++ b/components/soc/esp32c5/include/soc/gpio_struct.h @@ -0,0 +1,2661 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration register */ +/** Type of bt_select register + * GPIO bit select register + */ +typedef union { + struct { + /** bt_sel : R/W; bitpos: [31:0]; default: 0; + * GPIO bit select register + */ + uint32_t bt_sel:32; + }; + uint32_t val; +} gpio_bt_select_reg_t; + +/** Type of out register + * GPIO output register for GPIO0-30 + */ +typedef union { + struct { + /** out_data_orig : R/W/SC/WTC; bitpos: [30:0]; default: 0; + * GPIO output register for GPIO0-30 + */ + uint32_t out_data_orig:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_out_reg_t; + +/** Type of out_w1ts register + * GPIO output set register for GPIO0-30 + */ +typedef union { + struct { + /** out_w1ts : WT; bitpos: [30:0]; default: 0; + * GPIO output set register for GPIO0-30 + */ + uint32_t out_w1ts:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_out_w1ts_reg_t; + +/** Type of out_w1tc register + * GPIO output clear register for GPIO0-30 + */ +typedef union { + struct { + /** out_w1tc : WT; bitpos: [30:0]; default: 0; + * GPIO output clear register for GPIO0-30 + */ + uint32_t out_w1tc:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_out_w1tc_reg_t; + +/** Type of sdio_select register + * GPIO sdio select register + */ +typedef union { + struct { + /** sdio_sel : R/W; bitpos: [7:0]; default: 0; + * GPIO sdio select register + */ + uint32_t sdio_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_sdio_select_reg_t; + +/** Type of enable register + * GPIO output enable register for GPIO0-30 + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [30:0]; default: 0; + * GPIO output enable register for GPIO0-30 + */ + uint32_t enable_data:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_enable_reg_t; + +/** Type of enable_w1ts register + * GPIO output enable set register for GPIO0-30 + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [30:0]; default: 0; + * GPIO output enable set register for GPIO0-30 + */ + uint32_t enable_w1ts:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * GPIO output enable clear register for GPIO0-30 + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [30:0]; default: 0; + * GPIO output enable clear register for GPIO0-30 + */ + uint32_t enable_w1tc:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_enable_w1tc_reg_t; + +/** Type of strap register + * pad strapping register + */ +typedef union { + struct { + /** strapping : RO; bitpos: [15:0]; default: 0; + * pad strapping register + */ + uint32_t strapping:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} gpio_strap_reg_t; + +/** Type of in register + * GPIO input register for GPIO0-30 + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [30:0]; default: 0; + * GPIO input register for GPIO0-30 + */ + uint32_t in_data_next:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_in_reg_t; + +/** Type of status register + * GPIO interrupt status register for GPIO0-30 + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [30:0]; default: 0; + * GPIO interrupt status register for GPIO0-30 + */ + uint32_t status_interrupt:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_status_reg_t; + +/** Type of status_w1ts register + * GPIO interrupt status set register for GPIO0-30 + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [30:0]; default: 0; + * GPIO interrupt status set register for GPIO0-30 + */ + uint32_t status_w1ts:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_status_w1ts_reg_t; + +/** Type of status_w1tc register + * GPIO interrupt status clear register for GPIO0-30 + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [30:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-30 + */ + uint32_t status_w1tc:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_status_w1tc_reg_t; + +/** Type of pcpu_int register + * GPIO PRO_CPU interrupt status register for GPIO0-30 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [30:0]; default: 0; + * GPIO PRO_CPU interrupt status register for GPIO0-30 + */ + uint32_t procpu_int:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_pcpu_int_reg_t; + +/** Type of pcpu_nmi_int register + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30 + */ +typedef union { + struct { + /** procpu_nmi_int : RO; bitpos: [30:0]; default: 0; + * GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30 + */ + uint32_t procpu_nmi_int:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_pcpu_nmi_int_reg_t; + +/** Type of cpusdio_int register + * GPIO CPUSDIO interrupt status register for GPIO0-30 + */ +typedef union { + struct { + /** sdio_int : RO; bitpos: [30:0]; default: 0; + * GPIO CPUSDIO interrupt status register for GPIO0-30 + */ + uint32_t sdio_int:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_cpusdio_int_reg_t; + +/** Type of pinn register + * GPIO pin configuration register + */ +typedef union { + struct { + /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t pinn_sync2_bypass:2; + /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ + uint32_t pinn_pad_driver:1; + /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ + uint32_t pinn_sync1_bypass:2; + uint32_t reserved_5:2; + /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ + uint32_t pinn_int_type:3; + /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ + uint32_t pinn_wakeup_enable:1; + /** pinn_config : R/W; bitpos: [12:11]; default: 0; + * reserved + */ + uint32_t pinn_config:2; + /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) + * interrupt. + */ + uint32_t pinn_int_ena:5; + uint32_t reserved_18:14; + }; + uint32_t val; +} gpio_pinn_reg_t; + +/** Type of status_next register + * GPIO interrupt source register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [30:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ + uint32_t status_interrupt_next:31; + uint32_t reserved_31:1; + }; + uint32_t val; +} gpio_status_next_reg_t; + +/** Type of func0_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func0_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func0_in_sel:6; + /** func0_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func0_in_inv_sel:1; + /** sig0_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig0_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func0_in_sel_cfg_reg_t; + +/** Type of func6_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func6_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func6_in_sel:6; + /** func6_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func6_in_inv_sel:1; + /** sig6_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig6_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func6_in_sel_cfg_reg_t; + +/** Type of func7_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func7_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func7_in_sel:6; + /** func7_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func7_in_inv_sel:1; + /** sig7_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig7_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func7_in_sel_cfg_reg_t; + +/** Type of func8_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func8_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func8_in_sel:6; + /** func8_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func8_in_inv_sel:1; + /** sig8_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig8_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func8_in_sel_cfg_reg_t; + +/** Type of func9_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func9_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func9_in_sel:6; + /** func9_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func9_in_inv_sel:1; + /** sig9_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig9_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func9_in_sel_cfg_reg_t; + +/** Type of func10_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func10_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func10_in_sel:6; + /** func10_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func10_in_inv_sel:1; + /** sig10_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig10_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func10_in_sel_cfg_reg_t; + +/** Type of func11_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func11_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func11_in_sel:6; + /** func11_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func11_in_inv_sel:1; + /** sig11_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig11_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func11_in_sel_cfg_reg_t; + +/** Type of func12_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func12_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func12_in_sel:6; + /** func12_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func12_in_inv_sel:1; + /** sig12_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig12_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func12_in_sel_cfg_reg_t; + +/** Type of func13_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func13_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func13_in_sel:6; + /** func13_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func13_in_inv_sel:1; + /** sig13_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig13_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func13_in_sel_cfg_reg_t; + +/** Type of func14_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func14_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func14_in_sel:6; + /** func14_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func14_in_inv_sel:1; + /** sig14_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig14_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func14_in_sel_cfg_reg_t; + +/** Type of func15_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func15_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func15_in_sel:6; + /** func15_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func15_in_inv_sel:1; + /** sig15_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig15_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func15_in_sel_cfg_reg_t; + +/** Type of func16_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func16_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func16_in_sel:6; + /** func16_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func16_in_inv_sel:1; + /** sig16_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig16_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func16_in_sel_cfg_reg_t; + +/** Type of func17_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func17_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func17_in_sel:6; + /** func17_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func17_in_inv_sel:1; + /** sig17_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig17_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func17_in_sel_cfg_reg_t; + +/** Type of func19_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func19_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func19_in_sel:6; + /** func19_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func19_in_inv_sel:1; + /** sig19_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig19_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func19_in_sel_cfg_reg_t; + +/** Type of func21_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func21_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func21_in_sel:6; + /** func21_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func21_in_inv_sel:1; + /** sig21_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig21_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func21_in_sel_cfg_reg_t; + +/** Type of func22_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func22_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func22_in_sel:6; + /** func22_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func22_in_inv_sel:1; + /** sig22_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig22_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func22_in_sel_cfg_reg_t; + +/** Type of func23_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func23_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func23_in_sel:6; + /** func23_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func23_in_inv_sel:1; + /** sig23_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig23_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func23_in_sel_cfg_reg_t; + +/** Type of func24_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func24_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func24_in_sel:6; + /** func24_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func24_in_inv_sel:1; + /** sig24_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig24_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func24_in_sel_cfg_reg_t; + +/** Type of func28_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func28_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func28_in_sel:6; + /** func28_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func28_in_inv_sel:1; + /** sig28_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig28_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func28_in_sel_cfg_reg_t; + +/** Type of func29_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func29_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func29_in_sel:6; + /** func29_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func29_in_inv_sel:1; + /** sig29_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig29_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func29_in_sel_cfg_reg_t; + +/** Type of func30_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func30_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func30_in_sel:6; + /** func30_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func30_in_inv_sel:1; + /** sig30_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig30_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func30_in_sel_cfg_reg_t; + +/** Type of func31_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func31_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func31_in_sel:6; + /** func31_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func31_in_inv_sel:1; + /** sig31_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig31_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func31_in_sel_cfg_reg_t; + +/** Type of func32_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func32_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func32_in_sel:6; + /** func32_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func32_in_inv_sel:1; + /** sig32_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig32_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func32_in_sel_cfg_reg_t; + +/** Type of func33_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func33_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func33_in_sel:6; + /** func33_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func33_in_inv_sel:1; + /** sig33_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig33_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func33_in_sel_cfg_reg_t; + +/** Type of func34_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func34_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func34_in_sel:6; + /** func34_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func34_in_inv_sel:1; + /** sig34_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig34_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func34_in_sel_cfg_reg_t; + +/** Type of func35_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func35_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func35_in_sel:6; + /** func35_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func35_in_inv_sel:1; + /** sig35_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig35_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func35_in_sel_cfg_reg_t; + +/** Type of func40_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func40_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func40_in_sel:6; + /** func40_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func40_in_inv_sel:1; + /** sig40_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig40_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func40_in_sel_cfg_reg_t; + +/** Type of func41_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func41_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func41_in_sel:6; + /** func41_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func41_in_inv_sel:1; + /** sig41_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig41_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func41_in_sel_cfg_reg_t; + +/** Type of func42_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func42_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func42_in_sel:6; + /** func42_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func42_in_inv_sel:1; + /** sig42_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig42_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func42_in_sel_cfg_reg_t; + +/** Type of func45_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func45_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func45_in_sel:6; + /** func45_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func45_in_inv_sel:1; + /** sig45_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig45_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func45_in_sel_cfg_reg_t; + +/** Type of func46_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func46_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func46_in_sel:6; + /** func46_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func46_in_inv_sel:1; + /** sig46_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig46_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func46_in_sel_cfg_reg_t; + +/** Type of func47_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func47_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func47_in_sel:6; + /** func47_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func47_in_inv_sel:1; + /** sig47_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig47_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func47_in_sel_cfg_reg_t; + +/** Type of func48_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func48_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func48_in_sel:6; + /** func48_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func48_in_inv_sel:1; + /** sig48_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig48_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func48_in_sel_cfg_reg_t; + +/** Type of func49_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func49_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func49_in_sel:6; + /** func49_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func49_in_inv_sel:1; + /** sig49_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig49_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func49_in_sel_cfg_reg_t; + +/** Type of func50_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func50_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func50_in_sel:6; + /** func50_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func50_in_inv_sel:1; + /** sig50_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig50_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func50_in_sel_cfg_reg_t; + +/** Type of func51_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func51_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func51_in_sel:6; + /** func51_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func51_in_inv_sel:1; + /** sig51_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig51_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func51_in_sel_cfg_reg_t; + +/** Type of func52_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func52_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func52_in_sel:6; + /** func52_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func52_in_inv_sel:1; + /** sig52_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig52_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func52_in_sel_cfg_reg_t; + +/** Type of func53_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func53_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func53_in_sel:6; + /** func53_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func53_in_inv_sel:1; + /** sig53_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig53_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func53_in_sel_cfg_reg_t; + +/** Type of func54_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func54_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func54_in_sel:6; + /** func54_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func54_in_inv_sel:1; + /** sig54_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig54_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func54_in_sel_cfg_reg_t; + +/** Type of func63_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func63_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func63_in_sel:6; + /** func63_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func63_in_inv_sel:1; + /** sig63_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig63_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func63_in_sel_cfg_reg_t; + +/** Type of func64_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func64_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func64_in_sel:6; + /** func64_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func64_in_inv_sel:1; + /** sig64_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig64_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func64_in_sel_cfg_reg_t; + +/** Type of func65_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func65_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func65_in_sel:6; + /** func65_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func65_in_inv_sel:1; + /** sig65_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig65_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func65_in_sel_cfg_reg_t; + +/** Type of func66_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func66_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func66_in_sel:6; + /** func66_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func66_in_inv_sel:1; + /** sig66_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig66_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func66_in_sel_cfg_reg_t; + +/** Type of func67_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func67_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func67_in_sel:6; + /** func67_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func67_in_inv_sel:1; + /** sig67_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig67_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func67_in_sel_cfg_reg_t; + +/** Type of func68_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func68_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func68_in_sel:6; + /** func68_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func68_in_inv_sel:1; + /** sig68_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig68_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func68_in_sel_cfg_reg_t; + +/** Type of func69_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func69_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func69_in_sel:6; + /** func69_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func69_in_inv_sel:1; + /** sig69_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig69_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func69_in_sel_cfg_reg_t; + +/** Type of func70_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func70_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func70_in_sel:6; + /** func70_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func70_in_inv_sel:1; + /** sig70_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig70_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func70_in_sel_cfg_reg_t; + +/** Type of func71_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func71_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func71_in_sel:6; + /** func71_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func71_in_inv_sel:1; + /** sig71_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig71_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func71_in_sel_cfg_reg_t; + +/** Type of func72_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func72_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func72_in_sel:6; + /** func72_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func72_in_inv_sel:1; + /** sig72_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig72_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func72_in_sel_cfg_reg_t; + +/** Type of func73_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func73_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func73_in_sel:6; + /** func73_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func73_in_inv_sel:1; + /** sig73_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig73_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func73_in_sel_cfg_reg_t; + +/** Type of func77_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func77_in_sel : R/W; bitpos: [5:0]; default: 56; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func77_in_sel:6; + /** func77_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func77_in_inv_sel:1; + /** sig77_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig77_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func77_in_sel_cfg_reg_t; + +/** Type of func81_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func81_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func81_in_sel:6; + /** func81_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func81_in_inv_sel:1; + /** sig81_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig81_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func81_in_sel_cfg_reg_t; + +/** Type of func82_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func82_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func82_in_sel:6; + /** func82_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func82_in_inv_sel:1; + /** sig82_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig82_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func82_in_sel_cfg_reg_t; + +/** Type of func83_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func83_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func83_in_sel:6; + /** func83_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func83_in_inv_sel:1; + /** sig83_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig83_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func83_in_sel_cfg_reg_t; + +/** Type of func84_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func84_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func84_in_sel:6; + /** func84_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func84_in_inv_sel:1; + /** sig84_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig84_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func84_in_sel_cfg_reg_t; + +/** Type of func85_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func85_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func85_in_sel:6; + /** func85_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func85_in_inv_sel:1; + /** sig85_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig85_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func85_in_sel_cfg_reg_t; + +/** Type of func86_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func86_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func86_in_sel:6; + /** func86_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func86_in_inv_sel:1; + /** sig86_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig86_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func86_in_sel_cfg_reg_t; + +/** Type of func87_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func87_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func87_in_sel:6; + /** func87_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func87_in_inv_sel:1; + /** sig87_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig87_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func87_in_sel_cfg_reg_t; + +/** Type of func88_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func88_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func88_in_sel:6; + /** func88_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func88_in_inv_sel:1; + /** sig88_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig88_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func88_in_sel_cfg_reg_t; + +/** Type of func89_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func89_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func89_in_sel:6; + /** func89_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func89_in_inv_sel:1; + /** sig89_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig89_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func89_in_sel_cfg_reg_t; + +/** Type of func90_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func90_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func90_in_sel:6; + /** func90_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func90_in_inv_sel:1; + /** sig90_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig90_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func90_in_sel_cfg_reg_t; + +/** Type of func91_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func91_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func91_in_sel:6; + /** func91_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func91_in_inv_sel:1; + /** sig91_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig91_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func91_in_sel_cfg_reg_t; + +/** Type of func92_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func92_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func92_in_sel:6; + /** func92_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func92_in_inv_sel:1; + /** sig92_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig92_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func92_in_sel_cfg_reg_t; + +/** Type of func93_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func93_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func93_in_sel:6; + /** func93_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func93_in_inv_sel:1; + /** sig93_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig93_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func93_in_sel_cfg_reg_t; + +/** Type of func94_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func94_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func94_in_sel:6; + /** func94_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func94_in_inv_sel:1; + /** sig94_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig94_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func94_in_sel_cfg_reg_t; + +/** Type of func95_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func95_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func95_in_sel:6; + /** func95_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func95_in_inv_sel:1; + /** sig95_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig95_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func95_in_sel_cfg_reg_t; + +/** Type of func97_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func97_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func97_in_sel:6; + /** func97_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func97_in_inv_sel:1; + /** sig97_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig97_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func97_in_sel_cfg_reg_t; + +/** Type of func98_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func98_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func98_in_sel:6; + /** func98_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func98_in_inv_sel:1; + /** sig98_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig98_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func98_in_sel_cfg_reg_t; + +/** Type of func99_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func99_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func99_in_sel:6; + /** func99_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func99_in_inv_sel:1; + /** sig99_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig99_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func99_in_sel_cfg_reg_t; + +/** Type of func100_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func100_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func100_in_sel:6; + /** func100_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func100_in_inv_sel:1; + /** sig100_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig100_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func100_in_sel_cfg_reg_t; + +/** Type of func101_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func101_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func101_in_sel:6; + /** func101_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func101_in_inv_sel:1; + /** sig101_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig101_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func101_in_sel_cfg_reg_t; + +/** Type of func102_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func102_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func102_in_sel:6; + /** func102_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func102_in_inv_sel:1; + /** sig102_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig102_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func102_in_sel_cfg_reg_t; + +/** Type of func103_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func103_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func103_in_sel:6; + /** func103_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func103_in_inv_sel:1; + /** sig103_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig103_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func103_in_sel_cfg_reg_t; + +/** Type of func104_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func104_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func104_in_sel:6; + /** func104_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func104_in_inv_sel:1; + /** sig104_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig104_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func104_in_sel_cfg_reg_t; + +/** Type of func105_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func105_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func105_in_sel:6; + /** func105_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func105_in_inv_sel:1; + /** sig105_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig105_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func105_in_sel_cfg_reg_t; + +/** Type of func106_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func106_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func106_in_sel:6; + /** func106_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func106_in_inv_sel:1; + /** sig106_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig106_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func106_in_sel_cfg_reg_t; + +/** Type of func107_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func107_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func107_in_sel:6; + /** func107_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func107_in_inv_sel:1; + /** sig107_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig107_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func107_in_sel_cfg_reg_t; + +/** Type of func108_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func108_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func108_in_sel:6; + /** func108_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func108_in_inv_sel:1; + /** sig108_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig108_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func108_in_sel_cfg_reg_t; + +/** Type of func109_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func109_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func109_in_sel:6; + /** func109_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func109_in_inv_sel:1; + /** sig109_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig109_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func109_in_sel_cfg_reg_t; + +/** Type of func110_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func110_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func110_in_sel:6; + /** func110_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func110_in_inv_sel:1; + /** sig110_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig110_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func110_in_sel_cfg_reg_t; + +/** Type of func111_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func111_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func111_in_sel:6; + /** func111_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func111_in_inv_sel:1; + /** sig111_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig111_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func111_in_sel_cfg_reg_t; + +/** Type of func112_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func112_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func112_in_sel:6; + /** func112_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func112_in_inv_sel:1; + /** sig112_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig112_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func112_in_sel_cfg_reg_t; + +/** Type of func113_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func113_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func113_in_sel:6; + /** func113_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func113_in_inv_sel:1; + /** sig113_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig113_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func113_in_sel_cfg_reg_t; + +/** Type of func114_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func114_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func114_in_sel:6; + /** func114_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func114_in_inv_sel:1; + /** sig114_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig114_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func114_in_sel_cfg_reg_t; + +/** Type of func115_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func115_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func115_in_sel:6; + /** func115_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func115_in_inv_sel:1; + /** sig115_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig115_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func115_in_sel_cfg_reg_t; + +/** Type of func116_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func116_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func116_in_sel:6; + /** func116_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func116_in_inv_sel:1; + /** sig116_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig116_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func116_in_sel_cfg_reg_t; + +/** Type of func117_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func117_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func117_in_sel:6; + /** func117_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func117_in_inv_sel:1; + /** sig117_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig117_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func117_in_sel_cfg_reg_t; + +/** Type of func118_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func118_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func118_in_sel:6; + /** func118_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func118_in_inv_sel:1; + /** sig118_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig118_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func118_in_sel_cfg_reg_t; + +/** Type of func119_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func119_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func119_in_sel:6; + /** func119_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func119_in_inv_sel:1; + /** sig119_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig119_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func119_in_sel_cfg_reg_t; + +/** Type of func120_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func120_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func120_in_sel:6; + /** func120_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func120_in_inv_sel:1; + /** sig120_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig120_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func120_in_sel_cfg_reg_t; + +/** Type of func121_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func121_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func121_in_sel:6; + /** func121_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func121_in_inv_sel:1; + /** sig121_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig121_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func121_in_sel_cfg_reg_t; + +/** Type of func122_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func122_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func122_in_sel:6; + /** func122_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func122_in_inv_sel:1; + /** sig122_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig122_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func122_in_sel_cfg_reg_t; + +/** Type of func123_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func123_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func123_in_sel:6; + /** func123_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func123_in_inv_sel:1; + /** sig123_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig123_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func123_in_sel_cfg_reg_t; + +/** Type of func124_in_sel_cfg register + * GPIO input function configuration register + */ +typedef union { + struct { + /** func124_in_sel : R/W; bitpos: [5:0]; default: 60; + * set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always + * high level. s=0x3C: set this port always low level. + */ + uint32_t func124_in_sel:6; + /** func124_in_inv_sel : R/W; bitpos: [6]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. + */ + uint32_t func124_in_inv_sel:1; + /** sig124_in_sel : R/W; bitpos: [7]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + */ + uint32_t sig124_in_sel:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} gpio_func124_in_sel_cfg_reg_t; + +/** Type of funcn_out_sel_cfg register + * GPIO output function select register + */ +typedef union { + struct { + /** funcn_out_sel : R/W/SC; bitpos: [7:0]; default: 128; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ + uint32_t funcn_out_sel:8; + /** funcn_out_inv_sel : R/W/SC; bitpos: [8]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ + uint32_t funcn_out_inv_sel:1; + /** funcn_oen_sel : R/W; bitpos: [9]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ + uint32_t funcn_oen_sel:1; + /** funcn_oen_inv_sel : R/W; bitpos: [10]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ + uint32_t funcn_oen_inv_sel:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} gpio_funcn_out_sel_cfg_reg_t; + +/** Type of clock_gate register + * GPIO clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * set this bit to enable GPIO clock gate + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} gpio_clock_gate_reg_t; + +/** Type of date register + * GPIO version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36704512; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} gpio_date_reg_t; + + +typedef struct { + volatile gpio_bt_select_reg_t bt_select; + volatile gpio_out_reg_t out; + volatile gpio_out_w1ts_reg_t out_w1ts; + volatile gpio_out_w1tc_reg_t out_w1tc; + uint32_t reserved_010[3]; + volatile gpio_sdio_select_reg_t sdio_select; + volatile gpio_enable_reg_t enable; + volatile gpio_enable_w1ts_reg_t enable_w1ts; + volatile gpio_enable_w1tc_reg_t enable_w1tc; + uint32_t reserved_02c[3]; + volatile gpio_strap_reg_t strap; + volatile gpio_in_reg_t in; + uint32_t reserved_040; + volatile gpio_status_reg_t status; + volatile gpio_status_w1ts_reg_t status_w1ts; + volatile gpio_status_w1tc_reg_t status_w1tc; + uint32_t reserved_050[3]; + volatile gpio_pcpu_int_reg_t pcpu_int; + volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int; + volatile gpio_cpusdio_int_reg_t cpusdio_int; + uint32_t reserved_068[3]; + volatile gpio_pinn_reg_t pinn[31]; + uint32_t reserved_0f0[23]; + volatile gpio_status_next_reg_t status_next; + uint32_t reserved_150; + volatile gpio_func0_in_sel_cfg_reg_t func0_in_sel_cfg; + uint32_t reserved_158[5]; + volatile gpio_func6_in_sel_cfg_reg_t func6_in_sel_cfg; + volatile gpio_func7_in_sel_cfg_reg_t func7_in_sel_cfg; + volatile gpio_func8_in_sel_cfg_reg_t func8_in_sel_cfg; + volatile gpio_func9_in_sel_cfg_reg_t func9_in_sel_cfg; + volatile gpio_func10_in_sel_cfg_reg_t func10_in_sel_cfg; + volatile gpio_func11_in_sel_cfg_reg_t func11_in_sel_cfg; + volatile gpio_func12_in_sel_cfg_reg_t func12_in_sel_cfg; + volatile gpio_func13_in_sel_cfg_reg_t func13_in_sel_cfg; + volatile gpio_func14_in_sel_cfg_reg_t func14_in_sel_cfg; + volatile gpio_func15_in_sel_cfg_reg_t func15_in_sel_cfg; + volatile gpio_func16_in_sel_cfg_reg_t func16_in_sel_cfg; + volatile gpio_func17_in_sel_cfg_reg_t func17_in_sel_cfg; + uint32_t reserved_19c; + volatile gpio_func19_in_sel_cfg_reg_t func19_in_sel_cfg; + uint32_t reserved_1a4; + volatile gpio_func21_in_sel_cfg_reg_t func21_in_sel_cfg; + volatile gpio_func22_in_sel_cfg_reg_t func22_in_sel_cfg; + volatile gpio_func23_in_sel_cfg_reg_t func23_in_sel_cfg; + volatile gpio_func24_in_sel_cfg_reg_t func24_in_sel_cfg; + uint32_t reserved_1b8[3]; + volatile gpio_func28_in_sel_cfg_reg_t func28_in_sel_cfg; + volatile gpio_func29_in_sel_cfg_reg_t func29_in_sel_cfg; + volatile gpio_func30_in_sel_cfg_reg_t func30_in_sel_cfg; + volatile gpio_func31_in_sel_cfg_reg_t func31_in_sel_cfg; + volatile gpio_func32_in_sel_cfg_reg_t func32_in_sel_cfg; + volatile gpio_func33_in_sel_cfg_reg_t func33_in_sel_cfg; + volatile gpio_func34_in_sel_cfg_reg_t func34_in_sel_cfg; + volatile gpio_func35_in_sel_cfg_reg_t func35_in_sel_cfg; + uint32_t reserved_1e4[4]; + volatile gpio_func40_in_sel_cfg_reg_t func40_in_sel_cfg; + volatile gpio_func41_in_sel_cfg_reg_t func41_in_sel_cfg; + volatile gpio_func42_in_sel_cfg_reg_t func42_in_sel_cfg; + uint32_t reserved_200[2]; + volatile gpio_func45_in_sel_cfg_reg_t func45_in_sel_cfg; + volatile gpio_func46_in_sel_cfg_reg_t func46_in_sel_cfg; + volatile gpio_func47_in_sel_cfg_reg_t func47_in_sel_cfg; + volatile gpio_func48_in_sel_cfg_reg_t func48_in_sel_cfg; + volatile gpio_func49_in_sel_cfg_reg_t func49_in_sel_cfg; + volatile gpio_func50_in_sel_cfg_reg_t func50_in_sel_cfg; + volatile gpio_func51_in_sel_cfg_reg_t func51_in_sel_cfg; + volatile gpio_func52_in_sel_cfg_reg_t func52_in_sel_cfg; + volatile gpio_func53_in_sel_cfg_reg_t func53_in_sel_cfg; + volatile gpio_func54_in_sel_cfg_reg_t func54_in_sel_cfg; + uint32_t reserved_230[8]; + volatile gpio_func63_in_sel_cfg_reg_t func63_in_sel_cfg; + volatile gpio_func64_in_sel_cfg_reg_t func64_in_sel_cfg; + volatile gpio_func65_in_sel_cfg_reg_t func65_in_sel_cfg; + volatile gpio_func66_in_sel_cfg_reg_t func66_in_sel_cfg; + volatile gpio_func67_in_sel_cfg_reg_t func67_in_sel_cfg; + volatile gpio_func68_in_sel_cfg_reg_t func68_in_sel_cfg; + volatile gpio_func69_in_sel_cfg_reg_t func69_in_sel_cfg; + volatile gpio_func70_in_sel_cfg_reg_t func70_in_sel_cfg; + volatile gpio_func71_in_sel_cfg_reg_t func71_in_sel_cfg; + volatile gpio_func72_in_sel_cfg_reg_t func72_in_sel_cfg; + volatile gpio_func73_in_sel_cfg_reg_t func73_in_sel_cfg; + uint32_t reserved_27c[3]; + volatile gpio_func77_in_sel_cfg_reg_t func77_in_sel_cfg; + uint32_t reserved_28c[3]; + volatile gpio_func81_in_sel_cfg_reg_t func81_in_sel_cfg; + volatile gpio_func82_in_sel_cfg_reg_t func82_in_sel_cfg; + volatile gpio_func83_in_sel_cfg_reg_t func83_in_sel_cfg; + volatile gpio_func84_in_sel_cfg_reg_t func84_in_sel_cfg; + volatile gpio_func85_in_sel_cfg_reg_t func85_in_sel_cfg; + volatile gpio_func86_in_sel_cfg_reg_t func86_in_sel_cfg; + volatile gpio_func87_in_sel_cfg_reg_t func87_in_sel_cfg; + volatile gpio_func88_in_sel_cfg_reg_t func88_in_sel_cfg; + volatile gpio_func89_in_sel_cfg_reg_t func89_in_sel_cfg; + volatile gpio_func90_in_sel_cfg_reg_t func90_in_sel_cfg; + volatile gpio_func91_in_sel_cfg_reg_t func91_in_sel_cfg; + volatile gpio_func92_in_sel_cfg_reg_t func92_in_sel_cfg; + volatile gpio_func93_in_sel_cfg_reg_t func93_in_sel_cfg; + volatile gpio_func94_in_sel_cfg_reg_t func94_in_sel_cfg; + volatile gpio_func95_in_sel_cfg_reg_t func95_in_sel_cfg; + uint32_t reserved_2d4; + volatile gpio_func97_in_sel_cfg_reg_t func97_in_sel_cfg; + volatile gpio_func98_in_sel_cfg_reg_t func98_in_sel_cfg; + volatile gpio_func99_in_sel_cfg_reg_t func99_in_sel_cfg; + volatile gpio_func100_in_sel_cfg_reg_t func100_in_sel_cfg; + volatile gpio_func101_in_sel_cfg_reg_t func101_in_sel_cfg; + volatile gpio_func102_in_sel_cfg_reg_t func102_in_sel_cfg; + volatile gpio_func103_in_sel_cfg_reg_t func103_in_sel_cfg; + volatile gpio_func104_in_sel_cfg_reg_t func104_in_sel_cfg; + volatile gpio_func105_in_sel_cfg_reg_t func105_in_sel_cfg; + volatile gpio_func106_in_sel_cfg_reg_t func106_in_sel_cfg; + volatile gpio_func107_in_sel_cfg_reg_t func107_in_sel_cfg; + volatile gpio_func108_in_sel_cfg_reg_t func108_in_sel_cfg; + volatile gpio_func109_in_sel_cfg_reg_t func109_in_sel_cfg; + volatile gpio_func110_in_sel_cfg_reg_t func110_in_sel_cfg; + volatile gpio_func111_in_sel_cfg_reg_t func111_in_sel_cfg; + volatile gpio_func112_in_sel_cfg_reg_t func112_in_sel_cfg; + volatile gpio_func113_in_sel_cfg_reg_t func113_in_sel_cfg; + volatile gpio_func114_in_sel_cfg_reg_t func114_in_sel_cfg; + volatile gpio_func115_in_sel_cfg_reg_t func115_in_sel_cfg; + volatile gpio_func116_in_sel_cfg_reg_t func116_in_sel_cfg; + volatile gpio_func117_in_sel_cfg_reg_t func117_in_sel_cfg; + volatile gpio_func118_in_sel_cfg_reg_t func118_in_sel_cfg; + volatile gpio_func119_in_sel_cfg_reg_t func119_in_sel_cfg; + volatile gpio_func120_in_sel_cfg_reg_t func120_in_sel_cfg; + volatile gpio_func121_in_sel_cfg_reg_t func121_in_sel_cfg; + volatile gpio_func122_in_sel_cfg_reg_t func122_in_sel_cfg; + volatile gpio_func123_in_sel_cfg_reg_t func123_in_sel_cfg; + volatile gpio_func124_in_sel_cfg_reg_t func124_in_sel_cfg; + uint32_t reserved_348[131]; + volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[31]; + uint32_t reserved_5d0[23]; + volatile gpio_clock_gate_reg_t clock_gate; + uint32_t reserved_630[51]; + volatile gpio_date_reg_t date; +} gpio_dev_t; + +extern gpio_dev_t GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hardware_lock_reg.h b/components/soc/esp32c5/include/soc/hardware_lock_reg.h new file mode 100644 index 0000000000..75451751c6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hardware_lock_reg.h @@ -0,0 +1,76 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ATOMIC_ADDR_LOCK_REG register + * hardware lock regsiter + */ +#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0) +/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0; + * read to acquire hardware lock, write to release hardware lock + */ +#define ATOMIC_LOCK 0x00000003U +#define ATOMIC_LOCK_M (ATOMIC_LOCK_V << ATOMIC_LOCK_S) +#define ATOMIC_LOCK_V 0x00000003U +#define ATOMIC_LOCK_S 0 + +/** ATOMIC_LR_ADDR_REG register + * gloable lr address regsiter + */ +#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4) +/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0; + * backup gloable address + */ +#define ATOMIC_GLOABLE_LR_ADDR 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_ADDR_M (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S) +#define ATOMIC_GLOABLE_LR_ADDR_V 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_ADDR_S 0 + +/** ATOMIC_LR_VALUE_REG register + * gloable lr value regsiter + */ +#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8) +/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0; + * backup gloable value + */ +#define ATOMIC_GLOABLE_LR_VALUE 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_VALUE_M (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S) +#define ATOMIC_GLOABLE_LR_VALUE_V 0xFFFFFFFFU +#define ATOMIC_GLOABLE_LR_VALUE_S 0 + +/** ATOMIC_LOCK_STATUS_REG register + * lock status regsiter + */ +#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc) +/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0; + * read hareware lock status for debug + */ +#define ATOMIC_LOCK_STATUS 0x00000003U +#define ATOMIC_LOCK_STATUS_M (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S) +#define ATOMIC_LOCK_STATUS_V 0x00000003U +#define ATOMIC_LOCK_STATUS_S 0 + +/** ATOMIC_COUNTER_REG register + * wait counter register + */ +#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10) +/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0; + * delay counter + */ +#define ATOMIC_WAIT_COUNTER 0x0000FFFFU +#define ATOMIC_WAIT_COUNTER_M (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S) +#define ATOMIC_WAIT_COUNTER_V 0x0000FFFFU +#define ATOMIC_WAIT_COUNTER_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hardware_lock_struct.h b/components/soc/esp32c5/include/soc/hardware_lock_struct.h new file mode 100644 index 0000000000..2e6b7f2cf2 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hardware_lock_struct.h @@ -0,0 +1,99 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of addr_lock register + * hardware lock regsiter + */ +typedef union { + struct { + /** lock : R/W; bitpos: [1:0]; default: 0; + * read to acquire hardware lock, write to release hardware lock + */ + uint32_t lock:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} atomic_addr_lock_reg_t; + +/** Type of lr_addr register + * gloable lr address regsiter + */ +typedef union { + struct { + /** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0; + * backup gloable address + */ + uint32_t gloable_lr_addr:32; + }; + uint32_t val; +} atomic_lr_addr_reg_t; + +/** Type of lr_value register + * gloable lr value regsiter + */ +typedef union { + struct { + /** gloable_lr_value : R/W; bitpos: [31:0]; default: 0; + * backup gloable value + */ + uint32_t gloable_lr_value:32; + }; + uint32_t val; +} atomic_lr_value_reg_t; + +/** Type of lock_status register + * lock status regsiter + */ +typedef union { + struct { + /** lock_status : RO; bitpos: [1:0]; default: 0; + * read hareware lock status for debug + */ + uint32_t lock_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} atomic_lock_status_reg_t; + +/** Type of counter register + * wait counter register + */ +typedef union { + struct { + /** wait_counter : R/W; bitpos: [15:0]; default: 0; + * delay counter + */ + uint32_t wait_counter:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} atomic_counter_reg_t; + + +typedef struct { + volatile atomic_addr_lock_reg_t addr_lock; + volatile atomic_lr_addr_reg_t lr_addr; + volatile atomic_lr_value_reg_t lr_value; + volatile atomic_lock_status_reg_t lock_status; + volatile atomic_counter_reg_t counter; +} atomic_dev_t; + +extern atomic_dev_t ATOMIC_LOCKER; + +#ifndef __cplusplus +_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hmac_reg.h b/components/soc/esp32c5/include/soc/hmac_reg.h new file mode 100644 index 0000000000..9ed7eb1273 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hmac_reg.h @@ -0,0 +1,232 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HMAC_SET_START_REG register + * Process control register 0. + */ +#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40) +/** HMAC_SET_START : WS; bitpos: [0]; default: 0; + * Start hmac operation. + */ +#define HMAC_SET_START (BIT(0)) +#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S) +#define HMAC_SET_START_V 0x00000001U +#define HMAC_SET_START_S 0 + +/** HMAC_SET_PARA_PURPOSE_REG register + * Configure purpose. + */ +#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44) +/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0; + * Set hmac parameter purpose. + */ +#define HMAC_PURPOSE_SET 0x0000000FU +#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S) +#define HMAC_PURPOSE_SET_V 0x0000000FU +#define HMAC_PURPOSE_SET_S 0 + +/** HMAC_SET_PARA_KEY_REG register + * Configure key. + */ +#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48) +/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0; + * Set hmac parameter key. + */ +#define HMAC_KEY_SET 0x00000007U +#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S) +#define HMAC_KEY_SET_V 0x00000007U +#define HMAC_KEY_SET_S 0 + +/** HMAC_SET_PARA_FINISH_REG register + * Finish initial configuration. + */ +#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c) +/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0; + * Finish hmac configuration. + */ +#define HMAC_SET_PARA_END (BIT(0)) +#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S) +#define HMAC_SET_PARA_END_V 0x00000001U +#define HMAC_SET_PARA_END_S 0 + +/** HMAC_SET_MESSAGE_ONE_REG register + * Process control register 1. + */ +#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50) +/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0; + * Call SHA to calculate one message block. + */ +#define HMAC_SET_TEXT_ONE (BIT(0)) +#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S) +#define HMAC_SET_TEXT_ONE_V 0x00000001U +#define HMAC_SET_TEXT_ONE_S 0 + +/** HMAC_SET_MESSAGE_ING_REG register + * Process control register 2. + */ +#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54) +/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0; + * Continue typical hmac. + */ +#define HMAC_SET_TEXT_ING (BIT(0)) +#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S) +#define HMAC_SET_TEXT_ING_V 0x00000001U +#define HMAC_SET_TEXT_ING_S 0 + +/** HMAC_SET_MESSAGE_END_REG register + * Process control register 3. + */ +#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58) +/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0; + * Start hardware padding. + */ +#define HMAC_SET_TEXT_END (BIT(0)) +#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S) +#define HMAC_SET_TEXT_END_V 0x00000001U +#define HMAC_SET_TEXT_END_S 0 + +/** HMAC_SET_RESULT_FINISH_REG register + * Process control register 4. + */ +#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c) +/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0; + * After read result from upstream, then let hmac back to idle. + */ +#define HMAC_SET_RESULT_END (BIT(0)) +#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S) +#define HMAC_SET_RESULT_END_V 0x00000001U +#define HMAC_SET_RESULT_END_S 0 + +/** HMAC_SET_INVALIDATE_JTAG_REG register + * Invalidate register 0. + */ +#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60) +/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream JTAG. + */ +#define HMAC_SET_INVALIDATE_JTAG (BIT(0)) +#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S) +#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U +#define HMAC_SET_INVALIDATE_JTAG_S 0 + +/** HMAC_SET_INVALIDATE_DS_REG register + * Invalidate register 1. + */ +#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64) +/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream DS. + */ +#define HMAC_SET_INVALIDATE_DS (BIT(0)) +#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S) +#define HMAC_SET_INVALIDATE_DS_V 0x00000001U +#define HMAC_SET_INVALIDATE_DS_S 0 + +/** HMAC_QUERY_ERROR_REG register + * Error register. + */ +#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68) +/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0; + * Hmac configuration state. 0: key are agree with purpose. 1: error + */ +#define HMAC_QUREY_CHECK (BIT(0)) +#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S) +#define HMAC_QUREY_CHECK_V 0x00000001U +#define HMAC_QUREY_CHECK_S 0 + +/** HMAC_QUERY_BUSY_REG register + * Busy register. + */ +#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c) +/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Hmac state. 1'b0: idle. 1'b1: busy + */ +#define HMAC_BUSY_STATE (BIT(0)) +#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S) +#define HMAC_BUSY_STATE_V 0x00000001U +#define HMAC_BUSY_STATE_S 0 + +/** HMAC_WR_MESSAGE_MEM register + * Message block memory. + */ +#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80) +#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64 + +/** HMAC_RD_RESULT_MEM register + * Result from upstream. + */ +#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0) +#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32 + +/** HMAC_SET_MESSAGE_PAD_REG register + * Process control register 5. + */ +#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0) +/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0; + * Start software padding. + */ +#define HMAC_SET_TEXT_PAD (BIT(0)) +#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S) +#define HMAC_SET_TEXT_PAD_V 0x00000001U +#define HMAC_SET_TEXT_PAD_S 0 + +/** HMAC_ONE_BLOCK_REG register + * Process control register 6. + */ +#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4) +/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0; + * Don't have to do padding. + */ +#define HMAC_SET_ONE_BLOCK (BIT(0)) +#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S) +#define HMAC_SET_ONE_BLOCK_V 0x00000001U +#define HMAC_SET_ONE_BLOCK_S 0 + +/** HMAC_SOFT_JTAG_CTRL_REG register + * Jtag register 0. + */ +#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8) +/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0; + * Turn on JTAG verification. + */ +#define HMAC_SOFT_JTAG_CTRL (BIT(0)) +#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S) +#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U +#define HMAC_SOFT_JTAG_CTRL_S 0 + +/** HMAC_WR_JTAG_REG register + * Jtag register 1. + */ +#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc) +/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0; + * 32-bit of key to be compared. + */ +#define HMAC_WR_JTAG 0xFFFFFFFFU +#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S) +#define HMAC_WR_JTAG_V 0xFFFFFFFFU +#define HMAC_WR_JTAG_S 0 + +/** HMAC_DATE_REG register + * Date register. + */ +#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc) +/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624; + * Hmac date information/ hmac version information. + */ +#define HMAC_DATE 0x3FFFFFFFU +#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S) +#define HMAC_DATE_V 0x3FFFFFFFU +#define HMAC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hmac_struct.h b/components/soc/esp32c5/include/soc/hmac_struct.h new file mode 100644 index 0000000000..59aee85a2b --- /dev/null +++ b/components/soc/esp32c5/include/soc/hmac_struct.h @@ -0,0 +1,292 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of set_start register + * Process control register 0. + */ +typedef union { + struct { + /** set_start : WS; bitpos: [0]; default: 0; + * Start hmac operation. + */ + uint32_t set_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_start_reg_t; + +/** Type of set_para_purpose register + * Configure purpose. + */ +typedef union { + struct { + /** purpose_set : WO; bitpos: [3:0]; default: 0; + * Set hmac parameter purpose. + */ + uint32_t purpose_set:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} hmac_set_para_purpose_reg_t; + +/** Type of set_para_key register + * Configure key. + */ +typedef union { + struct { + /** key_set : WO; bitpos: [2:0]; default: 0; + * Set hmac parameter key. + */ + uint32_t key_set:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} hmac_set_para_key_reg_t; + +/** Type of set_para_finish register + * Finish initial configuration. + */ +typedef union { + struct { + /** set_para_end : WS; bitpos: [0]; default: 0; + * Finish hmac configuration. + */ + uint32_t set_para_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_para_finish_reg_t; + +/** Type of set_message_one register + * Process control register 1. + */ +typedef union { + struct { + /** set_text_one : WS; bitpos: [0]; default: 0; + * Call SHA to calculate one message block. + */ + uint32_t set_text_one:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_one_reg_t; + +/** Type of set_message_ing register + * Process control register 2. + */ +typedef union { + struct { + /** set_text_ing : WS; bitpos: [0]; default: 0; + * Continue typical hmac. + */ + uint32_t set_text_ing:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_ing_reg_t; + +/** Type of set_message_end register + * Process control register 3. + */ +typedef union { + struct { + /** set_text_end : WS; bitpos: [0]; default: 0; + * Start hardware padding. + */ + uint32_t set_text_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_end_reg_t; + +/** Type of set_result_finish register + * Process control register 4. + */ +typedef union { + struct { + /** set_result_end : WS; bitpos: [0]; default: 0; + * After read result from upstream, then let hmac back to idle. + */ + uint32_t set_result_end:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_result_finish_reg_t; + +/** Type of set_invalidate_jtag register + * Invalidate register 0. + */ +typedef union { + struct { + /** set_invalidate_jtag : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream JTAG. + */ + uint32_t set_invalidate_jtag:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_jtag_reg_t; + +/** Type of set_invalidate_ds register + * Invalidate register 1. + */ +typedef union { + struct { + /** set_invalidate_ds : WS; bitpos: [0]; default: 0; + * Clear result from hmac downstream DS. + */ + uint32_t set_invalidate_ds:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_invalidate_ds_reg_t; + +/** Type of set_message_pad register + * Process control register 5. + */ +typedef union { + struct { + /** set_text_pad : WO; bitpos: [0]; default: 0; + * Start software padding. + */ + uint32_t set_text_pad:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_set_message_pad_reg_t; + +/** Type of one_block register + * Process control register 6. + */ +typedef union { + struct { + /** set_one_block : WS; bitpos: [0]; default: 0; + * Don't have to do padding. + */ + uint32_t set_one_block:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_one_block_reg_t; + +/** Type of soft_jtag_ctrl register + * Jtag register 0. + */ +typedef union { + struct { + /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0; + * Turn on JTAG verification. + */ + uint32_t soft_jtag_ctrl:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_soft_jtag_ctrl_reg_t; + +/** Type of wr_jtag register + * Jtag register 1. + */ +typedef union { + struct { + /** wr_jtag : WO; bitpos: [31:0]; default: 0; + * 32-bit of key to be compared. + */ + uint32_t wr_jtag:32; + }; + uint32_t val; +} hmac_wr_jtag_reg_t; + + +/** Group: Status Register */ +/** Type of query_error register + * Error register. + */ +typedef union { + struct { + /** qurey_check : RO; bitpos: [0]; default: 0; + * Hmac configuration state. 0: key are agree with purpose. 1: error + */ + uint32_t qurey_check:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_error_reg_t; + +/** Type of query_busy register + * Busy register. + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Hmac state. 1'b0: idle. 1'b1: busy + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hmac_query_busy_reg_t; + + +/** Group: Memory Type */ + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538969624; + * Hmac date information/ hmac version information. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} hmac_date_reg_t; + + +typedef struct { + uint32_t reserved_000[16]; + volatile hmac_set_start_reg_t set_start; + volatile hmac_set_para_purpose_reg_t set_para_purpose; + volatile hmac_set_para_key_reg_t set_para_key; + volatile hmac_set_para_finish_reg_t set_para_finish; + volatile hmac_set_message_one_reg_t set_message_one; + volatile hmac_set_message_ing_reg_t set_message_ing; + volatile hmac_set_message_end_reg_t set_message_end; + volatile hmac_set_result_finish_reg_t set_result_finish; + volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag; + volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds; + volatile hmac_query_error_reg_t query_error; + volatile hmac_query_busy_reg_t query_busy; + uint32_t reserved_070[4]; + volatile uint32_t wr_message[16]; + volatile uint32_t rd_result[8]; + uint32_t reserved_0e0[4]; + volatile hmac_set_message_pad_reg_t set_message_pad; + volatile hmac_one_block_reg_t one_block; + volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl; + volatile hmac_wr_jtag_reg_t wr_jtag; + uint32_t reserved_100[63]; + volatile hmac_date_reg_t date; +} hmac_dev_t; + +extern hmac_dev_t HMAC; + +#ifndef __cplusplus +_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/host_reg.h b/components/soc/esp32c5/include/soc/host_reg.h new file mode 100644 index 0000000000..484da3d260 --- /dev/null +++ b/components/soc/esp32c5/include/soc/host_reg.h @@ -0,0 +1,3883 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SLCHOST_FUNC2_0_REG register + * *******Description*********** + */ +#define SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10) +/** SLCHOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_FUNC2_INT (BIT(24)) +#define SLCHOST_SLC_FUNC2_INT_M (SLCHOST_SLC_FUNC2_INT_V << SLCHOST_SLC_FUNC2_INT_S) +#define SLCHOST_SLC_FUNC2_INT_V 0x00000001U +#define SLCHOST_SLC_FUNC2_INT_S 24 + +/** SLCHOST_FUNC2_1_REG register + * *******Description*********** + */ +#define SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14) +/** SLCHOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_FUNC2_INT_EN (BIT(0)) +#define SLCHOST_SLC_FUNC2_INT_EN_M (SLCHOST_SLC_FUNC2_INT_EN_V << SLCHOST_SLC_FUNC2_INT_EN_S) +#define SLCHOST_SLC_FUNC2_INT_EN_V 0x00000001U +#define SLCHOST_SLC_FUNC2_INT_EN_S 0 + +/** SLCHOST_FUNC2_2_REG register + * *******Description*********** + */ +#define SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20) +/** SLCHOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ +#define SLCHOST_SLC_FUNC1_MDSTAT (BIT(0)) +#define SLCHOST_SLC_FUNC1_MDSTAT_M (SLCHOST_SLC_FUNC1_MDSTAT_V << SLCHOST_SLC_FUNC1_MDSTAT_S) +#define SLCHOST_SLC_FUNC1_MDSTAT_V 0x00000001U +#define SLCHOST_SLC_FUNC1_MDSTAT_S 0 + +/** SLCHOST_GPIO_STATUS0_REG register + * *******Description*********** + */ +#define SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34) +/** SLCHOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT0 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_INT0_M (SLCHOST_GPIO_SDIO_INT0_V << SLCHOST_GPIO_SDIO_INT0_S) +#define SLCHOST_GPIO_SDIO_INT0_V 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_INT0_S 0 + +/** SLCHOST_GPIO_STATUS1_REG register + * *******Description*********** + */ +#define SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38) +/** SLCHOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT1 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_INT1_M (SLCHOST_GPIO_SDIO_INT1_V << SLCHOST_GPIO_SDIO_INT1_S) +#define SLCHOST_GPIO_SDIO_INT1_V 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_INT1_S 0 + +/** SLCHOST_GPIO_IN0_REG register + * *******Description*********** + */ +#define SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3c) +/** SLCHOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_IN0 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_IN0_M (SLCHOST_GPIO_SDIO_IN0_V << SLCHOST_GPIO_SDIO_IN0_S) +#define SLCHOST_GPIO_SDIO_IN0_V 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_IN0_S 0 + +/** SLCHOST_GPIO_IN1_REG register + * *******Description*********** + */ +#define SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40) +/** SLCHOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_IN1 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_IN1_M (SLCHOST_GPIO_SDIO_IN1_V << SLCHOST_GPIO_SDIO_IN1_S) +#define SLCHOST_GPIO_SDIO_IN1_V 0xFFFFFFFFU +#define SLCHOST_GPIO_SDIO_IN1_S 0 + +/** SLCHOST_SLC0HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44) +/** SLCHOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0 0x00000FFFU +#define SLCHOST_SLC0_TOKEN0_M (SLCHOST_SLC0_TOKEN0_V << SLCHOST_SLC0_TOKEN0_S) +#define SLCHOST_SLC0_TOKEN0_V 0x00000FFFU +#define SLCHOST_SLC0_TOKEN0_S 0 +/** SLCHOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID (BIT(12)) +#define SLCHOST_SLC0_RX_PF_VALID_M (SLCHOST_SLC0_RX_PF_VALID_V << SLCHOST_SLC0_RX_PF_VALID_S) +#define SLCHOST_SLC0_RX_PF_VALID_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_S 12 +/** SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_M (SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S) +#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S 16 +/** SLCHOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_EOF 0x0000000FU +#define SLCHOST_SLC0_RX_PF_EOF_M (SLCHOST_SLC0_RX_PF_EOF_V << SLCHOST_SLC0_RX_PF_EOF_S) +#define SLCHOST_SLC0_RX_PF_EOF_V 0x0000000FU +#define SLCHOST_SLC0_RX_PF_EOF_S 28 + +/** SLCHOST_SLC0_HOST_PF_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48) +/** SLCHOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_PF_DATA 0xFFFFFFFFU +#define SLCHOST_SLC0_PF_DATA_M (SLCHOST_SLC0_PF_DATA_V << SLCHOST_SLC0_PF_DATA_S) +#define SLCHOST_SLC0_PF_DATA_V 0xFFFFFFFFU +#define SLCHOST_SLC0_PF_DATA_S 0 + +/** SLCHOST_SLC1_HOST_PF_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4c) +/** SLCHOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_PF_DATA 0xFFFFFFFFU +#define SLCHOST_SLC1_PF_DATA_M (SLCHOST_SLC1_PF_DATA_V << SLCHOST_SLC1_PF_DATA_S) +#define SLCHOST_SLC1_PF_DATA_V 0xFFFFFFFFU +#define SLCHOST_SLC1_PF_DATA_S 0 + +/** SLCHOST_SLC0HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_M (SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_M (SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_M (SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_RAW_M (SLCHOST_SLC0HOST_RX_START_INT_RAW_V << SLCHOST_SLC0HOST_RX_START_INT_RAW_S) +#define SLCHOST_SLC0HOST_RX_START_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_RAW_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_RAW_M (SLCHOST_SLC0HOST_TX_START_INT_RAW_V << SLCHOST_SLC0HOST_TX_START_INT_RAW_S) +#define SLCHOST_SLC0HOST_TX_START_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_RAW_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_RAW (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_RAW_M (SLCHOST_SLC0_RX_UDF_INT_RAW_V << SLCHOST_SLC0_RX_UDF_INT_RAW_S) +#define SLCHOST_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_RAW_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_RAW (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_RAW_M (SLCHOST_SLC0_TX_OVF_INT_RAW_V << SLCHOST_SLC0_TX_OVF_INT_RAW_S) +#define SLCHOST_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_RAW_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_M (SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_M (SLCHOST_SLC0_EXT_BIT0_INT_RAW_V << SLCHOST_SLC0_EXT_BIT0_INT_RAW_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_M (SLCHOST_SLC0_EXT_BIT1_INT_RAW_V << SLCHOST_SLC0_EXT_BIT1_INT_RAW_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_M (SLCHOST_SLC0_EXT_BIT2_INT_RAW_V << SLCHOST_SLC0_EXT_BIT2_INT_RAW_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_M (SLCHOST_SLC0_EXT_BIT3_INT_RAW_V << SLCHOST_SLC0_EXT_BIT3_INT_RAW_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 +/** SLCHOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_RAW (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_RAW_M (SLCHOST_GPIO_SDIO_INT_RAW_V << SLCHOST_GPIO_SDIO_INT_RAW_S) +#define SLCHOST_GPIO_SDIO_INT_RAW_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_RAW_S 25 + +/** SLCHOST_SLC1HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_M (SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_M (SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_M (SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_RAW (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_RAW_M (SLCHOST_SLC1HOST_RX_START_INT_RAW_V << SLCHOST_SLC1HOST_RX_START_INT_RAW_S) +#define SLCHOST_SLC1HOST_RX_START_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_RAW_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_RAW (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_RAW_M (SLCHOST_SLC1HOST_TX_START_INT_RAW_V << SLCHOST_SLC1HOST_TX_START_INT_RAW_S) +#define SLCHOST_SLC1HOST_TX_START_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_RAW_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_RAW (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_RAW_M (SLCHOST_SLC1_RX_UDF_INT_RAW_V << SLCHOST_SLC1_RX_UDF_INT_RAW_S) +#define SLCHOST_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_RAW_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_RAW (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_RAW_M (SLCHOST_SLC1_TX_OVF_INT_RAW_V << SLCHOST_SLC1_TX_OVF_INT_RAW_S) +#define SLCHOST_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_RAW_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_M (SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_RAW (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_M (SLCHOST_SLC1_EXT_BIT0_INT_RAW_V << SLCHOST_SLC1_EXT_BIT0_INT_RAW_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_RAW (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_M (SLCHOST_SLC1_EXT_BIT1_INT_RAW_V << SLCHOST_SLC1_EXT_BIT1_INT_RAW_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_RAW (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_M (SLCHOST_SLC1_EXT_BIT2_INT_RAW_V << SLCHOST_SLC1_EXT_BIT2_INT_RAW_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_RAW (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_M (SLCHOST_SLC1_EXT_BIT3_INT_RAW_V << SLCHOST_SLC1_EXT_BIT3_INT_RAW_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S 25 + +/** SLCHOST_SLC0HOST_INT_ST_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_M (SLCHOST_SLC0HOST_RX_SOF_INT_ST_V << SLCHOST_SLC0HOST_RX_SOF_INT_ST_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_M (SLCHOST_SLC0HOST_RX_EOF_INT_ST_V << SLCHOST_SLC0HOST_RX_EOF_INT_ST_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_ST (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_ST_M (SLCHOST_SLC0HOST_RX_START_INT_ST_V << SLCHOST_SLC0HOST_RX_START_INT_ST_S) +#define SLCHOST_SLC0HOST_RX_START_INT_ST_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_ST_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_ST (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_ST_M (SLCHOST_SLC0HOST_TX_START_INT_ST_V << SLCHOST_SLC0HOST_TX_START_INT_ST_S) +#define SLCHOST_SLC0HOST_TX_START_INT_ST_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_ST_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_ST (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_ST_M (SLCHOST_SLC0_RX_UDF_INT_ST_V << SLCHOST_SLC0_RX_UDF_INT_ST_S) +#define SLCHOST_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_ST_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_ST (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_ST_M (SLCHOST_SLC0_TX_OVF_INT_ST_V << SLCHOST_SLC0_TX_OVF_INT_ST_S) +#define SLCHOST_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_ST_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_M (SLCHOST_SLC0_RX_PF_VALID_INT_ST_V << SLCHOST_SLC0_RX_PF_VALID_INT_ST_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_ST_M (SLCHOST_SLC0_EXT_BIT0_INT_ST_V << SLCHOST_SLC0_EXT_BIT0_INT_ST_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_ST_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_ST_M (SLCHOST_SLC0_EXT_BIT1_INT_ST_V << SLCHOST_SLC0_EXT_BIT1_INT_ST_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_ST_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_ST_M (SLCHOST_SLC0_EXT_BIT2_INT_ST_V << SLCHOST_SLC0_EXT_BIT2_INT_ST_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_ST_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_ST_M (SLCHOST_SLC0_EXT_BIT3_INT_ST_V << SLCHOST_SLC0_EXT_BIT3_INT_ST_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_ST_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 +/** SLCHOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_ST (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_ST_M (SLCHOST_GPIO_SDIO_INT_ST_V << SLCHOST_GPIO_SDIO_INT_ST_S) +#define SLCHOST_GPIO_SDIO_INT_ST_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_ST_S 25 + +/** SLCHOST_SLC1HOST_INT_ST_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5c) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_ST (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_M (SLCHOST_SLC1HOST_RX_SOF_INT_ST_V << SLCHOST_SLC1HOST_RX_SOF_INT_ST_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_ST (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_M (SLCHOST_SLC1HOST_RX_EOF_INT_ST_V << SLCHOST_SLC1HOST_RX_EOF_INT_ST_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_ST (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_ST_M (SLCHOST_SLC1HOST_RX_START_INT_ST_V << SLCHOST_SLC1HOST_RX_START_INT_ST_S) +#define SLCHOST_SLC1HOST_RX_START_INT_ST_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_ST_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_ST (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_ST_M (SLCHOST_SLC1HOST_TX_START_INT_ST_V << SLCHOST_SLC1HOST_TX_START_INT_ST_S) +#define SLCHOST_SLC1HOST_TX_START_INT_ST_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_ST_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_ST (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_ST_M (SLCHOST_SLC1_RX_UDF_INT_ST_V << SLCHOST_SLC1_RX_UDF_INT_ST_S) +#define SLCHOST_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_ST_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_ST (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_ST_M (SLCHOST_SLC1_TX_OVF_INT_ST_V << SLCHOST_SLC1_TX_OVF_INT_ST_S) +#define SLCHOST_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_ST_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_ST (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_M (SLCHOST_SLC1_RX_PF_VALID_INT_ST_V << SLCHOST_SLC1_RX_PF_VALID_INT_ST_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_ST (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_ST_M (SLCHOST_SLC1_EXT_BIT0_INT_ST_V << SLCHOST_SLC1_EXT_BIT0_INT_ST_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_ST_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_ST (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_ST_M (SLCHOST_SLC1_EXT_BIT1_INT_ST_V << SLCHOST_SLC1_EXT_BIT1_INT_ST_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_ST_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_ST (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_ST_M (SLCHOST_SLC1_EXT_BIT2_INT_ST_V << SLCHOST_SLC1_EXT_BIT2_INT_ST_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_ST_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_ST (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_ST_M (SLCHOST_SLC1_EXT_BIT3_INT_ST_V << SLCHOST_SLC1_EXT_BIT3_INT_ST_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_ST_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S 25 + +/** SLCHOST_PKT_LEN_REG register + * *******Description*********** + */ +#define SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60) +/** SLCHOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_M (SLCHOST_HOSTSLCHOST_SLC0_LEN_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_V 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_S 0 +/** SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S 20 + +/** SLCHOST_STATE_W0_REG register + * *******Description*********** + */ +#define SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64) +/** SLCHOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE0 0x000000FFU +#define SLCHOST_SLCHOST_STATE0_M (SLCHOST_SLCHOST_STATE0_V << SLCHOST_SLCHOST_STATE0_S) +#define SLCHOST_SLCHOST_STATE0_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE0_S 0 +/** SLCHOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE1 0x000000FFU +#define SLCHOST_SLCHOST_STATE1_M (SLCHOST_SLCHOST_STATE1_V << SLCHOST_SLCHOST_STATE1_S) +#define SLCHOST_SLCHOST_STATE1_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE1_S 8 +/** SLCHOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE2 0x000000FFU +#define SLCHOST_SLCHOST_STATE2_M (SLCHOST_SLCHOST_STATE2_V << SLCHOST_SLCHOST_STATE2_S) +#define SLCHOST_SLCHOST_STATE2_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE2_S 16 +/** SLCHOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE3 0x000000FFU +#define SLCHOST_SLCHOST_STATE3_M (SLCHOST_SLCHOST_STATE3_V << SLCHOST_SLCHOST_STATE3_S) +#define SLCHOST_SLCHOST_STATE3_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE3_S 24 + +/** SLCHOST_STATE_W1_REG register + * *******Description*********** + */ +#define SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68) +/** SLCHOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE4 0x000000FFU +#define SLCHOST_SLCHOST_STATE4_M (SLCHOST_SLCHOST_STATE4_V << SLCHOST_SLCHOST_STATE4_S) +#define SLCHOST_SLCHOST_STATE4_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE4_S 0 +/** SLCHOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE5 0x000000FFU +#define SLCHOST_SLCHOST_STATE5_M (SLCHOST_SLCHOST_STATE5_V << SLCHOST_SLCHOST_STATE5_S) +#define SLCHOST_SLCHOST_STATE5_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE5_S 8 +/** SLCHOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE6 0x000000FFU +#define SLCHOST_SLCHOST_STATE6_M (SLCHOST_SLCHOST_STATE6_V << SLCHOST_SLCHOST_STATE6_S) +#define SLCHOST_SLCHOST_STATE6_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE6_S 16 +/** SLCHOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_STATE7 0x000000FFU +#define SLCHOST_SLCHOST_STATE7_M (SLCHOST_SLCHOST_STATE7_V << SLCHOST_SLCHOST_STATE7_S) +#define SLCHOST_SLCHOST_STATE7_V 0x000000FFU +#define SLCHOST_SLCHOST_STATE7_S 24 + +/** SLCHOST_CONF_W0_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6c) +/** SLCHOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF0 0x000000FFU +#define SLCHOST_SLCHOST_CONF0_M (SLCHOST_SLCHOST_CONF0_V << SLCHOST_SLCHOST_CONF0_S) +#define SLCHOST_SLCHOST_CONF0_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF0_S 0 +/** SLCHOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF1 0x000000FFU +#define SLCHOST_SLCHOST_CONF1_M (SLCHOST_SLCHOST_CONF1_V << SLCHOST_SLCHOST_CONF1_S) +#define SLCHOST_SLCHOST_CONF1_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF1_S 8 +/** SLCHOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF2 0x000000FFU +#define SLCHOST_SLCHOST_CONF2_M (SLCHOST_SLCHOST_CONF2_V << SLCHOST_SLCHOST_CONF2_S) +#define SLCHOST_SLCHOST_CONF2_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF2_S 16 +/** SLCHOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF3 0x000000FFU +#define SLCHOST_SLCHOST_CONF3_M (SLCHOST_SLCHOST_CONF3_V << SLCHOST_SLCHOST_CONF3_S) +#define SLCHOST_SLCHOST_CONF3_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF3_S 24 + +/** SLCHOST_CONF_W1_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70) +/** SLCHOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF4 0x000000FFU +#define SLCHOST_SLCHOST_CONF4_M (SLCHOST_SLCHOST_CONF4_V << SLCHOST_SLCHOST_CONF4_S) +#define SLCHOST_SLCHOST_CONF4_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF4_S 0 +/** SLCHOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF5 0x000000FFU +#define SLCHOST_SLCHOST_CONF5_M (SLCHOST_SLCHOST_CONF5_V << SLCHOST_SLCHOST_CONF5_S) +#define SLCHOST_SLCHOST_CONF5_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF5_S 8 +/** SLCHOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF6 0x000000FFU +#define SLCHOST_SLCHOST_CONF6_M (SLCHOST_SLCHOST_CONF6_V << SLCHOST_SLCHOST_CONF6_S) +#define SLCHOST_SLCHOST_CONF6_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF6_S 16 +/** SLCHOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF7 0x000000FFU +#define SLCHOST_SLCHOST_CONF7_M (SLCHOST_SLCHOST_CONF7_V << SLCHOST_SLCHOST_CONF7_S) +#define SLCHOST_SLCHOST_CONF7_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF7_S 24 + +/** SLCHOST_CONF_W2_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74) +/** SLCHOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF8 0x000000FFU +#define SLCHOST_SLCHOST_CONF8_M (SLCHOST_SLCHOST_CONF8_V << SLCHOST_SLCHOST_CONF8_S) +#define SLCHOST_SLCHOST_CONF8_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF8_S 0 +/** SLCHOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF9 0x000000FFU +#define SLCHOST_SLCHOST_CONF9_M (SLCHOST_SLCHOST_CONF9_V << SLCHOST_SLCHOST_CONF9_S) +#define SLCHOST_SLCHOST_CONF9_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF9_S 8 +/** SLCHOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF10 0x000000FFU +#define SLCHOST_SLCHOST_CONF10_M (SLCHOST_SLCHOST_CONF10_V << SLCHOST_SLCHOST_CONF10_S) +#define SLCHOST_SLCHOST_CONF10_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF10_S 16 +/** SLCHOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF11 0x000000FFU +#define SLCHOST_SLCHOST_CONF11_M (SLCHOST_SLCHOST_CONF11_V << SLCHOST_SLCHOST_CONF11_S) +#define SLCHOST_SLCHOST_CONF11_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF11_S 24 + +/** SLCHOST_CONF_W3_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78) +/** SLCHOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF12 0x000000FFU +#define SLCHOST_SLCHOST_CONF12_M (SLCHOST_SLCHOST_CONF12_V << SLCHOST_SLCHOST_CONF12_S) +#define SLCHOST_SLCHOST_CONF12_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF12_S 0 +/** SLCHOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF13 0x000000FFU +#define SLCHOST_SLCHOST_CONF13_M (SLCHOST_SLCHOST_CONF13_V << SLCHOST_SLCHOST_CONF13_S) +#define SLCHOST_SLCHOST_CONF13_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF13_S 8 +/** SLCHOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF14 0x000000FFU +#define SLCHOST_SLCHOST_CONF14_M (SLCHOST_SLCHOST_CONF14_V << SLCHOST_SLCHOST_CONF14_S) +#define SLCHOST_SLCHOST_CONF14_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF14_S 16 +/** SLCHOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF15 0x000000FFU +#define SLCHOST_SLCHOST_CONF15_M (SLCHOST_SLCHOST_CONF15_V << SLCHOST_SLCHOST_CONF15_S) +#define SLCHOST_SLCHOST_CONF15_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF15_S 24 + +/** SLCHOST_CONF_W4_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7c) +/** SLCHOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF16 0x000000FFU +#define SLCHOST_SLCHOST_CONF16_M (SLCHOST_SLCHOST_CONF16_V << SLCHOST_SLCHOST_CONF16_S) +#define SLCHOST_SLCHOST_CONF16_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF16_S 0 +/** SLCHOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF17 0x000000FFU +#define SLCHOST_SLCHOST_CONF17_M (SLCHOST_SLCHOST_CONF17_V << SLCHOST_SLCHOST_CONF17_S) +#define SLCHOST_SLCHOST_CONF17_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF17_S 8 +/** SLCHOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF18 0x000000FFU +#define SLCHOST_SLCHOST_CONF18_M (SLCHOST_SLCHOST_CONF18_V << SLCHOST_SLCHOST_CONF18_S) +#define SLCHOST_SLCHOST_CONF18_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF18_S 16 +/** SLCHOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF19 0x000000FFU +#define SLCHOST_SLCHOST_CONF19_M (SLCHOST_SLCHOST_CONF19_V << SLCHOST_SLCHOST_CONF19_S) +#define SLCHOST_SLCHOST_CONF19_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF19_S 24 + +/** SLCHOST_CONF_W5_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80) +/** SLCHOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF20 0x000000FFU +#define SLCHOST_SLCHOST_CONF20_M (SLCHOST_SLCHOST_CONF20_V << SLCHOST_SLCHOST_CONF20_S) +#define SLCHOST_SLCHOST_CONF20_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF20_S 0 +/** SLCHOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF21 0x000000FFU +#define SLCHOST_SLCHOST_CONF21_M (SLCHOST_SLCHOST_CONF21_V << SLCHOST_SLCHOST_CONF21_S) +#define SLCHOST_SLCHOST_CONF21_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF21_S 8 +/** SLCHOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF22 0x000000FFU +#define SLCHOST_SLCHOST_CONF22_M (SLCHOST_SLCHOST_CONF22_V << SLCHOST_SLCHOST_CONF22_S) +#define SLCHOST_SLCHOST_CONF22_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF22_S 16 +/** SLCHOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF23 0x000000FFU +#define SLCHOST_SLCHOST_CONF23_M (SLCHOST_SLCHOST_CONF23_V << SLCHOST_SLCHOST_CONF23_S) +#define SLCHOST_SLCHOST_CONF23_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF23_S 24 + +/** SLCHOST_WIN_CMD_REG register + * *******Description*********** + */ +#define SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84) +/** SLCHOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_WIN_CMD 0x0000FFFFU +#define SLCHOST_SLCHOST_WIN_CMD_M (SLCHOST_SLCHOST_WIN_CMD_V << SLCHOST_SLCHOST_WIN_CMD_S) +#define SLCHOST_SLCHOST_WIN_CMD_V 0x0000FFFFU +#define SLCHOST_SLCHOST_WIN_CMD_S 0 + +/** SLCHOST_CONF_W6_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88) +/** SLCHOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF24 0x000000FFU +#define SLCHOST_SLCHOST_CONF24_M (SLCHOST_SLCHOST_CONF24_V << SLCHOST_SLCHOST_CONF24_S) +#define SLCHOST_SLCHOST_CONF24_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF24_S 0 +/** SLCHOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF25 0x000000FFU +#define SLCHOST_SLCHOST_CONF25_M (SLCHOST_SLCHOST_CONF25_V << SLCHOST_SLCHOST_CONF25_S) +#define SLCHOST_SLCHOST_CONF25_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF25_S 8 +/** SLCHOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF26 0x000000FFU +#define SLCHOST_SLCHOST_CONF26_M (SLCHOST_SLCHOST_CONF26_V << SLCHOST_SLCHOST_CONF26_S) +#define SLCHOST_SLCHOST_CONF26_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF26_S 16 +/** SLCHOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF27 0x000000FFU +#define SLCHOST_SLCHOST_CONF27_M (SLCHOST_SLCHOST_CONF27_V << SLCHOST_SLCHOST_CONF27_S) +#define SLCHOST_SLCHOST_CONF27_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF27_S 24 + +/** SLCHOST_CONF_W7_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8c) +/** SLCHOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF28 0x000000FFU +#define SLCHOST_SLCHOST_CONF28_M (SLCHOST_SLCHOST_CONF28_V << SLCHOST_SLCHOST_CONF28_S) +#define SLCHOST_SLCHOST_CONF28_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF28_S 0 +/** SLCHOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF29 0x000000FFU +#define SLCHOST_SLCHOST_CONF29_M (SLCHOST_SLCHOST_CONF29_V << SLCHOST_SLCHOST_CONF29_S) +#define SLCHOST_SLCHOST_CONF29_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF29_S 8 +/** SLCHOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF30 0x000000FFU +#define SLCHOST_SLCHOST_CONF30_M (SLCHOST_SLCHOST_CONF30_V << SLCHOST_SLCHOST_CONF30_S) +#define SLCHOST_SLCHOST_CONF30_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF30_S 16 +/** SLCHOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF31 0x000000FFU +#define SLCHOST_SLCHOST_CONF31_M (SLCHOST_SLCHOST_CONF31_V << SLCHOST_SLCHOST_CONF31_S) +#define SLCHOST_SLCHOST_CONF31_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF31_S 24 + +/** SLCHOST_PKT_LEN0_REG register + * *******Description*********** + */ +#define SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90) +/** SLCHOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_M (SLCHOST_HOSTSLCHOST_SLC0_LEN0_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_V 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_S 0 +/** SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S 20 + +/** SLCHOST_PKT_LEN1_REG register + * *******Description*********** + */ +#define SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94) +/** SLCHOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_M (SLCHOST_HOSTSLCHOST_SLC0_LEN1_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_V 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_S 0 +/** SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S 20 + +/** SLCHOST_PKT_LEN2_REG register + * *******Description*********** + */ +#define SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98) +/** SLCHOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_M (SLCHOST_HOSTSLCHOST_SLC0_LEN2_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_V 0x000FFFFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_S 0 +/** SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M (SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S) +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S 20 + +/** SLCHOST_CONF_W8_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9c) +/** SLCHOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF32 0x000000FFU +#define SLCHOST_SLCHOST_CONF32_M (SLCHOST_SLCHOST_CONF32_V << SLCHOST_SLCHOST_CONF32_S) +#define SLCHOST_SLCHOST_CONF32_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF32_S 0 +/** SLCHOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF33 0x000000FFU +#define SLCHOST_SLCHOST_CONF33_M (SLCHOST_SLCHOST_CONF33_V << SLCHOST_SLCHOST_CONF33_S) +#define SLCHOST_SLCHOST_CONF33_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF33_S 8 +/** SLCHOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF34 0x000000FFU +#define SLCHOST_SLCHOST_CONF34_M (SLCHOST_SLCHOST_CONF34_V << SLCHOST_SLCHOST_CONF34_S) +#define SLCHOST_SLCHOST_CONF34_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF34_S 16 +/** SLCHOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF35 0x000000FFU +#define SLCHOST_SLCHOST_CONF35_M (SLCHOST_SLCHOST_CONF35_V << SLCHOST_SLCHOST_CONF35_S) +#define SLCHOST_SLCHOST_CONF35_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF35_S 24 + +/** SLCHOST_CONF_W9_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xa0) +/** SLCHOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF36 0x000000FFU +#define SLCHOST_SLCHOST_CONF36_M (SLCHOST_SLCHOST_CONF36_V << SLCHOST_SLCHOST_CONF36_S) +#define SLCHOST_SLCHOST_CONF36_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF36_S 0 +/** SLCHOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF37 0x000000FFU +#define SLCHOST_SLCHOST_CONF37_M (SLCHOST_SLCHOST_CONF37_V << SLCHOST_SLCHOST_CONF37_S) +#define SLCHOST_SLCHOST_CONF37_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF37_S 8 +/** SLCHOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF38 0x000000FFU +#define SLCHOST_SLCHOST_CONF38_M (SLCHOST_SLCHOST_CONF38_V << SLCHOST_SLCHOST_CONF38_S) +#define SLCHOST_SLCHOST_CONF38_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF38_S 16 +/** SLCHOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF39 0x000000FFU +#define SLCHOST_SLCHOST_CONF39_M (SLCHOST_SLCHOST_CONF39_V << SLCHOST_SLCHOST_CONF39_S) +#define SLCHOST_SLCHOST_CONF39_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF39_S 24 + +/** SLCHOST_CONF_W10_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xa4) +/** SLCHOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF40 0x000000FFU +#define SLCHOST_SLCHOST_CONF40_M (SLCHOST_SLCHOST_CONF40_V << SLCHOST_SLCHOST_CONF40_S) +#define SLCHOST_SLCHOST_CONF40_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF40_S 0 +/** SLCHOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF41 0x000000FFU +#define SLCHOST_SLCHOST_CONF41_M (SLCHOST_SLCHOST_CONF41_V << SLCHOST_SLCHOST_CONF41_S) +#define SLCHOST_SLCHOST_CONF41_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF41_S 8 +/** SLCHOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF42 0x000000FFU +#define SLCHOST_SLCHOST_CONF42_M (SLCHOST_SLCHOST_CONF42_V << SLCHOST_SLCHOST_CONF42_S) +#define SLCHOST_SLCHOST_CONF42_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF42_S 16 +/** SLCHOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF43 0x000000FFU +#define SLCHOST_SLCHOST_CONF43_M (SLCHOST_SLCHOST_CONF43_V << SLCHOST_SLCHOST_CONF43_S) +#define SLCHOST_SLCHOST_CONF43_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF43_S 24 + +/** SLCHOST_CONF_W11_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xa8) +/** SLCHOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF44 0x000000FFU +#define SLCHOST_SLCHOST_CONF44_M (SLCHOST_SLCHOST_CONF44_V << SLCHOST_SLCHOST_CONF44_S) +#define SLCHOST_SLCHOST_CONF44_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF44_S 0 +/** SLCHOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF45 0x000000FFU +#define SLCHOST_SLCHOST_CONF45_M (SLCHOST_SLCHOST_CONF45_V << SLCHOST_SLCHOST_CONF45_S) +#define SLCHOST_SLCHOST_CONF45_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF45_S 8 +/** SLCHOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF46 0x000000FFU +#define SLCHOST_SLCHOST_CONF46_M (SLCHOST_SLCHOST_CONF46_V << SLCHOST_SLCHOST_CONF46_S) +#define SLCHOST_SLCHOST_CONF46_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF46_S 16 +/** SLCHOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF47 0x000000FFU +#define SLCHOST_SLCHOST_CONF47_M (SLCHOST_SLCHOST_CONF47_V << SLCHOST_SLCHOST_CONF47_S) +#define SLCHOST_SLCHOST_CONF47_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF47_S 24 + +/** SLCHOST_CONF_W12_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xac) +/** SLCHOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF48 0x000000FFU +#define SLCHOST_SLCHOST_CONF48_M (SLCHOST_SLCHOST_CONF48_V << SLCHOST_SLCHOST_CONF48_S) +#define SLCHOST_SLCHOST_CONF48_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF48_S 0 +/** SLCHOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF49 0x000000FFU +#define SLCHOST_SLCHOST_CONF49_M (SLCHOST_SLCHOST_CONF49_V << SLCHOST_SLCHOST_CONF49_S) +#define SLCHOST_SLCHOST_CONF49_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF49_S 8 +/** SLCHOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF50 0x000000FFU +#define SLCHOST_SLCHOST_CONF50_M (SLCHOST_SLCHOST_CONF50_V << SLCHOST_SLCHOST_CONF50_S) +#define SLCHOST_SLCHOST_CONF50_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF50_S 16 +/** SLCHOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF51 0x000000FFU +#define SLCHOST_SLCHOST_CONF51_M (SLCHOST_SLCHOST_CONF51_V << SLCHOST_SLCHOST_CONF51_S) +#define SLCHOST_SLCHOST_CONF51_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF51_S 24 + +/** SLCHOST_CONF_W13_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xb0) +/** SLCHOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF52 0x000000FFU +#define SLCHOST_SLCHOST_CONF52_M (SLCHOST_SLCHOST_CONF52_V << SLCHOST_SLCHOST_CONF52_S) +#define SLCHOST_SLCHOST_CONF52_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF52_S 0 +/** SLCHOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF53 0x000000FFU +#define SLCHOST_SLCHOST_CONF53_M (SLCHOST_SLCHOST_CONF53_V << SLCHOST_SLCHOST_CONF53_S) +#define SLCHOST_SLCHOST_CONF53_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF53_S 8 +/** SLCHOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF54 0x000000FFU +#define SLCHOST_SLCHOST_CONF54_M (SLCHOST_SLCHOST_CONF54_V << SLCHOST_SLCHOST_CONF54_S) +#define SLCHOST_SLCHOST_CONF54_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF54_S 16 +/** SLCHOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF55 0x000000FFU +#define SLCHOST_SLCHOST_CONF55_M (SLCHOST_SLCHOST_CONF55_V << SLCHOST_SLCHOST_CONF55_S) +#define SLCHOST_SLCHOST_CONF55_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF55_S 24 + +/** SLCHOST_CONF_W14_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xb4) +/** SLCHOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF56 0x000000FFU +#define SLCHOST_SLCHOST_CONF56_M (SLCHOST_SLCHOST_CONF56_V << SLCHOST_SLCHOST_CONF56_S) +#define SLCHOST_SLCHOST_CONF56_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF56_S 0 +/** SLCHOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF57 0x000000FFU +#define SLCHOST_SLCHOST_CONF57_M (SLCHOST_SLCHOST_CONF57_V << SLCHOST_SLCHOST_CONF57_S) +#define SLCHOST_SLCHOST_CONF57_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF57_S 8 +/** SLCHOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF58 0x000000FFU +#define SLCHOST_SLCHOST_CONF58_M (SLCHOST_SLCHOST_CONF58_V << SLCHOST_SLCHOST_CONF58_S) +#define SLCHOST_SLCHOST_CONF58_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF58_S 16 +/** SLCHOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF59 0x000000FFU +#define SLCHOST_SLCHOST_CONF59_M (SLCHOST_SLCHOST_CONF59_V << SLCHOST_SLCHOST_CONF59_S) +#define SLCHOST_SLCHOST_CONF59_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF59_S 24 + +/** SLCHOST_CONF_W15_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xb8) +/** SLCHOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF60 0x000000FFU +#define SLCHOST_SLCHOST_CONF60_M (SLCHOST_SLCHOST_CONF60_V << SLCHOST_SLCHOST_CONF60_S) +#define SLCHOST_SLCHOST_CONF60_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF60_S 0 +/** SLCHOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF61 0x000000FFU +#define SLCHOST_SLCHOST_CONF61_M (SLCHOST_SLCHOST_CONF61_V << SLCHOST_SLCHOST_CONF61_S) +#define SLCHOST_SLCHOST_CONF61_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF61_S 8 +/** SLCHOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF62 0x000000FFU +#define SLCHOST_SLCHOST_CONF62_M (SLCHOST_SLCHOST_CONF62_V << SLCHOST_SLCHOST_CONF62_S) +#define SLCHOST_SLCHOST_CONF62_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF62_S 16 +/** SLCHOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CONF63 0x000000FFU +#define SLCHOST_SLCHOST_CONF63_M (SLCHOST_SLCHOST_CONF63_V << SLCHOST_SLCHOST_CONF63_S) +#define SLCHOST_SLCHOST_CONF63_V 0x000000FFU +#define SLCHOST_SLCHOST_CONF63_S 24 + +/** SLCHOST_CHECK_SUM0_REG register + * *******Description*********** + */ +#define SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xbc) +/** SLCHOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CHECK_SUM0 0xFFFFFFFFU +#define SLCHOST_SLCHOST_CHECK_SUM0_M (SLCHOST_SLCHOST_CHECK_SUM0_V << SLCHOST_SLCHOST_CHECK_SUM0_S) +#define SLCHOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFFU +#define SLCHOST_SLCHOST_CHECK_SUM0_S 0 + +/** SLCHOST_CHECK_SUM1_REG register + * *******Description*********** + */ +#define SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xc0) +/** SLCHOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_CHECK_SUM1 0xFFFFFFFFU +#define SLCHOST_SLCHOST_CHECK_SUM1_M (SLCHOST_SLCHOST_CHECK_SUM1_V << SLCHOST_SLCHOST_CHECK_SUM1_S) +#define SLCHOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFFU +#define SLCHOST_SLCHOST_CHECK_SUM1_S 0 + +/** SLCHOST_SLC1HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xc4) +/** SLCHOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0 0x00000FFFU +#define SLCHOST_SLC1_TOKEN0_M (SLCHOST_SLC1_TOKEN0_V << SLCHOST_SLC1_TOKEN0_S) +#define SLCHOST_SLC1_TOKEN0_V 0x00000FFFU +#define SLCHOST_SLC1_TOKEN0_S 0 +/** SLCHOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID (BIT(12)) +#define SLCHOST_SLC1_RX_PF_VALID_M (SLCHOST_SLC1_RX_PF_VALID_V << SLCHOST_SLC1_RX_PF_VALID_S) +#define SLCHOST_SLC1_RX_PF_VALID_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_S 12 +/** SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_M (SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S) +#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V 0x00000FFFU +#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S 16 +/** SLCHOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_EOF 0x0000000FU +#define SLCHOST_SLC1_RX_PF_EOF_M (SLCHOST_SLC1_RX_PF_EOF_V << SLCHOST_SLC1_RX_PF_EOF_S) +#define SLCHOST_SLC1_RX_PF_EOF_V 0x0000000FU +#define SLCHOST_SLC1_RX_PF_EOF_S 28 + +/** SLCHOST_SLC0HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xc8) +/** SLCHOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN0_WD 0x00000FFFU +#define SLCHOST_SLC0HOST_TOKEN0_WD_M (SLCHOST_SLC0HOST_TOKEN0_WD_V << SLCHOST_SLC0HOST_TOKEN0_WD_S) +#define SLCHOST_SLC0HOST_TOKEN0_WD_V 0x00000FFFU +#define SLCHOST_SLC0HOST_TOKEN0_WD_S 0 +/** SLCHOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN1_WD 0x00000FFFU +#define SLCHOST_SLC0HOST_TOKEN1_WD_M (SLCHOST_SLC0HOST_TOKEN1_WD_V << SLCHOST_SLC0HOST_TOKEN1_WD_S) +#define SLCHOST_SLC0HOST_TOKEN1_WD_V 0x00000FFFU +#define SLCHOST_SLC0HOST_TOKEN1_WD_S 16 + +/** SLCHOST_SLC1HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xcc) +/** SLCHOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN0_WD 0x00000FFFU +#define SLCHOST_SLC1HOST_TOKEN0_WD_M (SLCHOST_SLC1HOST_TOKEN0_WD_V << SLCHOST_SLC1HOST_TOKEN0_WD_S) +#define SLCHOST_SLC1HOST_TOKEN0_WD_V 0x00000FFFU +#define SLCHOST_SLC1HOST_TOKEN0_WD_S 0 +/** SLCHOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN1_WD 0x00000FFFU +#define SLCHOST_SLC1HOST_TOKEN1_WD_M (SLCHOST_SLC1HOST_TOKEN1_WD_V << SLCHOST_SLC1HOST_TOKEN1_WD_S) +#define SLCHOST_SLC1HOST_TOKEN1_WD_V 0x00000FFFU +#define SLCHOST_SLC1HOST_TOKEN1_WD_S 16 + +/** SLCHOST_TOKEN_CON_REG register + * *******Description*********** + */ +#define SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xd0) +/** SLCHOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN0_DEC (BIT(0)) +#define SLCHOST_SLC0HOST_TOKEN0_DEC_M (SLCHOST_SLC0HOST_TOKEN0_DEC_V << SLCHOST_SLC0HOST_TOKEN0_DEC_S) +#define SLCHOST_SLC0HOST_TOKEN0_DEC_V 0x00000001U +#define SLCHOST_SLC0HOST_TOKEN0_DEC_S 0 +/** SLCHOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN1_DEC (BIT(1)) +#define SLCHOST_SLC0HOST_TOKEN1_DEC_M (SLCHOST_SLC0HOST_TOKEN1_DEC_V << SLCHOST_SLC0HOST_TOKEN1_DEC_S) +#define SLCHOST_SLC0HOST_TOKEN1_DEC_V 0x00000001U +#define SLCHOST_SLC0HOST_TOKEN1_DEC_S 1 +/** SLCHOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN0_WR (BIT(2)) +#define SLCHOST_SLC0HOST_TOKEN0_WR_M (SLCHOST_SLC0HOST_TOKEN0_WR_V << SLCHOST_SLC0HOST_TOKEN0_WR_S) +#define SLCHOST_SLC0HOST_TOKEN0_WR_V 0x00000001U +#define SLCHOST_SLC0HOST_TOKEN0_WR_S 2 +/** SLCHOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TOKEN1_WR (BIT(3)) +#define SLCHOST_SLC0HOST_TOKEN1_WR_M (SLCHOST_SLC0HOST_TOKEN1_WR_V << SLCHOST_SLC0HOST_TOKEN1_WR_S) +#define SLCHOST_SLC0HOST_TOKEN1_WR_V 0x00000001U +#define SLCHOST_SLC0HOST_TOKEN1_WR_S 3 +/** SLCHOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN0_DEC (BIT(4)) +#define SLCHOST_SLC1HOST_TOKEN0_DEC_M (SLCHOST_SLC1HOST_TOKEN0_DEC_V << SLCHOST_SLC1HOST_TOKEN0_DEC_S) +#define SLCHOST_SLC1HOST_TOKEN0_DEC_V 0x00000001U +#define SLCHOST_SLC1HOST_TOKEN0_DEC_S 4 +/** SLCHOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN1_DEC (BIT(5)) +#define SLCHOST_SLC1HOST_TOKEN1_DEC_M (SLCHOST_SLC1HOST_TOKEN1_DEC_V << SLCHOST_SLC1HOST_TOKEN1_DEC_S) +#define SLCHOST_SLC1HOST_TOKEN1_DEC_V 0x00000001U +#define SLCHOST_SLC1HOST_TOKEN1_DEC_S 5 +/** SLCHOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN0_WR (BIT(6)) +#define SLCHOST_SLC1HOST_TOKEN0_WR_M (SLCHOST_SLC1HOST_TOKEN0_WR_V << SLCHOST_SLC1HOST_TOKEN0_WR_S) +#define SLCHOST_SLC1HOST_TOKEN0_WR_V 0x00000001U +#define SLCHOST_SLC1HOST_TOKEN0_WR_S 6 +/** SLCHOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TOKEN1_WR (BIT(7)) +#define SLCHOST_SLC1HOST_TOKEN1_WR_M (SLCHOST_SLC1HOST_TOKEN1_WR_V << SLCHOST_SLC1HOST_TOKEN1_WR_S) +#define SLCHOST_SLC1HOST_TOKEN1_WR_V 0x00000001U +#define SLCHOST_SLC1HOST_TOKEN1_WR_S 7 +/** SLCHOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_LEN_WR (BIT(8)) +#define SLCHOST_SLC0HOST_LEN_WR_M (SLCHOST_SLC0HOST_LEN_WR_V << SLCHOST_SLC0HOST_LEN_WR_S) +#define SLCHOST_SLC0HOST_LEN_WR_V 0x00000001U +#define SLCHOST_SLC0HOST_LEN_WR_S 8 + +/** SLCHOST_SLC0HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd4) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_M (SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_M (SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_M (SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_CLR_M (SLCHOST_SLC0HOST_RX_START_INT_CLR_V << SLCHOST_SLC0HOST_RX_START_INT_CLR_S) +#define SLCHOST_SLC0HOST_RX_START_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_CLR_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_CLR_M (SLCHOST_SLC0HOST_TX_START_INT_CLR_V << SLCHOST_SLC0HOST_TX_START_INT_CLR_S) +#define SLCHOST_SLC0HOST_TX_START_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_CLR_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_CLR (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_CLR_M (SLCHOST_SLC0_RX_UDF_INT_CLR_V << SLCHOST_SLC0_RX_UDF_INT_CLR_S) +#define SLCHOST_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_CLR_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_CLR (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_CLR_M (SLCHOST_SLC0_TX_OVF_INT_CLR_V << SLCHOST_SLC0_TX_OVF_INT_CLR_S) +#define SLCHOST_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_CLR_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_M (SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_M (SLCHOST_SLC0_EXT_BIT0_INT_CLR_V << SLCHOST_SLC0_EXT_BIT0_INT_CLR_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_M (SLCHOST_SLC0_EXT_BIT1_INT_CLR_V << SLCHOST_SLC0_EXT_BIT1_INT_CLR_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_M (SLCHOST_SLC0_EXT_BIT2_INT_CLR_V << SLCHOST_SLC0_EXT_BIT2_INT_CLR_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_M (SLCHOST_SLC0_EXT_BIT3_INT_CLR_V << SLCHOST_SLC0_EXT_BIT3_INT_CLR_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 +/** SLCHOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_CLR (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_CLR_M (SLCHOST_GPIO_SDIO_INT_CLR_V << SLCHOST_GPIO_SDIO_INT_CLR_S) +#define SLCHOST_GPIO_SDIO_INT_CLR_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_CLR_S 25 + +/** SLCHOST_SLC1HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd8) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_M (SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_M (SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_M (SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_CLR (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_CLR_M (SLCHOST_SLC1HOST_RX_START_INT_CLR_V << SLCHOST_SLC1HOST_RX_START_INT_CLR_S) +#define SLCHOST_SLC1HOST_RX_START_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_CLR_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_CLR (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_CLR_M (SLCHOST_SLC1HOST_TX_START_INT_CLR_V << SLCHOST_SLC1HOST_TX_START_INT_CLR_S) +#define SLCHOST_SLC1HOST_TX_START_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_CLR_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_CLR (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_CLR_M (SLCHOST_SLC1_RX_UDF_INT_CLR_V << SLCHOST_SLC1_RX_UDF_INT_CLR_S) +#define SLCHOST_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_CLR_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_CLR (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_CLR_M (SLCHOST_SLC1_TX_OVF_INT_CLR_V << SLCHOST_SLC1_TX_OVF_INT_CLR_S) +#define SLCHOST_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_CLR_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_M (SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_CLR (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_M (SLCHOST_SLC1_EXT_BIT0_INT_CLR_V << SLCHOST_SLC1_EXT_BIT0_INT_CLR_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_CLR (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_M (SLCHOST_SLC1_EXT_BIT1_INT_CLR_V << SLCHOST_SLC1_EXT_BIT1_INT_CLR_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_CLR (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_M (SLCHOST_SLC1_EXT_BIT2_INT_CLR_V << SLCHOST_SLC1_EXT_BIT2_INT_CLR_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_CLR (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_M (SLCHOST_SLC1_EXT_BIT3_INT_CLR_V << SLCHOST_SLC1_EXT_BIT3_INT_CLR_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S 25 + +/** SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xdc) +/** SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S) +#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S) +#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_M (SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S) +#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 +/** SLCHOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_M (SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S) +#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 +/** SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S) +#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S) +#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S) +#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S) +#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) +#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_M (SLCHOST_FN1_GPIO_SDIO_INT_ENA_V << SLCHOST_FN1_GPIO_SDIO_INT_ENA_S) +#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_S 25 + +/** SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe0) +/** SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S) +#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S) +#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_M (SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S) +#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S 16 +/** SLCHOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_M (SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S) +#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S 17 +/** SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S) +#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S) +#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S) +#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S) +#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe4) +/** SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S) +#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S) +#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_M (SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S) +#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S 16 +/** SLCHOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_M (SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S) +#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S 17 +/** SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S) +#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S) +#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S) +#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S) +#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_GPIO_SDIO_INT_ENA (BIT(25)) +#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_M (SLCHOST_FN2_GPIO_SDIO_INT_ENA_V << SLCHOST_FN2_GPIO_SDIO_INT_ENA_S) +#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_S 25 + +/** SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe8) +/** SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S) +#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S) +#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_M (SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S) +#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S 16 +/** SLCHOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_M (SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S) +#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S 17 +/** SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S) +#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S) +#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S) +#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S) +#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SLCHOST_SLC0HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xec) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_M (SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_M (SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_ENA_M (SLCHOST_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_SLC0HOST_RX_START_INT_ENA_S) +#define SLCHOST_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_ENA_M (SLCHOST_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_SLC0HOST_TX_START_INT_ENA_S) +#define SLCHOST_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_ENA_M (SLCHOST_SLC0_RX_UDF_INT_ENA_V << SLCHOST_SLC0_RX_UDF_INT_ENA_S) +#define SLCHOST_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_ENA_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_ENA_M (SLCHOST_SLC0_TX_OVF_INT_ENA_V << SLCHOST_SLC0_TX_OVF_INT_ENA_S) +#define SLCHOST_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_ENA_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_M (SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_M (SLCHOST_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_M (SLCHOST_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_M (SLCHOST_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_M (SLCHOST_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_ENA (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_ENA_M (SLCHOST_GPIO_SDIO_INT_ENA_V << SLCHOST_GPIO_SDIO_INT_ENA_S) +#define SLCHOST_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_ENA_S 25 + +/** SLCHOST_SLC1HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xf0) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_M (SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_M (SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_ENA_M (SLCHOST_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_SLC1HOST_RX_START_INT_ENA_S) +#define SLCHOST_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_ENA_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_ENA_M (SLCHOST_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_SLC1HOST_TX_START_INT_ENA_S) +#define SLCHOST_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_ENA_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_ENA_M (SLCHOST_SLC1_RX_UDF_INT_ENA_V << SLCHOST_SLC1_RX_UDF_INT_ENA_S) +#define SLCHOST_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_ENA_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_ENA_M (SLCHOST_SLC1_TX_OVF_INT_ENA_V << SLCHOST_SLC1_TX_OVF_INT_ENA_S) +#define SLCHOST_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_ENA_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_M (SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_M (SLCHOST_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_M (SLCHOST_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_M (SLCHOST_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_M (SLCHOST_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SLCHOST_SLC0HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf4) +/** SLCHOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_INFOR 0x000FFFFFU +#define SLCHOST_SLC0HOST_RX_INFOR_M (SLCHOST_SLC0HOST_RX_INFOR_V << SLCHOST_SLC0HOST_RX_INFOR_S) +#define SLCHOST_SLC0HOST_RX_INFOR_V 0x000FFFFFU +#define SLCHOST_SLC0HOST_RX_INFOR_S 0 + +/** SLCHOST_SLC1HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf8) +/** SLCHOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_INFOR 0x000FFFFFU +#define SLCHOST_SLC1HOST_RX_INFOR_M (SLCHOST_SLC1HOST_RX_INFOR_V << SLCHOST_SLC1HOST_RX_INFOR_S) +#define SLCHOST_SLC1HOST_RX_INFOR_V 0x000FFFFFU +#define SLCHOST_SLC1HOST_RX_INFOR_S 0 + +/** SLCHOST_SLC0HOST_LEN_WD_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xfc) +/** SLCHOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_LEN_WD 0xFFFFFFFFU +#define SLCHOST_SLC0HOST_LEN_WD_M (SLCHOST_SLC0HOST_LEN_WD_V << SLCHOST_SLC0HOST_LEN_WD_S) +#define SLCHOST_SLC0HOST_LEN_WD_V 0xFFFFFFFFU +#define SLCHOST_SLC0HOST_LEN_WD_S 0 + +/** SLCHOST_SLC_APBWIN_WDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100) +/** SLCHOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_WDATA 0xFFFFFFFFU +#define SLCHOST_SLC_APBWIN_WDATA_M (SLCHOST_SLC_APBWIN_WDATA_V << SLCHOST_SLC_APBWIN_WDATA_S) +#define SLCHOST_SLC_APBWIN_WDATA_V 0xFFFFFFFFU +#define SLCHOST_SLC_APBWIN_WDATA_S 0 + +/** SLCHOST_SLC_APBWIN_CONF_REG register + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104) +/** SLCHOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_ADDR 0x0FFFFFFFU +#define SLCHOST_SLC_APBWIN_ADDR_M (SLCHOST_SLC_APBWIN_ADDR_V << SLCHOST_SLC_APBWIN_ADDR_S) +#define SLCHOST_SLC_APBWIN_ADDR_V 0x0FFFFFFFU +#define SLCHOST_SLC_APBWIN_ADDR_S 0 +/** SLCHOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_WR (BIT(28)) +#define SLCHOST_SLC_APBWIN_WR_M (SLCHOST_SLC_APBWIN_WR_V << SLCHOST_SLC_APBWIN_WR_S) +#define SLCHOST_SLC_APBWIN_WR_V 0x00000001U +#define SLCHOST_SLC_APBWIN_WR_S 28 +/** SLCHOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_START (BIT(29)) +#define SLCHOST_SLC_APBWIN_START_M (SLCHOST_SLC_APBWIN_START_V << SLCHOST_SLC_APBWIN_START_S) +#define SLCHOST_SLC_APBWIN_START_V 0x00000001U +#define SLCHOST_SLC_APBWIN_START_S 29 + +/** SLCHOST_SLC_APBWIN_RDATA_REG register + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108) +/** SLCHOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC_APBWIN_RDATA 0xFFFFFFFFU +#define SLCHOST_SLC_APBWIN_RDATA_M (SLCHOST_SLC_APBWIN_RDATA_V << SLCHOST_SLC_APBWIN_RDATA_S) +#define SLCHOST_SLC_APBWIN_RDATA_V 0xFFFFFFFFU +#define SLCHOST_SLC_APBWIN_RDATA_S 0 + +/** SLCHOST_RDCLR0_REG register + * *******Description*********** + */ +#define SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10c) +/** SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FFU +#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_M (SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S) +#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x000001FFU +#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 +/** SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FFU +#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_M (SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S) +#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x000001FFU +#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 + +/** SLCHOST_RDCLR1_REG register + * *******Description*********** + */ +#define SLCHOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110) +/** SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR 0x000001FFU +#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_M (SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S) +#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V 0x000001FFU +#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S 0 +/** SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR 0x000001FFU +#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_M (SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S) +#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V 0x000001FFU +#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S 9 + +/** SLCHOST_SLC0HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114) +/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 +/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 +/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 +/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 +/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 +/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 +/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 +/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_M (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S) +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 +/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 +/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 +/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S) +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 +/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S) +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 +/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_M (SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S) +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 +/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_M (SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S) +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 +/** SLCHOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) +#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_M (SLCHOST_SLC0HOST_RX_START_INT_ENA1_V << SLCHOST_SLC0HOST_RX_START_INT_ENA1_S) +#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_S 14 +/** SLCHOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) +#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_M (SLCHOST_SLC0HOST_TX_START_INT_ENA1_V << SLCHOST_SLC0HOST_TX_START_INT_ENA1_S) +#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_S 15 +/** SLCHOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) +#define SLCHOST_SLC0_RX_UDF_INT_ENA1_M (SLCHOST_SLC0_RX_UDF_INT_ENA1_V << SLCHOST_SLC0_RX_UDF_INT_ENA1_S) +#define SLCHOST_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_RX_UDF_INT_ENA1_S 16 +/** SLCHOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) +#define SLCHOST_SLC0_TX_OVF_INT_ENA1_M (SLCHOST_SLC0_TX_OVF_INT_ENA1_V << SLCHOST_SLC0_TX_OVF_INT_ENA1_S) +#define SLCHOST_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_TX_OVF_INT_ENA1_S 17 +/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_M (SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S) +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 +/** SLCHOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S) +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S 19 +/** SLCHOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S) +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S 20 +/** SLCHOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S) +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S 21 +/** SLCHOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_M (SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S) +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S 22 +/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S) +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 +/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S) +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 +/** SLCHOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_GPIO_SDIO_INT_ENA1 (BIT(25)) +#define SLCHOST_GPIO_SDIO_INT_ENA1_M (SLCHOST_GPIO_SDIO_INT_ENA1_V << SLCHOST_GPIO_SDIO_INT_ENA1_S) +#define SLCHOST_GPIO_SDIO_INT_ENA1_V 0x00000001U +#define SLCHOST_GPIO_SDIO_INT_ENA1_S 25 + +/** SLCHOST_SLC1HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118) +/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S 0 +/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S 1 +/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S 2 +/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S 3 +/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S 4 +/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S 5 +/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S 6 +/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_M (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S) +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S 7 +/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_M (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S 8 +/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_M (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S 9 +/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_M (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S) +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S 10 +/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_M (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S) +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S 11 +/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_M (SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S) +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S 12 +/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_M (SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S) +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S 13 +/** SLCHOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_RX_START_INT_ENA1 (BIT(14)) +#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_M (SLCHOST_SLC1HOST_RX_START_INT_ENA1_V << SLCHOST_SLC1HOST_RX_START_INT_ENA1_S) +#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_S 14 +/** SLCHOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1HOST_TX_START_INT_ENA1 (BIT(15)) +#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_M (SLCHOST_SLC1HOST_TX_START_INT_ENA1_V << SLCHOST_SLC1HOST_TX_START_INT_ENA1_S) +#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_S 15 +/** SLCHOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_UDF_INT_ENA1 (BIT(16)) +#define SLCHOST_SLC1_RX_UDF_INT_ENA1_M (SLCHOST_SLC1_RX_UDF_INT_ENA1_V << SLCHOST_SLC1_RX_UDF_INT_ENA1_S) +#define SLCHOST_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_RX_UDF_INT_ENA1_S 16 +/** SLCHOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_TX_OVF_INT_ENA1 (BIT(17)) +#define SLCHOST_SLC1_TX_OVF_INT_ENA1_M (SLCHOST_SLC1_TX_OVF_INT_ENA1_V << SLCHOST_SLC1_TX_OVF_INT_ENA1_S) +#define SLCHOST_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_TX_OVF_INT_ENA1_S 17 +/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_M (SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S) +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S 18 +/** SLCHOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S) +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S 19 +/** SLCHOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S) +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S 20 +/** SLCHOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S) +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S 21 +/** SLCHOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_M (SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S) +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S 22 +/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S) +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S 23 +/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_M (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S) +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S 24 +/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 (BIT(25)) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S) +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S 25 + +/** SLCHOST_SLCHOSTDATE_REG register + * *******Description*********** + */ +#define SLCHOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178) +/** SLCHOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_DATE 0xFFFFFFFFU +#define SLCHOST_SLCHOST_DATE_M (SLCHOST_SLCHOST_DATE_V << SLCHOST_SLCHOST_DATE_S) +#define SLCHOST_SLCHOST_DATE_V 0xFFFFFFFFU +#define SLCHOST_SLCHOST_DATE_S 0 + +/** SLCHOST_SLCHOSTID_REG register + * *******Description*********** + */ +#define SLCHOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17c) +/** SLCHOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ +#define SLCHOST_SLCHOST_ID 0xFFFFFFFFU +#define SLCHOST_SLCHOST_ID_M (SLCHOST_SLCHOST_ID_V << SLCHOST_SLCHOST_ID_S) +#define SLCHOST_SLCHOST_ID_V 0xFFFFFFFFU +#define SLCHOST_SLCHOST_ID_S 0 + +/** SLCHOST_CONF_REG register + * *******Description*********** + */ +#define SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1f0) +/** SLCHOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_SDIO11 0x0000001FU +#define SLCHOST_FRC_SDIO11_M (SLCHOST_FRC_SDIO11_V << SLCHOST_FRC_SDIO11_S) +#define SLCHOST_FRC_SDIO11_V 0x0000001FU +#define SLCHOST_FRC_SDIO11_S 0 +/** SLCHOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_SDIO20 0x0000001FU +#define SLCHOST_FRC_SDIO20_M (SLCHOST_FRC_SDIO20_V << SLCHOST_FRC_SDIO20_S) +#define SLCHOST_FRC_SDIO20_V 0x0000001FU +#define SLCHOST_FRC_SDIO20_S 5 +/** SLCHOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_NEG_SAMP 0x0000001FU +#define SLCHOST_FRC_NEG_SAMP_M (SLCHOST_FRC_NEG_SAMP_V << SLCHOST_FRC_NEG_SAMP_S) +#define SLCHOST_FRC_NEG_SAMP_V 0x0000001FU +#define SLCHOST_FRC_NEG_SAMP_S 10 +/** SLCHOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_POS_SAMP 0x0000001FU +#define SLCHOST_FRC_POS_SAMP_M (SLCHOST_FRC_POS_SAMP_V << SLCHOST_FRC_POS_SAMP_S) +#define SLCHOST_FRC_POS_SAMP_V 0x0000001FU +#define SLCHOST_FRC_POS_SAMP_S 15 +/** SLCHOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ +#define SLCHOST_FRC_QUICK_IN 0x0000001FU +#define SLCHOST_FRC_QUICK_IN_M (SLCHOST_FRC_QUICK_IN_V << SLCHOST_FRC_QUICK_IN_S) +#define SLCHOST_FRC_QUICK_IN_V 0x0000001FU +#define SLCHOST_FRC_QUICK_IN_S 20 +/** SLCHOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO20_INT_DELAY (BIT(25)) +#define SLCHOST_SDIO20_INT_DELAY_M (SLCHOST_SDIO20_INT_DELAY_V << SLCHOST_SDIO20_INT_DELAY_S) +#define SLCHOST_SDIO20_INT_DELAY_V 0x00000001U +#define SLCHOST_SDIO20_INT_DELAY_S 25 +/** SLCHOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO_PAD_PULLUP (BIT(26)) +#define SLCHOST_SDIO_PAD_PULLUP_M (SLCHOST_SDIO_PAD_PULLUP_V << SLCHOST_SDIO_PAD_PULLUP_S) +#define SLCHOST_SDIO_PAD_PULLUP_V 0x00000001U +#define SLCHOST_SDIO_PAD_PULLUP_S 26 +/** SLCHOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ +#define SLCHOST_HSPEED_CON_EN (BIT(27)) +#define SLCHOST_HSPEED_CON_EN_M (SLCHOST_HSPEED_CON_EN_V << SLCHOST_HSPEED_CON_EN_S) +#define SLCHOST_HSPEED_CON_EN_V 0x00000001U +#define SLCHOST_HSPEED_CON_EN_S 27 + +/** SLCHOST_INF_ST_REG register + * *******Description*********** + */ +#define SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1f4) +/** SLCHOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO20_MODE 0x0000001FU +#define SLCHOST_SDIO20_MODE_M (SLCHOST_SDIO20_MODE_V << SLCHOST_SDIO20_MODE_S) +#define SLCHOST_SDIO20_MODE_V 0x0000001FU +#define SLCHOST_SDIO20_MODE_S 0 +/** SLCHOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO_NEG_SAMP 0x0000001FU +#define SLCHOST_SDIO_NEG_SAMP_M (SLCHOST_SDIO_NEG_SAMP_V << SLCHOST_SDIO_NEG_SAMP_S) +#define SLCHOST_SDIO_NEG_SAMP_V 0x0000001FU +#define SLCHOST_SDIO_NEG_SAMP_S 5 +/** SLCHOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SLCHOST_SDIO_QUICK_IN 0x0000001FU +#define SLCHOST_SDIO_QUICK_IN_M (SLCHOST_SDIO_QUICK_IN_V << SLCHOST_SDIO_QUICK_IN_S) +#define SLCHOST_SDIO_QUICK_IN_V 0x0000001FU +#define SLCHOST_SDIO_QUICK_IN_S 10 +/** SLCHOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ +#define SLCHOST_DLL_ON_SW (BIT(15)) +#define SLCHOST_DLL_ON_SW_M (SLCHOST_DLL_ON_SW_V << SLCHOST_DLL_ON_SW_S) +#define SLCHOST_DLL_ON_SW_V 0x00000001U +#define SLCHOST_DLL_ON_SW_S 15 +/** SLCHOST_DLL_ON : R/W; bitpos: [16]; default: 0; + * Software dll on + */ +#define SLCHOST_DLL_ON (BIT(16)) +#define SLCHOST_DLL_ON_M (SLCHOST_DLL_ON_V << SLCHOST_DLL_ON_S) +#define SLCHOST_DLL_ON_V 0x00000001U +#define SLCHOST_DLL_ON_S 16 +/** SLCHOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ +#define SLCHOST_CLK_MODE_SW (BIT(17)) +#define SLCHOST_CLK_MODE_SW_M (SLCHOST_CLK_MODE_SW_V << SLCHOST_CLK_MODE_SW_S) +#define SLCHOST_CLK_MODE_SW_V 0x00000001U +#define SLCHOST_CLK_MODE_SW_S 17 +/** SLCHOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ +#define SLCHOST_CLK_MODE 0x00000003U +#define SLCHOST_CLK_MODE_M (SLCHOST_CLK_MODE_V << SLCHOST_CLK_MODE_S) +#define SLCHOST_CLK_MODE_V 0x00000003U +#define SLCHOST_CLK_MODE_S 18 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/host_struct.h b/components/soc/esp32c5/include/soc/host_struct.h new file mode 100644 index 0000000000..e14afe78f2 --- /dev/null +++ b/components/soc/esp32c5/include/soc/host_struct.h @@ -0,0 +1,2738 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: ********Registers */ +/** Type of func2_0 register + * *******Description*********** + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** slc_func2_int : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc_func2_int:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} slchost_func2_0_reg_t; + +/** Type of func2_1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc_func2_int_en : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc_func2_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} slchost_func2_1_reg_t; + +/** Type of func2_2 register + * *******Description*********** + */ +typedef union { + struct { + /** slc_func1_mdstat : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ + uint32_t slc_func1_mdstat:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} slchost_func2_2_reg_t; + +/** Type of gpio_status0 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int0:32; + }; + uint32_t val; +} slchost_gpio_status0_reg_t; + +/** Type of gpio_status1 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int1:32; + }; + uint32_t val; +} slchost_gpio_status1_reg_t; + +/** Type of gpio_in0 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_in0:32; + }; + uint32_t val; +} slchost_gpio_in0_reg_t; + +/** Type of gpio_in1 register + * *******Description*********** + */ +typedef union { + struct { + /** gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_in1:32; + }; + uint32_t val; +} slchost_gpio_in1_reg_t; + +/** Type of slc0host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0:12; + /** slc0_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid:1; + uint32_t reserved_13:3; + /** hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_token1:12; + /** slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_eof:4; + }; + uint32_t val; +} slchost_slc0host_token_rdata_reg_t; + +/** Type of slc0_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_pf_data:32; + }; + uint32_t val; +} slchost_slc0_host_pf_reg_t; + +/** Type of slc1_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_pf_data:32; + }; + uint32_t val; +} slchost_slc1_host_pf_reg_t; + +/** Type of slc0host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_raw:1; + /** slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_raw:1; + /** slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_raw:1; + /** slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_raw:1; + /** slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_raw:1; + /** slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_raw:1; + /** slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_raw:1; + /** slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_raw:1; + /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_raw:1; + /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_raw:1; + /** slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_raw:1; + /** slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_raw:1; + /** slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_raw:1; + /** slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_raw:1; + /** slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_raw:1; + /** slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_raw:1; + /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_raw:1; + /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_raw:1; + /** slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_raw:1; + /** slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_raw:1; + /** slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_raw:1; + /** slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_raw:1; + /** slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_raw:1; + /** slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_raw:1; + /** slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_raw:1; + /** gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_raw_reg_t; + +/** Type of slc1host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_raw:1; + /** slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_raw:1; + /** slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_raw:1; + /** slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_raw:1; + /** slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_raw:1; + /** slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_raw:1; + /** slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_raw:1; + /** slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_raw:1; + /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_raw:1; + /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_raw:1; + /** slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_raw:1; + /** slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_raw:1; + /** slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_raw:1; + /** slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_raw:1; + /** slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_raw:1; + /** slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_raw:1; + /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_raw:1; + /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_raw:1; + /** slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_raw:1; + /** slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_raw:1; + /** slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_raw:1; + /** slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_raw:1; + /** slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_raw:1; + /** slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_raw:1; + /** slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_raw:1; + /** slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_raw_reg_t; + +/** Type of slc0host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_st:1; + /** slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_st:1; + /** slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_st:1; + /** slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_st:1; + /** slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_st:1; + /** slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_st:1; + /** slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_st:1; + /** slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_st:1; + /** slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_st:1; + /** slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_st:1; + /** slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_st:1; + /** slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_st:1; + /** slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_st:1; + /** slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_st:1; + /** slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_st:1; + /** slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_st:1; + /** slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_st:1; + /** slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_st:1; + /** slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_st:1; + /** slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_st:1; + /** slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_st:1; + /** slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_st:1; + /** slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_st:1; + /** slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_st:1; + /** slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_st:1; + /** gpio_sdio_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_st_reg_t; + +/** Type of slc1host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_st:1; + /** slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_st:1; + /** slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_st:1; + /** slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_st:1; + /** slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_st:1; + /** slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_st:1; + /** slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_st:1; + /** slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_st:1; + /** slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_st:1; + /** slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_st:1; + /** slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_st:1; + /** slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_st:1; + /** slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_st:1; + /** slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_st:1; + /** slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_st:1; + /** slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_st:1; + /** slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_st:1; + /** slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_st:1; + /** slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_st:1; + /** slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_st:1; + /** slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_st:1; + /** slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_st:1; + /** slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_st:1; + /** slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_st:1; + /** slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_st:1; + /** slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_st_reg_t; + +/** Type of pkt_len register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len:20; + /** hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len_check:12; + }; + uint32_t val; +} slchost_pkt_len_reg_t; + +/** Type of state_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_state0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state0:8; + /** slchost_state1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state1:8; + /** slchost_state2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state2:8; + /** slchost_state3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state3:8; + }; + uint32_t val; +} slchost_state_w0_reg_t; + +/** Type of state_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_state4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state4:8; + /** slchost_state5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state5:8; + /** slchost_state6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state6:8; + /** slchost_state7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_state7:8; + }; + uint32_t val; +} slchost_state_w1_reg_t; + +/** Type of conf_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf0:8; + /** slchost_conf1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf1:8; + /** slchost_conf2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf2:8; + /** slchost_conf3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf3:8; + }; + uint32_t val; +} slchost_conf_w0_reg_t; + +/** Type of conf_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf4:8; + /** slchost_conf5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf5:8; + /** slchost_conf6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf6:8; + /** slchost_conf7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf7:8; + }; + uint32_t val; +} slchost_conf_w1_reg_t; + +/** Type of conf_w2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf8:8; + /** slchost_conf9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf9:8; + /** slchost_conf10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf10:8; + /** slchost_conf11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf11:8; + }; + uint32_t val; +} slchost_conf_w2_reg_t; + +/** Type of conf_w3 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ + uint32_t slchost_conf12:8; + /** slchost_conf13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf13:8; + /** slchost_conf14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf14:8; + /** slchost_conf15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf15:8; + }; + uint32_t val; +} slchost_conf_w3_reg_t; + +/** Type of conf_w4 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ + uint32_t slchost_conf16:8; + /** slchost_conf17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ + uint32_t slchost_conf17:8; + /** slchost_conf18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf18:8; + /** slchost_conf19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf19:8; + }; + uint32_t val; +} slchost_conf_w4_reg_t; + +/** Type of conf_w5 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf20:8; + /** slchost_conf21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf21:8; + /** slchost_conf22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf22:8; + /** slchost_conf23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf23:8; + }; + uint32_t val; +} slchost_conf_w5_reg_t; + +/** Type of win_cmd register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_win_cmd : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_win_cmd:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} slchost_win_cmd_reg_t; + +/** Type of conf_w6 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf24:8; + /** slchost_conf25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf25:8; + /** slchost_conf26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf26:8; + /** slchost_conf27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf27:8; + }; + uint32_t val; +} slchost_conf_w6_reg_t; + +/** Type of conf_w7 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf28:8; + /** slchost_conf29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf29:8; + /** slchost_conf30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf30:8; + /** slchost_conf31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf31:8; + }; + uint32_t val; +} slchost_conf_w7_reg_t; + +/** Type of pkt_len0 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len0:20; + /** hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len0_check:12; + }; + uint32_t val; +} slchost_pkt_len0_reg_t; + +/** Type of pkt_len1 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len1:20; + /** hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len1_check:12; + }; + uint32_t val; +} slchost_pkt_len1_reg_t; + +/** Type of pkt_len2 register + * *******Description*********** + */ +typedef union { + struct { + /** hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len2:20; + /** hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc0_len2_check:12; + }; + uint32_t val; +} slchost_pkt_len2_reg_t; + +/** Type of conf_w8 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf32:8; + /** slchost_conf33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf33:8; + /** slchost_conf34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf34:8; + /** slchost_conf35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf35:8; + }; + uint32_t val; +} slchost_conf_w8_reg_t; + +/** Type of conf_w9 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf36:8; + /** slchost_conf37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf37:8; + /** slchost_conf38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf38:8; + /** slchost_conf39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf39:8; + }; + uint32_t val; +} slchost_conf_w9_reg_t; + +/** Type of conf_w10 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf40:8; + /** slchost_conf41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf41:8; + /** slchost_conf42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf42:8; + /** slchost_conf43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf43:8; + }; + uint32_t val; +} slchost_conf_w10_reg_t; + +/** Type of conf_w11 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf44:8; + /** slchost_conf45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf45:8; + /** slchost_conf46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf46:8; + /** slchost_conf47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf47:8; + }; + uint32_t val; +} slchost_conf_w11_reg_t; + +/** Type of conf_w12 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf48:8; + /** slchost_conf49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf49:8; + /** slchost_conf50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf50:8; + /** slchost_conf51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf51:8; + }; + uint32_t val; +} slchost_conf_w12_reg_t; + +/** Type of conf_w13 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf52:8; + /** slchost_conf53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf53:8; + /** slchost_conf54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf54:8; + /** slchost_conf55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf55:8; + }; + uint32_t val; +} slchost_conf_w13_reg_t; + +/** Type of conf_w14 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf56:8; + /** slchost_conf57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf57:8; + /** slchost_conf58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf58:8; + /** slchost_conf59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf59:8; + }; + uint32_t val; +} slchost_conf_w14_reg_t; + +/** Type of conf_w15 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_conf60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf60:8; + /** slchost_conf61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf61:8; + /** slchost_conf62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf62:8; + /** slchost_conf63 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_conf63:8; + }; + uint32_t val; +} slchost_conf_w15_reg_t; + +/** Type of check_sum0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_check_sum0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_check_sum0:32; + }; + uint32_t val; +} slchost_check_sum0_reg_t; + +/** Type of check_sum1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_check_sum1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ + uint32_t slchost_check_sum1:32; + }; + uint32_t val; +} slchost_check_sum1_reg_t; + +/** Type of slc1host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0:12; + /** slc1_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid:1; + uint32_t reserved_13:3; + /** hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t hostslchost_slc1_token1:12; + /** slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_eof:4; + }; + uint32_t val; +} slchost_slc1host_token_rdata_reg_t; + +/** Type of slc0host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_wd:12; + uint32_t reserved_12:4; + /** slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} slchost_slc0host_token_wdata_reg_t; + +/** Type of slc1host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_wd:12; + uint32_t reserved_12:4; + /** slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} slchost_slc1host_token_wdata_reg_t; + +/** Type of token_con register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_token0_dec : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_dec:1; + /** slc0host_token1_dec : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_dec:1; + /** slc0host_token0_wr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token0_wr:1; + /** slc0host_token1_wr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_token1_wr:1; + /** slc1host_token0_dec : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_dec:1; + /** slc1host_token1_dec : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_dec:1; + /** slc1host_token0_wr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token0_wr:1; + /** slc1host_token1_wr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_token1_wr:1; + /** slc0host_len_wr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_len_wr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} slchost_token_con_reg_t; + +/** Type of slc0host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_clr:1; + /** slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_clr:1; + /** slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_clr:1; + /** slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_clr:1; + /** slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_clr:1; + /** slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_clr:1; + /** slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_clr:1; + /** slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_clr:1; + /** slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_clr:1; + /** slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_clr:1; + /** slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_clr:1; + /** slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_clr:1; + /** slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_clr:1; + /** slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_clr:1; + /** slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_clr:1; + /** slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_clr:1; + /** slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_clr:1; + /** slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_clr:1; + /** slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_clr:1; + /** slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_clr:1; + /** slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_clr:1; + /** slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_clr:1; + /** slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_clr:1; + /** slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_clr:1; + /** slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_clr:1; + /** gpio_sdio_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_clr_reg_t; + +/** Type of slc1host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_clr:1; + /** slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_clr:1; + /** slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_clr:1; + /** slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_clr:1; + /** slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_clr:1; + /** slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_clr:1; + /** slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_clr:1; + /** slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_clr:1; + /** slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_clr:1; + /** slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_clr:1; + /** slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_clr:1; + /** slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_clr:1; + /** slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_clr:1; + /** slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_clr:1; + /** slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_clr:1; + /** slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_clr:1; + /** slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_clr:1; + /** slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_clr:1; + /** slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_clr:1; + /** slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_clr:1; + /** slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_clr:1; + /** slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_clr:1; + /** slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_clr:1; + /** slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_clr:1; + /** slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_clr:1; + /** slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_clr_reg_t; + +/** Type of slc0host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit0_int_ena:1; + /** fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit1_int_ena:1; + /** fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit2_int_ena:1; + /** fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit3_int_ena:1; + /** fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit4_int_ena:1; + /** fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit5_int_ena:1; + /** fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit6_int_ena:1; + /** fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tohost_bit7_int_ena:1; + /** fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token0_1to0_int_ena:1; + /** fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token1_1to0_int_ena:1; + /** fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token0_0to1_int_ena:1; + /** fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_token1_0to1_int_ena:1; + /** fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_sof_int_ena:1; + /** fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_eof_int_ena:1; + /** fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_rx_start_int_ena:1; + /** fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0host_tx_start_int_ena:1; + /** fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_udf_int_ena:1; + /** fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_tx_ovf_int_ena:1; + /** fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_pf_valid_int_ena:1; + /** fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit0_int_ena:1; + /** fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit1_int_ena:1; + /** fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit2_int_ena:1; + /** fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_ext_bit3_int_ena:1; + /** fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_rx_new_packet_int_ena:1; + /** fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc0_host_rd_retry_int_ena:1; + /** fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn1_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_func1_int_ena_reg_t; + +/** Type of slc1host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit0_int_ena:1; + /** fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit1_int_ena:1; + /** fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit2_int_ena:1; + /** fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit3_int_ena:1; + /** fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit4_int_ena:1; + /** fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit5_int_ena:1; + /** fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit6_int_ena:1; + /** fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tohost_bit7_int_ena:1; + /** fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token0_1to0_int_ena:1; + /** fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token1_1to0_int_ena:1; + /** fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token0_0to1_int_ena:1; + /** fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_token1_0to1_int_ena:1; + /** fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_sof_int_ena:1; + /** fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_eof_int_ena:1; + /** fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_rx_start_int_ena:1; + /** fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1host_tx_start_int_ena:1; + /** fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_rx_udf_int_ena:1; + /** fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_tx_ovf_int_ena:1; + /** fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_rx_pf_valid_int_ena:1; + /** fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit0_int_ena:1; + /** fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit1_int_ena:1; + /** fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit2_int_ena:1; + /** fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_ext_bit3_int_ena:1; + /** fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_wifi_rx_new_packet_int_ena:1; + /** fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_host_rd_retry_int_ena:1; + /** fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn1_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_func1_int_ena_reg_t; + +/** Type of slc0host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit0_int_ena:1; + /** fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit1_int_ena:1; + /** fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit2_int_ena:1; + /** fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit3_int_ena:1; + /** fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit4_int_ena:1; + /** fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit5_int_ena:1; + /** fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit6_int_ena:1; + /** fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tohost_bit7_int_ena:1; + /** fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token0_1to0_int_ena:1; + /** fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token1_1to0_int_ena:1; + /** fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token0_0to1_int_ena:1; + /** fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_token1_0to1_int_ena:1; + /** fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_sof_int_ena:1; + /** fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_eof_int_ena:1; + /** fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_rx_start_int_ena:1; + /** fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0host_tx_start_int_ena:1; + /** fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_udf_int_ena:1; + /** fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_tx_ovf_int_ena:1; + /** fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_pf_valid_int_ena:1; + /** fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit0_int_ena:1; + /** fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit1_int_ena:1; + /** fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit2_int_ena:1; + /** fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_ext_bit3_int_ena:1; + /** fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_rx_new_packet_int_ena:1; + /** fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc0_host_rd_retry_int_ena:1; + /** fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn2_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_func2_int_ena_reg_t; + +/** Type of slc1host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit0_int_ena:1; + /** fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit1_int_ena:1; + /** fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit2_int_ena:1; + /** fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit3_int_ena:1; + /** fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit4_int_ena:1; + /** fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit5_int_ena:1; + /** fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit6_int_ena:1; + /** fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tohost_bit7_int_ena:1; + /** fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token0_1to0_int_ena:1; + /** fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token1_1to0_int_ena:1; + /** fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token0_0to1_int_ena:1; + /** fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_token1_0to1_int_ena:1; + /** fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_sof_int_ena:1; + /** fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_eof_int_ena:1; + /** fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_rx_start_int_ena:1; + /** fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1host_tx_start_int_ena:1; + /** fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_rx_udf_int_ena:1; + /** fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_tx_ovf_int_ena:1; + /** fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_rx_pf_valid_int_ena:1; + /** fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit0_int_ena:1; + /** fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit1_int_ena:1; + /** fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit2_int_ena:1; + /** fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_ext_bit3_int_ena:1; + /** fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_wifi_rx_new_packet_int_ena:1; + /** fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_host_rd_retry_int_ena:1; + /** fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t fn2_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_func2_int_ena_reg_t; + +/** Type of slc0host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_ena:1; + /** slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_ena:1; + /** slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_ena:1; + /** slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_ena:1; + /** slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_ena:1; + /** slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_ena:1; + /** slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_ena:1; + /** slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_ena:1; + /** slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_ena:1; + /** slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_ena:1; + /** slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_ena:1; + /** slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_ena:1; + /** slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_ena:1; + /** slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_ena:1; + /** slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_ena:1; + /** slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_ena:1; + /** slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_ena:1; + /** slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_ena:1; + /** slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_ena:1; + /** slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_ena:1; + /** slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_ena:1; + /** slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_ena:1; + /** slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_ena:1; + /** slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_ena:1; + /** slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_ena:1; + /** gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_ena_reg_t; + +/** Type of slc1host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_ena:1; + /** slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_ena:1; + /** slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_ena:1; + /** slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_ena:1; + /** slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_ena:1; + /** slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_ena:1; + /** slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_ena:1; + /** slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_ena:1; + /** slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_ena:1; + /** slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_ena:1; + /** slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_ena:1; + /** slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_ena:1; + /** slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_ena:1; + /** slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_ena:1; + /** slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_ena:1; + /** slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_ena:1; + /** slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_ena:1; + /** slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_ena:1; + /** slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_ena:1; + /** slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_ena:1; + /** slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_ena:1; + /** slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_ena:1; + /** slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_ena:1; + /** slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_ena:1; + /** slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_ena:1; + /** slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_ena_reg_t; + +/** Type of slc0host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} slchost_slc0host_rx_infor_reg_t; + +/** Type of slc1host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} slchost_slc1host_rx_infor_reg_t; + +/** Type of slc0host_len_wd register + * *******Description*********** + */ +typedef union { + struct { + /** slc0host_len_wd : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_len_wd:32; + }; + uint32_t val; +} slchost_slc0host_len_wd_reg_t; + +/** Type of slc_apbwin_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_wdata:32; + }; + uint32_t val; +} slchost_slc_apbwin_wdata_reg_t; + +/** Type of slc_apbwin_conf register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_addr:28; + /** slc_apbwin_wr : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_wr:1; + /** slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_start:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} slchost_slc_apbwin_conf_reg_t; + +/** Type of slc_apbwin_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slc_apbwin_rdata:32; + }; + uint32_t val; +} slchost_slc_apbwin_rdata_reg_t; + +/** Type of rdclr0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ + uint32_t slchost_slc0_bit7_clraddr:9; + /** slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc0_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} slchost_rdclr0_reg_t; + +/** Type of rdclr1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc1_bit7_clraddr:9; + /** slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slc1_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} slchost_rdclr1_reg_t; + +/** Type of slc0host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit0_int_ena1:1; + /** slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit1_int_ena1:1; + /** slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit2_int_ena1:1; + /** slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit3_int_ena1:1; + /** slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit4_int_ena1:1; + /** slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit5_int_ena1:1; + /** slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit6_int_ena1:1; + /** slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tohost_bit7_int_ena1:1; + /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_1to0_int_ena1:1; + /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_1to0_int_ena1:1; + /** slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token0_0to1_int_ena1:1; + /** slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc0_token1_0to1_int_ena1:1; + /** slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_sof_int_ena1:1; + /** slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_eof_int_ena1:1; + /** slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_rx_start_int_ena1:1; + /** slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc0host_tx_start_int_ena1:1; + /** slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_udf_int_ena1:1; + /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc0_tx_ovf_int_ena1:1; + /** slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_pf_valid_int_ena1:1; + /** slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit0_int_ena1:1; + /** slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit1_int_ena1:1; + /** slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit2_int_ena1:1; + /** slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc0_ext_bit3_int_ena1:1; + /** slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc0_rx_new_packet_int_ena1:1; + /** slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc0_host_rd_retry_int_ena1:1; + /** gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t gpio_sdio_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc0host_int_ena1_reg_t; + +/** Type of slc1host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit0_int_ena1:1; + /** slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit1_int_ena1:1; + /** slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit2_int_ena1:1; + /** slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit3_int_ena1:1; + /** slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit4_int_ena1:1; + /** slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit5_int_ena1:1; + /** slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit6_int_ena1:1; + /** slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tohost_bit7_int_ena1:1; + /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_1to0_int_ena1:1; + /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_1to0_int_ena1:1; + /** slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token0_0to1_int_ena1:1; + /** slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slc1_token1_0to1_int_ena1:1; + /** slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_sof_int_ena1:1; + /** slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_eof_int_ena1:1; + /** slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_rx_start_int_ena1:1; + /** slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slc1host_tx_start_int_ena1:1; + /** slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_udf_int_ena1:1; + /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slc1_tx_ovf_int_ena1:1; + /** slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slc1_rx_pf_valid_int_ena1:1; + /** slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit0_int_ena1:1; + /** slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit1_int_ena1:1; + /** slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit2_int_ena1:1; + /** slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slc1_ext_bit3_int_ena1:1; + /** slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slc1_wifi_rx_new_packet_int_ena1:1; + /** slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slc1_host_rd_retry_int_ena1:1; + /** slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slc1_bt_rx_new_packet_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} slchost_slc1host_int_ena1_reg_t; + +/** Type of slchostdate register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_date : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ + uint32_t slchost_date:32; + }; + uint32_t val; +} slchost_slchostdate_reg_t; + +/** Type of slchostid register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_id : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ + uint32_t slchost_id:32; + }; + uint32_t val; +} slchost_slchostid_reg_t; + +/** Type of conf register + * *******Description*********** + */ +typedef union { + struct { + /** frc_sdio11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t frc_sdio11:5; + /** frc_sdio20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t frc_sdio20:5; + /** frc_neg_samp : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t frc_neg_samp:5; + /** frc_pos_samp : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ + uint32_t frc_pos_samp:5; + /** frc_quick_in : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ + uint32_t frc_quick_in:5; + /** sdio20_int_delay : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t sdio20_int_delay:1; + /** sdio_pad_pullup : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ + uint32_t sdio_pad_pullup:1; + /** hspeed_con_en : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ + uint32_t hspeed_con_en:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} slchost_conf_reg_t; + +/** Type of inf_st register + * *******Description*********** + */ +typedef union { + struct { + /** sdio20_mode : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t sdio20_mode:5; + /** sdio_neg_samp : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t sdio_neg_samp:5; + /** sdio_quick_in : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t sdio_quick_in:5; + /** dll_on_sw : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ + uint32_t dll_on_sw:1; + /** dll_on : R/W; bitpos: [16]; default: 0; + * Software dll on + */ + uint32_t dll_on:1; + /** clk_mode_sw : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ + uint32_t clk_mode_sw:1; + /** clk_mode : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ + uint32_t clk_mode:2; + uint32_t reserved_20:12; + }; + uint32_t val; +} slchost_inf_st_reg_t; + + +typedef struct { + uint32_t reserved_000[4]; + volatile slchost_func2_0_reg_t func2_0; + volatile slchost_func2_1_reg_t func2_1; + uint32_t reserved_018[2]; + volatile slchost_func2_2_reg_t func2_2; + uint32_t reserved_024[4]; + volatile slchost_gpio_status0_reg_t gpio_status0; + volatile slchost_gpio_status1_reg_t gpio_status1; + volatile slchost_gpio_in0_reg_t gpio_in0; + volatile slchost_gpio_in1_reg_t gpio_in1; + volatile slchost_slc0host_token_rdata_reg_t slc0host_token_rdata; + volatile slchost_slc0_host_pf_reg_t slc0_host_pf; + volatile slchost_slc1_host_pf_reg_t slc1_host_pf; + volatile slchost_slc0host_int_raw_reg_t slc0host_int_raw; + volatile slchost_slc1host_int_raw_reg_t slc1host_int_raw; + volatile slchost_slc0host_int_st_reg_t slc0host_int_st; + volatile slchost_slc1host_int_st_reg_t slc1host_int_st; + volatile slchost_pkt_len_reg_t pkt_len; + volatile slchost_state_w0_reg_t state_w0; + volatile slchost_state_w1_reg_t state_w1; + volatile slchost_conf_w0_reg_t conf_w0; + volatile slchost_conf_w1_reg_t conf_w1; + volatile slchost_conf_w2_reg_t conf_w2; + volatile slchost_conf_w3_reg_t conf_w3; + volatile slchost_conf_w4_reg_t conf_w4; + volatile slchost_conf_w5_reg_t conf_w5; + volatile slchost_win_cmd_reg_t win_cmd; + volatile slchost_conf_w6_reg_t conf_w6; + volatile slchost_conf_w7_reg_t conf_w7; + volatile slchost_pkt_len0_reg_t pkt_len0; + volatile slchost_pkt_len1_reg_t pkt_len1; + volatile slchost_pkt_len2_reg_t pkt_len2; + volatile slchost_conf_w8_reg_t conf_w8; + volatile slchost_conf_w9_reg_t conf_w9; + volatile slchost_conf_w10_reg_t conf_w10; + volatile slchost_conf_w11_reg_t conf_w11; + volatile slchost_conf_w12_reg_t conf_w12; + volatile slchost_conf_w13_reg_t conf_w13; + volatile slchost_conf_w14_reg_t conf_w14; + volatile slchost_conf_w15_reg_t conf_w15; + volatile slchost_check_sum0_reg_t check_sum0; + volatile slchost_check_sum1_reg_t check_sum1; + volatile slchost_slc1host_token_rdata_reg_t slc1host_token_rdata; + volatile slchost_slc0host_token_wdata_reg_t slc0host_token_wdata; + volatile slchost_slc1host_token_wdata_reg_t slc1host_token_wdata; + volatile slchost_token_con_reg_t token_con; + volatile slchost_slc0host_int_clr_reg_t slc0host_int_clr; + volatile slchost_slc1host_int_clr_reg_t slc1host_int_clr; + volatile slchost_slc0host_func1_int_ena_reg_t slc0host_func1_int_ena; + volatile slchost_slc1host_func1_int_ena_reg_t slc1host_func1_int_ena; + volatile slchost_slc0host_func2_int_ena_reg_t slc0host_func2_int_ena; + volatile slchost_slc1host_func2_int_ena_reg_t slc1host_func2_int_ena; + volatile slchost_slc0host_int_ena_reg_t slc0host_int_ena; + volatile slchost_slc1host_int_ena_reg_t slc1host_int_ena; + volatile slchost_slc0host_rx_infor_reg_t slc0host_rx_infor; + volatile slchost_slc1host_rx_infor_reg_t slc1host_rx_infor; + volatile slchost_slc0host_len_wd_reg_t slc0host_len_wd; + volatile slchost_slc_apbwin_wdata_reg_t slc_apbwin_wdata; + volatile slchost_slc_apbwin_conf_reg_t slc_apbwin_conf; + volatile slchost_slc_apbwin_rdata_reg_t slc_apbwin_rdata; + volatile slchost_rdclr0_reg_t rdclr0; + volatile slchost_rdclr1_reg_t rdclr1; + volatile slchost_slc0host_int_ena1_reg_t slc0host_int_ena1; + volatile slchost_slc1host_int_ena1_reg_t slc1host_int_ena1; + uint32_t reserved_11c[23]; + volatile slchost_slchostdate_reg_t slchostdate; + volatile slchost_slchostid_reg_t slchostid; + uint32_t reserved_180[28]; + volatile slchost_conf_reg_t conf; + volatile slchost_inf_st_reg_t inf_st; +} slchost_dev_t; + +extern slchost_dev_t HOST; + +#ifndef __cplusplus +_Static_assert(sizeof(slchost_dev_t) == 0x1f8, "Invalid size of slchost_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hp_system_reg.h b/components/soc/esp32c5/include/soc/hp_system_reg.h new file mode 100644 index 0000000000..d6bcde83a6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hp_system_reg.h @@ -0,0 +1,436 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + */ +#define HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYS_BASE + 0x0) +/** HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + */ +#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S 0 +/** HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U +#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/** HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + */ +#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U +#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/** HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + */ +#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U +#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/** HP_SYS_SRAM_USAGE_CONF_REG register + * HP memory usage configuration register + */ +#define HP_SYS_SRAM_USAGE_CONF_REG (DR_REG_HP_SYS_BASE + 0x4) +/** HP_SYS_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0; + * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + */ +#define HP_SYS_SRAM_USAGE 0x0000000FU +#define HP_SYS_SRAM_USAGE_M (HP_SYS_SRAM_USAGE_V << HP_SYS_SRAM_USAGE_S) +#define HP_SYS_SRAM_USAGE_V 0x0000000FU +#define HP_SYS_SRAM_USAGE_S 8 +/** HP_SYS_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0; + * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + */ +#define HP_SYS_MAC_DUMP_ALLOC (BIT(16)) +#define HP_SYS_MAC_DUMP_ALLOC_M (HP_SYS_MAC_DUMP_ALLOC_V << HP_SYS_MAC_DUMP_ALLOC_S) +#define HP_SYS_MAC_DUMP_ALLOC_V 0x00000001U +#define HP_SYS_MAC_DUMP_ALLOC_S 16 + +/** HP_SYS_SEC_DPA_CONF_REG register + * HP anti-DPA security configuration register + */ +#define HP_SYS_SEC_DPA_CONF_REG (DR_REG_HP_SYS_BASE + 0x8) +/** HP_SYS_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0; + * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger + * the number, the stronger the ability to resist DPA attacks and the higher the + * security level, but it will increase the computational overhead of the hardware + * crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + */ +#define HP_SYS_SEC_DPA_LEVEL 0x00000003U +#define HP_SYS_SEC_DPA_LEVEL_M (HP_SYS_SEC_DPA_LEVEL_V << HP_SYS_SEC_DPA_LEVEL_S) +#define HP_SYS_SEC_DPA_LEVEL_V 0x00000003U +#define HP_SYS_SEC_DPA_LEVEL_S 0 +/** HP_SYS_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0; + * This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL + * (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + */ +#define HP_SYS_SEC_DPA_CFG_SEL (BIT(2)) +#define HP_SYS_SEC_DPA_CFG_SEL_M (HP_SYS_SEC_DPA_CFG_SEL_V << HP_SYS_SEC_DPA_CFG_SEL_S) +#define HP_SYS_SEC_DPA_CFG_SEL_V 0x00000001U +#define HP_SYS_SEC_DPA_CFG_SEL_S 2 + +/** HP_SYS_CPU_PERI_TIMEOUT_CONF_REG register + * CPU_PERI_TIMEOUT configuration register + */ +#define HP_SYS_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0xc) +/** HP_SYS_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYS_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYS_CPU_PERI_TIMEOUT_THRES_M (HP_SYS_CPU_PERI_TIMEOUT_THRES_V << HP_SYS_CPU_PERI_TIMEOUT_THRES_S) +#define HP_SYS_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYS_CPU_PERI_TIMEOUT_THRES_S 0 +/** HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing cpu peripheral + * registers + */ +#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG register + * CPU_PERI_TIMEOUT_ADDR register + */ +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x10) +/** HP_SYS_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_M (HP_SYS_CPU_PERI_TIMEOUT_ADDR_V << HP_SYS_CPU_PERI_TIMEOUT_ADDR_S) +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYS_CPU_PERI_TIMEOUT_UID_REG register + * CPU_PERI_TIMEOUT_UID register + */ +#define HP_SYS_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x14) +/** HP_SYS_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYS_CPU_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYS_CPU_PERI_TIMEOUT_UID_M (HP_SYS_CPU_PERI_TIMEOUT_UID_V << HP_SYS_CPU_PERI_TIMEOUT_UID_S) +#define HP_SYS_CPU_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYS_CPU_PERI_TIMEOUT_UID_S 0 + +/** HP_SYS_HP_PERI_TIMEOUT_CONF_REG register + * HP_PERI_TIMEOUT configuration register + */ +#define HP_SYS_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x18) +/** HP_SYS_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ +#define HP_SYS_HP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define HP_SYS_HP_PERI_TIMEOUT_THRES_M (HP_SYS_HP_PERI_TIMEOUT_THRES_V << HP_SYS_HP_PERI_TIMEOUT_THRES_S) +#define HP_SYS_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define HP_SYS_HP_PERI_TIMEOUT_THRES_S 0 +/** HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ +#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16)) +#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S) +#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S 16 +/** HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + */ +#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17)) +#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S) +#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S 17 + +/** HP_SYS_HP_PERI_TIMEOUT_ADDR_REG register + * HP_PERI_TIMEOUT_ADDR register + */ +#define HP_SYS_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x1c) +/** HP_SYS_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ +#define HP_SYS_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define HP_SYS_HP_PERI_TIMEOUT_ADDR_M (HP_SYS_HP_PERI_TIMEOUT_ADDR_V << HP_SYS_HP_PERI_TIMEOUT_ADDR_S) +#define HP_SYS_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define HP_SYS_HP_PERI_TIMEOUT_ADDR_S 0 + +/** HP_SYS_HP_PERI_TIMEOUT_UID_REG register + * HP_PERI_TIMEOUT_UID register + */ +#define HP_SYS_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x20) +/** HP_SYS_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ +#define HP_SYS_HP_PERI_TIMEOUT_UID 0x0000007FU +#define HP_SYS_HP_PERI_TIMEOUT_UID_M (HP_SYS_HP_PERI_TIMEOUT_UID_V << HP_SYS_HP_PERI_TIMEOUT_UID_S) +#define HP_SYS_HP_PERI_TIMEOUT_UID_V 0x0000007FU +#define HP_SYS_HP_PERI_TIMEOUT_UID_S 0 + +/** HP_SYS_SDIO_CTRL_REG register + * SDIO Control configuration register + */ +#define HP_SYS_SDIO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x30) +/** HP_SYS_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ +#define HP_SYS_DIS_SDIO_PROB (BIT(0)) +#define HP_SYS_DIS_SDIO_PROB_M (HP_SYS_DIS_SDIO_PROB_V << HP_SYS_DIS_SDIO_PROB_S) +#define HP_SYS_DIS_SDIO_PROB_V 0x00000001U +#define HP_SYS_DIS_SDIO_PROB_S 0 +/** HP_SYS_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ +#define HP_SYS_SDIO_WIN_ACCESS_EN (BIT(1)) +#define HP_SYS_SDIO_WIN_ACCESS_EN_M (HP_SYS_SDIO_WIN_ACCESS_EN_V << HP_SYS_SDIO_WIN_ACCESS_EN_S) +#define HP_SYS_SDIO_WIN_ACCESS_EN_V 0x00000001U +#define HP_SYS_SDIO_WIN_ACCESS_EN_S 1 + +/** HP_SYS_ROM_TABLE_LOCK_REG register + * Rom-Table lock register + */ +#define HP_SYS_ROM_TABLE_LOCK_REG (DR_REG_HP_SYS_BASE + 0x38) +/** HP_SYS_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; + * XXXX + */ +#define HP_SYS_ROM_TABLE_LOCK (BIT(0)) +#define HP_SYS_ROM_TABLE_LOCK_M (HP_SYS_ROM_TABLE_LOCK_V << HP_SYS_ROM_TABLE_LOCK_S) +#define HP_SYS_ROM_TABLE_LOCK_V 0x00000001U +#define HP_SYS_ROM_TABLE_LOCK_S 0 + +/** HP_SYS_ROM_TABLE_REG register + * Rom-Table register + */ +#define HP_SYS_ROM_TABLE_REG (DR_REG_HP_SYS_BASE + 0x3c) +/** HP_SYS_ROM_TABLE : R/W; bitpos: [31:0]; default: 0; + * XXXX + */ +#define HP_SYS_ROM_TABLE 0xFFFFFFFFU +#define HP_SYS_ROM_TABLE_M (HP_SYS_ROM_TABLE_V << HP_SYS_ROM_TABLE_S) +#define HP_SYS_ROM_TABLE_V 0xFFFFFFFFU +#define HP_SYS_ROM_TABLE_S 0 + +/** HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG register + * Core Debug runstall configure register + */ +#define HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x40) +/** HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0; + * Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + */ +#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE (BIT(0)) +#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_M (HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S) +#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V 0x00000001U +#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S 0 +/** HP_SYS_CORE_RUNSTALLED : RO; bitpos: [1]; default: 0; + * Software can read this field to get the runstall status of hp-core. 1: stalled, 0: + * not stalled. + */ +#define HP_SYS_CORE_RUNSTALLED (BIT(1)) +#define HP_SYS_CORE_RUNSTALLED_M (HP_SYS_CORE_RUNSTALLED_V << HP_SYS_CORE_RUNSTALLED_S) +#define HP_SYS_CORE_RUNSTALLED_V 0x00000001U +#define HP_SYS_CORE_RUNSTALLED_S 1 + +/** HP_SYS_SPROM_CTRL_REG register + * reserved + */ +#define HP_SYS_SPROM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70) +/** HP_SYS_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112; + * reserved + */ +#define HP_SYS_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYS_SPROM_MEM_AUX_CTRL_M (HP_SYS_SPROM_MEM_AUX_CTRL_V << HP_SYS_SPROM_MEM_AUX_CTRL_S) +#define HP_SYS_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYS_SPROM_MEM_AUX_CTRL_S 0 + +/** HP_SYS_SPRAM_CTRL_REG register + * reserved + */ +#define HP_SYS_SPRAM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x74) +/** HP_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ +#define HP_SYS_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYS_SPRAM_MEM_AUX_CTRL_M (HP_SYS_SPRAM_MEM_AUX_CTRL_V << HP_SYS_SPRAM_MEM_AUX_CTRL_S) +#define HP_SYS_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYS_SPRAM_MEM_AUX_CTRL_S 0 + +/** HP_SYS_SPRF_CTRL_REG register + * reserved + */ +#define HP_SYS_SPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x78) +/** HP_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ +#define HP_SYS_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYS_SPRF_MEM_AUX_CTRL_M (HP_SYS_SPRF_MEM_AUX_CTRL_V << HP_SYS_SPRF_MEM_AUX_CTRL_S) +#define HP_SYS_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYS_SPRF_MEM_AUX_CTRL_S 0 + +/** HP_SYS_SDPRF_CTRL_REG register + * reserved + */ +#define HP_SYS_SDPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x7c) +/** HP_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define HP_SYS_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define HP_SYS_SDPRF_MEM_AUX_CTRL_M (HP_SYS_SDPRF_MEM_AUX_CTRL_V << HP_SYS_SDPRF_MEM_AUX_CTRL_S) +#define HP_SYS_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define HP_SYS_SDPRF_MEM_AUX_CTRL_S 0 + +/** HP_SYS_AUDIO_CODEX_CTRL0_REG register + * reserved + */ +#define HP_SYS_AUDIO_CODEX_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x80) +/** HP_SYS_DAC_IN_R1_IE : R/W; bitpos: [0]; default: 1; + * reserved + */ +#define HP_SYS_DAC_IN_R1_IE (BIT(0)) +#define HP_SYS_DAC_IN_R1_IE_M (HP_SYS_DAC_IN_R1_IE_V << HP_SYS_DAC_IN_R1_IE_S) +#define HP_SYS_DAC_IN_R1_IE_V 0x00000001U +#define HP_SYS_DAC_IN_R1_IE_S 0 +/** HP_SYS_DAC_IN_R1_OE : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define HP_SYS_DAC_IN_R1_OE (BIT(1)) +#define HP_SYS_DAC_IN_R1_OE_M (HP_SYS_DAC_IN_R1_OE_V << HP_SYS_DAC_IN_R1_OE_S) +#define HP_SYS_DAC_IN_R1_OE_V 0x00000001U +#define HP_SYS_DAC_IN_R1_OE_S 1 +/** HP_SYS_DAC_IN_R0_IE : R/W; bitpos: [2]; default: 1; + * reserved + */ +#define HP_SYS_DAC_IN_R0_IE (BIT(2)) +#define HP_SYS_DAC_IN_R0_IE_M (HP_SYS_DAC_IN_R0_IE_V << HP_SYS_DAC_IN_R0_IE_S) +#define HP_SYS_DAC_IN_R0_IE_V 0x00000001U +#define HP_SYS_DAC_IN_R0_IE_S 2 +/** HP_SYS_DAC_IN_R0_OE : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define HP_SYS_DAC_IN_R0_OE (BIT(3)) +#define HP_SYS_DAC_IN_R0_OE_M (HP_SYS_DAC_IN_R0_OE_V << HP_SYS_DAC_IN_R0_OE_S) +#define HP_SYS_DAC_IN_R0_OE_V 0x00000001U +#define HP_SYS_DAC_IN_R0_OE_S 3 +/** HP_SYS_ADC_DATA_4_IE : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_4_IE (BIT(4)) +#define HP_SYS_ADC_DATA_4_IE_M (HP_SYS_ADC_DATA_4_IE_V << HP_SYS_ADC_DATA_4_IE_S) +#define HP_SYS_ADC_DATA_4_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_4_IE_S 4 +/** HP_SYS_ADC_DATA_4_OE : R/W; bitpos: [5]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_4_OE (BIT(5)) +#define HP_SYS_ADC_DATA_4_OE_M (HP_SYS_ADC_DATA_4_OE_V << HP_SYS_ADC_DATA_4_OE_S) +#define HP_SYS_ADC_DATA_4_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_4_OE_S 5 +/** HP_SYS_ADC_DATA_3_IE : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_3_IE (BIT(6)) +#define HP_SYS_ADC_DATA_3_IE_M (HP_SYS_ADC_DATA_3_IE_V << HP_SYS_ADC_DATA_3_IE_S) +#define HP_SYS_ADC_DATA_3_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_3_IE_S 6 +/** HP_SYS_ADC_DATA_3_OE : R/W; bitpos: [7]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_3_OE (BIT(7)) +#define HP_SYS_ADC_DATA_3_OE_M (HP_SYS_ADC_DATA_3_OE_V << HP_SYS_ADC_DATA_3_OE_S) +#define HP_SYS_ADC_DATA_3_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_3_OE_S 7 +/** HP_SYS_ADC_DATA_2_IE : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_2_IE (BIT(8)) +#define HP_SYS_ADC_DATA_2_IE_M (HP_SYS_ADC_DATA_2_IE_V << HP_SYS_ADC_DATA_2_IE_S) +#define HP_SYS_ADC_DATA_2_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_2_IE_S 8 +/** HP_SYS_ADC_DATA_2_OE : R/W; bitpos: [9]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_2_OE (BIT(9)) +#define HP_SYS_ADC_DATA_2_OE_M (HP_SYS_ADC_DATA_2_OE_V << HP_SYS_ADC_DATA_2_OE_S) +#define HP_SYS_ADC_DATA_2_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_2_OE_S 9 +/** HP_SYS_ADC_DATA_1_IE : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_1_IE (BIT(10)) +#define HP_SYS_ADC_DATA_1_IE_M (HP_SYS_ADC_DATA_1_IE_V << HP_SYS_ADC_DATA_1_IE_S) +#define HP_SYS_ADC_DATA_1_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_1_IE_S 10 +/** HP_SYS_ADC_DATA_1_OE : R/W; bitpos: [11]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_1_OE (BIT(11)) +#define HP_SYS_ADC_DATA_1_OE_M (HP_SYS_ADC_DATA_1_OE_V << HP_SYS_ADC_DATA_1_OE_S) +#define HP_SYS_ADC_DATA_1_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_1_OE_S 11 +/** HP_SYS_ADC_DATA_0_IE : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define HP_SYS_ADC_DATA_0_IE (BIT(12)) +#define HP_SYS_ADC_DATA_0_IE_M (HP_SYS_ADC_DATA_0_IE_V << HP_SYS_ADC_DATA_0_IE_S) +#define HP_SYS_ADC_DATA_0_IE_V 0x00000001U +#define HP_SYS_ADC_DATA_0_IE_S 12 +/** HP_SYS_ADC_DATA_0_OE : R/W; bitpos: [13]; default: 1; + * reserved + */ +#define HP_SYS_ADC_DATA_0_OE (BIT(13)) +#define HP_SYS_ADC_DATA_0_OE_M (HP_SYS_ADC_DATA_0_OE_V << HP_SYS_ADC_DATA_0_OE_S) +#define HP_SYS_ADC_DATA_0_OE_V 0x00000001U +#define HP_SYS_ADC_DATA_0_OE_S 13 +/** HP_SYS_ADC_CK_DATA_IE : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define HP_SYS_ADC_CK_DATA_IE (BIT(14)) +#define HP_SYS_ADC_CK_DATA_IE_M (HP_SYS_ADC_CK_DATA_IE_V << HP_SYS_ADC_CK_DATA_IE_S) +#define HP_SYS_ADC_CK_DATA_IE_V 0x00000001U +#define HP_SYS_ADC_CK_DATA_IE_S 14 +/** HP_SYS_ADC_CK_DATA_OE : R/W; bitpos: [15]; default: 1; + * reserved + */ +#define HP_SYS_ADC_CK_DATA_OE (BIT(15)) +#define HP_SYS_ADC_CK_DATA_OE_M (HP_SYS_ADC_CK_DATA_OE_V << HP_SYS_ADC_CK_DATA_OE_S) +#define HP_SYS_ADC_CK_DATA_OE_V 0x00000001U +#define HP_SYS_ADC_CK_DATA_OE_S 15 + +/** HP_SYS_DATE_REG register + * Date register. + */ +#define HP_SYS_DATE_REG (DR_REG_HP_SYS_BASE + 0x3fc) +/** HP_SYS_DATE : R/W; bitpos: [27:0]; default: 36720768; + * HP-SYSTEM date information/ HP-SYSTEM version information. + */ +#define HP_SYS_DATE 0x0FFFFFFFU +#define HP_SYS_DATE_M (HP_SYS_DATE_V << HP_SYS_DATE_S) +#define HP_SYS_DATE_V 0x0FFFFFFFU +#define HP_SYS_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/hp_system_struct.h b/components/soc/esp32c5/include/soc/hp_system_struct.h new file mode 100644 index 0000000000..6e39e28bd0 --- /dev/null +++ b/components/soc/esp32c5/include/soc/hp_system_struct.h @@ -0,0 +1,428 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of external_device_encrypt_decrypt_control register + * EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + */ +typedef union { + struct { + /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + */ + uint32_t enable_spi_manual_encrypt:1; + /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t enable_download_db_encrypt:1; + /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + * Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + */ + uint32_t enable_download_g0cb_decrypt:1; + /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + * Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + */ + uint32_t enable_download_manual_encrypt:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_sys_external_device_encrypt_decrypt_control_reg_t; + +/** Type of sram_usage_conf register + * HP memory usage configuration register + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** sram_usage : R/W; bitpos: [11:8]; default: 0; + * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. + */ + uint32_t sram_usage:4; + uint32_t reserved_12:4; + /** mac_dump_alloc : R/W; bitpos: [16]; default: 0; + * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + */ + uint32_t mac_dump_alloc:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hp_sys_sram_usage_conf_reg_t; + +/** Type of sec_dpa_conf register + * HP anti-DPA security configuration register + */ +typedef union { + struct { + /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0; + * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger + * the number, the stronger the ability to resist DPA attacks and the higher the + * security level, but it will increase the computational overhead of the hardware + * crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + */ + uint32_t sec_dpa_level:2; + /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; + * This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL + * (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL. + */ + uint32_t sec_dpa_cfg_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} hp_sys_sec_dpa_conf_reg_t; + +/** Type of sdio_ctrl register + * SDIO Control configuration register + */ +typedef union { + struct { + /** dis_sdio_prob : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ + uint32_t dis_sdio_prob:1; + /** sdio_win_access_en : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ + uint32_t sdio_win_access_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_sys_sdio_ctrl_reg_t; + +/** Type of rom_table_lock register + * Rom-Table lock register + */ +typedef union { + struct { + /** rom_table_lock : R/W; bitpos: [0]; default: 0; + * XXXX + */ + uint32_t rom_table_lock:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_sys_rom_table_lock_reg_t; + +/** Type of rom_table register + * Rom-Table register + */ +typedef union { + struct { + /** rom_table : R/W; bitpos: [31:0]; default: 0; + * XXXX + */ + uint32_t rom_table:32; + }; + uint32_t val; +} hp_sys_rom_table_reg_t; + +/** Type of core_debug_runstall_conf register + * Core Debug runstall configure register + */ +typedef union { + struct { + /** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0; + * Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + */ + uint32_t core_debug_runstall_enable:1; + /** core_runstalled : RO; bitpos: [1]; default: 0; + * Software can read this field to get the runstall status of hp-core. 1: stalled, 0: + * not stalled. + */ + uint32_t core_runstalled:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_sys_core_debug_runstall_conf_reg_t; + +/** Type of sprom_ctrl register + * reserved + */ +typedef union { + struct { + /** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112; + * reserved + */ + uint32_t sprom_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_sys_sprom_ctrl_reg_t; + +/** Type of spram_ctrl register + * reserved + */ +typedef union { + struct { + /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ + uint32_t spram_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_sys_spram_ctrl_reg_t; + +/** Type of sprf_ctrl register + * reserved + */ +typedef union { + struct { + /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * reserved + */ + uint32_t sprf_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_sys_sprf_ctrl_reg_t; + +/** Type of sdprf_ctrl register + * reserved + */ +typedef union { + struct { + /** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdprf_mem_aux_ctrl:32; + }; + uint32_t val; +} hp_sys_sdprf_ctrl_reg_t; + +/** Type of audio_codex_ctrl0 register + * reserved + */ +typedef union { + struct { + /** dac_in_r1_ie : R/W; bitpos: [0]; default: 1; + * reserved + */ + uint32_t dac_in_r1_ie:1; + /** dac_in_r1_oe : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t dac_in_r1_oe:1; + /** dac_in_r0_ie : R/W; bitpos: [2]; default: 1; + * reserved + */ + uint32_t dac_in_r0_ie:1; + /** dac_in_r0_oe : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t dac_in_r0_oe:1; + /** adc_data_4_ie : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t adc_data_4_ie:1; + /** adc_data_4_oe : R/W; bitpos: [5]; default: 1; + * reserved + */ + uint32_t adc_data_4_oe:1; + /** adc_data_3_ie : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t adc_data_3_ie:1; + /** adc_data_3_oe : R/W; bitpos: [7]; default: 1; + * reserved + */ + uint32_t adc_data_3_oe:1; + /** adc_data_2_ie : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t adc_data_2_ie:1; + /** adc_data_2_oe : R/W; bitpos: [9]; default: 1; + * reserved + */ + uint32_t adc_data_2_oe:1; + /** adc_data_1_ie : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t adc_data_1_ie:1; + /** adc_data_1_oe : R/W; bitpos: [11]; default: 1; + * reserved + */ + uint32_t adc_data_1_oe:1; + /** adc_data_0_ie : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t adc_data_0_ie:1; + /** adc_data_0_oe : R/W; bitpos: [13]; default: 1; + * reserved + */ + uint32_t adc_data_0_oe:1; + /** adc_ck_data_ie : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t adc_ck_data_ie:1; + /** adc_ck_data_oe : R/W; bitpos: [15]; default: 1; + * reserved + */ + uint32_t adc_ck_data_oe:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} hp_sys_audio_codex_ctrl0_reg_t; + + +/** Group: Timeout Register */ +/** Type of cpu_peri_timeout_conf register + * CPU_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t cpu_peri_timeout_thres:16; + /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t cpu_peri_timeout_int_clear:1; + /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing cpu peripheral + * registers + */ + uint32_t cpu_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_conf_reg_t; + +/** Type of cpu_peri_timeout_addr register + * CPU_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t cpu_peri_timeout_addr:32; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_addr_reg_t; + +/** Type of cpu_peri_timeout_uid register + * CPU_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t cpu_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_sys_cpu_peri_timeout_uid_reg_t; + +/** Type of hp_peri_timeout_conf register + * HP_PERI_TIMEOUT configuration register + */ +typedef union { + struct { + /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + * Set the timeout threshold for bus access, corresponding to the number of clock + * cycles of the clock domain. + */ + uint32_t hp_peri_timeout_thres:16; + /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Set this bit as 1 to clear timeout interrupt + */ + uint32_t hp_peri_timeout_int_clear:1; + /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + * Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + */ + uint32_t hp_peri_timeout_protect_en:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_conf_reg_t; + +/** Type of hp_peri_timeout_addr register + * HP_PERI_TIMEOUT_ADDR register + */ +typedef union { + struct { + /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * Record the address information of abnormal access + */ + uint32_t hp_peri_timeout_addr:32; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_addr_reg_t; + +/** Type of hp_peri_timeout_uid register + * HP_PERI_TIMEOUT_UID register + */ +typedef union { + struct { + /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * Record master id[4:0] & master permission[6:5] when trigger timeout. This register + * will be cleared after the interrupt is cleared. + */ + uint32_t hp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} hp_sys_hp_peri_timeout_uid_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720768; + * HP-SYSTEM date information/ HP-SYSTEM version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_sys_date_reg_t; + + +typedef struct { + volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; + volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf; + volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf; + volatile hp_sys_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf; + volatile hp_sys_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr; + volatile hp_sys_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid; + volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf; + volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr; + volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid; + uint32_t reserved_024[3]; + volatile hp_sys_sdio_ctrl_reg_t sdio_ctrl; + uint32_t reserved_034; + volatile hp_sys_rom_table_lock_reg_t rom_table_lock; + volatile hp_sys_rom_table_reg_t rom_table; + volatile hp_sys_core_debug_runstall_conf_reg_t core_debug_runstall_conf; + uint32_t reserved_044[11]; + volatile hp_sys_sprom_ctrl_reg_t sprom_ctrl; + volatile hp_sys_spram_ctrl_reg_t spram_ctrl; + volatile hp_sys_sprf_ctrl_reg_t sprf_ctrl; + volatile hp_sys_sdprf_ctrl_reg_t sdprf_ctrl; + volatile hp_sys_audio_codex_ctrl0_reg_t audio_codex_ctrl0; + uint32_t reserved_084[222]; + volatile hp_sys_date_reg_t date; +} hp_sys_dev_t; + +extern hp_sys_dev_t HP_SYSTEM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_sys_dev_t) == 0x400, "Invalid size of hp_sys_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h new file mode 100644 index 0000000000..f8d5d41bb5 --- /dev/null +++ b/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h @@ -0,0 +1,1105 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register + * WIFI_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register + * WIFI_MAC_NMI mapping register + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register + * WIFI_PWR_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register + * WIFI_BB_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register + * BT_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register + * BT_BB_INTR mapping register + */ +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_BB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S) +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register + * BT_BB_NMI mapping register + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 + +/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register + * LP_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register + * COEX_INTR mapping register + */ +#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_COEX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S) +#define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_COEX_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register + * BLE_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register + * BLE_SEC_INTR mapping register + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S) +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register + * I2C_MST_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register + * ZB_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register + * PMU_INTR mapping register + */ +#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PMU_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S) +#define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PMU_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register + * EFUSE_INTR mapping register + */ +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_EFUSE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S) +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register + * LP_RTC_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_UART_INTR_MAP_REG register + * LP_UART_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +/** INTERRUPT_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_UART_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_UART_INTR_MAP_M (INTERRUPT_CORE0_LP_UART_INTR_MAP_V << INTERRUPT_CORE0_LP_UART_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_UART_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_UART_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG register + * LP_I2C_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +/** INTERRUPT_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_M (INTERRUPT_CORE0_LP_I2C_INTR_MAP_V << INTERRUPT_CORE0_LP_I2C_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register + * LP_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register + * LP_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register + * LP_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG register + * LP_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HUK_INTR_MAP_REG register + * HUK_INTR mapping register + */ +#define INTERRUPT_CORE0_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +/** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HUK_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HUK_INTR_MAP_M (INTERRUPT_CORE0_HUK_INTR_MAP_V << INTERRUPT_CORE0_HUK_INTR_MAP_S) +#define INTERRUPT_CORE0_HUK_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HUK_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register + * CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register + * CPU_INTR_FROM_CPU_1 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register + * CPU_INTR_FROM_CPU_2 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register + * CPU_INTR_FROM_CPU_3 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 + +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register + * ASSIST_DEBUG_INTR mapping register + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register + * TRACE_INTR mapping register + */ +#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +/** INTERRUPT_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TRACE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S) +#define INTERRUPT_CORE0_TRACE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TRACE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register + * CACHE_INTR mapping register + */ +#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CACHE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S) +#define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register + * CPU_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register + * GPIO_INTERRUPT_PRO mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register + * GPIO_INTERRUPT_PRO_NMI mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_REG register + * GPIO_INTERRUPT_SD mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_S 0 + +/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register + * PAU_INTR mapping register + */ +#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PAU_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S) +#define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PAU_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register + * HP_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register + * MODEM_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register + * HP_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register + * HP_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register + * HP_APM_M2_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register + * HP_APM_M3_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG register + * LP_APM0_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +/** INTERRUPT_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM0_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register + * MSPI_INTR mapping register + */ +#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MSPI_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S) +#define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register + * I2S1_INTR mapping register + */ +#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +/** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2S1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INTR_MAP_M (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S) +#define INTERRUPT_CORE0_I2S1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2S1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register + * UHCI0_INTR mapping register + */ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register + * UART0_INTR mapping register + */ +#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S) +#define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register + * UART1_INTR mapping register + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register + * LEDC_INTR mapping register + */ +#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LEDC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S) +#define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register + * CAN0_INTR mapping register + */ +#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CAN0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INTR_MAP_M (INTERRUPT_CORE0_CAN0_INTR_MAP_V << INTERRUPT_CORE0_CAN0_INTR_MAP_S) +#define INTERRUPT_CORE0_CAN0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_CAN1_INTR_MAP_REG register + * CAN1_INTR mapping register + */ +#define INTERRUPT_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +/** INTERRUPT_CORE0_CAN1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CAN1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN1_INTR_MAP_M (INTERRUPT_CORE0_CAN1_INTR_MAP_V << INTERRUPT_CORE0_CAN1_INTR_MAP_S) +#define INTERRUPT_CORE0_CAN1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_INTR_MAP_REG register + * USB_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +/** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register + * RMT_INTR mapping register + */ +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_RMT_INTR_MAP_M (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S) +#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register + * I2C_EXT0_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register + * TG0_T0_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG register + * TG0_T1_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +/** INTERRUPT_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_M (INTERRUPT_CORE0_TG0_T1_INTR_MAP_V << INTERRUPT_CORE0_TG0_T1_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register + * TG0_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register + * TG1_T0_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG register + * TG1_T1_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +/** INTERRUPT_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_M (INTERRUPT_CORE0_TG1_T1_INTR_MAP_V << INTERRUPT_CORE0_TG1_T1_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register + * TG1_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register + * SYSTIMER_TARGET0_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register + * SYSTIMER_TARGET1_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register + * SYSTIMER_TARGET2_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register + * APB_ADC_INTR mapping register + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S) +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PWM_INTR_MAP_REG register + * PWM_INTR mapping register + */ +#define INTERRUPT_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +/** INTERRUPT_CORE0_PWM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PWM_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PWM_INTR_MAP_M (INTERRUPT_CORE0_PWM_INTR_MAP_V << INTERRUPT_CORE0_PWM_INTR_MAP_S) +#define INTERRUPT_CORE0_PWM_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PWM_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register + * PCNT_INTR mapping register + */ +#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INTR_MAP_M (INTERRUPT_CORE0_PCNT_INTR_MAP_V << INTERRUPT_CORE0_PCNT_INTR_MAP_S) +#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register + * PARL_IO_TX_INTR mapping register + */ +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register + * PARL_IO_RX_INTR mapping register + */ +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register + * SLC0_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) +/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register + * SLC1_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG20_INTR_MAP_REG register + * USB_OTG20_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/** INTERRUPT_CORE0_USB_OTG20_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_REG register + * USB_OTG20_MULTI_PROC_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/** INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_REG register + * USB_OTG20_MISC_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) +/** INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register + * DMA_IN_CH0_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register + * DMA_IN_CH1_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register + * DMA_IN_CH2_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register + * DMA_OUT_CH0_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register + * DMA_OUT_CH1_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register + * DMA_OUT_CH2_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register + * GPSPI2_INTR mapping register + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S) +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_AES_INTR_MAP_REG register + * AES_INTR mapping register + */ +#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) +/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_AES_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_AES_INTR_MAP_M (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S) +#define INTERRUPT_CORE0_AES_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AES_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register + * SHA_INTR mapping register + */ +#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SHA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S) +#define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SHA_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_RSA_INTR_MAP_REG register + * RSA_INTR mapping register + */ +#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +/** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_RSA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_RSA_INTR_MAP_M (INTERRUPT_CORE0_RSA_INTR_MAP_V << INTERRUPT_CORE0_RSA_INTR_MAP_S) +#define INTERRUPT_CORE0_RSA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_RSA_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register + * ECC_INTR mapping register + */ +#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ECC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S) +#define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECC_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register + * ECDSA_INTR mapping register + */ +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) +/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ECDSA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S) +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_KM_INTR_MAP_REG register + * KM_INTR mapping register + */ +#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_KM_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_KM_INTR_MAP_M (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S) +#define INTERRUPT_CORE0_KM_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_KM_INTR_MAP_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register + * Status register for interrupt sources 0 ~ 31 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_0_M (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S) +#define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_0_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register + * Status register for interrupt sources 32 ~ 63 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_1_M (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S) +#define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_1_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register + * Status register for interrupt sources 64 ~ 95 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c) +/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_2_M (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S) +#define INTERRUPT_CORE0_INT_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_2_S 0 + +/** INTERRUPT_CORE0_CLOCK_GATE_REG register + * Interrupt clock gating configure register + */ +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Interrupt clock gating configure register + */ +#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_REG_CLK_EN_M (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S) +#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U +#define INTERRUPT_CORE0_REG_CLK_EN_S 0 + +/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register + * Version control register + */ +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) +/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36717104; + * Version control register + */ +#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_DATE_M (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S) +#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h new file mode 100644 index 0000000000..fd8641708d --- /dev/null +++ b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h @@ -0,0 +1,1385 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of wifi_mac_intr_map register + * WIFI_MAC_INTR mapping register + */ +typedef union { + struct { + /** wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_wifi_mac_intr_map_reg_t; + +/** Type of wifi_mac_nmi_map register + * WIFI_MAC_NMI mapping register + */ +typedef union { + struct { + /** wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_mac_nmi_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_wifi_mac_nmi_map_reg_t; + +/** Type of wifi_pwr_intr_map register + * WIFI_PWR_INTR mapping register + */ +typedef union { + struct { + /** wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_pwr_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_wifi_pwr_intr_map_reg_t; + +/** Type of wifi_bb_intr_map register + * WIFI_BB_INTR mapping register + */ +typedef union { + struct { + /** wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_bb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_wifi_bb_intr_map_reg_t; + +/** Type of bt_mac_intr_map register + * BT_MAC_INTR mapping register + */ +typedef union { + struct { + /** bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_bt_mac_intr_map_reg_t; + +/** Type of bt_bb_intr_map register + * BT_BB_INTR mapping register + */ +typedef union { + struct { + /** bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_bb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_bt_bb_intr_map_reg_t; + +/** Type of bt_bb_nmi_map register + * BT_BB_NMI mapping register + */ +typedef union { + struct { + /** bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_bb_nmi_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_bt_bb_nmi_map_reg_t; + +/** Type of lp_timer_intr_map register + * LP_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_timer_intr_map_reg_t; + +/** Type of coex_intr_map register + * COEX_INTR mapping register + */ +typedef union { + struct { + /** coex_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t coex_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_coex_intr_map_reg_t; + +/** Type of ble_timer_intr_map register + * BLE_TIMER_INTR mapping register + */ +typedef union { + struct { + /** ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ble_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ble_timer_intr_map_reg_t; + +/** Type of ble_sec_intr_map register + * BLE_SEC_INTR mapping register + */ +typedef union { + struct { + /** ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ble_sec_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ble_sec_intr_map_reg_t; + +/** Type of i2c_mst_intr_map register + * I2C_MST_INTR mapping register + */ +typedef union { + struct { + /** i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_mst_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2c_mst_intr_map_reg_t; + +/** Type of zb_mac_intr_map register + * ZB_MAC_INTR mapping register + */ +typedef union { + struct { + /** zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t zb_mac_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_zb_mac_intr_map_reg_t; + +/** Type of pmu_intr_map register + * PMU_INTR mapping register + */ +typedef union { + struct { + /** pmu_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pmu_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pmu_intr_map_reg_t; + +/** Type of efuse_intr_map register + * EFUSE_INTR mapping register + */ +typedef union { + struct { + /** efuse_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t efuse_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_efuse_intr_map_reg_t; + +/** Type of lp_rtc_timer_intr_map register + * LP_RTC_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_rtc_timer_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_rtc_timer_intr_map_reg_t; + +/** Type of lp_uart_intr_map register + * LP_UART_INTR mapping register + */ +typedef union { + struct { + /** lp_uart_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_uart_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_uart_intr_map_reg_t; + +/** Type of lp_i2c_intr_map register + * LP_I2C_INTR mapping register + */ +typedef union { + struct { + /** lp_i2c_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_i2c_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_i2c_intr_map_reg_t; + +/** Type of lp_wdt_intr_map register + * LP_WDT_INTR mapping register + */ +typedef union { + struct { + /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_wdt_intr_map_reg_t; + +/** Type of lp_peri_timeout_intr_map register + * LP_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_peri_timeout_intr_map_reg_t; + +/** Type of lp_apm_m0_intr_map register + * LP_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_apm_m0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_apm_m0_intr_map_reg_t; + +/** Type of lp_apm_m1_intr_map register + * LP_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** lp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_apm_m1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_apm_m1_intr_map_reg_t; + +/** Type of huk_intr_map register + * HUK_INTR mapping register + */ +typedef union { + struct { + /** huk_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t huk_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_huk_intr_map_reg_t; + +/** Type of cpu_intr_from_cpu_0_map register + * CPU_INTR_FROM_CPU_0 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_0_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_0_map_reg_t; + +/** Type of cpu_intr_from_cpu_1_map register + * CPU_INTR_FROM_CPU_1 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_1_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_1_map_reg_t; + +/** Type of cpu_intr_from_cpu_2_map register + * CPU_INTR_FROM_CPU_2 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_2_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_2_map_reg_t; + +/** Type of cpu_intr_from_cpu_3_map register + * CPU_INTR_FROM_CPU_3 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_3_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_3_map_reg_t; + +/** Type of assist_debug_intr_map register + * ASSIST_DEBUG_INTR mapping register + */ +typedef union { + struct { + /** assist_debug_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t assist_debug_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_assist_debug_intr_map_reg_t; + +/** Type of trace_intr_map register + * TRACE_INTR mapping register + */ +typedef union { + struct { + /** trace_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t trace_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_trace_intr_map_reg_t; + +/** Type of cache_intr_map register + * CACHE_INTR mapping register + */ +typedef union { + struct { + /** cache_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cache_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cache_intr_map_reg_t; + +/** Type of cpu_peri_timeout_intr_map register + * CPU_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_cpu_peri_timeout_intr_map_reg_t; + +/** Type of gpio_interrupt_pro_map register + * GPIO_INTERRUPT_PRO mapping register + */ +typedef union { + struct { + /** gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_pro_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_interrupt_pro_map_reg_t; + +/** Type of gpio_interrupt_pro_nmi_map register + * GPIO_INTERRUPT_PRO_NMI mapping register + */ +typedef union { + struct { + /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_pro_nmi_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_interrupt_pro_nmi_map_reg_t; + +/** Type of gpio_interrupt_sd_map register + * GPIO_INTERRUPT_SD mapping register + */ +typedef union { + struct { + /** gpio_interrupt_sd_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_sd_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpio_interrupt_sd_map_reg_t; + +/** Type of pau_intr_map register + * PAU_INTR mapping register + */ +typedef union { + struct { + /** pau_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pau_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pau_intr_map_reg_t; + +/** Type of hp_peri_timeout_intr_map register + * HP_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_peri_timeout_intr_map_reg_t; + +/** Type of modem_peri_timeout_intr_map register + * MODEM_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** modem_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t modem_peri_timeout_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_modem_peri_timeout_intr_map_reg_t; + +/** Type of hp_apm_m0_intr_map register + * HP_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_apm_m0_intr_map_reg_t; + +/** Type of hp_apm_m1_intr_map register + * HP_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_apm_m1_intr_map_reg_t; + +/** Type of hp_apm_m2_intr_map register + * HP_APM_M2_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_apm_m2_intr_map_reg_t; + +/** Type of hp_apm_m3_intr_map register + * HP_APM_M3_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m3_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_hp_apm_m3_intr_map_reg_t; + +/** Type of lp_apm0_intr_map register + * LP_APM0_INTR mapping register + */ +typedef union { + struct { + /** lp_apm0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_apm0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_lp_apm0_intr_map_reg_t; + +/** Type of mspi_intr_map register + * MSPI_INTR mapping register + */ +typedef union { + struct { + /** mspi_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t mspi_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_mspi_intr_map_reg_t; + +/** Type of i2s1_intr_map register + * I2S1_INTR mapping register + */ +typedef union { + struct { + /** i2s1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2s1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2s1_intr_map_reg_t; + +/** Type of uhci0_intr_map register + * UHCI0_INTR mapping register + */ +typedef union { + struct { + /** uhci0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uhci0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uhci0_intr_map_reg_t; + +/** Type of uart0_intr_map register + * UART0_INTR mapping register + */ +typedef union { + struct { + /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart0_intr_map_reg_t; + +/** Type of uart1_intr_map register + * UART1_INTR mapping register + */ +typedef union { + struct { + /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_uart1_intr_map_reg_t; + +/** Type of ledc_intr_map register + * LEDC_INTR mapping register + */ +typedef union { + struct { + /** ledc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ledc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ledc_intr_map_reg_t; + +/** Type of can0_intr_map register + * CAN0_INTR mapping register + */ +typedef union { + struct { + /** can0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t can0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can0_intr_map_reg_t; + +/** Type of can1_intr_map register + * CAN1_INTR mapping register + */ +typedef union { + struct { + /** can1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t can1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_can1_intr_map_reg_t; + +/** Type of usb_intr_map register + * USB_INTR mapping register + */ +typedef union { + struct { + /** usb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_intr_map_reg_t; + +/** Type of rmt_intr_map register + * RMT_INTR mapping register + */ +typedef union { + struct { + /** rmt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t rmt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_rmt_intr_map_reg_t; + +/** Type of i2c_ext0_intr_map register + * I2C_EXT0_INTR mapping register + */ +typedef union { + struct { + /** i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_ext0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_i2c_ext0_intr_map_reg_t; + +/** Type of tg0_t0_intr_map register + * TG0_T0_INTR mapping register + */ +typedef union { + struct { + /** tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_t0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg0_t0_intr_map_reg_t; + +/** Type of tg0_t1_intr_map register + * TG0_T1_INTR mapping register + */ +typedef union { + struct { + /** tg0_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_t1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg0_t1_intr_map_reg_t; + +/** Type of tg0_wdt_intr_map register + * TG0_WDT_INTR mapping register + */ +typedef union { + struct { + /** tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg0_wdt_intr_map_reg_t; + +/** Type of tg1_t0_intr_map register + * TG1_T0_INTR mapping register + */ +typedef union { + struct { + /** tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_t0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg1_t0_intr_map_reg_t; + +/** Type of tg1_t1_intr_map register + * TG1_T1_INTR mapping register + */ +typedef union { + struct { + /** tg1_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_t1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg1_t1_intr_map_reg_t; + +/** Type of tg1_wdt_intr_map register + * TG1_WDT_INTR mapping register + */ +typedef union { + struct { + /** tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_wdt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_tg1_wdt_intr_map_reg_t; + +/** Type of systimer_target0_intr_map register + * SYSTIMER_TARGET0_INTR mapping register + */ +typedef union { + struct { + /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target0_intr_map_reg_t; + +/** Type of systimer_target1_intr_map register + * SYSTIMER_TARGET1_INTR mapping register + */ +typedef union { + struct { + /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target1_intr_map_reg_t; + +/** Type of systimer_target2_intr_map register + * SYSTIMER_TARGET2_INTR mapping register + */ +typedef union { + struct { + /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_systimer_target2_intr_map_reg_t; + +/** Type of apb_adc_intr_map register + * APB_ADC_INTR mapping register + */ +typedef union { + struct { + /** apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t apb_adc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_apb_adc_intr_map_reg_t; + +/** Type of pwm_intr_map register + * PWM_INTR mapping register + */ +typedef union { + struct { + /** pwm_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pwm_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pwm_intr_map_reg_t; + +/** Type of pcnt_intr_map register + * PCNT_INTR mapping register + */ +typedef union { + struct { + /** pcnt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pcnt_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_pcnt_intr_map_reg_t; + +/** Type of parl_io_tx_intr_map register + * PARL_IO_TX_INTR mapping register + */ +typedef union { + struct { + /** parl_io_tx_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t parl_io_tx_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_parl_io_tx_intr_map_reg_t; + +/** Type of parl_io_rx_intr_map register + * PARL_IO_RX_INTR mapping register + */ +typedef union { + struct { + /** parl_io_rx_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t parl_io_rx_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_parl_io_rx_intr_map_reg_t; + +/** Type of slc0_intr_map register + * SLC0_INTR mapping register + */ +typedef union { + struct { + /** slc0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t slc0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_slc0_intr_map_reg_t; + +/** Type of slc1_intr_map register + * SLC1_INTR mapping register + */ +typedef union { + struct { + /** slc1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t slc1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_slc1_intr_map_reg_t; + +/** Type of usb_otg20_intr_map register + * USB_OTG20_INTR mapping register + */ +typedef union { + struct { + /** usb_otg20_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_otg20_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg20_intr_map_reg_t; + +/** Type of usb_otg20_multi_proc_intr_map register + * USB_OTG20_MULTI_PROC_INTR mapping register + */ +typedef union { + struct { + /** usb_otg20_multi_proc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_otg20_multi_proc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg20_multi_proc_intr_map_reg_t; + +/** Type of usb_otg20_misc_intr_map register + * USB_OTG20_MISC_INTR mapping register + */ +typedef union { + struct { + /** usb_otg20_misc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_otg20_misc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_usb_otg20_misc_intr_map_reg_t; + +/** Type of dma_in_ch0_intr_map register + * DMA_IN_CH0_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_in_ch0_intr_map_reg_t; + +/** Type of dma_in_ch1_intr_map register + * DMA_IN_CH1_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_in_ch1_intr_map_reg_t; + +/** Type of dma_in_ch2_intr_map register + * DMA_IN_CH2_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_in_ch2_intr_map_reg_t; + +/** Type of dma_out_ch0_intr_map register + * DMA_OUT_CH0_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch0_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_out_ch0_intr_map_reg_t; + +/** Type of dma_out_ch1_intr_map register + * DMA_OUT_CH1_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch1_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_out_ch1_intr_map_reg_t; + +/** Type of dma_out_ch2_intr_map register + * DMA_OUT_CH2_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_dma_out_ch2_intr_map_reg_t; + +/** Type of gpspi2_intr_map register + * GPSPI2_INTR mapping register + */ +typedef union { + struct { + /** gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpspi2_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_gpspi2_intr_map_reg_t; + +/** Type of aes_intr_map register + * AES_INTR mapping register + */ +typedef union { + struct { + /** aes_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t aes_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_aes_intr_map_reg_t; + +/** Type of sha_intr_map register + * SHA_INTR mapping register + */ +typedef union { + struct { + /** sha_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t sha_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sha_intr_map_reg_t; + +/** Type of rsa_intr_map register + * RSA_INTR mapping register + */ +typedef union { + struct { + /** rsa_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t rsa_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_rsa_intr_map_reg_t; + +/** Type of ecc_intr_map register + * ECC_INTR mapping register + */ +typedef union { + struct { + /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ecc_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ecc_intr_map_reg_t; + +/** Type of ecdsa_intr_map register + * ECDSA_INTR mapping register + */ +typedef union { + struct { + /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ecdsa_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_ecdsa_intr_map_reg_t; + +/** Type of km_intr_map register + * KM_INTR mapping register + */ +typedef union { + struct { + /** km_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t km_intr_map:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_km_intr_map_reg_t; + +/** Type of int_status_reg_0 register + * Status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** int_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_0:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_0_reg_t; + +/** Type of int_status_reg_1 register + * Status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** int_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_1:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_1_reg_t; + +/** Type of int_status_reg_2 register + * Status register for interrupt sources 64 ~ 95 + */ +typedef union { + struct { + /** int_status_2 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources numbered from .Each bit corresponds + * to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_2:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_2_reg_t; + +/** Type of clock_gate register + * Interrupt clock gating configure register + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 0; + * Interrupt clock gating configure register + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_core0_clock_gate_reg_t; + + +/** Group: Version Register */ +/** Type of interrupt_date register + * Version control register + */ +typedef union { + struct { + /** interrupt_date : R/W; bitpos: [27:0]; default: 36717104; + * Version control register + */ + uint32_t interrupt_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_core0_interrupt_date_reg_t; + + +typedef struct { + volatile interrupt_core0_wifi_mac_intr_map_reg_t wifi_mac_intr_map; + volatile interrupt_core0_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map; + volatile interrupt_core0_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map; + volatile interrupt_core0_wifi_bb_intr_map_reg_t wifi_bb_intr_map; + volatile interrupt_core0_bt_mac_intr_map_reg_t bt_mac_intr_map; + volatile interrupt_core0_bt_bb_intr_map_reg_t bt_bb_intr_map; + volatile interrupt_core0_bt_bb_nmi_map_reg_t bt_bb_nmi_map; + volatile interrupt_core0_lp_timer_intr_map_reg_t lp_timer_intr_map; + volatile interrupt_core0_coex_intr_map_reg_t coex_intr_map; + volatile interrupt_core0_ble_timer_intr_map_reg_t ble_timer_intr_map; + volatile interrupt_core0_ble_sec_intr_map_reg_t ble_sec_intr_map; + volatile interrupt_core0_i2c_mst_intr_map_reg_t i2c_mst_intr_map; + volatile interrupt_core0_zb_mac_intr_map_reg_t zb_mac_intr_map; + volatile interrupt_core0_pmu_intr_map_reg_t pmu_intr_map; + volatile interrupt_core0_efuse_intr_map_reg_t efuse_intr_map; + volatile interrupt_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; + volatile interrupt_core0_lp_uart_intr_map_reg_t lp_uart_intr_map; + volatile interrupt_core0_lp_i2c_intr_map_reg_t lp_i2c_intr_map; + volatile interrupt_core0_lp_wdt_intr_map_reg_t lp_wdt_intr_map; + volatile interrupt_core0_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map; + volatile interrupt_core0_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map; + volatile interrupt_core0_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map; + volatile interrupt_core0_huk_intr_map_reg_t huk_intr_map; + volatile interrupt_core0_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; + volatile interrupt_core0_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; + volatile interrupt_core0_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; + volatile interrupt_core0_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; + volatile interrupt_core0_assist_debug_intr_map_reg_t assist_debug_intr_map; + volatile interrupt_core0_trace_intr_map_reg_t trace_intr_map; + volatile interrupt_core0_cache_intr_map_reg_t cache_intr_map; + volatile interrupt_core0_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; + volatile interrupt_core0_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; + volatile interrupt_core0_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map; + volatile interrupt_core0_gpio_interrupt_sd_map_reg_t gpio_interrupt_sd_map; + volatile interrupt_core0_pau_intr_map_reg_t pau_intr_map; + volatile interrupt_core0_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; + volatile interrupt_core0_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map; + volatile interrupt_core0_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; + volatile interrupt_core0_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; + volatile interrupt_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; + volatile interrupt_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; + volatile interrupt_core0_lp_apm0_intr_map_reg_t lp_apm0_intr_map; + volatile interrupt_core0_mspi_intr_map_reg_t mspi_intr_map; + volatile interrupt_core0_i2s1_intr_map_reg_t i2s1_intr_map; + volatile interrupt_core0_uhci0_intr_map_reg_t uhci0_intr_map; + volatile interrupt_core0_uart0_intr_map_reg_t uart0_intr_map; + volatile interrupt_core0_uart1_intr_map_reg_t uart1_intr_map; + volatile interrupt_core0_ledc_intr_map_reg_t ledc_intr_map; + volatile interrupt_core0_can0_intr_map_reg_t can0_intr_map; + volatile interrupt_core0_can1_intr_map_reg_t can1_intr_map; + volatile interrupt_core0_usb_intr_map_reg_t usb_intr_map; + volatile interrupt_core0_rmt_intr_map_reg_t rmt_intr_map; + volatile interrupt_core0_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; + volatile interrupt_core0_tg0_t0_intr_map_reg_t tg0_t0_intr_map; + volatile interrupt_core0_tg0_t1_intr_map_reg_t tg0_t1_intr_map; + volatile interrupt_core0_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; + volatile interrupt_core0_tg1_t0_intr_map_reg_t tg1_t0_intr_map; + volatile interrupt_core0_tg1_t1_intr_map_reg_t tg1_t1_intr_map; + volatile interrupt_core0_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; + volatile interrupt_core0_systimer_target0_intr_map_reg_t systimer_target0_intr_map; + volatile interrupt_core0_systimer_target1_intr_map_reg_t systimer_target1_intr_map; + volatile interrupt_core0_systimer_target2_intr_map_reg_t systimer_target2_intr_map; + volatile interrupt_core0_apb_adc_intr_map_reg_t apb_adc_intr_map; + volatile interrupt_core0_pwm_intr_map_reg_t pwm_intr_map; + volatile interrupt_core0_pcnt_intr_map_reg_t pcnt_intr_map; + volatile interrupt_core0_parl_io_tx_intr_map_reg_t parl_io_tx_intr_map; + volatile interrupt_core0_parl_io_rx_intr_map_reg_t parl_io_rx_intr_map; + volatile interrupt_core0_slc0_intr_map_reg_t slc0_intr_map; + volatile interrupt_core0_slc1_intr_map_reg_t slc1_intr_map; + volatile interrupt_core0_usb_otg20_intr_map_reg_t usb_otg20_intr_map; + volatile interrupt_core0_usb_otg20_multi_proc_intr_map_reg_t usb_otg20_multi_proc_intr_map; + volatile interrupt_core0_usb_otg20_misc_intr_map_reg_t usb_otg20_misc_intr_map; + volatile interrupt_core0_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; + volatile interrupt_core0_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; + volatile interrupt_core0_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map; + volatile interrupt_core0_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; + volatile interrupt_core0_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; + volatile interrupt_core0_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map; + volatile interrupt_core0_gpspi2_intr_map_reg_t gpspi2_intr_map; + volatile interrupt_core0_aes_intr_map_reg_t aes_intr_map; + volatile interrupt_core0_sha_intr_map_reg_t sha_intr_map; + volatile interrupt_core0_rsa_intr_map_reg_t rsa_intr_map; + volatile interrupt_core0_ecc_intr_map_reg_t ecc_intr_map; + volatile interrupt_core0_ecdsa_intr_map_reg_t ecdsa_intr_map; + volatile interrupt_core0_km_intr_map_reg_t km_intr_map; + volatile interrupt_core0_int_status_reg_0_reg_t int_status_reg_0; + volatile interrupt_core0_int_status_reg_1_reg_t int_status_reg_1; + volatile interrupt_core0_int_status_reg_2_reg_t int_status_reg_2; + volatile interrupt_core0_clock_gate_reg_t clock_gate; + uint32_t reserved_164[422]; + volatile interrupt_core0_interrupt_date_reg_t interrupt_date; +} interrupt_core0_dev_t; + +extern intmtx_core0_dev_t INTMTX; + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_core0_dev_t) == 0x800, "Invalid size of interrupt_core0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/intpri_reg.h b/components/soc/esp32c5/include/soc/intpri_reg.h new file mode 100644 index 0000000000..67aa1c8cff --- /dev/null +++ b/components/soc/esp32c5/include/soc/intpri_reg.h @@ -0,0 +1,88 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTPRI_CPU_INTR_FROM_CPU_0_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90) +/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S) +#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_0_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_1_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94) +/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S) +#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_1_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_2_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98) +/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S) +#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_2_S 0 + +/** INTPRI_CPU_INTR_FROM_CPU_3_REG register + * register description + */ +#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c) +/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * Need add description + */ +#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S) +#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U +#define INTPRI_CPU_INTR_FROM_CPU_3_S 0 + +/** INTPRI_DATE_REG register + * register description + */ +#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0) +/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784; + * Need add description + */ +#define INTPRI_DATE 0x0FFFFFFFU +#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S) +#define INTPRI_DATE_V 0x0FFFFFFFU +#define INTPRI_DATE_S 0 + +/** INTPRI_CLOCK_GATE_REG register + * register description + */ +#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4) +/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Need add description + */ +#define INTPRI_CLK_EN (BIT(0)) +#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S) +#define INTPRI_CLK_EN_V 0x00000001U +#define INTPRI_CLK_EN_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/intpri_struct.h b/components/soc/esp32c5/include/soc/intpri_struct.h new file mode 100644 index 0000000000..be97e09506 --- /dev/null +++ b/components/soc/esp32c5/include/soc/intpri_struct.h @@ -0,0 +1,120 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of cpu_intr_from_cpu_0 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_0:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_0_reg_t; + +/** Type of cpu_intr_from_cpu_1 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_1_reg_t; + +/** Type of cpu_intr_from_cpu_2 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_2:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_2_reg_t; + +/** Type of cpu_intr_from_cpu_3 register + * register description + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0; + * Need add description + */ + uint32_t cpu_intr_from_cpu_3:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_cpu_intr_from_cpu_3_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * register description + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36712784; + * Need add description + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} intpri_date_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clock_gate register + * register description + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Need add description + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} intpri_clock_gate_reg_t; + + +typedef struct { + uint32_t reserved_000[36]; + volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0; + volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1; + volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2; + volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3; + volatile intpri_date_reg_t date; + volatile intpri_clock_gate_reg_t clock_gate; +} intpri_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(intpri_dev_t) == 0xa8, "Invalid size of intpri_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/io_mux_reg.h b/components/soc/esp32c5/include/soc/io_mux_reg.h new file mode 100644 index 0000000000..f97e3c0b44 --- /dev/null +++ b/components/soc/esp32c5/include/soc/io_mux_reg.h @@ -0,0 +1,3054 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** IO_MUX_PIN_CTRL_REG register + * Clock Output Configuration Register + */ +#define IO_MUX_PIN_CTRL_REG (DR_REG_IO_MUX_BASE + 0x0) +/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. + * CLK_OUT_out1 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT1 0x0000001FU +#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S) +#define IO_MUX_CLK_OUT1_V 0x0000001FU +#define IO_MUX_CLK_OUT1_S 0 +/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. + * CLK_OUT_out2 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT2 0x0000001FU +#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S) +#define IO_MUX_CLK_OUT2_V 0x0000001FU +#define IO_MUX_CLK_OUT2_S 5 +/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7; + * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. + * CLK_OUT_out3 can be found in peripheral output signals. + */ +#define IO_MUX_CLK_OUT3 0x0000001FU +#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S) +#define IO_MUX_CLK_OUT3_V 0x0000001FU +#define IO_MUX_CLK_OUT3_S 10 + +/** IO_MUX_GPIO0_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4) +/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO0_MCU_OE (BIT(0)) +#define IO_MUX_GPIO0_MCU_OE_M (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S) +#define IO_MUX_GPIO0_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO0_MCU_OE_S 0 +/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO0_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO0_SLP_SEL_M (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S) +#define IO_MUX_GPIO0_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO0_SLP_SEL_S 1 +/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO0_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO0_MCU_WPD_M (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S) +#define IO_MUX_GPIO0_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO0_MCU_WPD_S 2 +/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO0_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO0_MCU_WPU_M (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S) +#define IO_MUX_GPIO0_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO0_MCU_WPU_S 3 +/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO0_MCU_IE (BIT(4)) +#define IO_MUX_GPIO0_MCU_IE_M (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S) +#define IO_MUX_GPIO0_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO0_MCU_IE_S 4 +/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO0_MCU_DRV 0x00000003U +#define IO_MUX_GPIO0_MCU_DRV_M (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S) +#define IO_MUX_GPIO0_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO0_MCU_DRV_S 5 +/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO0_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO0_FUN_WPD_M (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S) +#define IO_MUX_GPIO0_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO0_FUN_WPD_S 7 +/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO0_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO0_FUN_WPU_M (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S) +#define IO_MUX_GPIO0_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO0_FUN_WPU_S 8 +/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO0_FUN_IE (BIT(9)) +#define IO_MUX_GPIO0_FUN_IE_M (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S) +#define IO_MUX_GPIO0_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO0_FUN_IE_S 9 +/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO0_FUN_DRV 0x00000003U +#define IO_MUX_GPIO0_FUN_DRV_M (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S) +#define IO_MUX_GPIO0_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO0_FUN_DRV_S 10 +/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO0_MCU_SEL 0x00000007U +#define IO_MUX_GPIO0_MCU_SEL_M (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S) +#define IO_MUX_GPIO0_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO0_MCU_SEL_S 12 +/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO0_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO0_FILTER_EN_M (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S) +#define IO_MUX_GPIO0_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO0_FILTER_EN_S 15 +/** IO_MUX_GPIO0_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO0_HYS_EN (BIT(16)) +#define IO_MUX_GPIO0_HYS_EN_M (IO_MUX_GPIO0_HYS_EN_V << IO_MUX_GPIO0_HYS_EN_S) +#define IO_MUX_GPIO0_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO0_HYS_EN_S 16 +/** IO_MUX_GPIO0_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO0_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO0_HYS_SEL_M (IO_MUX_GPIO0_HYS_SEL_V << IO_MUX_GPIO0_HYS_SEL_S) +#define IO_MUX_GPIO0_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO0_HYS_SEL_S 17 + +/** IO_MUX_GPIO1_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8) +/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO1_MCU_OE (BIT(0)) +#define IO_MUX_GPIO1_MCU_OE_M (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S) +#define IO_MUX_GPIO1_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO1_MCU_OE_S 0 +/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO1_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO1_SLP_SEL_M (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S) +#define IO_MUX_GPIO1_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO1_SLP_SEL_S 1 +/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO1_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO1_MCU_WPD_M (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S) +#define IO_MUX_GPIO1_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO1_MCU_WPD_S 2 +/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO1_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO1_MCU_WPU_M (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S) +#define IO_MUX_GPIO1_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO1_MCU_WPU_S 3 +/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO1_MCU_IE (BIT(4)) +#define IO_MUX_GPIO1_MCU_IE_M (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S) +#define IO_MUX_GPIO1_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO1_MCU_IE_S 4 +/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO1_MCU_DRV 0x00000003U +#define IO_MUX_GPIO1_MCU_DRV_M (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S) +#define IO_MUX_GPIO1_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO1_MCU_DRV_S 5 +/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO1_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO1_FUN_WPD_M (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S) +#define IO_MUX_GPIO1_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO1_FUN_WPD_S 7 +/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO1_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO1_FUN_WPU_M (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S) +#define IO_MUX_GPIO1_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO1_FUN_WPU_S 8 +/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO1_FUN_IE (BIT(9)) +#define IO_MUX_GPIO1_FUN_IE_M (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S) +#define IO_MUX_GPIO1_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO1_FUN_IE_S 9 +/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO1_FUN_DRV 0x00000003U +#define IO_MUX_GPIO1_FUN_DRV_M (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S) +#define IO_MUX_GPIO1_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO1_FUN_DRV_S 10 +/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO1_MCU_SEL 0x00000007U +#define IO_MUX_GPIO1_MCU_SEL_M (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S) +#define IO_MUX_GPIO1_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO1_MCU_SEL_S 12 +/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO1_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO1_FILTER_EN_M (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S) +#define IO_MUX_GPIO1_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO1_FILTER_EN_S 15 +/** IO_MUX_GPIO1_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO1_HYS_EN (BIT(16)) +#define IO_MUX_GPIO1_HYS_EN_M (IO_MUX_GPIO1_HYS_EN_V << IO_MUX_GPIO1_HYS_EN_S) +#define IO_MUX_GPIO1_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO1_HYS_EN_S 16 +/** IO_MUX_GPIO1_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO1_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO1_HYS_SEL_M (IO_MUX_GPIO1_HYS_SEL_V << IO_MUX_GPIO1_HYS_SEL_S) +#define IO_MUX_GPIO1_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO1_HYS_SEL_S 17 + +/** IO_MUX_GPIO2_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc) +/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO2_MCU_OE (BIT(0)) +#define IO_MUX_GPIO2_MCU_OE_M (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S) +#define IO_MUX_GPIO2_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO2_MCU_OE_S 0 +/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO2_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO2_SLP_SEL_M (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S) +#define IO_MUX_GPIO2_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO2_SLP_SEL_S 1 +/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO2_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO2_MCU_WPD_M (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S) +#define IO_MUX_GPIO2_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO2_MCU_WPD_S 2 +/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO2_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO2_MCU_WPU_M (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S) +#define IO_MUX_GPIO2_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO2_MCU_WPU_S 3 +/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO2_MCU_IE (BIT(4)) +#define IO_MUX_GPIO2_MCU_IE_M (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S) +#define IO_MUX_GPIO2_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO2_MCU_IE_S 4 +/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO2_MCU_DRV 0x00000003U +#define IO_MUX_GPIO2_MCU_DRV_M (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S) +#define IO_MUX_GPIO2_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO2_MCU_DRV_S 5 +/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO2_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO2_FUN_WPD_M (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S) +#define IO_MUX_GPIO2_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO2_FUN_WPD_S 7 +/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO2_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO2_FUN_WPU_M (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S) +#define IO_MUX_GPIO2_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO2_FUN_WPU_S 8 +/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO2_FUN_IE (BIT(9)) +#define IO_MUX_GPIO2_FUN_IE_M (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S) +#define IO_MUX_GPIO2_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO2_FUN_IE_S 9 +/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO2_FUN_DRV 0x00000003U +#define IO_MUX_GPIO2_FUN_DRV_M (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S) +#define IO_MUX_GPIO2_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO2_FUN_DRV_S 10 +/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO2_MCU_SEL 0x00000007U +#define IO_MUX_GPIO2_MCU_SEL_M (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S) +#define IO_MUX_GPIO2_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO2_MCU_SEL_S 12 +/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO2_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO2_FILTER_EN_M (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S) +#define IO_MUX_GPIO2_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO2_FILTER_EN_S 15 +/** IO_MUX_GPIO2_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO2_HYS_EN (BIT(16)) +#define IO_MUX_GPIO2_HYS_EN_M (IO_MUX_GPIO2_HYS_EN_V << IO_MUX_GPIO2_HYS_EN_S) +#define IO_MUX_GPIO2_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO2_HYS_EN_S 16 +/** IO_MUX_GPIO2_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO2_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO2_HYS_SEL_M (IO_MUX_GPIO2_HYS_SEL_V << IO_MUX_GPIO2_HYS_SEL_S) +#define IO_MUX_GPIO2_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO2_HYS_SEL_S 17 + +/** IO_MUX_GPIO3_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10) +/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO3_MCU_OE (BIT(0)) +#define IO_MUX_GPIO3_MCU_OE_M (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S) +#define IO_MUX_GPIO3_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO3_MCU_OE_S 0 +/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO3_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO3_SLP_SEL_M (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S) +#define IO_MUX_GPIO3_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO3_SLP_SEL_S 1 +/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO3_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO3_MCU_WPD_M (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S) +#define IO_MUX_GPIO3_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO3_MCU_WPD_S 2 +/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO3_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO3_MCU_WPU_M (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S) +#define IO_MUX_GPIO3_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO3_MCU_WPU_S 3 +/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO3_MCU_IE (BIT(4)) +#define IO_MUX_GPIO3_MCU_IE_M (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S) +#define IO_MUX_GPIO3_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO3_MCU_IE_S 4 +/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO3_MCU_DRV 0x00000003U +#define IO_MUX_GPIO3_MCU_DRV_M (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S) +#define IO_MUX_GPIO3_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO3_MCU_DRV_S 5 +/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO3_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO3_FUN_WPD_M (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S) +#define IO_MUX_GPIO3_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO3_FUN_WPD_S 7 +/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO3_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO3_FUN_WPU_M (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S) +#define IO_MUX_GPIO3_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO3_FUN_WPU_S 8 +/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO3_FUN_IE (BIT(9)) +#define IO_MUX_GPIO3_FUN_IE_M (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S) +#define IO_MUX_GPIO3_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO3_FUN_IE_S 9 +/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO3_FUN_DRV 0x00000003U +#define IO_MUX_GPIO3_FUN_DRV_M (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S) +#define IO_MUX_GPIO3_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO3_FUN_DRV_S 10 +/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO3_MCU_SEL 0x00000007U +#define IO_MUX_GPIO3_MCU_SEL_M (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S) +#define IO_MUX_GPIO3_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO3_MCU_SEL_S 12 +/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO3_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO3_FILTER_EN_M (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S) +#define IO_MUX_GPIO3_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO3_FILTER_EN_S 15 +/** IO_MUX_GPIO3_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO3_HYS_EN (BIT(16)) +#define IO_MUX_GPIO3_HYS_EN_M (IO_MUX_GPIO3_HYS_EN_V << IO_MUX_GPIO3_HYS_EN_S) +#define IO_MUX_GPIO3_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO3_HYS_EN_S 16 +/** IO_MUX_GPIO3_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO3_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO3_HYS_SEL_M (IO_MUX_GPIO3_HYS_SEL_V << IO_MUX_GPIO3_HYS_SEL_S) +#define IO_MUX_GPIO3_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO3_HYS_SEL_S 17 + +/** IO_MUX_GPIO4_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14) +/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO4_MCU_OE (BIT(0)) +#define IO_MUX_GPIO4_MCU_OE_M (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S) +#define IO_MUX_GPIO4_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO4_MCU_OE_S 0 +/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO4_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO4_SLP_SEL_M (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S) +#define IO_MUX_GPIO4_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO4_SLP_SEL_S 1 +/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO4_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO4_MCU_WPD_M (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S) +#define IO_MUX_GPIO4_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO4_MCU_WPD_S 2 +/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO4_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO4_MCU_WPU_M (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S) +#define IO_MUX_GPIO4_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO4_MCU_WPU_S 3 +/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO4_MCU_IE (BIT(4)) +#define IO_MUX_GPIO4_MCU_IE_M (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S) +#define IO_MUX_GPIO4_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO4_MCU_IE_S 4 +/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO4_MCU_DRV 0x00000003U +#define IO_MUX_GPIO4_MCU_DRV_M (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S) +#define IO_MUX_GPIO4_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO4_MCU_DRV_S 5 +/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO4_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO4_FUN_WPD_M (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S) +#define IO_MUX_GPIO4_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO4_FUN_WPD_S 7 +/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO4_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO4_FUN_WPU_M (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S) +#define IO_MUX_GPIO4_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO4_FUN_WPU_S 8 +/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO4_FUN_IE (BIT(9)) +#define IO_MUX_GPIO4_FUN_IE_M (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S) +#define IO_MUX_GPIO4_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO4_FUN_IE_S 9 +/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO4_FUN_DRV 0x00000003U +#define IO_MUX_GPIO4_FUN_DRV_M (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S) +#define IO_MUX_GPIO4_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO4_FUN_DRV_S 10 +/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO4_MCU_SEL 0x00000007U +#define IO_MUX_GPIO4_MCU_SEL_M (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S) +#define IO_MUX_GPIO4_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO4_MCU_SEL_S 12 +/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO4_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO4_FILTER_EN_M (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S) +#define IO_MUX_GPIO4_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO4_FILTER_EN_S 15 +/** IO_MUX_GPIO4_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO4_HYS_EN (BIT(16)) +#define IO_MUX_GPIO4_HYS_EN_M (IO_MUX_GPIO4_HYS_EN_V << IO_MUX_GPIO4_HYS_EN_S) +#define IO_MUX_GPIO4_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO4_HYS_EN_S 16 +/** IO_MUX_GPIO4_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO4_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO4_HYS_SEL_M (IO_MUX_GPIO4_HYS_SEL_V << IO_MUX_GPIO4_HYS_SEL_S) +#define IO_MUX_GPIO4_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO4_HYS_SEL_S 17 + +/** IO_MUX_GPIO5_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18) +/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO5_MCU_OE (BIT(0)) +#define IO_MUX_GPIO5_MCU_OE_M (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S) +#define IO_MUX_GPIO5_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO5_MCU_OE_S 0 +/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO5_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO5_SLP_SEL_M (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S) +#define IO_MUX_GPIO5_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO5_SLP_SEL_S 1 +/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO5_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO5_MCU_WPD_M (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S) +#define IO_MUX_GPIO5_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO5_MCU_WPD_S 2 +/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO5_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO5_MCU_WPU_M (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S) +#define IO_MUX_GPIO5_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO5_MCU_WPU_S 3 +/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO5_MCU_IE (BIT(4)) +#define IO_MUX_GPIO5_MCU_IE_M (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S) +#define IO_MUX_GPIO5_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO5_MCU_IE_S 4 +/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO5_MCU_DRV 0x00000003U +#define IO_MUX_GPIO5_MCU_DRV_M (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S) +#define IO_MUX_GPIO5_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO5_MCU_DRV_S 5 +/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO5_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO5_FUN_WPD_M (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S) +#define IO_MUX_GPIO5_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO5_FUN_WPD_S 7 +/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO5_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO5_FUN_WPU_M (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S) +#define IO_MUX_GPIO5_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO5_FUN_WPU_S 8 +/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO5_FUN_IE (BIT(9)) +#define IO_MUX_GPIO5_FUN_IE_M (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S) +#define IO_MUX_GPIO5_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO5_FUN_IE_S 9 +/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO5_FUN_DRV 0x00000003U +#define IO_MUX_GPIO5_FUN_DRV_M (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S) +#define IO_MUX_GPIO5_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO5_FUN_DRV_S 10 +/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO5_MCU_SEL 0x00000007U +#define IO_MUX_GPIO5_MCU_SEL_M (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S) +#define IO_MUX_GPIO5_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO5_MCU_SEL_S 12 +/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO5_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO5_FILTER_EN_M (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S) +#define IO_MUX_GPIO5_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO5_FILTER_EN_S 15 +/** IO_MUX_GPIO5_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO5_HYS_EN (BIT(16)) +#define IO_MUX_GPIO5_HYS_EN_M (IO_MUX_GPIO5_HYS_EN_V << IO_MUX_GPIO5_HYS_EN_S) +#define IO_MUX_GPIO5_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO5_HYS_EN_S 16 +/** IO_MUX_GPIO5_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO5_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO5_HYS_SEL_M (IO_MUX_GPIO5_HYS_SEL_V << IO_MUX_GPIO5_HYS_SEL_S) +#define IO_MUX_GPIO5_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO5_HYS_SEL_S 17 + +/** IO_MUX_GPIO6_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c) +/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO6_MCU_OE (BIT(0)) +#define IO_MUX_GPIO6_MCU_OE_M (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S) +#define IO_MUX_GPIO6_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO6_MCU_OE_S 0 +/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO6_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO6_SLP_SEL_M (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S) +#define IO_MUX_GPIO6_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO6_SLP_SEL_S 1 +/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO6_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO6_MCU_WPD_M (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S) +#define IO_MUX_GPIO6_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO6_MCU_WPD_S 2 +/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO6_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO6_MCU_WPU_M (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S) +#define IO_MUX_GPIO6_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO6_MCU_WPU_S 3 +/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO6_MCU_IE (BIT(4)) +#define IO_MUX_GPIO6_MCU_IE_M (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S) +#define IO_MUX_GPIO6_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO6_MCU_IE_S 4 +/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO6_MCU_DRV 0x00000003U +#define IO_MUX_GPIO6_MCU_DRV_M (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S) +#define IO_MUX_GPIO6_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO6_MCU_DRV_S 5 +/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO6_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO6_FUN_WPD_M (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S) +#define IO_MUX_GPIO6_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO6_FUN_WPD_S 7 +/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO6_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO6_FUN_WPU_M (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S) +#define IO_MUX_GPIO6_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO6_FUN_WPU_S 8 +/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO6_FUN_IE (BIT(9)) +#define IO_MUX_GPIO6_FUN_IE_M (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S) +#define IO_MUX_GPIO6_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO6_FUN_IE_S 9 +/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO6_FUN_DRV 0x00000003U +#define IO_MUX_GPIO6_FUN_DRV_M (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S) +#define IO_MUX_GPIO6_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO6_FUN_DRV_S 10 +/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO6_MCU_SEL 0x00000007U +#define IO_MUX_GPIO6_MCU_SEL_M (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S) +#define IO_MUX_GPIO6_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO6_MCU_SEL_S 12 +/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO6_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO6_FILTER_EN_M (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S) +#define IO_MUX_GPIO6_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO6_FILTER_EN_S 15 +/** IO_MUX_GPIO6_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO6_HYS_EN (BIT(16)) +#define IO_MUX_GPIO6_HYS_EN_M (IO_MUX_GPIO6_HYS_EN_V << IO_MUX_GPIO6_HYS_EN_S) +#define IO_MUX_GPIO6_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO6_HYS_EN_S 16 +/** IO_MUX_GPIO6_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO6_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO6_HYS_SEL_M (IO_MUX_GPIO6_HYS_SEL_V << IO_MUX_GPIO6_HYS_SEL_S) +#define IO_MUX_GPIO6_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO6_HYS_SEL_S 17 + +/** IO_MUX_GPIO7_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20) +/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO7_MCU_OE (BIT(0)) +#define IO_MUX_GPIO7_MCU_OE_M (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S) +#define IO_MUX_GPIO7_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO7_MCU_OE_S 0 +/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO7_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO7_SLP_SEL_M (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S) +#define IO_MUX_GPIO7_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO7_SLP_SEL_S 1 +/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO7_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO7_MCU_WPD_M (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S) +#define IO_MUX_GPIO7_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO7_MCU_WPD_S 2 +/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO7_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO7_MCU_WPU_M (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S) +#define IO_MUX_GPIO7_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO7_MCU_WPU_S 3 +/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO7_MCU_IE (BIT(4)) +#define IO_MUX_GPIO7_MCU_IE_M (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S) +#define IO_MUX_GPIO7_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO7_MCU_IE_S 4 +/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO7_MCU_DRV 0x00000003U +#define IO_MUX_GPIO7_MCU_DRV_M (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S) +#define IO_MUX_GPIO7_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO7_MCU_DRV_S 5 +/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO7_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO7_FUN_WPD_M (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S) +#define IO_MUX_GPIO7_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO7_FUN_WPD_S 7 +/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO7_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO7_FUN_WPU_M (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S) +#define IO_MUX_GPIO7_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO7_FUN_WPU_S 8 +/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO7_FUN_IE (BIT(9)) +#define IO_MUX_GPIO7_FUN_IE_M (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S) +#define IO_MUX_GPIO7_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO7_FUN_IE_S 9 +/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO7_FUN_DRV 0x00000003U +#define IO_MUX_GPIO7_FUN_DRV_M (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S) +#define IO_MUX_GPIO7_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO7_FUN_DRV_S 10 +/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO7_MCU_SEL 0x00000007U +#define IO_MUX_GPIO7_MCU_SEL_M (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S) +#define IO_MUX_GPIO7_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO7_MCU_SEL_S 12 +/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO7_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO7_FILTER_EN_M (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S) +#define IO_MUX_GPIO7_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO7_FILTER_EN_S 15 +/** IO_MUX_GPIO7_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO7_HYS_EN (BIT(16)) +#define IO_MUX_GPIO7_HYS_EN_M (IO_MUX_GPIO7_HYS_EN_V << IO_MUX_GPIO7_HYS_EN_S) +#define IO_MUX_GPIO7_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO7_HYS_EN_S 16 +/** IO_MUX_GPIO7_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO7_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO7_HYS_SEL_M (IO_MUX_GPIO7_HYS_SEL_V << IO_MUX_GPIO7_HYS_SEL_S) +#define IO_MUX_GPIO7_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO7_HYS_SEL_S 17 + +/** IO_MUX_GPIO8_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24) +/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO8_MCU_OE (BIT(0)) +#define IO_MUX_GPIO8_MCU_OE_M (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S) +#define IO_MUX_GPIO8_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO8_MCU_OE_S 0 +/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO8_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO8_SLP_SEL_M (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S) +#define IO_MUX_GPIO8_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO8_SLP_SEL_S 1 +/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO8_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO8_MCU_WPD_M (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S) +#define IO_MUX_GPIO8_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO8_MCU_WPD_S 2 +/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO8_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO8_MCU_WPU_M (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S) +#define IO_MUX_GPIO8_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO8_MCU_WPU_S 3 +/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO8_MCU_IE (BIT(4)) +#define IO_MUX_GPIO8_MCU_IE_M (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S) +#define IO_MUX_GPIO8_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO8_MCU_IE_S 4 +/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO8_MCU_DRV 0x00000003U +#define IO_MUX_GPIO8_MCU_DRV_M (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S) +#define IO_MUX_GPIO8_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO8_MCU_DRV_S 5 +/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO8_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO8_FUN_WPD_M (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S) +#define IO_MUX_GPIO8_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO8_FUN_WPD_S 7 +/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO8_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO8_FUN_WPU_M (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S) +#define IO_MUX_GPIO8_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO8_FUN_WPU_S 8 +/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO8_FUN_IE (BIT(9)) +#define IO_MUX_GPIO8_FUN_IE_M (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S) +#define IO_MUX_GPIO8_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO8_FUN_IE_S 9 +/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO8_FUN_DRV 0x00000003U +#define IO_MUX_GPIO8_FUN_DRV_M (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S) +#define IO_MUX_GPIO8_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO8_FUN_DRV_S 10 +/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO8_MCU_SEL 0x00000007U +#define IO_MUX_GPIO8_MCU_SEL_M (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S) +#define IO_MUX_GPIO8_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO8_MCU_SEL_S 12 +/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO8_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO8_FILTER_EN_M (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S) +#define IO_MUX_GPIO8_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO8_FILTER_EN_S 15 +/** IO_MUX_GPIO8_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO8_HYS_EN (BIT(16)) +#define IO_MUX_GPIO8_HYS_EN_M (IO_MUX_GPIO8_HYS_EN_V << IO_MUX_GPIO8_HYS_EN_S) +#define IO_MUX_GPIO8_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO8_HYS_EN_S 16 +/** IO_MUX_GPIO8_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO8_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO8_HYS_SEL_M (IO_MUX_GPIO8_HYS_SEL_V << IO_MUX_GPIO8_HYS_SEL_S) +#define IO_MUX_GPIO8_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO8_HYS_SEL_S 17 + +/** IO_MUX_GPIO9_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28) +/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO9_MCU_OE (BIT(0)) +#define IO_MUX_GPIO9_MCU_OE_M (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S) +#define IO_MUX_GPIO9_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO9_MCU_OE_S 0 +/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO9_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO9_SLP_SEL_M (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S) +#define IO_MUX_GPIO9_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO9_SLP_SEL_S 1 +/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO9_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO9_MCU_WPD_M (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S) +#define IO_MUX_GPIO9_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO9_MCU_WPD_S 2 +/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO9_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO9_MCU_WPU_M (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S) +#define IO_MUX_GPIO9_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO9_MCU_WPU_S 3 +/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO9_MCU_IE (BIT(4)) +#define IO_MUX_GPIO9_MCU_IE_M (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S) +#define IO_MUX_GPIO9_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO9_MCU_IE_S 4 +/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO9_MCU_DRV 0x00000003U +#define IO_MUX_GPIO9_MCU_DRV_M (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S) +#define IO_MUX_GPIO9_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO9_MCU_DRV_S 5 +/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO9_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO9_FUN_WPD_M (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S) +#define IO_MUX_GPIO9_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO9_FUN_WPD_S 7 +/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO9_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO9_FUN_WPU_M (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S) +#define IO_MUX_GPIO9_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO9_FUN_WPU_S 8 +/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO9_FUN_IE (BIT(9)) +#define IO_MUX_GPIO9_FUN_IE_M (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S) +#define IO_MUX_GPIO9_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO9_FUN_IE_S 9 +/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO9_FUN_DRV 0x00000003U +#define IO_MUX_GPIO9_FUN_DRV_M (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S) +#define IO_MUX_GPIO9_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO9_FUN_DRV_S 10 +/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO9_MCU_SEL 0x00000007U +#define IO_MUX_GPIO9_MCU_SEL_M (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S) +#define IO_MUX_GPIO9_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO9_MCU_SEL_S 12 +/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO9_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO9_FILTER_EN_M (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S) +#define IO_MUX_GPIO9_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO9_FILTER_EN_S 15 +/** IO_MUX_GPIO9_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO9_HYS_EN (BIT(16)) +#define IO_MUX_GPIO9_HYS_EN_M (IO_MUX_GPIO9_HYS_EN_V << IO_MUX_GPIO9_HYS_EN_S) +#define IO_MUX_GPIO9_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO9_HYS_EN_S 16 +/** IO_MUX_GPIO9_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO9_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO9_HYS_SEL_M (IO_MUX_GPIO9_HYS_SEL_V << IO_MUX_GPIO9_HYS_SEL_S) +#define IO_MUX_GPIO9_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO9_HYS_SEL_S 17 + +/** IO_MUX_GPIO10_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c) +/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO10_MCU_OE (BIT(0)) +#define IO_MUX_GPIO10_MCU_OE_M (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S) +#define IO_MUX_GPIO10_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO10_MCU_OE_S 0 +/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO10_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO10_SLP_SEL_M (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S) +#define IO_MUX_GPIO10_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO10_SLP_SEL_S 1 +/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO10_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO10_MCU_WPD_M (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S) +#define IO_MUX_GPIO10_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO10_MCU_WPD_S 2 +/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO10_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO10_MCU_WPU_M (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S) +#define IO_MUX_GPIO10_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO10_MCU_WPU_S 3 +/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO10_MCU_IE (BIT(4)) +#define IO_MUX_GPIO10_MCU_IE_M (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S) +#define IO_MUX_GPIO10_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO10_MCU_IE_S 4 +/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO10_MCU_DRV 0x00000003U +#define IO_MUX_GPIO10_MCU_DRV_M (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S) +#define IO_MUX_GPIO10_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO10_MCU_DRV_S 5 +/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO10_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO10_FUN_WPD_M (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S) +#define IO_MUX_GPIO10_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO10_FUN_WPD_S 7 +/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO10_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO10_FUN_WPU_M (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S) +#define IO_MUX_GPIO10_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO10_FUN_WPU_S 8 +/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO10_FUN_IE (BIT(9)) +#define IO_MUX_GPIO10_FUN_IE_M (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S) +#define IO_MUX_GPIO10_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO10_FUN_IE_S 9 +/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO10_FUN_DRV 0x00000003U +#define IO_MUX_GPIO10_FUN_DRV_M (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S) +#define IO_MUX_GPIO10_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO10_FUN_DRV_S 10 +/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO10_MCU_SEL 0x00000007U +#define IO_MUX_GPIO10_MCU_SEL_M (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S) +#define IO_MUX_GPIO10_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO10_MCU_SEL_S 12 +/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO10_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO10_FILTER_EN_M (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S) +#define IO_MUX_GPIO10_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO10_FILTER_EN_S 15 +/** IO_MUX_GPIO10_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO10_HYS_EN (BIT(16)) +#define IO_MUX_GPIO10_HYS_EN_M (IO_MUX_GPIO10_HYS_EN_V << IO_MUX_GPIO10_HYS_EN_S) +#define IO_MUX_GPIO10_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO10_HYS_EN_S 16 +/** IO_MUX_GPIO10_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO10_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO10_HYS_SEL_M (IO_MUX_GPIO10_HYS_SEL_V << IO_MUX_GPIO10_HYS_SEL_S) +#define IO_MUX_GPIO10_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO10_HYS_SEL_S 17 + +/** IO_MUX_GPIO11_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30) +/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO11_MCU_OE (BIT(0)) +#define IO_MUX_GPIO11_MCU_OE_M (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S) +#define IO_MUX_GPIO11_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO11_MCU_OE_S 0 +/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO11_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO11_SLP_SEL_M (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S) +#define IO_MUX_GPIO11_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO11_SLP_SEL_S 1 +/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO11_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO11_MCU_WPD_M (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S) +#define IO_MUX_GPIO11_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO11_MCU_WPD_S 2 +/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO11_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO11_MCU_WPU_M (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S) +#define IO_MUX_GPIO11_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO11_MCU_WPU_S 3 +/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO11_MCU_IE (BIT(4)) +#define IO_MUX_GPIO11_MCU_IE_M (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S) +#define IO_MUX_GPIO11_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO11_MCU_IE_S 4 +/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO11_MCU_DRV 0x00000003U +#define IO_MUX_GPIO11_MCU_DRV_M (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S) +#define IO_MUX_GPIO11_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO11_MCU_DRV_S 5 +/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO11_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO11_FUN_WPD_M (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S) +#define IO_MUX_GPIO11_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO11_FUN_WPD_S 7 +/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO11_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO11_FUN_WPU_M (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S) +#define IO_MUX_GPIO11_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO11_FUN_WPU_S 8 +/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO11_FUN_IE (BIT(9)) +#define IO_MUX_GPIO11_FUN_IE_M (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S) +#define IO_MUX_GPIO11_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO11_FUN_IE_S 9 +/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO11_FUN_DRV 0x00000003U +#define IO_MUX_GPIO11_FUN_DRV_M (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S) +#define IO_MUX_GPIO11_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO11_FUN_DRV_S 10 +/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO11_MCU_SEL 0x00000007U +#define IO_MUX_GPIO11_MCU_SEL_M (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S) +#define IO_MUX_GPIO11_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO11_MCU_SEL_S 12 +/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO11_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO11_FILTER_EN_M (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S) +#define IO_MUX_GPIO11_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO11_FILTER_EN_S 15 +/** IO_MUX_GPIO11_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO11_HYS_EN (BIT(16)) +#define IO_MUX_GPIO11_HYS_EN_M (IO_MUX_GPIO11_HYS_EN_V << IO_MUX_GPIO11_HYS_EN_S) +#define IO_MUX_GPIO11_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO11_HYS_EN_S 16 +/** IO_MUX_GPIO11_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO11_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO11_HYS_SEL_M (IO_MUX_GPIO11_HYS_SEL_V << IO_MUX_GPIO11_HYS_SEL_S) +#define IO_MUX_GPIO11_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO11_HYS_SEL_S 17 + +/** IO_MUX_GPIO12_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34) +/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO12_MCU_OE (BIT(0)) +#define IO_MUX_GPIO12_MCU_OE_M (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S) +#define IO_MUX_GPIO12_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO12_MCU_OE_S 0 +/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO12_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO12_SLP_SEL_M (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S) +#define IO_MUX_GPIO12_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO12_SLP_SEL_S 1 +/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO12_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO12_MCU_WPD_M (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S) +#define IO_MUX_GPIO12_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO12_MCU_WPD_S 2 +/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO12_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO12_MCU_WPU_M (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S) +#define IO_MUX_GPIO12_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO12_MCU_WPU_S 3 +/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO12_MCU_IE (BIT(4)) +#define IO_MUX_GPIO12_MCU_IE_M (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S) +#define IO_MUX_GPIO12_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO12_MCU_IE_S 4 +/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO12_MCU_DRV 0x00000003U +#define IO_MUX_GPIO12_MCU_DRV_M (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S) +#define IO_MUX_GPIO12_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO12_MCU_DRV_S 5 +/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO12_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO12_FUN_WPD_M (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S) +#define IO_MUX_GPIO12_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO12_FUN_WPD_S 7 +/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO12_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO12_FUN_WPU_M (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S) +#define IO_MUX_GPIO12_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO12_FUN_WPU_S 8 +/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO12_FUN_IE (BIT(9)) +#define IO_MUX_GPIO12_FUN_IE_M (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S) +#define IO_MUX_GPIO12_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO12_FUN_IE_S 9 +/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO12_FUN_DRV 0x00000003U +#define IO_MUX_GPIO12_FUN_DRV_M (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S) +#define IO_MUX_GPIO12_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO12_FUN_DRV_S 10 +/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO12_MCU_SEL 0x00000007U +#define IO_MUX_GPIO12_MCU_SEL_M (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S) +#define IO_MUX_GPIO12_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO12_MCU_SEL_S 12 +/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO12_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO12_FILTER_EN_M (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S) +#define IO_MUX_GPIO12_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO12_FILTER_EN_S 15 +/** IO_MUX_GPIO12_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO12_HYS_EN (BIT(16)) +#define IO_MUX_GPIO12_HYS_EN_M (IO_MUX_GPIO12_HYS_EN_V << IO_MUX_GPIO12_HYS_EN_S) +#define IO_MUX_GPIO12_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO12_HYS_EN_S 16 +/** IO_MUX_GPIO12_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO12_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO12_HYS_SEL_M (IO_MUX_GPIO12_HYS_SEL_V << IO_MUX_GPIO12_HYS_SEL_S) +#define IO_MUX_GPIO12_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO12_HYS_SEL_S 17 + +/** IO_MUX_GPIO13_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38) +/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO13_MCU_OE (BIT(0)) +#define IO_MUX_GPIO13_MCU_OE_M (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S) +#define IO_MUX_GPIO13_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO13_MCU_OE_S 0 +/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO13_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO13_SLP_SEL_M (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S) +#define IO_MUX_GPIO13_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO13_SLP_SEL_S 1 +/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO13_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO13_MCU_WPD_M (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S) +#define IO_MUX_GPIO13_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO13_MCU_WPD_S 2 +/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO13_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO13_MCU_WPU_M (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S) +#define IO_MUX_GPIO13_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO13_MCU_WPU_S 3 +/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO13_MCU_IE (BIT(4)) +#define IO_MUX_GPIO13_MCU_IE_M (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S) +#define IO_MUX_GPIO13_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO13_MCU_IE_S 4 +/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO13_MCU_DRV 0x00000003U +#define IO_MUX_GPIO13_MCU_DRV_M (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S) +#define IO_MUX_GPIO13_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO13_MCU_DRV_S 5 +/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO13_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO13_FUN_WPD_M (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S) +#define IO_MUX_GPIO13_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO13_FUN_WPD_S 7 +/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO13_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO13_FUN_WPU_M (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S) +#define IO_MUX_GPIO13_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO13_FUN_WPU_S 8 +/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO13_FUN_IE (BIT(9)) +#define IO_MUX_GPIO13_FUN_IE_M (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S) +#define IO_MUX_GPIO13_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO13_FUN_IE_S 9 +/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO13_FUN_DRV 0x00000003U +#define IO_MUX_GPIO13_FUN_DRV_M (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S) +#define IO_MUX_GPIO13_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO13_FUN_DRV_S 10 +/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO13_MCU_SEL 0x00000007U +#define IO_MUX_GPIO13_MCU_SEL_M (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S) +#define IO_MUX_GPIO13_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO13_MCU_SEL_S 12 +/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO13_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO13_FILTER_EN_M (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S) +#define IO_MUX_GPIO13_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO13_FILTER_EN_S 15 +/** IO_MUX_GPIO13_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO13_HYS_EN (BIT(16)) +#define IO_MUX_GPIO13_HYS_EN_M (IO_MUX_GPIO13_HYS_EN_V << IO_MUX_GPIO13_HYS_EN_S) +#define IO_MUX_GPIO13_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO13_HYS_EN_S 16 +/** IO_MUX_GPIO13_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO13_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO13_HYS_SEL_M (IO_MUX_GPIO13_HYS_SEL_V << IO_MUX_GPIO13_HYS_SEL_S) +#define IO_MUX_GPIO13_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO13_HYS_SEL_S 17 + +/** IO_MUX_GPIO14_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c) +/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO14_MCU_OE (BIT(0)) +#define IO_MUX_GPIO14_MCU_OE_M (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S) +#define IO_MUX_GPIO14_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO14_MCU_OE_S 0 +/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO14_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO14_SLP_SEL_M (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S) +#define IO_MUX_GPIO14_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO14_SLP_SEL_S 1 +/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO14_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO14_MCU_WPD_M (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S) +#define IO_MUX_GPIO14_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO14_MCU_WPD_S 2 +/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO14_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO14_MCU_WPU_M (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S) +#define IO_MUX_GPIO14_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO14_MCU_WPU_S 3 +/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO14_MCU_IE (BIT(4)) +#define IO_MUX_GPIO14_MCU_IE_M (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S) +#define IO_MUX_GPIO14_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO14_MCU_IE_S 4 +/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO14_MCU_DRV 0x00000003U +#define IO_MUX_GPIO14_MCU_DRV_M (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S) +#define IO_MUX_GPIO14_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO14_MCU_DRV_S 5 +/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO14_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO14_FUN_WPD_M (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S) +#define IO_MUX_GPIO14_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO14_FUN_WPD_S 7 +/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO14_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO14_FUN_WPU_M (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S) +#define IO_MUX_GPIO14_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO14_FUN_WPU_S 8 +/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO14_FUN_IE (BIT(9)) +#define IO_MUX_GPIO14_FUN_IE_M (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S) +#define IO_MUX_GPIO14_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO14_FUN_IE_S 9 +/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO14_FUN_DRV 0x00000003U +#define IO_MUX_GPIO14_FUN_DRV_M (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S) +#define IO_MUX_GPIO14_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO14_FUN_DRV_S 10 +/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO14_MCU_SEL 0x00000007U +#define IO_MUX_GPIO14_MCU_SEL_M (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S) +#define IO_MUX_GPIO14_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO14_MCU_SEL_S 12 +/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO14_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO14_FILTER_EN_M (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S) +#define IO_MUX_GPIO14_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO14_FILTER_EN_S 15 +/** IO_MUX_GPIO14_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO14_HYS_EN (BIT(16)) +#define IO_MUX_GPIO14_HYS_EN_M (IO_MUX_GPIO14_HYS_EN_V << IO_MUX_GPIO14_HYS_EN_S) +#define IO_MUX_GPIO14_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO14_HYS_EN_S 16 +/** IO_MUX_GPIO14_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO14_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO14_HYS_SEL_M (IO_MUX_GPIO14_HYS_SEL_V << IO_MUX_GPIO14_HYS_SEL_S) +#define IO_MUX_GPIO14_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO14_HYS_SEL_S 17 + +/** IO_MUX_GPIO15_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40) +/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO15_MCU_OE (BIT(0)) +#define IO_MUX_GPIO15_MCU_OE_M (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S) +#define IO_MUX_GPIO15_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO15_MCU_OE_S 0 +/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO15_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO15_SLP_SEL_M (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S) +#define IO_MUX_GPIO15_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO15_SLP_SEL_S 1 +/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO15_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO15_MCU_WPD_M (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S) +#define IO_MUX_GPIO15_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO15_MCU_WPD_S 2 +/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO15_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO15_MCU_WPU_M (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S) +#define IO_MUX_GPIO15_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO15_MCU_WPU_S 3 +/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO15_MCU_IE (BIT(4)) +#define IO_MUX_GPIO15_MCU_IE_M (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S) +#define IO_MUX_GPIO15_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO15_MCU_IE_S 4 +/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO15_MCU_DRV 0x00000003U +#define IO_MUX_GPIO15_MCU_DRV_M (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S) +#define IO_MUX_GPIO15_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO15_MCU_DRV_S 5 +/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO15_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO15_FUN_WPD_M (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S) +#define IO_MUX_GPIO15_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO15_FUN_WPD_S 7 +/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO15_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO15_FUN_WPU_M (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S) +#define IO_MUX_GPIO15_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO15_FUN_WPU_S 8 +/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO15_FUN_IE (BIT(9)) +#define IO_MUX_GPIO15_FUN_IE_M (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S) +#define IO_MUX_GPIO15_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO15_FUN_IE_S 9 +/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO15_FUN_DRV 0x00000003U +#define IO_MUX_GPIO15_FUN_DRV_M (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S) +#define IO_MUX_GPIO15_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO15_FUN_DRV_S 10 +/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO15_MCU_SEL 0x00000007U +#define IO_MUX_GPIO15_MCU_SEL_M (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S) +#define IO_MUX_GPIO15_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO15_MCU_SEL_S 12 +/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO15_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO15_FILTER_EN_M (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S) +#define IO_MUX_GPIO15_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO15_FILTER_EN_S 15 +/** IO_MUX_GPIO15_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO15_HYS_EN (BIT(16)) +#define IO_MUX_GPIO15_HYS_EN_M (IO_MUX_GPIO15_HYS_EN_V << IO_MUX_GPIO15_HYS_EN_S) +#define IO_MUX_GPIO15_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO15_HYS_EN_S 16 +/** IO_MUX_GPIO15_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO15_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO15_HYS_SEL_M (IO_MUX_GPIO15_HYS_SEL_V << IO_MUX_GPIO15_HYS_SEL_S) +#define IO_MUX_GPIO15_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO15_HYS_SEL_S 17 + +/** IO_MUX_GPIO16_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44) +/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO16_MCU_OE (BIT(0)) +#define IO_MUX_GPIO16_MCU_OE_M (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S) +#define IO_MUX_GPIO16_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO16_MCU_OE_S 0 +/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO16_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO16_SLP_SEL_M (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S) +#define IO_MUX_GPIO16_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO16_SLP_SEL_S 1 +/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO16_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO16_MCU_WPD_M (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S) +#define IO_MUX_GPIO16_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO16_MCU_WPD_S 2 +/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO16_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO16_MCU_WPU_M (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S) +#define IO_MUX_GPIO16_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO16_MCU_WPU_S 3 +/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO16_MCU_IE (BIT(4)) +#define IO_MUX_GPIO16_MCU_IE_M (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S) +#define IO_MUX_GPIO16_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO16_MCU_IE_S 4 +/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO16_MCU_DRV 0x00000003U +#define IO_MUX_GPIO16_MCU_DRV_M (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S) +#define IO_MUX_GPIO16_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO16_MCU_DRV_S 5 +/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO16_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO16_FUN_WPD_M (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S) +#define IO_MUX_GPIO16_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO16_FUN_WPD_S 7 +/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO16_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO16_FUN_WPU_M (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S) +#define IO_MUX_GPIO16_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO16_FUN_WPU_S 8 +/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO16_FUN_IE (BIT(9)) +#define IO_MUX_GPIO16_FUN_IE_M (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S) +#define IO_MUX_GPIO16_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO16_FUN_IE_S 9 +/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO16_FUN_DRV 0x00000003U +#define IO_MUX_GPIO16_FUN_DRV_M (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S) +#define IO_MUX_GPIO16_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO16_FUN_DRV_S 10 +/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO16_MCU_SEL 0x00000007U +#define IO_MUX_GPIO16_MCU_SEL_M (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S) +#define IO_MUX_GPIO16_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO16_MCU_SEL_S 12 +/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO16_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO16_FILTER_EN_M (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S) +#define IO_MUX_GPIO16_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO16_FILTER_EN_S 15 +/** IO_MUX_GPIO16_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO16_HYS_EN (BIT(16)) +#define IO_MUX_GPIO16_HYS_EN_M (IO_MUX_GPIO16_HYS_EN_V << IO_MUX_GPIO16_HYS_EN_S) +#define IO_MUX_GPIO16_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO16_HYS_EN_S 16 +/** IO_MUX_GPIO16_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO16_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO16_HYS_SEL_M (IO_MUX_GPIO16_HYS_SEL_V << IO_MUX_GPIO16_HYS_SEL_S) +#define IO_MUX_GPIO16_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO16_HYS_SEL_S 17 + +/** IO_MUX_GPIO17_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48) +/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO17_MCU_OE (BIT(0)) +#define IO_MUX_GPIO17_MCU_OE_M (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S) +#define IO_MUX_GPIO17_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO17_MCU_OE_S 0 +/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO17_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO17_SLP_SEL_M (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S) +#define IO_MUX_GPIO17_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO17_SLP_SEL_S 1 +/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO17_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO17_MCU_WPD_M (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S) +#define IO_MUX_GPIO17_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO17_MCU_WPD_S 2 +/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO17_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO17_MCU_WPU_M (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S) +#define IO_MUX_GPIO17_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO17_MCU_WPU_S 3 +/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO17_MCU_IE (BIT(4)) +#define IO_MUX_GPIO17_MCU_IE_M (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S) +#define IO_MUX_GPIO17_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO17_MCU_IE_S 4 +/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO17_MCU_DRV 0x00000003U +#define IO_MUX_GPIO17_MCU_DRV_M (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S) +#define IO_MUX_GPIO17_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO17_MCU_DRV_S 5 +/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO17_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO17_FUN_WPD_M (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S) +#define IO_MUX_GPIO17_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO17_FUN_WPD_S 7 +/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO17_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO17_FUN_WPU_M (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S) +#define IO_MUX_GPIO17_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO17_FUN_WPU_S 8 +/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO17_FUN_IE (BIT(9)) +#define IO_MUX_GPIO17_FUN_IE_M (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S) +#define IO_MUX_GPIO17_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO17_FUN_IE_S 9 +/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO17_FUN_DRV 0x00000003U +#define IO_MUX_GPIO17_FUN_DRV_M (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S) +#define IO_MUX_GPIO17_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO17_FUN_DRV_S 10 +/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO17_MCU_SEL 0x00000007U +#define IO_MUX_GPIO17_MCU_SEL_M (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S) +#define IO_MUX_GPIO17_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO17_MCU_SEL_S 12 +/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO17_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO17_FILTER_EN_M (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S) +#define IO_MUX_GPIO17_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO17_FILTER_EN_S 15 +/** IO_MUX_GPIO17_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO17_HYS_EN (BIT(16)) +#define IO_MUX_GPIO17_HYS_EN_M (IO_MUX_GPIO17_HYS_EN_V << IO_MUX_GPIO17_HYS_EN_S) +#define IO_MUX_GPIO17_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO17_HYS_EN_S 16 +/** IO_MUX_GPIO17_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO17_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO17_HYS_SEL_M (IO_MUX_GPIO17_HYS_SEL_V << IO_MUX_GPIO17_HYS_SEL_S) +#define IO_MUX_GPIO17_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO17_HYS_SEL_S 17 + +/** IO_MUX_GPIO18_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c) +/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO18_MCU_OE (BIT(0)) +#define IO_MUX_GPIO18_MCU_OE_M (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S) +#define IO_MUX_GPIO18_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO18_MCU_OE_S 0 +/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO18_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO18_SLP_SEL_M (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S) +#define IO_MUX_GPIO18_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO18_SLP_SEL_S 1 +/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO18_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO18_MCU_WPD_M (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S) +#define IO_MUX_GPIO18_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO18_MCU_WPD_S 2 +/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO18_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO18_MCU_WPU_M (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S) +#define IO_MUX_GPIO18_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO18_MCU_WPU_S 3 +/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO18_MCU_IE (BIT(4)) +#define IO_MUX_GPIO18_MCU_IE_M (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S) +#define IO_MUX_GPIO18_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO18_MCU_IE_S 4 +/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO18_MCU_DRV 0x00000003U +#define IO_MUX_GPIO18_MCU_DRV_M (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S) +#define IO_MUX_GPIO18_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO18_MCU_DRV_S 5 +/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO18_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO18_FUN_WPD_M (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S) +#define IO_MUX_GPIO18_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO18_FUN_WPD_S 7 +/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO18_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO18_FUN_WPU_M (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S) +#define IO_MUX_GPIO18_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO18_FUN_WPU_S 8 +/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO18_FUN_IE (BIT(9)) +#define IO_MUX_GPIO18_FUN_IE_M (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S) +#define IO_MUX_GPIO18_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO18_FUN_IE_S 9 +/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO18_FUN_DRV 0x00000003U +#define IO_MUX_GPIO18_FUN_DRV_M (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S) +#define IO_MUX_GPIO18_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO18_FUN_DRV_S 10 +/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO18_MCU_SEL 0x00000007U +#define IO_MUX_GPIO18_MCU_SEL_M (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S) +#define IO_MUX_GPIO18_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO18_MCU_SEL_S 12 +/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO18_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO18_FILTER_EN_M (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S) +#define IO_MUX_GPIO18_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO18_FILTER_EN_S 15 +/** IO_MUX_GPIO18_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO18_HYS_EN (BIT(16)) +#define IO_MUX_GPIO18_HYS_EN_M (IO_MUX_GPIO18_HYS_EN_V << IO_MUX_GPIO18_HYS_EN_S) +#define IO_MUX_GPIO18_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO18_HYS_EN_S 16 +/** IO_MUX_GPIO18_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO18_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO18_HYS_SEL_M (IO_MUX_GPIO18_HYS_SEL_V << IO_MUX_GPIO18_HYS_SEL_S) +#define IO_MUX_GPIO18_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO18_HYS_SEL_S 17 + +/** IO_MUX_GPIO19_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50) +/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO19_MCU_OE (BIT(0)) +#define IO_MUX_GPIO19_MCU_OE_M (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S) +#define IO_MUX_GPIO19_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO19_MCU_OE_S 0 +/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO19_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO19_SLP_SEL_M (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S) +#define IO_MUX_GPIO19_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO19_SLP_SEL_S 1 +/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO19_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO19_MCU_WPD_M (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S) +#define IO_MUX_GPIO19_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO19_MCU_WPD_S 2 +/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO19_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO19_MCU_WPU_M (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S) +#define IO_MUX_GPIO19_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO19_MCU_WPU_S 3 +/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO19_MCU_IE (BIT(4)) +#define IO_MUX_GPIO19_MCU_IE_M (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S) +#define IO_MUX_GPIO19_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO19_MCU_IE_S 4 +/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO19_MCU_DRV 0x00000003U +#define IO_MUX_GPIO19_MCU_DRV_M (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S) +#define IO_MUX_GPIO19_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO19_MCU_DRV_S 5 +/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO19_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO19_FUN_WPD_M (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S) +#define IO_MUX_GPIO19_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO19_FUN_WPD_S 7 +/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO19_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO19_FUN_WPU_M (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S) +#define IO_MUX_GPIO19_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO19_FUN_WPU_S 8 +/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO19_FUN_IE (BIT(9)) +#define IO_MUX_GPIO19_FUN_IE_M (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S) +#define IO_MUX_GPIO19_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO19_FUN_IE_S 9 +/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO19_FUN_DRV 0x00000003U +#define IO_MUX_GPIO19_FUN_DRV_M (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S) +#define IO_MUX_GPIO19_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO19_FUN_DRV_S 10 +/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO19_MCU_SEL 0x00000007U +#define IO_MUX_GPIO19_MCU_SEL_M (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S) +#define IO_MUX_GPIO19_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO19_MCU_SEL_S 12 +/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO19_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO19_FILTER_EN_M (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S) +#define IO_MUX_GPIO19_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO19_FILTER_EN_S 15 +/** IO_MUX_GPIO19_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO19_HYS_EN (BIT(16)) +#define IO_MUX_GPIO19_HYS_EN_M (IO_MUX_GPIO19_HYS_EN_V << IO_MUX_GPIO19_HYS_EN_S) +#define IO_MUX_GPIO19_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO19_HYS_EN_S 16 +/** IO_MUX_GPIO19_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO19_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO19_HYS_SEL_M (IO_MUX_GPIO19_HYS_SEL_V << IO_MUX_GPIO19_HYS_SEL_S) +#define IO_MUX_GPIO19_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO19_HYS_SEL_S 17 + +/** IO_MUX_GPIO20_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54) +/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO20_MCU_OE (BIT(0)) +#define IO_MUX_GPIO20_MCU_OE_M (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S) +#define IO_MUX_GPIO20_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO20_MCU_OE_S 0 +/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO20_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO20_SLP_SEL_M (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S) +#define IO_MUX_GPIO20_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO20_SLP_SEL_S 1 +/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO20_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO20_MCU_WPD_M (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S) +#define IO_MUX_GPIO20_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO20_MCU_WPD_S 2 +/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO20_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO20_MCU_WPU_M (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S) +#define IO_MUX_GPIO20_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO20_MCU_WPU_S 3 +/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO20_MCU_IE (BIT(4)) +#define IO_MUX_GPIO20_MCU_IE_M (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S) +#define IO_MUX_GPIO20_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO20_MCU_IE_S 4 +/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO20_MCU_DRV 0x00000003U +#define IO_MUX_GPIO20_MCU_DRV_M (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S) +#define IO_MUX_GPIO20_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO20_MCU_DRV_S 5 +/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO20_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO20_FUN_WPD_M (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S) +#define IO_MUX_GPIO20_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO20_FUN_WPD_S 7 +/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO20_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO20_FUN_WPU_M (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S) +#define IO_MUX_GPIO20_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO20_FUN_WPU_S 8 +/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO20_FUN_IE (BIT(9)) +#define IO_MUX_GPIO20_FUN_IE_M (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S) +#define IO_MUX_GPIO20_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO20_FUN_IE_S 9 +/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO20_FUN_DRV 0x00000003U +#define IO_MUX_GPIO20_FUN_DRV_M (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S) +#define IO_MUX_GPIO20_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO20_FUN_DRV_S 10 +/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO20_MCU_SEL 0x00000007U +#define IO_MUX_GPIO20_MCU_SEL_M (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S) +#define IO_MUX_GPIO20_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO20_MCU_SEL_S 12 +/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO20_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO20_FILTER_EN_M (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S) +#define IO_MUX_GPIO20_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO20_FILTER_EN_S 15 +/** IO_MUX_GPIO20_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO20_HYS_EN (BIT(16)) +#define IO_MUX_GPIO20_HYS_EN_M (IO_MUX_GPIO20_HYS_EN_V << IO_MUX_GPIO20_HYS_EN_S) +#define IO_MUX_GPIO20_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO20_HYS_EN_S 16 +/** IO_MUX_GPIO20_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO20_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO20_HYS_SEL_M (IO_MUX_GPIO20_HYS_SEL_V << IO_MUX_GPIO20_HYS_SEL_S) +#define IO_MUX_GPIO20_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO20_HYS_SEL_S 17 + +/** IO_MUX_GPIO21_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58) +/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO21_MCU_OE (BIT(0)) +#define IO_MUX_GPIO21_MCU_OE_M (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S) +#define IO_MUX_GPIO21_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO21_MCU_OE_S 0 +/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO21_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO21_SLP_SEL_M (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S) +#define IO_MUX_GPIO21_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO21_SLP_SEL_S 1 +/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO21_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO21_MCU_WPD_M (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S) +#define IO_MUX_GPIO21_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO21_MCU_WPD_S 2 +/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO21_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO21_MCU_WPU_M (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S) +#define IO_MUX_GPIO21_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO21_MCU_WPU_S 3 +/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO21_MCU_IE (BIT(4)) +#define IO_MUX_GPIO21_MCU_IE_M (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S) +#define IO_MUX_GPIO21_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO21_MCU_IE_S 4 +/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO21_MCU_DRV 0x00000003U +#define IO_MUX_GPIO21_MCU_DRV_M (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S) +#define IO_MUX_GPIO21_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO21_MCU_DRV_S 5 +/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO21_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO21_FUN_WPD_M (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S) +#define IO_MUX_GPIO21_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO21_FUN_WPD_S 7 +/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO21_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO21_FUN_WPU_M (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S) +#define IO_MUX_GPIO21_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO21_FUN_WPU_S 8 +/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO21_FUN_IE (BIT(9)) +#define IO_MUX_GPIO21_FUN_IE_M (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S) +#define IO_MUX_GPIO21_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO21_FUN_IE_S 9 +/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO21_FUN_DRV 0x00000003U +#define IO_MUX_GPIO21_FUN_DRV_M (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S) +#define IO_MUX_GPIO21_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO21_FUN_DRV_S 10 +/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO21_MCU_SEL 0x00000007U +#define IO_MUX_GPIO21_MCU_SEL_M (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S) +#define IO_MUX_GPIO21_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO21_MCU_SEL_S 12 +/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO21_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO21_FILTER_EN_M (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S) +#define IO_MUX_GPIO21_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO21_FILTER_EN_S 15 +/** IO_MUX_GPIO21_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO21_HYS_EN (BIT(16)) +#define IO_MUX_GPIO21_HYS_EN_M (IO_MUX_GPIO21_HYS_EN_V << IO_MUX_GPIO21_HYS_EN_S) +#define IO_MUX_GPIO21_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO21_HYS_EN_S 16 +/** IO_MUX_GPIO21_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO21_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO21_HYS_SEL_M (IO_MUX_GPIO21_HYS_SEL_V << IO_MUX_GPIO21_HYS_SEL_S) +#define IO_MUX_GPIO21_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO21_HYS_SEL_S 17 + +/** IO_MUX_GPIO22_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c) +/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO22_MCU_OE (BIT(0)) +#define IO_MUX_GPIO22_MCU_OE_M (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S) +#define IO_MUX_GPIO22_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO22_MCU_OE_S 0 +/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO22_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO22_SLP_SEL_M (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S) +#define IO_MUX_GPIO22_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO22_SLP_SEL_S 1 +/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO22_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO22_MCU_WPD_M (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S) +#define IO_MUX_GPIO22_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO22_MCU_WPD_S 2 +/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO22_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO22_MCU_WPU_M (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S) +#define IO_MUX_GPIO22_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO22_MCU_WPU_S 3 +/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO22_MCU_IE (BIT(4)) +#define IO_MUX_GPIO22_MCU_IE_M (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S) +#define IO_MUX_GPIO22_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO22_MCU_IE_S 4 +/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO22_MCU_DRV 0x00000003U +#define IO_MUX_GPIO22_MCU_DRV_M (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S) +#define IO_MUX_GPIO22_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO22_MCU_DRV_S 5 +/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO22_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO22_FUN_WPD_M (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S) +#define IO_MUX_GPIO22_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO22_FUN_WPD_S 7 +/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO22_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO22_FUN_WPU_M (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S) +#define IO_MUX_GPIO22_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO22_FUN_WPU_S 8 +/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO22_FUN_IE (BIT(9)) +#define IO_MUX_GPIO22_FUN_IE_M (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S) +#define IO_MUX_GPIO22_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO22_FUN_IE_S 9 +/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO22_FUN_DRV 0x00000003U +#define IO_MUX_GPIO22_FUN_DRV_M (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S) +#define IO_MUX_GPIO22_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO22_FUN_DRV_S 10 +/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO22_MCU_SEL 0x00000007U +#define IO_MUX_GPIO22_MCU_SEL_M (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S) +#define IO_MUX_GPIO22_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO22_MCU_SEL_S 12 +/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO22_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO22_FILTER_EN_M (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S) +#define IO_MUX_GPIO22_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO22_FILTER_EN_S 15 +/** IO_MUX_GPIO22_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO22_HYS_EN (BIT(16)) +#define IO_MUX_GPIO22_HYS_EN_M (IO_MUX_GPIO22_HYS_EN_V << IO_MUX_GPIO22_HYS_EN_S) +#define IO_MUX_GPIO22_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO22_HYS_EN_S 16 +/** IO_MUX_GPIO22_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO22_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO22_HYS_SEL_M (IO_MUX_GPIO22_HYS_SEL_V << IO_MUX_GPIO22_HYS_SEL_S) +#define IO_MUX_GPIO22_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO22_HYS_SEL_S 17 + +/** IO_MUX_GPIO23_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60) +/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO23_MCU_OE (BIT(0)) +#define IO_MUX_GPIO23_MCU_OE_M (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S) +#define IO_MUX_GPIO23_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO23_MCU_OE_S 0 +/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO23_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO23_SLP_SEL_M (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S) +#define IO_MUX_GPIO23_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO23_SLP_SEL_S 1 +/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO23_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO23_MCU_WPD_M (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S) +#define IO_MUX_GPIO23_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO23_MCU_WPD_S 2 +/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO23_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO23_MCU_WPU_M (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S) +#define IO_MUX_GPIO23_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO23_MCU_WPU_S 3 +/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO23_MCU_IE (BIT(4)) +#define IO_MUX_GPIO23_MCU_IE_M (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S) +#define IO_MUX_GPIO23_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO23_MCU_IE_S 4 +/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO23_MCU_DRV 0x00000003U +#define IO_MUX_GPIO23_MCU_DRV_M (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S) +#define IO_MUX_GPIO23_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO23_MCU_DRV_S 5 +/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO23_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO23_FUN_WPD_M (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S) +#define IO_MUX_GPIO23_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO23_FUN_WPD_S 7 +/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO23_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO23_FUN_WPU_M (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S) +#define IO_MUX_GPIO23_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO23_FUN_WPU_S 8 +/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO23_FUN_IE (BIT(9)) +#define IO_MUX_GPIO23_FUN_IE_M (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S) +#define IO_MUX_GPIO23_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO23_FUN_IE_S 9 +/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO23_FUN_DRV 0x00000003U +#define IO_MUX_GPIO23_FUN_DRV_M (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S) +#define IO_MUX_GPIO23_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO23_FUN_DRV_S 10 +/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO23_MCU_SEL 0x00000007U +#define IO_MUX_GPIO23_MCU_SEL_M (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S) +#define IO_MUX_GPIO23_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO23_MCU_SEL_S 12 +/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO23_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO23_FILTER_EN_M (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S) +#define IO_MUX_GPIO23_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO23_FILTER_EN_S 15 +/** IO_MUX_GPIO23_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO23_HYS_EN (BIT(16)) +#define IO_MUX_GPIO23_HYS_EN_M (IO_MUX_GPIO23_HYS_EN_V << IO_MUX_GPIO23_HYS_EN_S) +#define IO_MUX_GPIO23_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO23_HYS_EN_S 16 +/** IO_MUX_GPIO23_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO23_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO23_HYS_SEL_M (IO_MUX_GPIO23_HYS_SEL_V << IO_MUX_GPIO23_HYS_SEL_S) +#define IO_MUX_GPIO23_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO23_HYS_SEL_S 17 + +/** IO_MUX_GPIO24_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64) +/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO24_MCU_OE (BIT(0)) +#define IO_MUX_GPIO24_MCU_OE_M (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S) +#define IO_MUX_GPIO24_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO24_MCU_OE_S 0 +/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO24_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO24_SLP_SEL_M (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S) +#define IO_MUX_GPIO24_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO24_SLP_SEL_S 1 +/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO24_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO24_MCU_WPD_M (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S) +#define IO_MUX_GPIO24_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO24_MCU_WPD_S 2 +/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO24_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO24_MCU_WPU_M (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S) +#define IO_MUX_GPIO24_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO24_MCU_WPU_S 3 +/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO24_MCU_IE (BIT(4)) +#define IO_MUX_GPIO24_MCU_IE_M (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S) +#define IO_MUX_GPIO24_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO24_MCU_IE_S 4 +/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO24_MCU_DRV 0x00000003U +#define IO_MUX_GPIO24_MCU_DRV_M (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S) +#define IO_MUX_GPIO24_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO24_MCU_DRV_S 5 +/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO24_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO24_FUN_WPD_M (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S) +#define IO_MUX_GPIO24_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO24_FUN_WPD_S 7 +/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO24_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO24_FUN_WPU_M (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S) +#define IO_MUX_GPIO24_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO24_FUN_WPU_S 8 +/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO24_FUN_IE (BIT(9)) +#define IO_MUX_GPIO24_FUN_IE_M (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S) +#define IO_MUX_GPIO24_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO24_FUN_IE_S 9 +/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO24_FUN_DRV 0x00000003U +#define IO_MUX_GPIO24_FUN_DRV_M (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S) +#define IO_MUX_GPIO24_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO24_FUN_DRV_S 10 +/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO24_MCU_SEL 0x00000007U +#define IO_MUX_GPIO24_MCU_SEL_M (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S) +#define IO_MUX_GPIO24_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO24_MCU_SEL_S 12 +/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO24_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO24_FILTER_EN_M (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S) +#define IO_MUX_GPIO24_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO24_FILTER_EN_S 15 +/** IO_MUX_GPIO24_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO24_HYS_EN (BIT(16)) +#define IO_MUX_GPIO24_HYS_EN_M (IO_MUX_GPIO24_HYS_EN_V << IO_MUX_GPIO24_HYS_EN_S) +#define IO_MUX_GPIO24_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO24_HYS_EN_S 16 +/** IO_MUX_GPIO24_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO24_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO24_HYS_SEL_M (IO_MUX_GPIO24_HYS_SEL_V << IO_MUX_GPIO24_HYS_SEL_S) +#define IO_MUX_GPIO24_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO24_HYS_SEL_S 17 + +/** IO_MUX_GPIO25_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68) +/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO25_MCU_OE (BIT(0)) +#define IO_MUX_GPIO25_MCU_OE_M (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S) +#define IO_MUX_GPIO25_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO25_MCU_OE_S 0 +/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO25_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO25_SLP_SEL_M (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S) +#define IO_MUX_GPIO25_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO25_SLP_SEL_S 1 +/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO25_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO25_MCU_WPD_M (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S) +#define IO_MUX_GPIO25_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO25_MCU_WPD_S 2 +/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO25_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO25_MCU_WPU_M (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S) +#define IO_MUX_GPIO25_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO25_MCU_WPU_S 3 +/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO25_MCU_IE (BIT(4)) +#define IO_MUX_GPIO25_MCU_IE_M (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S) +#define IO_MUX_GPIO25_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO25_MCU_IE_S 4 +/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO25_MCU_DRV 0x00000003U +#define IO_MUX_GPIO25_MCU_DRV_M (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S) +#define IO_MUX_GPIO25_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO25_MCU_DRV_S 5 +/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO25_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO25_FUN_WPD_M (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S) +#define IO_MUX_GPIO25_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO25_FUN_WPD_S 7 +/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO25_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO25_FUN_WPU_M (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S) +#define IO_MUX_GPIO25_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO25_FUN_WPU_S 8 +/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO25_FUN_IE (BIT(9)) +#define IO_MUX_GPIO25_FUN_IE_M (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S) +#define IO_MUX_GPIO25_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO25_FUN_IE_S 9 +/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO25_FUN_DRV 0x00000003U +#define IO_MUX_GPIO25_FUN_DRV_M (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S) +#define IO_MUX_GPIO25_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO25_FUN_DRV_S 10 +/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO25_MCU_SEL 0x00000007U +#define IO_MUX_GPIO25_MCU_SEL_M (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S) +#define IO_MUX_GPIO25_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO25_MCU_SEL_S 12 +/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO25_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO25_FILTER_EN_M (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S) +#define IO_MUX_GPIO25_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO25_FILTER_EN_S 15 +/** IO_MUX_GPIO25_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO25_HYS_EN (BIT(16)) +#define IO_MUX_GPIO25_HYS_EN_M (IO_MUX_GPIO25_HYS_EN_V << IO_MUX_GPIO25_HYS_EN_S) +#define IO_MUX_GPIO25_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO25_HYS_EN_S 16 +/** IO_MUX_GPIO25_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO25_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO25_HYS_SEL_M (IO_MUX_GPIO25_HYS_SEL_V << IO_MUX_GPIO25_HYS_SEL_S) +#define IO_MUX_GPIO25_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO25_HYS_SEL_S 17 + +/** IO_MUX_GPIO26_REG register + * IO MUX Configure Register for pad XTAL_32K_P + */ +#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c) +/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ +#define IO_MUX_GPIO26_MCU_OE (BIT(0)) +#define IO_MUX_GPIO26_MCU_OE_M (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S) +#define IO_MUX_GPIO26_MCU_OE_V 0x00000001U +#define IO_MUX_GPIO26_MCU_OE_S 0 +/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ +#define IO_MUX_GPIO26_SLP_SEL (BIT(1)) +#define IO_MUX_GPIO26_SLP_SEL_M (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S) +#define IO_MUX_GPIO26_SLP_SEL_V 0x00000001U +#define IO_MUX_GPIO26_SLP_SEL_S 1 +/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ +#define IO_MUX_GPIO26_MCU_WPD (BIT(2)) +#define IO_MUX_GPIO26_MCU_WPD_M (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S) +#define IO_MUX_GPIO26_MCU_WPD_V 0x00000001U +#define IO_MUX_GPIO26_MCU_WPD_S 2 +/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ +#define IO_MUX_GPIO26_MCU_WPU (BIT(3)) +#define IO_MUX_GPIO26_MCU_WPU_M (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S) +#define IO_MUX_GPIO26_MCU_WPU_V 0x00000001U +#define IO_MUX_GPIO26_MCU_WPU_S 3 +/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO26_MCU_IE (BIT(4)) +#define IO_MUX_GPIO26_MCU_IE_M (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S) +#define IO_MUX_GPIO26_MCU_IE_V 0x00000001U +#define IO_MUX_GPIO26_MCU_IE_S 4 +/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO26_MCU_DRV 0x00000003U +#define IO_MUX_GPIO26_MCU_DRV_M (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S) +#define IO_MUX_GPIO26_MCU_DRV_V 0x00000003U +#define IO_MUX_GPIO26_MCU_DRV_S 5 +/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ +#define IO_MUX_GPIO26_FUN_WPD (BIT(7)) +#define IO_MUX_GPIO26_FUN_WPD_M (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S) +#define IO_MUX_GPIO26_FUN_WPD_V 0x00000001U +#define IO_MUX_GPIO26_FUN_WPD_S 7 +/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ +#define IO_MUX_GPIO26_FUN_WPU (BIT(8)) +#define IO_MUX_GPIO26_FUN_WPU_M (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S) +#define IO_MUX_GPIO26_FUN_WPU_V 0x00000001U +#define IO_MUX_GPIO26_FUN_WPU_S 8 +/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ +#define IO_MUX_GPIO26_FUN_IE (BIT(9)) +#define IO_MUX_GPIO26_FUN_IE_M (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S) +#define IO_MUX_GPIO26_FUN_IE_V 0x00000001U +#define IO_MUX_GPIO26_FUN_IE_S 9 +/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ +#define IO_MUX_GPIO26_FUN_DRV 0x00000003U +#define IO_MUX_GPIO26_FUN_DRV_M (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S) +#define IO_MUX_GPIO26_FUN_DRV_V 0x00000003U +#define IO_MUX_GPIO26_FUN_DRV_S 10 +/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ +#define IO_MUX_GPIO26_MCU_SEL 0x00000007U +#define IO_MUX_GPIO26_MCU_SEL_M (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S) +#define IO_MUX_GPIO26_MCU_SEL_V 0x00000007U +#define IO_MUX_GPIO26_MCU_SEL_S 12 +/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ +#define IO_MUX_GPIO26_FILTER_EN (BIT(15)) +#define IO_MUX_GPIO26_FILTER_EN_M (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S) +#define IO_MUX_GPIO26_FILTER_EN_V 0x00000001U +#define IO_MUX_GPIO26_FILTER_EN_S 15 +/** IO_MUX_GPIO26_HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ +#define IO_MUX_GPIO26_HYS_EN (BIT(16)) +#define IO_MUX_GPIO26_HYS_EN_M (IO_MUX_GPIO26_HYS_EN_V << IO_MUX_GPIO26_HYS_EN_S) +#define IO_MUX_GPIO26_HYS_EN_V 0x00000001U +#define IO_MUX_GPIO26_HYS_EN_S 16 +/** IO_MUX_GPIO26_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ +#define IO_MUX_GPIO26_HYS_SEL (BIT(17)) +#define IO_MUX_GPIO26_HYS_SEL_M (IO_MUX_GPIO26_HYS_SEL_V << IO_MUX_GPIO26_HYS_SEL_S) +#define IO_MUX_GPIO26_HYS_SEL_V 0x00000001U +#define IO_MUX_GPIO26_HYS_SEL_S 17 + +/** IO_MUX_DATE_REG register + * IO MUX Version Control Register + */ +#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0xfc) +/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36708704; + * Version control register + */ +#define IO_MUX_REG_DATE 0x0FFFFFFFU +#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S) +#define IO_MUX_REG_DATE_V 0x0FFFFFFFU +#define IO_MUX_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/io_mux_struct.h b/components/soc/esp32c5/include/soc/io_mux_struct.h new file mode 100644 index 0000000000..33b6319240 --- /dev/null +++ b/components/soc/esp32c5/include/soc/io_mux_struct.h @@ -0,0 +1,143 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configure Registers */ +/** Type of pin_ctrl register + * Clock Output Configuration Register + */ +typedef union { + struct { + /** clk_out1 : R/W; bitpos: [4:0]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. + * CLK_OUT_out1 can be found in peripheral output signals. + */ + uint32_t clk_out1:5; + /** clk_out2 : R/W; bitpos: [9:5]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. + * CLK_OUT_out2 can be found in peripheral output signals. + */ + uint32_t clk_out2:5; + /** clk_out3 : R/W; bitpos: [14:10]; default: 7; + * If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. + * CLK_OUT_out3 can be found in peripheral output signals. + */ + uint32_t clk_out3:5; + uint32_t reserved_15:17; + }; + uint32_t val; +} io_mux_pin_ctrl_reg_t; + +/** Type of gpion register + * IO MUX Configure Register for pad XTAL_32K_P + */ +typedef union { + struct { + /** gpion_mcu_oe : R/W; bitpos: [0]; default: 0; + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. + */ + uint32_t gpion_mcu_oe:1; + /** gpion_slp_sel : R/W; bitpos: [1]; default: 0; + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + */ + uint32_t gpion_slp_sel:1; + /** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0; + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. + */ + uint32_t gpion_mcu_wpd:1; + /** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0; + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. + */ + uint32_t gpion_mcu_wpu:1; + /** gpion_mcu_ie : R/W; bitpos: [4]; default: 0; + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. + */ + uint32_t gpion_mcu_ie:1; + /** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: + * ~20mA. 3: ~40mA. + */ + uint32_t gpion_mcu_drv:2; + /** gpion_fun_wpd : R/W; bitpos: [7]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. + */ + uint32_t gpion_fun_wpd:1; + /** gpion_fun_wpu : R/W; bitpos: [8]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. + */ + uint32_t gpion_fun_wpu:1; + /** gpion_fun_ie : R/W; bitpos: [9]; default: 0; + * Input enable of the pad. 1: input enabled. 0: input disabled. + */ + uint32_t gpion_fun_ie:1; + /** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. + */ + uint32_t gpion_fun_drv:2; + /** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. + */ + uint32_t gpion_mcu_sel:3; + /** gpion_filter_en : R/W; bitpos: [15]; default: 0; + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. + */ + uint32_t gpion_filter_en:1; + /** gpion_hys_en : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. + */ + uint32_t gpion_hys_en:1; + /** gpion_hys_sel : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling siganl from slftware. 0: Select enabling signal from efuse hardware. + */ + uint32_t gpion_hys_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} io_mux_gpion_reg_t; + +/** Type of date register + * IO MUX Version Control Register + */ +typedef union { + struct { + /** reg_date : R/W; bitpos: [27:0]; default: 36708704; + * Version control register + */ + uint32_t reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} io_mux_date_reg_t; + + +typedef struct { + volatile io_mux_pin_ctrl_reg_t pin_ctrl; + volatile io_mux_gpion_reg_t gpion[27]; + uint32_t reserved_070[35]; + volatile io_mux_date_reg_t date; +} io_mux_dev_t; + +extern io_mux_dev_t IO_MUX; + +#ifndef __cplusplus +_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/keymng_reg.h b/components/soc/esp32c5/include/soc/keymng_reg.h new file mode 100644 index 0000000000..d75565dbc8 --- /dev/null +++ b/components/soc/esp32c5/include/soc/keymng_reg.h @@ -0,0 +1,337 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** KEYMNG_CLK_REG register + * Key Manager clock gate control register + */ +#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4) +/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ +#define KEYMNG_CLK_EN (BIT(0)) +#define KEYMNG_CLK_EN_M (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S) +#define KEYMNG_CLK_EN_V 0x00000001U +#define KEYMNG_CLK_EN_S 0 +/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ +#define KEYMNG_MEM_CG_FORCE_ON (BIT(1)) +#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S) +#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U +#define KEYMNG_MEM_CG_FORCE_ON_S 1 + +/** KEYMNG_INT_RAW_REG register + * Key Manager interrupt raw register, valid in level. + */ +#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8) +/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_RAW (BIT(0)) +#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S) +#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_RAW_S 0 +/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_RAW (BIT(1)) +#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S) +#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_RAW_S 1 +/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_RAW (BIT(2)) +#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S) +#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U +#define KEYMNG_POST_DONE_INT_RAW_S 2 + +/** KEYMNG_INT_ST_REG register + * Key Manager interrupt status register. + */ +#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc) +/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ST (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S) +#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ST_S 0 +/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ST (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S) +#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ST_S 1 +/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ST (BIT(2)) +#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S) +#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ST_S 2 + +/** KEYMNG_INT_ENA_REG register + * Key Manager interrupt enable register. + */ +#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10) +/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_ENA (BIT(0)) +#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S) +#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_ENA_S 0 +/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_ENA (BIT(1)) +#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S) +#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_ENA_S 1 +/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_ENA (BIT(2)) +#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S) +#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U +#define KEYMNG_POST_DONE_INT_ENA_S 2 + +/** KEYMNG_INT_CLR_REG register + * Key Manager interrupt clear register. + */ +#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14) +/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ +#define KEYMNG_PREP_DONE_INT_CLR (BIT(0)) +#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S) +#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PREP_DONE_INT_CLR_S 0 +/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ +#define KEYMNG_PROC_DONE_INT_CLR (BIT(1)) +#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S) +#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_PROC_DONE_INT_CLR_S 1 +/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ +#define KEYMNG_POST_DONE_INT_CLR (BIT(2)) +#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S) +#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U +#define KEYMNG_POST_DONE_INT_CLR_S 2 + +/** KEYMNG_STATIC_REG register + * Key Manager static configuration register + */ +#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18) +/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [1:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key + */ +#define KEYMNG_USE_EFUSE_KEY 0x00000003U +#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S) +#define KEYMNG_USE_EFUSE_KEY_V 0x00000003U +#define KEYMNG_USE_EFUSE_KEY_S 0 +/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ +#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S) +#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU +#define KEYMNG_RND_SWITCH_CYCLE_S 4 +/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY (BIT(9)) +#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S) +#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_S 9 +/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0; + * Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use + * xts-aes-128. + */ +#define KEYMNG_XTS_AES_KEY_LEN (BIT(10)) +#define KEYMNG_XTS_AES_KEY_LEN_M (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S) +#define KEYMNG_XTS_AES_KEY_LEN_V 0x00000001U +#define KEYMNG_XTS_AES_KEY_LEN_S 10 + +/** KEYMNG_LOCK_REG register + * Key Manager static configuration locker register + */ +#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c) +/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [1:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ +#define KEYMNG_USE_EFUSE_KEY_LOCK 0x00000003U +#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x00000003U +#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0 +/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ +#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(4)) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S) +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U +#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 4 +/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ +#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(5)) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S) +#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U +#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 5 +/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_xts_aes_key_len. + */ +#define KEYMNG_XTS_AES_KEY_LEN_LOCK (BIT(6)) +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S) +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V 0x00000001U +#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S 6 + +/** KEYMNG_CONF_REG register + * Key Manager configuration register + */ +#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20) +/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ +#define KEYMNG_KGEN_MODE 0x00000007U +#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S) +#define KEYMNG_KGEN_MODE_V 0x00000007U +#define KEYMNG_KGEN_MODE_S 0 +/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3: + * xts_256_2_key. 4. xts_128_key. others: reserved. + */ +#define KEYMNG_KEY_PURPOSE 0x0000000FU +#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S) +#define KEYMNG_KEY_PURPOSE_V 0x0000000FU +#define KEYMNG_KEY_PURPOSE_S 3 + +/** KEYMNG_START_REG register + * Key Manager control register + */ +#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24) +/** KEYMNG_START : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ +#define KEYMNG_START (BIT(0)) +#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S) +#define KEYMNG_START_V 0x00000001U +#define KEYMNG_START_S 0 +/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ +#define KEYMNG_CONTINUE (BIT(1)) +#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S) +#define KEYMNG_CONTINUE_V 0x00000001U +#define KEYMNG_CONTINUE_S 1 + +/** KEYMNG_STATE_REG register + * Key Manager state register + */ +#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28) +/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ +#define KEYMNG_STATE 0x00000003U +#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S) +#define KEYMNG_STATE_V 0x00000003U +#define KEYMNG_STATE_S 0 + +/** KEYMNG_RESULT_REG register + * Key Manager operation result register + */ +#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c) +/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ +#define KEYMNG_PROC_RESULT (BIT(0)) +#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S) +#define KEYMNG_PROC_RESULT_V 0x00000001U +#define KEYMNG_PROC_RESULT_S 0 + +/** KEYMNG_KEY_VLD_REG register + * Key Manager key status register + */ +#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30) +/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_VLD (BIT(0)) +#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S) +#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_VLD_S 0 +/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0; + * The status bit for key_xts. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_XTS_VLD (BIT(1)) +#define KEYMNG_KEY_XTS_VLD_M (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S) +#define KEYMNG_KEY_XTS_VLD_V 0x00000001U +#define KEYMNG_KEY_XTS_VLD_S 1 + +/** KEYMNG_HUK_VLD_REG register + * Key Manager HUK status register + */ +#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34) +/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ +#define KEYMNG_HUK_VALID (BIT(0)) +#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S) +#define KEYMNG_HUK_VALID_V 0x00000001U +#define KEYMNG_HUK_VALID_S 0 + +/** KEYMNG_DATE_REG register + * Version control register + */ +#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc) +/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704; + * Key Manager version control register. + */ +#define KEYMNG_DATE 0x0FFFFFFFU +#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S) +#define KEYMNG_DATE_V 0x0FFFFFFFU +#define KEYMNG_DATE_S 0 + +/** KEYMNG_ASSIST_INFO_MEM register + * The memory that stores assist key info. + */ +#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100) +#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_PUBLIC_INFO_MEM register + * The memory that stores public key info. + */ +#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140) +#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64 + +/** KEYMNG_SW_INIT_KEY_MEM register + * The memory that stores software written init key. + */ +#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180) +#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/keymng_struct.h b/components/soc/esp32c5/include/soc/keymng_struct.h new file mode 100644 index 0000000000..13b13d1fc3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/keymng_struct.h @@ -0,0 +1,339 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Clock gate register */ +/** Type of clk register + * Key Manager clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Write 1 to force on register clock gate. + */ + uint32_t clk_en:1; + /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; + * Write 1 to force on memory clock gate. + */ + uint32_t mem_cg_force_on:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Key Manager interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_raw_reg_t; + +/** Type of int_st register + * Key Manager interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_st_reg_t; + +/** Type of int_ena register + * Key Manager interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the km_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the km_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the km_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_ena_reg_t; + +/** Type of int_clr register + * Key Manager interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the km_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the km_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the km_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} keymng_int_clr_reg_t; + + +/** Group: Static configuration registers */ +/** Type of static register + * Key Manager static configuration register + */ +typedef union { + struct { + /** use_efuse_key : R/W; bitpos: [1:0]; default: 0; + * Set each bit to choose efuse key instead of key manager deployed key. Each bit + * stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key + */ + uint32_t use_efuse_key:2; + uint32_t reserved_2:2; + /** rnd_switch_cycle : R/W; bitpos: [8:4]; default: 15; + * The core clock cycle number to sample one rng input data. Please set it bigger than + * the clock cycle ratio: T_rng/T_km + */ + uint32_t rnd_switch_cycle:5; + /** use_sw_init_key : R/W; bitpos: [9]; default: 0; + * Set this bit to use software written init key instead of efuse_init_key. + */ + uint32_t use_sw_init_key:1; + /** xts_aes_key_len : R/W; bitpos: [10]; default: 0; + * Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use + * xts-aes-128. + */ + uint32_t xts_aes_key_len:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} keymng_static_reg_t; + +/** Type of lock register + * Key Manager static configuration locker register + */ +typedef union { + struct { + /** use_efuse_key_lock : R/W1; bitpos: [1:0]; default: 0; + * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of + * reg_use_efuse_key. + */ + uint32_t use_efuse_key_lock:2; + uint32_t reserved_2:2; + /** rnd_switch_cycle_lock : R/W1; bitpos: [4]; default: 0; + * Write 1 to lock reg_rnd_switch_cycle. + */ + uint32_t rnd_switch_cycle_lock:1; + /** use_sw_init_key_lock : R/W1; bitpos: [5]; default: 0; + * Write 1 to lock reg_use_sw_init_key. + */ + uint32_t use_sw_init_key_lock:1; + /** xts_aes_key_len_lock : R/W1; bitpos: [6]; default: 0; + * Write 1 to lock reg_xts_aes_key_len. + */ + uint32_t xts_aes_key_len_lock:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_lock_reg_t; + + +/** Group: Configuration registers */ +/** Type of conf register + * Key Manager configuration register + */ +typedef union { + struct { + /** kgen_mode : R/W; bitpos: [2:0]; default: 0; + * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES + * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. + */ + uint32_t kgen_mode:3; + /** key_purpose : R/W; bitpos: [6:3]; default: 0; + * Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3: + * xts_256_2_key. 4. xts_128_key. others: reserved. + */ + uint32_t key_purpose:4; + uint32_t reserved_7:25; + }; + uint32_t val; +} keymng_conf_reg_t; + + +/** Group: Control registers */ +/** Type of start register + * Key Manager control register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to continue Key Manager operation at LOAD/GAIN state. + */ + uint32_t start:1; + /** continue : WT; bitpos: [1]; default: 0; + * Write 1 to start Key Manager at IDLE state. + */ + uint32_t continue:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_start_reg_t; + + +/** Group: State registers */ +/** Type of state register + * Key Manager state register + */ +typedef union { + struct { + /** state : RO; bitpos: [1:0]; default: 0; + * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + */ + uint32_t state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * Key Manager operation result register + */ +typedef union { + struct { + /** proc_result : RO/SS; bitpos: [0]; default: 0; + * The procedure result bit of Key Manager, only valid when Key Manager procedure is + * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. + */ + uint32_t proc_result:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_result_reg_t; + +/** Type of key_vld register + * Key Manager key status register + */ +typedef union { + struct { + /** key_ecdsa_vld : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key + * has not been deployed yet. + */ + uint32_t key_ecdsa_vld:1; + /** key_xts_vld : RO; bitpos: [1]; default: 0; + * The status bit for key_xts. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_xts_vld:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} keymng_key_vld_reg_t; + +/** Type of huk_vld register + * Key Manager HUK status register + */ +typedef union { + struct { + /** huk_valid : RO; bitpos: [0]; default: 0; + * The HUK status. 0: HUK is not valid. 1: HUK is valid. + */ + uint32_t huk_valid:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} keymng_huk_vld_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720704; + * Key Manager version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} keymng_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile keymng_clk_reg_t clk; + volatile keymng_int_raw_reg_t int_raw; + volatile keymng_int_st_reg_t int_st; + volatile keymng_int_ena_reg_t int_ena; + volatile keymng_int_clr_reg_t int_clr; + volatile keymng_static_reg_t static; + volatile keymng_lock_reg_t lock; + volatile keymng_conf_reg_t conf; + volatile keymng_start_reg_t start; + volatile keymng_state_reg_t state; + volatile keymng_result_reg_t result; + volatile keymng_key_vld_reg_t key_vld; + volatile keymng_huk_vld_reg_t huk_vld; + uint32_t reserved_038[49]; + volatile keymng_date_reg_t date; + volatile uint32_t assist_info[16]; + volatile uint32_t public_info[16]; + volatile uint32_t sw_init_key[8]; +} keymng_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ledc_reg.h b/components/soc/esp32c5/include/soc/ledc_reg.h new file mode 100644 index 0000000000..6f13034d72 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ledc_reg.h @@ -0,0 +1,2334 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) +/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH0 0x00000003U +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003U +#define LEDC_TIMER_SEL_CH0_S 0 +/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 0.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH0_S 2 +/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 0 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001U +#define LEDC_IDLE_LV_CH0_S 3 +/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0, + * LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0, + * LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel + * 0, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001U +#define LEDC_PARA_UP_CH0_S 4 +/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt + * will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times. + */ +#define LEDC_OVF_NUM_CH0 0x000003FFU +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FFU +#define LEDC_OVF_NUM_CH0_S 5 +/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH0_S 15 +/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 0.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/** LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) +/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 0. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH0 0x000FFFFFU +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x000FFFFFU +#define LEDC_HPOINT_CH0_S 0 + +/** LEDC_CH0_DUTY_REG register + * Initial duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) +/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 0. + */ +#define LEDC_DUTY_CH0 0x01FFFFFFU +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_S 0 + +/** LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) +/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001U +#define LEDC_DUTY_START_CH0_S 31 + +/** LEDC_CH0_DUTY_R_REG register + * Current duty cycle register for channel 0 + */ +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) +/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 0. + */ +#define LEDC_DUTY_CH0_R 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) +#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH0_R_S 0 + +/** LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) +/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH1 0x00000003U +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003U +#define LEDC_TIMER_SEL_CH1_S 0 +/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 1.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH1_S 2 +/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 1 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001U +#define LEDC_IDLE_LV_CH1_S 3 +/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, + * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, + * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel + * 1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001U +#define LEDC_PARA_UP_CH1_S 4 +/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt + * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. + */ +#define LEDC_OVF_NUM_CH1 0x000003FFU +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FFU +#define LEDC_OVF_NUM_CH1_S 5 +/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH1_S 15 +/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 1.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/** LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) +/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 1. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH1 0x000FFFFFU +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x000FFFFFU +#define LEDC_HPOINT_CH1_S 0 + +/** LEDC_CH1_DUTY_REG register + * Initial duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) +/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 1. + */ +#define LEDC_DUTY_CH1 0x01FFFFFFU +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_S 0 + +/** LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) +/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001U +#define LEDC_DUTY_START_CH1_S 31 + +/** LEDC_CH1_DUTY_R_REG register + * Current duty cycle register for channel 1 + */ +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) +/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 1. + */ +#define LEDC_DUTY_CH1_R 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) +#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_S 0 + +/** LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) +/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH2 0x00000003U +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003U +#define LEDC_TIMER_SEL_CH2_S 0 +/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 2.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH2_S 2 +/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 2 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001U +#define LEDC_IDLE_LV_CH2_S 3 +/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, + * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, + * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel + * 2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001U +#define LEDC_PARA_UP_CH2_S 4 +/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt + * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. + */ +#define LEDC_OVF_NUM_CH2 0x000003FFU +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FFU +#define LEDC_OVF_NUM_CH2_S 5 +/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH2_S 15 +/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 2.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/** LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) +/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 2. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH2 0x000FFFFFU +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x000FFFFFU +#define LEDC_HPOINT_CH2_S 0 + +/** LEDC_CH2_DUTY_REG register + * Initial duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) +/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 2. + */ +#define LEDC_DUTY_CH2 0x01FFFFFFU +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_S 0 + +/** LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) +/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001U +#define LEDC_DUTY_START_CH2_S 31 + +/** LEDC_CH2_DUTY_R_REG register + * Current duty cycle register for channel 2 + */ +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) +/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 2. + */ +#define LEDC_DUTY_CH2_R 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) +#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_S 0 + +/** LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) +/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH3 0x00000003U +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003U +#define LEDC_TIMER_SEL_CH3_S 0 +/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 3.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH3_S 2 +/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 3 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001U +#define LEDC_IDLE_LV_CH3_S 3 +/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, + * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, + * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel + * 3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001U +#define LEDC_PARA_UP_CH3_S 4 +/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt + * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. + */ +#define LEDC_OVF_NUM_CH3 0x000003FFU +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FFU +#define LEDC_OVF_NUM_CH3_S 5 +/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH3_S 15 +/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 3.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/** LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) +/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 3. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH3 0x000FFFFFU +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x000FFFFFU +#define LEDC_HPOINT_CH3_S 0 + +/** LEDC_CH3_DUTY_REG register + * Initial duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) +/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 3. + */ +#define LEDC_DUTY_CH3 0x01FFFFFFU +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_S 0 + +/** LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) +/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001U +#define LEDC_DUTY_START_CH3_S 31 + +/** LEDC_CH3_DUTY_R_REG register + * Current duty cycle register for channel 3 + */ +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) +/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 3. + */ +#define LEDC_DUTY_CH3_R 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) +#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_S 0 + +/** LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) +/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH4 0x00000003U +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003U +#define LEDC_TIMER_SEL_CH4_S 0 +/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 4.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH4_S 2 +/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 4 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001U +#define LEDC_IDLE_LV_CH4_S 3 +/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, + * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, + * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel + * 4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001U +#define LEDC_PARA_UP_CH4_S 4 +/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt + * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. + */ +#define LEDC_OVF_NUM_CH4 0x000003FFU +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FFU +#define LEDC_OVF_NUM_CH4_S 5 +/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH4_S 15 +/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 4.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/** LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) +/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 4. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH4 0x000FFFFFU +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x000FFFFFU +#define LEDC_HPOINT_CH4_S 0 + +/** LEDC_CH4_DUTY_REG register + * Initial duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) +/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 4. + */ +#define LEDC_DUTY_CH4 0x01FFFFFFU +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_S 0 + +/** LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) +/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001U +#define LEDC_DUTY_START_CH4_S 31 + +/** LEDC_CH4_DUTY_R_REG register + * Current duty cycle register for channel 4 + */ +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) +/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 4. + */ +#define LEDC_DUTY_CH4_R 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) +#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_S 0 + +/** LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) +/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ +#define LEDC_TIMER_SEL_CH5 0x00000003U +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003U +#define LEDC_TIMER_SEL_CH5_S 0 +/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel 5.\\0: Signal output + * disable\\1: Signal output enable + */ +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH5_S 2 +/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel 5 is inactive. Valid only when + * LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high + */ +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001U +#define LEDC_IDLE_LV_CH5_S 3 +/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, + * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, + * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel + * 5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001U +#define LEDC_PARA_UP_CH5_S 4 +/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt + * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. + */ +#define LEDC_OVF_NUM_CH5 0x000003FFU +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FFU +#define LEDC_OVF_NUM_CH5_S 5 +/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable + */ +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH5_S 15 +/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel 5.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/** LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) +/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel 5. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ +#define LEDC_HPOINT_CH5 0x000FFFFFU +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x000FFFFFU +#define LEDC_HPOINT_CH5_S 0 + +/** LEDC_CH5_DUTY_REG register + * Initial duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) +/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel 5. + */ +#define LEDC_DUTY_CH5 0x01FFFFFFU +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_S 0 + +/** LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) +/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001U +#define LEDC_DUTY_START_CH5_S 31 + +/** LEDC_CH5_DUTY_R_REG register + * Current duty cycle register for channel 5 + */ +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) +/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel 5. + */ +#define LEDC_DUTY_CH5_R 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) +#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_S 0 + +/** LEDC_TIMER0_CONF_REG register + * Timer 0 configuration register + */ +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) +/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 0. + */ +#define LEDC_TIMER0_DUTY_RES 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER0_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 0.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER0_S 5 +/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER0_PAUSE (BIT(23)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001U +#define LEDC_TIMER0_PAUSE_S 23 +/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 0. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER0_RST (BIT(24)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001U +#define LEDC_TIMER0_RST_S 24 +/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER0 and + * LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER0_PARA_UP (BIT(26)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001U +#define LEDC_TIMER0_PARA_UP_S 26 + +/** LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value register + */ +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) +/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 0. + */ +#define LEDC_TIMER0_CNT 0x000FFFFFU +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_S 0 + +/** LEDC_TIMER1_CONF_REG register + * Timer 1 configuration register + */ +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) +/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 1. + */ +#define LEDC_TIMER1_DUTY_RES 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 1.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_S 5 +/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER1_PAUSE (BIT(23)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001U +#define LEDC_TIMER1_PAUSE_S 23 +/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 1. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER1_RST (BIT(24)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001U +#define LEDC_TIMER1_RST_S 24 +/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and + * LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER1_PARA_UP (BIT(26)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001U +#define LEDC_TIMER1_PARA_UP_S 26 + +/** LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value register + */ +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) +/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 1. + */ +#define LEDC_TIMER1_CNT 0x000FFFFFU +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_S 0 + +/** LEDC_TIMER2_CONF_REG register + * Timer 2 configuration register + */ +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) +/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 2. + */ +#define LEDC_TIMER2_DUTY_RES 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 2.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_S 5 +/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER2_PAUSE (BIT(23)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001U +#define LEDC_TIMER2_PAUSE_S 23 +/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 2. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER2_RST (BIT(24)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001U +#define LEDC_TIMER2_RST_S 24 +/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and + * LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER2_PARA_UP (BIT(26)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001U +#define LEDC_TIMER2_PARA_UP_S 26 + +/** LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value register + */ +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) +/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 2. + */ +#define LEDC_TIMER2_CNT 0x000FFFFFU +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_S 0 + +/** LEDC_TIMER3_CONF_REG register + * Timer 3 configuration register + */ +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) +/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer 3. + */ +#define LEDC_TIMER3_DUTY_RES 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer 3.The least significant eight bits + * represent the fractional part. + */ +#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_S 5 +/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause + */ +#define LEDC_TIMER3_PAUSE (BIT(23)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001U +#define LEDC_TIMER3_PAUSE_S 23 +/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer 3. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ +#define LEDC_TIMER3_RST (BIT(24)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001U +#define LEDC_TIMER3_RST_S 24 +/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and + * LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ +#define LEDC_TIMER3_PARA_UP (BIT(26)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001U +#define LEDC_TIMER3_PARA_UP_S 26 + +/** LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value register + */ +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) +/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer 3. + */ +#define LEDC_TIMER3_CNT 0x000FFFFFU +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_S 0 + +/** LEDC_INT_RAW_REG register + * Interrupt raw status register + */ +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) +/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_RAW_S 0 +/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_RAW_S 1 +/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_RAW_S 2 +/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_RAW_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 +/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 +/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 +/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 +/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 +/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 +/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 + +/** LEDC_INT_ST_REG register + * Interrupt masked status register + */ +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) +/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ST_S 0 +/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ST_S 1 +/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ST_S 2 +/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ST_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 +/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 +/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 +/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 +/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 +/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 +/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 + +/** LEDC_INT_ENA_REG register + * Interrupt enable register + */ +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) +/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_ENA_S 0 +/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_ENA_S 1 +/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_ENA_S 2 +/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_ENA_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 +/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 +/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 +/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 +/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 +/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 +/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 + +/** LEDC_INT_CLR_REG register + * Interrupt clear register + */ +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) +/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER0_OVF_INT_CLR_S 0 +/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER1_OVF_INT_CLR_S 1 +/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER2_OVF_INT_CLR_S 2 +/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001U +#define LEDC_TIMER3_OVF_INT_CLR_S 3 +/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 +/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 +/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 +/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 +/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 +/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001U +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 +/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 +/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 +/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 +/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 +/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 +/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001U +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 + +/** LEDC_CH0_GAMMA_CONF_REG register + * Ledc ch0 gamma config register. + */ +#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100) +/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch0. + */ +#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) +#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) +#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH0_GAMMA_PAUSE_S 5 +/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH0_GAMMA_RESUME (BIT(6)) +#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) +#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH0_GAMMA_RESUME_S 6 + +/** LEDC_CH1_GAMMA_CONF_REG register + * Ledc ch1 gamma config register. + */ +#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) +/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch1. + */ +#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) +#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) +#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH1_GAMMA_PAUSE_S 5 +/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH1_GAMMA_RESUME (BIT(6)) +#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) +#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH1_GAMMA_RESUME_S 6 + +/** LEDC_CH2_GAMMA_CONF_REG register + * Ledc ch2 gamma config register. + */ +#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) +/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch2. + */ +#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) +#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) +#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH2_GAMMA_PAUSE_S 5 +/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH2_GAMMA_RESUME (BIT(6)) +#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) +#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH2_GAMMA_RESUME_S 6 + +/** LEDC_CH3_GAMMA_CONF_REG register + * Ledc ch3 gamma config register. + */ +#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) +/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch3. + */ +#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) +#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) +#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH3_GAMMA_PAUSE_S 5 +/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH3_GAMMA_RESUME (BIT(6)) +#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) +#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH3_GAMMA_RESUME_S 6 + +/** LEDC_CH4_GAMMA_CONF_REG register + * Ledc ch4 gamma config register. + */ +#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) +/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch4. + */ +#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) +#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) +#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH4_GAMMA_PAUSE_S 5 +/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH4_GAMMA_RESUME (BIT(6)) +#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) +#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH4_GAMMA_RESUME_S 6 + +/** LEDC_CH5_GAMMA_CONF_REG register + * Ledc ch5 gamma config register. + */ +#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) +/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC ch5. + */ +#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) +#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No + * effect\\1: Pause + */ +#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) +#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH5_GAMMA_PAUSE_S 5 +/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No + * effect\\1: Resume + */ +#define LEDC_CH5_GAMMA_RESUME (BIT(6)) +#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) +#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH5_GAMMA_RESUME_S 6 + +/** LEDC_EVT_TASK_EN0_REG register + * Ledc event task enable bit register0. + */ +#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120) +/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN (BIT(0)) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S 0 +/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN (BIT(1)) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S 1 +/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN (BIT(2)) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S 2 +/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN (BIT(3)) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S 3 +/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN (BIT(4)) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S 4 +/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: + * Disable\\1: Enable + */ +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN (BIT(5)) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S) +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V 0x00000001U +#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S 5 +/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN (BIT(8)) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S 8 +/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN (BIT(9)) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S 9 +/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN (BIT(10)) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S 10 +/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN (BIT(11)) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S 11 +/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN (BIT(12)) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S 12 +/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN (BIT(13)) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S) +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V 0x00000001U +#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S 13 +/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER0_EN (BIT(16)) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_M (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER0_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER0_EN_S 16 +/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER1_EN (BIT(17)) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_M (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER1_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER1_EN_S 17 +/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER2_EN (BIT(18)) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_M (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER2_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER2_EN_S 18 +/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME_OVF_TIMER3_EN (BIT(19)) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_M (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S) +#define LEDC_EVT_TIME_OVF_TIMER3_EN_V 0x00000001U +#define LEDC_EVT_TIME_OVF_TIMER3_EN_S 19 +/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME0_CMP_EN (BIT(20)) +#define LEDC_EVT_TIME0_CMP_EN_M (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S) +#define LEDC_EVT_TIME0_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME0_CMP_EN_S 20 +/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME1_CMP_EN (BIT(21)) +#define LEDC_EVT_TIME1_CMP_EN_M (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S) +#define LEDC_EVT_TIME1_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME1_CMP_EN_S 21 +/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME2_CMP_EN (BIT(22)) +#define LEDC_EVT_TIME2_CMP_EN_M (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S) +#define LEDC_EVT_TIME2_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME2_CMP_EN_S 22 +/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: + * Enable + */ +#define LEDC_EVT_TIME3_CMP_EN (BIT(23)) +#define LEDC_EVT_TIME3_CMP_EN_M (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S) +#define LEDC_EVT_TIME3_CMP_EN_V 0x00000001U +#define LEDC_EVT_TIME3_CMP_EN_S 23 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN (BIT(24)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S 24 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN (BIT(25)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S 25 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN (BIT(26)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S 26 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN (BIT(27)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S 27 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN (BIT(28)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S 28 +/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: + * Disable\\1: Enable + */ +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN (BIT(29)) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S) +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V 0x00000001U +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S 29 + +/** LEDC_EVT_TASK_EN1_REG register + * Ledc event task enable bit register1. + */ +#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124) +/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER0_RES_UPDATE_EN (BIT(0)) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S 0 +/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER1_RES_UPDATE_EN (BIT(1)) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S 1 +/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER2_RES_UPDATE_EN (BIT(2)) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S 2 +/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER3_RES_UPDATE_EN (BIT(3)) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S) +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S 3 +/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER0_CAP_EN (BIT(4)) +#define LEDC_TASK_TIMER0_CAP_EN_M (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S) +#define LEDC_TASK_TIMER0_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_CAP_EN_S 4 +/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER1_CAP_EN (BIT(5)) +#define LEDC_TASK_TIMER1_CAP_EN_M (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S) +#define LEDC_TASK_TIMER1_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_CAP_EN_S 5 +/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER2_CAP_EN (BIT(6)) +#define LEDC_TASK_TIMER2_CAP_EN_M (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S) +#define LEDC_TASK_TIMER2_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_CAP_EN_S 6 +/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER3_CAP_EN (BIT(7)) +#define LEDC_TASK_TIMER3_CAP_EN_M (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S) +#define LEDC_TASK_TIMER3_CAP_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_CAP_EN_S 7 +/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN (BIT(8)) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S 8 +/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN (BIT(9)) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S 9 +/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN (BIT(10)) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S 10 +/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN (BIT(11)) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S 11 +/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN (BIT(12)) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S 12 +/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN (BIT(13)) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S) +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V 0x00000001U +#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S 13 +/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH0_EN (BIT(16)) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S 16 +/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH1_EN (BIT(17)) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S 17 +/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH2_EN (BIT(18)) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S 18 +/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH3_EN (BIT(19)) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S 19 +/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH4_EN (BIT(20)) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S 20 +/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_OVF_CNT_RST_CH5_EN (BIT(21)) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S) +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V 0x00000001U +#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S 21 +/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER0_RST_EN (BIT(24)) +#define LEDC_TASK_TIMER0_RST_EN_M (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S) +#define LEDC_TASK_TIMER0_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_RST_EN_S 24 +/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER1_RST_EN (BIT(25)) +#define LEDC_TASK_TIMER1_RST_EN_M (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S) +#define LEDC_TASK_TIMER1_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_RST_EN_S 25 +/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER2_RST_EN (BIT(26)) +#define LEDC_TASK_TIMER2_RST_EN_M (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S) +#define LEDC_TASK_TIMER2_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_RST_EN_S 26 +/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + */ +#define LEDC_TASK_TIMER3_RST_EN (BIT(27)) +#define LEDC_TASK_TIMER3_RST_EN_M (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S) +#define LEDC_TASK_TIMER3_RST_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_RST_EN_S 27 +/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN (BIT(28)) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S 28 +/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN (BIT(29)) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S 29 +/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN (BIT(30)) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S 30 +/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN (BIT(31)) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S) +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V 0x00000001U +#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S 31 + +/** LEDC_EVT_TASK_EN2_REG register + * Ledc event task enable bit register2. + */ +#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128) +/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH0_EN (BIT(0)) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S 0 +/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH1_EN (BIT(1)) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S 1 +/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH2_EN (BIT(2)) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S 2 +/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH3_EN (BIT(3)) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S 3 +/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH4_EN (BIT(4)) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S 4 +/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESTART_CH5_EN (BIT(5)) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S 5 +/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN (BIT(8)) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S 8 +/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN (BIT(9)) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S 9 +/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN (BIT(10)) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S 10 +/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN (BIT(11)) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S 11 +/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN (BIT(12)) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S 12 +/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN (BIT(13)) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S) +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S 13 +/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH0_EN (BIT(16)) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S 16 +/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH1_EN (BIT(17)) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S 17 +/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH2_EN (BIT(18)) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S 18 +/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH3_EN (BIT(19)) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S 19 +/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH4_EN (BIT(20)) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S 20 +/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: + * Enable + */ +#define LEDC_TASK_GAMMA_RESUME_CH5_EN (BIT(21)) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S) +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V 0x00000001U +#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S 21 + +/** LEDC_TIMER0_CMP_REG register + * Ledc timer0 compare value register. + */ +#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140) +/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer0. + */ +#define LEDC_TIMER0_CMP 0x000FFFFFU +#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) +#define LEDC_TIMER0_CMP_V 0x000FFFFFU +#define LEDC_TIMER0_CMP_S 0 + +/** LEDC_TIMER1_CMP_REG register + * Ledc timer1 compare value register. + */ +#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) +/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer1. + */ +#define LEDC_TIMER1_CMP 0x000FFFFFU +#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) +#define LEDC_TIMER1_CMP_V 0x000FFFFFU +#define LEDC_TIMER1_CMP_S 0 + +/** LEDC_TIMER2_CMP_REG register + * Ledc timer2 compare value register. + */ +#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) +/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer2. + */ +#define LEDC_TIMER2_CMP 0x000FFFFFU +#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) +#define LEDC_TIMER2_CMP_V 0x000FFFFFU +#define LEDC_TIMER2_CMP_S 0 + +/** LEDC_TIMER3_CMP_REG register + * Ledc timer3 compare value register. + */ +#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) +/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timer3. + */ +#define LEDC_TIMER3_CMP 0x000FFFFFU +#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) +#define LEDC_TIMER3_CMP_V 0x000FFFFFU +#define LEDC_TIMER3_CMP_S 0 + +/** LEDC_TIMER0_CNT_CAP_REG register + * Ledc timer0 captured count value register. + */ +#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150) +/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer0 count value. + */ +#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) +#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER0_CNT_CAP_S 0 + +/** LEDC_TIMER1_CNT_CAP_REG register + * Ledc timer1 captured count value register. + */ +#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) +/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer1 count value. + */ +#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) +#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_S 0 + +/** LEDC_TIMER2_CNT_CAP_REG register + * Ledc timer2 captured count value register. + */ +#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) +/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer2 count value. + */ +#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) +#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_S 0 + +/** LEDC_TIMER3_CNT_CAP_REG register + * Ledc timer3 captured count value register. + */ +#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) +/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timer3 count value. + */ +#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) +#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_S 0 + +/** LEDC_CONF_REG register + * LEDC global configuration register + */ +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170) +/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the + * clock gate for LEDC ch0 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH0 (BIT(2)) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_M (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH0_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH0_S 2 +/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the + * clock gate for LEDC ch1 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH1 (BIT(3)) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_M (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH1_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH1_S 3 +/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the + * clock gate for LEDC ch2 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH2 (BIT(4)) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_M (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH2_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH2_S 4 +/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the + * clock gate for LEDC ch3 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH3 (BIT(5)) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_M (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH3_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH3_S 5 +/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the + * clock gate for LEDC ch4 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH4 (BIT(6)) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_M (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH4_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH4_S 6 +/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the + * clock gate for LEDC ch5 gamma ram + */ +#define LEDC_GAMMA_RAM_CLK_EN_CH5 (BIT(7)) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_M (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S) +#define LEDC_GAMMA_RAM_CLK_EN_CH5_V 0x00000001U +#define LEDC_GAMMA_RAM_CLK_EN_CH5_S 7 +/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001U +#define LEDC_CLK_EN_S 31 + +/** LEDC_DATE_REG register + * Version control register + */ +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174) +/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 36716928; + * Configures the version. + */ +#define LEDC_LEDC_DATE 0x0FFFFFFFU +#define LEDC_LEDC_DATE_M (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S) +#define LEDC_LEDC_DATE_V 0x0FFFFFFFU +#define LEDC_LEDC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/ledc_struct.h b/components/soc/esp32c5/include/soc/ledc_struct.h new file mode 100644 index 0000000000..23c38c2eeb --- /dev/null +++ b/components/soc/esp32c5/include/soc/ledc_struct.h @@ -0,0 +1,1084 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of chn_conf0 register + * Configuration register 0 for channel n + */ +typedef union { + struct { + /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0; + * Configures which timer is channel n selected.\\0: Select timer0\\1: Select + * timer1\\2: Select timer2\\3: Select timer3 + */ + uint32_t timer_sel_chn:2; + /** sig_out_en_chn : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable signal output on channel n.\\0: Signal output + * disable\\1: Signal output enable + */ + uint32_t sig_out_en_chn:1; + /** idle_lv_chn : R/W; bitpos: [3]; default: 0; + * Configures the output value when channel n is inactive. Valid only when + * LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high + */ + uint32_t idle_lv_chn:1; + /** para_up_chn : WT; bitpos: [4]; default: 0; + * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, + * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, + * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel + * n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + */ + uint32_t para_up_chn:1; + /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0; + * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt + * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. + */ + uint32_t ovf_num_chn:10; + /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable + */ + uint32_t ovf_cnt_en_chn:1; + /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0; + * Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No + * effect\\1: Reset the ovf_cnt + */ + uint32_t ovf_cnt_reset_chn:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} ledc_chn_conf0_reg_t; + +/** Type of chn_hpoint register + * High point register for channel n + */ +typedef union { + struct { + /** hpoint_chn : R/W; bitpos: [19:0]; default: 0; + * Configures high point of signal output on channel n. The output value changes to + * high when the selected timers has reached the value specified by this register. + */ + uint32_t hpoint_chn:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_chn_hpoint_reg_t; + +/** Type of chn_duty register + * Initial duty cycle register for channel n + */ +typedef union { + struct { + /** duty_chn : R/W; bitpos: [24:0]; default: 0; + * Configures the duty of signal output on channel n. + */ + uint32_t duty_chn:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_reg_t; + +/** Type of chn_conf1 register + * Configuration register 1 for channel n + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0; + * Configures whether the duty cycle fading configurations take effect.\\0: Not take + * effect\\1: Take effect + */ + uint32_t duty_start_chn:1; + }; + uint32_t val; +} ledc_chn_conf1_reg_t; + +/** Type of chn_duty_r register + * Current duty cycle register for channel n + */ +typedef union { + struct { + /** duty_chn_r : RO; bitpos: [24:0]; default: 0; + * Represents the current duty of output signal on channel n. + */ + uint32_t duty_chn_r:25; + uint32_t reserved_25:7; + }; + uint32_t val; +} ledc_chn_duty_r_reg_t; + + +/** Group: timer conf */ +/** Type of timern_conf register + * Timer n configuration register + */ +typedef union { + struct { + /** timern_duty_res : R/W; bitpos: [4:0]; default: 0; + * Configures the range of the counter in timer n. + */ + uint32_t timern_duty_res:5; + /** clk_div_timern : R/W; bitpos: [22:5]; default: 0; + * Configures the divisor for the divider in timer n.The least significant eight bits + * represent the fractional part. + */ + uint32_t clk_div_timern:18; + /** timern_pause : R/W; bitpos: [23]; default: 0; + * Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause + */ + uint32_t timern_pause:1; + /** timern_rst : R/W; bitpos: [24]; default: 1; + * Configures whether or not to reset timer n. The counter will show 0 after + * reset.\\0: Not reset\\1: Reset + */ + uint32_t timern_rst:1; + uint32_t reserved_25:1; + /** timern_para_up : WT; bitpos: [26]; default: 0; + * Configures whether or not to update LEDC_CLK_DIV_TIMERn and + * LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update + */ + uint32_t timern_para_up:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ledc_timern_conf_reg_t; + +/** Type of timern_value register + * Timer n current counter value register + */ +typedef union { + struct { + /** timern_cnt : RO; bitpos: [19:0]; default: 0; + * Represents the current counter value of timer n. + */ + uint32_t timern_cnt:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_value_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the + * timer0 has reached its maximum counter value. + */ + uint32_t timer0_ovf_int_raw:1; + /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the + * timer1 has reached its maximum counter value. + */ + uint32_t timer1_ovf_int_raw:1; + /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the + * timer2 has reached its maximum counter value. + */ + uint32_t timer2_ovf_int_raw:1; + /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the + * timer3 has reached its maximum counter value. + */ + uint32_t timer3_ovf_int_raw:1; + /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch0_int_raw:1; + /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch1_int_raw:1; + /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch2_int_raw:1; + /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch3_int_raw:1; + /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch4_int_raw:1; + /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered + * when the fading of duty has finished. + */ + uint32_t duty_chng_end_ch5_int_raw:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + */ + uint32_t ovf_cnt_ch0_int_raw:1; + /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + */ + uint32_t ovf_cnt_ch1_int_raw:1; + /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + */ + uint32_t ovf_cnt_ch2_int_raw:1; + /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + */ + uint32_t ovf_cnt_ch3_int_raw:1; + /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + */ + uint32_t ovf_cnt_ch4_int_raw:1; + /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when + * the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + */ + uint32_t ovf_cnt_ch5_int_raw:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_raw_reg_t; + +/** Type of int_st register + * Interrupt masked status register + */ +typedef union { + struct { + /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only + * when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + uint32_t timer0_ovf_int_st:1; + /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only + * when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + uint32_t timer1_ovf_int_st:1; + /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only + * when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + uint32_t timer2_ovf_int_st:1; + /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only + * when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + uint32_t timer3_ovf_int_st:1; + /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch0_int_st:1; + /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch1_int_st:1; + /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch2_int_st:1; + /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch3_int_st:1; + /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch4_int_st:1; + /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid + * only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + */ + uint32_t duty_chng_end_ch5_int_st:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only + * when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch0_int_st:1; + /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only + * when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch1_int_st:1; + /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only + * when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch2_int_st:1; + /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only + * when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch3_int_st:1; + /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only + * when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch4_int_st:1; + /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0; + * Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only + * when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + uint32_t ovf_cnt_ch5_int_st:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_ena:1; + /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_ena:1; + /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_ena:1; + /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0; + * Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_ena:1; + /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_ena:1; + /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_ena:1; + /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_ena:1; + /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_ena:1; + /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_ena:1; + /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0; + * Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_ena:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_ena:1; + /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_ena:1; + /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_ena:1; + /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_ena:1; + /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_ena:1; + /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0; + * Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_ena:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + */ + uint32_t timer0_ovf_int_clr:1; + /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + */ + uint32_t timer1_ovf_int_clr:1; + /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + */ + uint32_t timer2_ovf_int_clr:1; + /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0; + * Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + */ + uint32_t timer3_ovf_int_clr:1; + /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + */ + uint32_t duty_chng_end_ch0_int_clr:1; + /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + */ + uint32_t duty_chng_end_ch1_int_clr:1; + /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + */ + uint32_t duty_chng_end_ch2_int_clr:1; + /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + */ + uint32_t duty_chng_end_ch3_int_clr:1; + /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + */ + uint32_t duty_chng_end_ch4_int_clr:1; + /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0; + * Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + */ + uint32_t duty_chng_end_ch5_int_clr:1; + uint32_t reserved_10:2; + /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + */ + uint32_t ovf_cnt_ch0_int_clr:1; + /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + */ + uint32_t ovf_cnt_ch1_int_clr:1; + /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + */ + uint32_t ovf_cnt_ch2_int_clr:1; + /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + */ + uint32_t ovf_cnt_ch3_int_clr:1; + /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + */ + uint32_t ovf_cnt_ch4_int_clr:1; + /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0; + * Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + */ + uint32_t ovf_cnt_ch5_int_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} ledc_int_clr_reg_t; + + +/** Group: gamma */ +/** Type of chn_gamma_conf register + * Ledc chn gamma config register. + */ +typedef union { + struct { + /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0; + * Configures the number of duty cycle fading rages for LEDC chn. + */ + uint32_t chn_gamma_entry_num:5; + /** chn_gamma_pause : WT; bitpos: [5]; default: 0; + * Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No + * effect\\1: Pause + */ + uint32_t chn_gamma_pause:1; + /** chn_gamma_resume : WT; bitpos: [6]; default: 0; + * Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No + * effect\\1: Resume + */ + uint32_t chn_gamma_resume:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} ledc_chn_gamma_conf_reg_t; + + +/** Group: ledc etm */ +/** Type of evt_task_en0 register + * Ledc event task enable bit register0. + */ +typedef union { + struct { + /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch0_en:1; + /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch1_en:1; + /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch2_en:1; + /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch3_en:1; + /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch4_en:1; + /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: + * Disable\\1: Enable + */ + uint32_t evt_duty_chng_end_ch5_en:1; + uint32_t reserved_6:2; + /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch0_en:1; + /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch1_en:1; + /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch2_en:1; + /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch3_en:1; + /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch4_en:1; + /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_ovf_cnt_pls_ch5_en:1; + uint32_t reserved_14:2; + /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer0_en:1; + /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer1_en:1; + /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer2_en:1; + /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time_ovf_timer3_en:1; + /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time0_cmp_en:1; + /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time1_cmp_en:1; + /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0; + * Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time2_cmp_en:1; + /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0; + * Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: + * Enable + */ + uint32_t evt_time3_cmp_en:1; + /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch0_en:1; + /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch1_en:1; + /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch2_en:1; + /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch3_en:1; + /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch4_en:1; + /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: + * Disable\\1: Enable + */ + uint32_t task_duty_scale_update_ch5_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} ledc_evt_task_en0_reg_t; + +/** Type of evt_task_en1 register + * Ledc event task enable bit register1. + */ +typedef union { + struct { + /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer0_res_update_en:1; + /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer1_res_update_en:1; + /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer2_res_update_en:1; + /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer3_res_update_en:1; + /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_cap_en:1; + /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_cap_en:1; + /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0; + * Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_cap_en:1; + /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + */ + uint32_t task_timer3_cap_en:1; + /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch0_en:1; + /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch1_en:1; + /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch2_en:1; + /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch3_en:1; + /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch4_en:1; + /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: + * Enable + */ + uint32_t task_sig_out_dis_ch5_en:1; + uint32_t reserved_14:2; + /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch0_en:1; + /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch1_en:1; + /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch2_en:1; + /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch3_en:1; + /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch4_en:1; + /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: + * Enable + */ + uint32_t task_ovf_cnt_rst_ch5_en:1; + uint32_t reserved_22:2; + /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0; + * Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer0_rst_en:1; + /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer1_rst_en:1; + /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0; + * Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer2_rst_en:1; + /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0; + * Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + */ + uint32_t task_timer3_rst_en:1; + /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer0_pause_resume_en:1; + /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer1_pause_resume_en:1; + /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer2_pause_resume_en:1; + /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_timer3_pause_resume_en:1; + }; + uint32_t val; +} ledc_evt_task_en1_reg_t; + +/** Type of evt_task_en2 register + * Ledc event task enable bit register2. + */ +typedef union { + struct { + /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch0_en:1; + /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch1_en:1; + /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch2_en:1; + /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch3_en:1; + /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch4_en:1; + /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_restart_ch5_en:1; + uint32_t reserved_6:2; + /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch0_en:1; + /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch1_en:1; + /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch2_en:1; + /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch3_en:1; + /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch4_en:1; + /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_pause_ch5_en:1; + uint32_t reserved_14:2; + /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch0_en:1; + /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0; + * Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch1_en:1; + /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0; + * Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch2_en:1; + /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0; + * Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch3_en:1; + /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0; + * Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch4_en:1; + /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0; + * Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: + * Enable + */ + uint32_t task_gamma_resume_ch5_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} ledc_evt_task_en2_reg_t; + + +/** Group: timer */ +/** Type of timern_cmp register + * Ledc timern compare value register. + */ +typedef union { + struct { + /** timern_cmp : R/W; bitpos: [19:0]; default: 0; + * Configures the comparison value for LEDC timern. + */ + uint32_t timern_cmp:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cmp_reg_t; + +/** Type of timern_cnt_cap register + * Ledc timern captured count value register. + */ +typedef union { + struct { + /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0; + * Represents the captured LEDC timern count value. + */ + uint32_t timern_cnt_cap:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} ledc_timern_cnt_cap_reg_t; + + +/** Group: ram */ +/** Type of conf register + * LEDC global configuration register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0; + * Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the + * clock gate for LEDC ch0 gamma ram + */ + uint32_t gamma_ram_clk_en_ch0:1; + /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0; + * Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the + * clock gate for LEDC ch1 gamma ram + */ + uint32_t gamma_ram_clk_en_ch1:1; + /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0; + * Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the + * clock gate for LEDC ch2 gamma ram + */ + uint32_t gamma_ram_clk_en_ch2:1; + /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0; + * Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the + * clock gate for LEDC ch3 gamma ram + */ + uint32_t gamma_ram_clk_en_ch3:1; + /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0; + * Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the + * clock gate for LEDC ch4 gamma ram + */ + uint32_t gamma_ram_clk_en_ch4:1; + /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0; + * Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock + * gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the + * clock gate for LEDC ch5 gamma ram + */ + uint32_t gamma_ram_clk_en_ch5:1; + uint32_t reserved_8:23; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to open register clock gate.\\0: Open the clock gate only + * when application writes registers\\1: Force open the clock gate for register + */ + uint32_t clk_en:1; + }; + uint32_t val; +} ledc_conf_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** ledc_date : R/W; bitpos: [27:0]; default: 36716928; + * Configures the version. + */ + uint32_t ledc_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ledc_date_reg_t; + + +typedef struct { + volatile ledc_chn_conf0_reg_t ch0_conf0; + volatile ledc_chn_hpoint_reg_t ch0_hpoint; + volatile ledc_chn_duty_reg_t ch0_duty; + volatile ledc_chn_conf1_reg_t ch0_conf1; + volatile ledc_chn_duty_r_reg_t ch0_duty_r; + volatile ledc_chn_conf0_reg_t ch1_conf0; + volatile ledc_chn_hpoint_reg_t ch1_hpoint; + volatile ledc_chn_duty_reg_t ch1_duty; + volatile ledc_chn_conf1_reg_t ch1_conf1; + volatile ledc_chn_duty_r_reg_t ch1_duty_r; + volatile ledc_chn_conf0_reg_t ch2_conf0; + volatile ledc_chn_hpoint_reg_t ch2_hpoint; + volatile ledc_chn_duty_reg_t ch2_duty; + volatile ledc_chn_conf1_reg_t ch2_conf1; + volatile ledc_chn_duty_r_reg_t ch2_duty_r; + volatile ledc_chn_conf0_reg_t ch3_conf0; + volatile ledc_chn_hpoint_reg_t ch3_hpoint; + volatile ledc_chn_duty_reg_t ch3_duty; + volatile ledc_chn_conf1_reg_t ch3_conf1; + volatile ledc_chn_duty_r_reg_t ch3_duty_r; + volatile ledc_chn_conf0_reg_t ch4_conf0; + volatile ledc_chn_hpoint_reg_t ch4_hpoint; + volatile ledc_chn_duty_reg_t ch4_duty; + volatile ledc_chn_conf1_reg_t ch4_conf1; + volatile ledc_chn_duty_r_reg_t ch4_duty_r; + volatile ledc_chn_conf0_reg_t ch5_conf0; + volatile ledc_chn_hpoint_reg_t ch5_hpoint; + volatile ledc_chn_duty_reg_t ch5_duty; + volatile ledc_chn_conf1_reg_t ch5_conf1; + volatile ledc_chn_duty_r_reg_t ch5_duty_r; + uint32_t reserved_078[10]; + volatile ledc_timern_conf_reg_t timer0_conf; + volatile ledc_timern_value_reg_t timer0_value; + volatile ledc_timern_conf_reg_t timer1_conf; + volatile ledc_timern_value_reg_t timer1_value; + volatile ledc_timern_conf_reg_t timer2_conf; + volatile ledc_timern_value_reg_t timer2_value; + volatile ledc_timern_conf_reg_t timer3_conf; + volatile ledc_timern_value_reg_t timer3_value; + volatile ledc_int_raw_reg_t int_raw; + volatile ledc_int_st_reg_t int_st; + volatile ledc_int_ena_reg_t int_ena; + volatile ledc_int_clr_reg_t int_clr; + uint32_t reserved_0d0[12]; + volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[6]; + uint32_t reserved_118[2]; + volatile ledc_evt_task_en0_reg_t evt_task_en0; + volatile ledc_evt_task_en1_reg_t evt_task_en1; + volatile ledc_evt_task_en2_reg_t evt_task_en2; + uint32_t reserved_12c[5]; + volatile ledc_timern_cmp_reg_t timern_cmp[4]; + volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4]; + uint32_t reserved_160[4]; + volatile ledc_conf_reg_t conf; + volatile ledc_date_reg_t date; +} ledc_dev_t; + +extern ledc_dev_t LEDC; + +#ifndef __cplusplus +_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h new file mode 100644 index 0000000000..079aff0bd3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h @@ -0,0 +1,228 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANA_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0) +/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANA_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4) +/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANA_CK_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8) +/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S) +#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANA_CK_GLITCH_RESET_ENA_S 31 + +/** LP_ANA_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc) +/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU +#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S) +#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU +#define LP_ANA_ANA_FIB_ENA_S 0 + +/** LP_ANA_INT_RAW_REG register + * need_des + */ +#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10) +/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANA_INT_ST_REG register + * need_des + */ +#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14) +/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANA_INT_ENA_REG register + * need_des + */ +#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18) +/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANA_INT_CLR_REG register + * need_des + */ +#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c) +/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANA_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20) +/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANA_LP_INT_ST_REG register + * need_des + */ +#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24) +/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANA_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28) +/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANA_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c) +/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANA_DATE_REG register + * need_des + */ +#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc) +/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 35660384; + * need_des + */ +#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S) +#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_S 0 +/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CLK_EN (BIT(31)) +#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S) +#define LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h new file mode 100644 index 0000000000..043f908f7a --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h @@ -0,0 +1,252 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t bod_mode0_close_flash_ena:1; + /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t bod_mode0_pd_rf_ena:1; + /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t bod_mode0_intr_wait:10; + /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t bod_mode0_reset_wait:10; + /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t bod_mode0_cnt_clr:1; + /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t bod_mode0_intr_ena:1; + /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_sel:1; + /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of ck_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_ck_glitch_cntl_reg_t; + +/** Type of fib_enable register + * need_des + */ +typedef union { + struct { + /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t ana_fib_ena:32; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_st:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_ana_date : R/W; bitpos: [30:0]; default: 35660384; + * need_des + */ + uint32_t lp_ana_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct { + volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl; + volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl; + volatile lp_ana_fib_enable_reg_t fib_enable; + volatile lp_ana_int_raw_reg_t int_raw; + volatile lp_ana_int_st_reg_t int_st; + volatile lp_ana_int_ena_reg_t int_ena; + volatile lp_ana_int_clr_reg_t int_clr; + volatile lp_ana_lp_int_raw_reg_t lp_int_raw; + volatile lp_ana_lp_int_st_reg_t lp_int_st; + volatile lp_ana_lp_int_ena_reg_t lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_030[243]; + volatile lp_ana_date_reg_t date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_aon_reg.h b/components/soc/esp32c5/include/soc/lp_aon_reg.h new file mode 100644 index 0000000000..39b2fb9674 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_aon_reg.h @@ -0,0 +1,466 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_AON_STORE0_REG register + * need_des + */ +#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) +#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_S 0 + +/** LP_AON_STORE1_REG register + * need_des + */ +#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) +#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_S 0 + +/** LP_AON_STORE2_REG register + * need_des + */ +#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) +#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_S 0 + +/** LP_AON_STORE3_REG register + * need_des + */ +#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) +#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_S 0 + +/** LP_AON_STORE4_REG register + * need_des + */ +#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) +#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_S 0 + +/** LP_AON_STORE5_REG register + * need_des + */ +#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) +#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_S 0 + +/** LP_AON_STORE6_REG register + * need_des + */ +#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) +#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_S 0 + +/** LP_AON_STORE7_REG register + * need_des + */ +#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) +#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_S 0 + +/** LP_AON_STORE8_REG register + * need_des + */ +#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) +#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_S 0 + +/** LP_AON_STORE9_REG register + * need_des + */ +#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) +#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_S 0 + +/** LP_AON_GPIO_MUX_REG register + * need_des + */ +#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_MUX_SEL 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) +#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_S 0 + +/** LP_AON_GPIO_HOLD0_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) +#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_S 0 + +/** LP_AON_GPIO_HOLD1_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) +#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_S 0 + +/** LP_AON_SYS_CFG_REG register + * need_des + */ +#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) +#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) +#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U +#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 +/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_HPSYS_SW_RESET (BIT(31)) +#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) +#define LP_AON_HPSYS_SW_RESET_V 0x00000001U +#define LP_AON_HPSYS_SW_RESET_S 31 + +/** LP_AON_CPUCORE0_CFG_REG register + * need_des + */ +#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) +#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_S 0 +/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) +#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) +#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_SW_RESET_S 28 +/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 +/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 +/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) +#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) +#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U +#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 + +/** LP_AON_IO_MUX_REG register + * need_des + */ +#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) +#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) +#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_AON_IO_MUX_RESET_DISABLE_S 31 + +/** LP_AON_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) +/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) +#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_S 0 +/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 +/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) +#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_S 15 +/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_LV 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) +#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_S 23 +/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) +#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) +#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U +#define LP_AON_EXT_WAKEUP_FILTER_S 31 + +/** LP_AON_USB_REG register + * need_des + */ +#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) +/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_USB_RESET_DISABLE (BIT(31)) +#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) +#define LP_AON_USB_RESET_DISABLE_V 0x00000001U +#define LP_AON_USB_RESET_DISABLE_S 31 + +/** LP_AON_LPBUS_REG register + * need_des + */ +#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) +/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28)) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S) +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28 +/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29)) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S) +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29 +/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30)) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S) +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30 +/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_AON_FAST_MEM_MUX_SEL (BIT(31)) +#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S) +#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U +#define LP_AON_FAST_MEM_MUX_SEL_S 31 + +/** LP_AON_SDIO_ACTIVE_REG register + * need_des + */ +#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; + * need_des + */ +#define LP_AON_SDIO_ACT_DNUM 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) +#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_S 22 + +/** LP_AON_LPCORE_REG register + * need_des + */ +#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 +/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_DISABLE (BIT(31)) +#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) +#define LP_AON_LPCORE_DISABLE_V 0x00000001U +#define LP_AON_LPCORE_DISABLE_S 31 + +/** LP_AON_SAR_CCT_REG register + * need_des + */ +#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) +/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; + * need_des + */ +#define LP_AON_SAR2_PWDET_CCT 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) +#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_S 29 + +/** LP_AON_MODEM_BUS_REG register + * need_des + */ +#define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58) +/** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_MODEM_SYNC_BRIDGE_EN (BIT(31)) +#define LP_AON_MODEM_SYNC_BRIDGE_EN_M (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S) +#define LP_AON_MODEM_SYNC_BRIDGE_EN_V 0x00000001U +#define LP_AON_MODEM_SYNC_BRIDGE_EN_S 31 + +/** LP_AON_AUDIO_CODEC_CTRL_REG register + * need_des + */ +#define LP_AON_AUDIO_CODEC_CTRL_REG (DR_REG_LP_AON_BASE + 0x5c) +/** LP_AON_RTC_XPD_SDADC : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_RTC_XPD_SDADC (BIT(0)) +#define LP_AON_RTC_XPD_SDADC_M (LP_AON_RTC_XPD_SDADC_V << LP_AON_RTC_XPD_SDADC_S) +#define LP_AON_RTC_XPD_SDADC_V 0x00000001U +#define LP_AON_RTC_XPD_SDADC_S 0 +/** LP_AON_RTC_EN_CLK_AUDIO_DAC : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_RTC_EN_CLK_AUDIO_DAC (BIT(1)) +#define LP_AON_RTC_EN_CLK_AUDIO_DAC_M (LP_AON_RTC_EN_CLK_AUDIO_DAC_V << LP_AON_RTC_EN_CLK_AUDIO_DAC_S) +#define LP_AON_RTC_EN_CLK_AUDIO_DAC_V 0x00000001U +#define LP_AON_RTC_EN_CLK_AUDIO_DAC_S 1 +/** LP_AON_RTC_XPD_BIAS_AUDIO_DAC : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC (BIT(2)) +#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_M (LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V << LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S) +#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V 0x00000001U +#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S 2 +/** LP_AON_RTC_XPD_PLLA : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define LP_AON_RTC_XPD_PLLA (BIT(3)) +#define LP_AON_RTC_XPD_PLLA_M (LP_AON_RTC_XPD_PLLA_V << LP_AON_RTC_XPD_PLLA_S) +#define LP_AON_RTC_XPD_PLLA_V 0x00000001U +#define LP_AON_RTC_XPD_PLLA_S 3 + +/** LP_AON_SPRAM_CTRL_REG register + * need_des + */ +#define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60) +/** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define LP_AON_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU +#define LP_AON_SPRAM_MEM_AUX_CTRL_M (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S) +#define LP_AON_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_AON_SPRAM_MEM_AUX_CTRL_S 0 + +/** LP_AON_SPRF_CTRL_REG register + * need_des + */ +#define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64) +/** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define LP_AON_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define LP_AON_SPRF_MEM_AUX_CTRL_M (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S) +#define LP_AON_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_AON_SPRF_MEM_AUX_CTRL_S 0 + +/** LP_AON_DATE_REG register + * need_des + */ +#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36720768; + * need_des + */ +#define LP_AON_DATE 0x7FFFFFFFU +#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) +#define LP_AON_DATE_V 0x7FFFFFFFU +#define LP_AON_DATE_S 0 +/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CLK_EN (BIT(31)) +#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) +#define LP_AON_CLK_EN_V 0x00000001U +#define LP_AON_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_aon_struct.h b/components/soc/esp32c5/include/soc/lp_aon_struct.h new file mode 100644 index 0000000000..b219a17df8 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_aon_struct.h @@ -0,0 +1,491 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of store0 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store0:32; + }; + uint32_t val; +} lp_aon_store0_reg_t; + +/** Type of store1 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store1:32; + }; + uint32_t val; +} lp_aon_store1_reg_t; + +/** Type of store2 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store2:32; + }; + uint32_t val; +} lp_aon_store2_reg_t; + +/** Type of store3 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store3:32; + }; + uint32_t val; +} lp_aon_store3_reg_t; + +/** Type of store4 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store4:32; + }; + uint32_t val; +} lp_aon_store4_reg_t; + +/** Type of store5 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store5:32; + }; + uint32_t val; +} lp_aon_store5_reg_t; + +/** Type of store6 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store6:32; + }; + uint32_t val; +} lp_aon_store6_reg_t; + +/** Type of store7 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store7:32; + }; + uint32_t val; +} lp_aon_store7_reg_t; + +/** Type of store8 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store8:32; + }; + uint32_t val; +} lp_aon_store8_reg_t; + +/** Type of store9 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store9:32; + }; + uint32_t val; +} lp_aon_store9_reg_t; + +/** Type of gpio_mux register + * need_des + */ +typedef union { + struct { + /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t gpio_mux_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_gpio_mux_reg_t; + +/** Type of gpio_hold0 register + * need_des + */ +typedef union { + struct { + /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold0:32; + }; + uint32_t val; +} lp_aon_gpio_hold0_reg_t; + +/** Type of gpio_hold1 register + * need_des + */ +typedef union { + struct { + /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold1:32; + }; + uint32_t val; +} lp_aon_gpio_hold1_reg_t; + +/** Type of sys_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** force_download_boot : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t force_download_boot:1; + /** hpsys_sw_reset : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hpsys_sw_reset:1; + }; + uint32_t val; +} lp_aon_sys_cfg_reg_t; + +/** Type of cpucore0_cfg register + * need_des + */ +typedef union { + struct { + /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_stall:8; + uint32_t reserved_8:20; + /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_reset:1; + /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t cpu_core0_ocd_halt_on_reset:1; + /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t cpu_core0_stat_vector_sel:1; + /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_core0_dreset_mask:1; + }; + uint32_t val; +} lp_aon_cpucore0_cfg_reg_t; + +/** Type of io_mux register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t io_mux_reset_disable:1; + }; + uint32_t val; +} lp_aon_io_mux_reg_t; + +/** Type of ext_wakeup_cntl register + * need_des + */ +typedef union { + struct { + /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status:8; + uint32_t reserved_8:6; + /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status_clr:1; + /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0; + * need_des + */ + uint32_t ext_wakeup_sel:8; + /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0; + * need_des + */ + uint32_t ext_wakeup_lv:8; + /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_wakeup_filter:1; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl_reg_t; + +/** Type of usb register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** usb_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t usb_reset_disable:1; + }; + uint32_t val; +} lp_aon_usb_reg_t; + +/** Type of lpbus register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_fsm_idle:1; + /** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_sel_status:1; + /** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t fast_mem_mux_sel_update:1; + /** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t fast_mem_mux_sel:1; + }; + uint32_t val; +} lp_aon_lpbus_reg_t; + +/** Type of sdio_active register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; + * need_des + */ + uint32_t sdio_act_dnum:10; + }; + uint32_t val; +} lp_aon_sdio_active_reg_t; + +/** Type of lpcore register + * need_des + */ +typedef union { + struct { + /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag_clr:1; + /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag:1; + uint32_t reserved_2:29; + /** lpcore_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpcore_disable:1; + }; + uint32_t val; +} lp_aon_lpcore_reg_t; + +/** Type of sar_cct register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; + * need_des + */ + uint32_t sar2_pwdet_cct:3; + }; + uint32_t val; +} lp_aon_sar_cct_reg_t; + +/** Type of modem_bus register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** modem_sync_bridge_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t modem_sync_bridge_en:1; + }; + uint32_t val; +} lp_aon_modem_bus_reg_t; + +/** Type of audio_codec_ctrl register + * need_des + */ +typedef union { + struct { + /** rtc_xpd_sdadc : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t rtc_xpd_sdadc:1; + /** rtc_en_clk_audio_dac : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t rtc_en_clk_audio_dac:1; + /** rtc_xpd_bias_audio_dac : R/W; bitpos: [2]; default: 0; + * need_des + */ + uint32_t rtc_xpd_bias_audio_dac:1; + /** rtc_xpd_plla : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t rtc_xpd_plla:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_aon_audio_codec_ctrl_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 36720768; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_aon_date_reg_t; + + +/** Group: Configuration Register */ +/** Type of spram_ctrl register + * need_des + */ +typedef union { + struct { + /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ + uint32_t spram_mem_aux_ctrl:32; + }; + uint32_t val; +} lp_aon_spram_ctrl_reg_t; + +/** Type of sprf_ctrl register + * need_des + */ +typedef union { + struct { + /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ + uint32_t sprf_mem_aux_ctrl:32; + }; + uint32_t val; +} lp_aon_sprf_ctrl_reg_t; + + +typedef struct { + volatile lp_aon_store0_reg_t store0; + volatile lp_aon_store1_reg_t store1; + volatile lp_aon_store2_reg_t store2; + volatile lp_aon_store3_reg_t store3; + volatile lp_aon_store4_reg_t store4; + volatile lp_aon_store5_reg_t store5; + volatile lp_aon_store6_reg_t store6; + volatile lp_aon_store7_reg_t store7; + volatile lp_aon_store8_reg_t store8; + volatile lp_aon_store9_reg_t store9; + volatile lp_aon_gpio_mux_reg_t gpio_mux; + volatile lp_aon_gpio_hold0_reg_t gpio_hold0; + volatile lp_aon_gpio_hold1_reg_t gpio_hold1; + volatile lp_aon_sys_cfg_reg_t sys_cfg; + volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg; + volatile lp_aon_io_mux_reg_t io_mux; + volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile lp_aon_usb_reg_t usb; + volatile lp_aon_lpbus_reg_t lpbus; + volatile lp_aon_sdio_active_reg_t sdio_active; + volatile lp_aon_lpcore_reg_t lpcore; + volatile lp_aon_sar_cct_reg_t sar_cct; + volatile lp_aon_modem_bus_reg_t modem_bus; + volatile lp_aon_audio_codec_ctrl_reg_t audio_codec_ctrl; + volatile lp_aon_spram_ctrl_reg_t spram_ctrl; + volatile lp_aon_sprf_ctrl_reg_t sprf_ctrl; + uint32_t reserved_068[229]; + volatile lp_aon_date_reg_t date; +} lp_aon_dev_t; + +extern lp_aon_dev_t LP_AON; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_apm0_reg.h b/components/soc/esp32c5/include/soc/lp_apm0_reg.h new file mode 100644 index 0000000000..f2228c5ab3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_apm0_reg.h @@ -0,0 +1,534 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM0_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) +/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM0_REGION_FILTER_EN 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) +#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_S 0 + +/** LP_APM0_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) +/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) +#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_S 0 + +/** LP_APM0_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) +/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) +#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_S 0 + +/** LP_APM0_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) +/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S) +#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_X_S 0 +/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S) +#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_W_S 1 +/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S) +#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_R_S 2 +/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S) +#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_X_S 4 +/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S) +#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_W_S 5 +/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S) +#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_R_S 6 +/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S) +#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_X_S 8 +/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S) +#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_W_S 9 +/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S) +#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_R_S 10 +/** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM0_REGION0_LOCK (BIT(11)) +#define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S) +#define LP_APM0_REGION0_LOCK_V 0x00000001U +#define LP_APM0_REGION0_LOCK_S 11 + +/** LP_APM0_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) +/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) +#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_S 0 + +/** LP_APM0_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) +/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) +#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_S 0 + +/** LP_APM0_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) +/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S) +#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_X_S 0 +/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S) +#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_W_S 1 +/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S) +#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_R_S 2 +/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S) +#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_X_S 4 +/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S) +#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_W_S 5 +/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S) +#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_R_S 6 +/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S) +#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_X_S 8 +/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S) +#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_W_S 9 +/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S) +#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_R_S 10 +/** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ +#define LP_APM0_REGION1_LOCK (BIT(11)) +#define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S) +#define LP_APM0_REGION1_LOCK_V 0x00000001U +#define LP_APM0_REGION1_LOCK_S 11 + +/** LP_APM0_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) +/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) +#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_S 0 + +/** LP_APM0_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) +/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) +#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_S 0 + +/** LP_APM0_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) +/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S) +#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_X_S 0 +/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S) +#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_W_S 1 +/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S) +#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_R_S 2 +/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S) +#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_X_S 4 +/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S) +#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_W_S 5 +/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S) +#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_R_S 6 +/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S) +#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_X_S 8 +/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S) +#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_W_S 9 +/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S) +#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_R_S 10 +/** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ +#define LP_APM0_REGION2_LOCK (BIT(11)) +#define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S) +#define LP_APM0_REGION2_LOCK_V 0x00000001U +#define LP_APM0_REGION2_LOCK_S 11 + +/** LP_APM0_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) +/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) +#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_S 0 + +/** LP_APM0_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) +/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) +#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_S 0 + +/** LP_APM0_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) +/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S) +#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_X_S 0 +/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S) +#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_W_S 1 +/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S) +#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_R_S 2 +/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S) +#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_X_S 4 +/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S) +#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_W_S 5 +/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S) +#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_R_S 6 +/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S) +#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_X_S 8 +/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S) +#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_W_S 9 +/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S) +#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_R_S 10 +/** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ +#define LP_APM0_REGION3_LOCK (BIT(11)) +#define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S) +#define LP_APM0_REGION3_LOCK_V 0x00000001U +#define LP_APM0_REGION3_LOCK_S 11 + +/** LP_APM0_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) +/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM0_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S) +#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM0_M0_PMS_FUNC_EN_S 0 + +/** LP_APM0_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) +/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) +#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM0_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) +/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S) +#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM0_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM0_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) +/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) +#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_S 0 +/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) +#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_S 16 +/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) +#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_S 18 + +/** LP_APM0_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) +/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) +#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM0_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) +/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM0_M0_APM_INT_EN (BIT(0)) +#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) +#define LP_APM0_M0_APM_INT_EN_V 0x00000001U +#define LP_APM0_M0_APM_INT_EN_S 0 + +/** LP_APM0_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) +/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM0_CLK_EN (BIT(0)) +#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) +#define LP_APM0_CLK_EN_V 0x00000001U +#define LP_APM0_CLK_EN_S 0 + +/** LP_APM0_DATE_REG register + * Version register + */ +#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) +/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ +#define LP_APM0_DATE 0x0FFFFFFFU +#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) +#define LP_APM0_DATE_V 0x0FFFFFFFU +#define LP_APM0_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_apm0_struct.h b/components/soc/esp32c5/include/soc/lp_apm0_struct.h new file mode 100644 index 0000000000..afffb7456a --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_apm0_struct.h @@ -0,0 +1,514 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm0_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm0_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm0_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm0_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm0_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} lp_apm0_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} lp_apm0_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} lp_apm0_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} lp_apm0_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + /** region0_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t region0_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm0_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + /** region1_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ + uint32_t region1_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm0_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + /** region2_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ + uint32_t region2_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm0_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + /** region3_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ + uint32_t region3_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm0_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm0_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm0_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm0_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm0_date_reg_t; + + +typedef struct { + volatile lp_apm0_region_filter_en_reg_t region_filter_en; + volatile lp_apm0_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm0_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm0_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm0_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr; + volatile lp_apm0_region2_addr_start_reg_t region2_addr_start; + volatile lp_apm0_region2_addr_end_reg_t region2_addr_end; + volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr; + volatile lp_apm0_region3_addr_start_reg_t region3_addr_start; + volatile lp_apm0_region3_addr_end_reg_t region3_addr_end; + volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm0_func_ctrl_reg_t func_ctrl; + volatile lp_apm0_m0_status_reg_t m0_status; + volatile lp_apm0_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1; + volatile lp_apm0_int_en_reg_t int_en; + volatile lp_apm0_clock_gate_reg_t clock_gate; + uint32_t reserved_0e0[455]; + volatile lp_apm0_date_reg_t date; +} lp_apm0_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_apm_reg.h b/components/soc/esp32c5/include/soc/lp_apm_reg.h new file mode 100644 index 0000000000..17b6ef43a6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_apm_reg.h @@ -0,0 +1,610 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM_REGION_FILTER_EN 0x0000000FU +#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) +#define LP_APM_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM_REGION_FILTER_EN_S 0 + +/** LP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) +/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) +#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_S 0 + +/** LP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) +/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) +#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_S 0 + +/** LP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) +/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S) +#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_X_S 0 +/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S) +#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_W_S 1 +/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S) +#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_R_S 2 +/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S) +#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_X_S 4 +/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S) +#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_W_S 5 +/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S) +#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_R_S 6 +/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S) +#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_X_S 8 +/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S) +#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_W_S 9 +/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S) +#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_R_S 10 +/** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION0_LOCK (BIT(11)) +#define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S) +#define LP_APM_REGION0_LOCK_V 0x00000001U +#define LP_APM_REGION0_LOCK_S 11 + +/** LP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) +/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) +#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_S 0 + +/** LP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) +/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) +#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_S 0 + +/** LP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) +/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S) +#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_X_S 0 +/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S) +#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_W_S 1 +/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S) +#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_R_S 2 +/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S) +#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_X_S 4 +/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S) +#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_W_S 5 +/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S) +#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_R_S 6 +/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S) +#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_X_S 8 +/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S) +#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_W_S 9 +/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S) +#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_R_S 10 +/** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ +#define LP_APM_REGION1_LOCK (BIT(11)) +#define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S) +#define LP_APM_REGION1_LOCK_V 0x00000001U +#define LP_APM_REGION1_LOCK_S 11 + +/** LP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) +/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) +#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_S 0 + +/** LP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) +/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) +#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_S 0 + +/** LP_APM_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) +/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM_REGION2_R0_PMS_X_M (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S) +#define LP_APM_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_X_S 0 +/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM_REGION2_R0_PMS_W_M (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S) +#define LP_APM_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_W_S 1 +/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM_REGION2_R0_PMS_R_M (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S) +#define LP_APM_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R0_PMS_R_S 2 +/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM_REGION2_R1_PMS_X_M (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S) +#define LP_APM_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_X_S 4 +/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM_REGION2_R1_PMS_W_M (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S) +#define LP_APM_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_W_S 5 +/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM_REGION2_R1_PMS_R_M (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S) +#define LP_APM_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R1_PMS_R_S 6 +/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM_REGION2_R2_PMS_X_M (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S) +#define LP_APM_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_X_S 8 +/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM_REGION2_R2_PMS_W_M (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S) +#define LP_APM_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_W_S 9 +/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM_REGION2_R2_PMS_R_M (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S) +#define LP_APM_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION2_R2_PMS_R_S 10 +/** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ +#define LP_APM_REGION2_LOCK (BIT(11)) +#define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S) +#define LP_APM_REGION2_LOCK_V 0x00000001U +#define LP_APM_REGION2_LOCK_S 11 + +/** LP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) +/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) +#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_S 0 + +/** LP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) +/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) +#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_S 0 + +/** LP_APM_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) +/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM_REGION3_R0_PMS_X_M (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S) +#define LP_APM_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_X_S 0 +/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM_REGION3_R0_PMS_W_M (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S) +#define LP_APM_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_W_S 1 +/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM_REGION3_R0_PMS_R_M (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S) +#define LP_APM_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R0_PMS_R_S 2 +/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM_REGION3_R1_PMS_X_M (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S) +#define LP_APM_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_X_S 4 +/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM_REGION3_R1_PMS_W_M (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S) +#define LP_APM_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_W_S 5 +/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM_REGION3_R1_PMS_R_M (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S) +#define LP_APM_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R1_PMS_R_S 6 +/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM_REGION3_R2_PMS_X_M (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S) +#define LP_APM_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_X_S 8 +/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM_REGION3_R2_PMS_W_M (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S) +#define LP_APM_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_W_S 9 +/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM_REGION3_R2_PMS_R_M (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S) +#define LP_APM_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION3_R2_PMS_R_S 10 +/** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ +#define LP_APM_REGION3_LOCK (BIT(11)) +#define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S) +#define LP_APM_REGION3_LOCK_V 0x00000001U +#define LP_APM_REGION3_LOCK_S 11 + +/** LP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) +/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S) +#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M0_PMS_FUNC_EN_S 0 +/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define LP_APM_M1_PMS_FUNC_EN (BIT(1)) +#define LP_APM_M1_PMS_FUNC_EN_M (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S) +#define LP_APM_M1_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M1_PMS_FUNC_EN_S 1 + +/** LP_APM_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) +/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) +#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) +/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S) +#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) +#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_S 0 +/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) +#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_S 16 +/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) +#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_S 18 + +/** LP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) +/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) +#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM_M1_STATUS_REG register + * M1 status register + */ +#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8) +/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M1_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S) +#define LP_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M1_EXCEPTION_STATUS_S 0 + +/** LP_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc) +/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M1_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M1_REGION_STATUS_CLR_M (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S) +#define LP_APM_M1_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M1_REGION_STATUS_CLR_S 0 + +/** LP_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0) +/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM_M1_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S) +#define LP_APM_M1_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M1_EXCEPTION_REGION_S 0 +/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M1_EXCEPTION_MODE 0x00000003U +#define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S) +#define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M1_EXCEPTION_MODE_S 16 +/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M1_EXCEPTION_ID 0x0000001FU +#define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S) +#define LP_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M1_EXCEPTION_ID_S 18 + +/** LP_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4) +/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S) +#define LP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M1_EXCEPTION_ADDR_S 0 + +/** LP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) +/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM_M0_APM_INT_EN (BIT(0)) +#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) +#define LP_APM_M0_APM_INT_EN_V 0x00000001U +#define LP_APM_M0_APM_INT_EN_S 0 +/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ +#define LP_APM_M1_APM_INT_EN (BIT(1)) +#define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S) +#define LP_APM_M1_APM_INT_EN_V 0x00000001U +#define LP_APM_M1_APM_INT_EN_S 1 + +/** LP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) +/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM_CLK_EN (BIT(0)) +#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) +#define LP_APM_CLK_EN_V 0x00000001U +#define LP_APM_CLK_EN_S 0 + +/** LP_APM_DATE_REG register + * Version register + */ +#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc) +/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ +#define LP_APM_DATE 0x0FFFFFFFU +#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) +#define LP_APM_DATE_V 0x0FFFFFFFU +#define LP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_apm_struct.h b/components/soc/esp32c5/include/soc/lp_apm_struct.h new file mode 100644 index 0000000000..b75f8a09e7 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_apm_struct.h @@ -0,0 +1,599 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t region0_addr_start:32; + }; + uint32_t val; +} lp_apm_region0_addr_start_reg_t; + +/** Type of region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t region0_addr_end:32; + }; + uint32_t val; +} lp_apm_region0_addr_end_reg_t; + +/** Type of region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t region1_addr_start:32; + }; + uint32_t val; +} lp_apm_region1_addr_start_reg_t; + +/** Type of region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t region1_addr_end:32; + }; + uint32_t val; +} lp_apm_region1_addr_end_reg_t; + +/** Type of region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t region2_addr_start:32; + }; + uint32_t val; +} lp_apm_region2_addr_start_reg_t; + +/** Type of region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t region2_addr_end:32; + }; + uint32_t val; +} lp_apm_region2_addr_end_reg_t; + +/** Type of region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t region3_addr_start:32; + }; + uint32_t val; +} lp_apm_region3_addr_start_reg_t; + +/** Type of region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t region3_addr_end:32; + }; + uint32_t val; +} lp_apm_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region0_r0_pms_x:1; + /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region0_r0_pms_w:1; + /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region0_r1_pms_x:1; + /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region0_r1_pms_w:1; + /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region0_r2_pms_x:1; + /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region0_r2_pms_w:1; + /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region0_r2_pms_r:1; + /** region0_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t region0_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_region0_pms_attr_reg_t; + +/** Type of region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region1_r0_pms_x:1; + /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region1_r0_pms_w:1; + /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region1_r1_pms_x:1; + /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region1_r1_pms_w:1; + /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region1_r2_pms_x:1; + /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region1_r2_pms_w:1; + /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region1_r2_pms_r:1; + /** region1_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region1 configuration + */ + uint32_t region1_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_region1_pms_attr_reg_t; + +/** Type of region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region2_r0_pms_x:1; + /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region2_r0_pms_w:1; + /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region2_r1_pms_x:1; + /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region2_r1_pms_w:1; + /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region2_r2_pms_x:1; + /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region2_r2_pms_w:1; + /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region2_r2_pms_r:1; + /** region2_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region2 configuration + */ + uint32_t region2_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_region2_pms_attr_reg_t; + +/** Type of region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t region3_r0_pms_x:1; + /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t region3_r0_pms_w:1; + /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t region3_r1_pms_x:1; + /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t region3_r1_pms_w:1; + /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t region3_r2_pms_x:1; + /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t region3_r2_pms_w:1; + /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t region3_r2_pms_r:1; + /** region3_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region3 configuration + */ + uint32_t region3_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_pms_func_en:1; + /** m1_pms_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_pms_func_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t m1_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t m1_exception_region:4; + uint32_t reserved_4:12; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} lp_apm_m1_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * APM M1 interrupt enable + */ + uint32_t m1_apm_int_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725664; + * reg_date + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm_date_reg_t; + + +typedef struct { + volatile lp_apm_region_filter_en_reg_t region_filter_en; + volatile lp_apm_region0_addr_start_reg_t region0_addr_start; + volatile lp_apm_region0_addr_end_reg_t region0_addr_end; + volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr; + volatile lp_apm_region1_addr_start_reg_t region1_addr_start; + volatile lp_apm_region1_addr_end_reg_t region1_addr_end; + volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr; + volatile lp_apm_region2_addr_start_reg_t region2_addr_start; + volatile lp_apm_region2_addr_end_reg_t region2_addr_end; + volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr; + volatile lp_apm_region3_addr_start_reg_t region3_addr_start; + volatile lp_apm_region3_addr_end_reg_t region3_addr_end; + volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm_func_ctrl_reg_t func_ctrl; + volatile lp_apm_m0_status_reg_t m0_status; + volatile lp_apm_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile lp_apm_m1_status_reg_t m1_status; + volatile lp_apm_m1_status_clr_reg_t m1_status_clr; + volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile lp_apm_int_en_reg_t int_en; + volatile lp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_0f0[3]; + volatile lp_apm_date_reg_t date; +} lp_apm_dev_t; + +extern lp_apm_dev_t LP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_reg.h b/components/soc/esp32c5/include/soc/lp_clkrst_reg.h new file mode 100644 index 0000000000..6cd5afc503 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_clkrst_reg.h @@ -0,0 +1,404 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) +#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) +#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_AON_SLOW_OEN_S 0 +/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_FAST_OEN (BIT(1)) +#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) +#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_AON_FAST_OEN_S 1 +/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define LP_CLKRST_SOSC_OEN (BIT(2)) +#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) +#define LP_CLKRST_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_SOSC_OEN_S 2 +/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define LP_CLKRST_FOSC_OEN (BIT(3)) +#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) +#define LP_CLKRST_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_FOSC_OEN_S 3 +/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define LP_CLKRST_OSC32K_OEN (BIT(4)) +#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) +#define LP_CLKRST_OSC32K_OEN_V 0x00000001U +#define LP_CLKRST_OSC32K_OEN_S 4 +/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_XTAL32K_OEN (BIT(5)) +#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) +#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U +#define LP_CLKRST_XTAL32K_OEN_S 5 +/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) +#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CORE_EFUSE_OEN_S 6 +/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define LP_CLKRST_SLOW_OEN (BIT(7)) +#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) +#define LP_CLKRST_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_SLOW_OEN_S 7 +/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_OEN (BIT(8)) +#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) +#define LP_CLKRST_FAST_OEN_V 0x00000001U +#define LP_CLKRST_FAST_OEN_S 8 +/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_CLKRST_RNG_OEN (BIT(9)) +#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) +#define LP_CLKRST_RNG_OEN_V 0x00000001U +#define LP_CLKRST_RNG_OEN_S 9 +/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; + * need_des + */ +#define LP_CLKRST_LPBUS_OEN (BIT(10)) +#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) +#define LP_CLKRST_LPBUS_OEN_V 0x00000001U +#define LP_CLKRST_LPBUS_OEN_S 10 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) +#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) +#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U +#define LP_CLKRST_FAST_ORI_GATE_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_HUK_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_HUK_RESET_EN (BIT(27)) +#define LP_CLKRST_HUK_RESET_EN_M (LP_CLKRST_HUK_RESET_EN_V << LP_CLKRST_HUK_RESET_EN_S) +#define LP_CLKRST_HUK_RESET_EN_V 0x00000001U +#define LP_CLKRST_HUK_RESET_EN_S 27 +/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 +/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) +#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) +#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 +/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_WDT_RESET_EN (BIT(30)) +#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) +#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U +#define LP_CLKRST_WDT_RESET_EN_S 30 +/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) +#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) +#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U +#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * need_des + */ +#define LP_CLKRST_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) +#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) +#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_S 5 +/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_CPU_RESET_REG register + * need_des + */ +#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21)) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21 +/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 +/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * need_des + */ +#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) +#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CPU_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) +#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_STALL_EN_S 31 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LPPERI_REG register + * need_des + */ +#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_HUK_CLK_SEL : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_HUK_CLK_SEL (BIT(29)) +#define LP_CLKRST_HUK_CLK_SEL_M (LP_CLKRST_HUK_CLK_SEL_V << LP_CLKRST_HUK_CLK_SEL_S) +#define LP_CLKRST_HUK_CLK_SEL_V 0x00000001U +#define LP_CLKRST_HUK_CLK_SEL_S 29 +/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30)) +#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S) +#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_I2C_CLK_SEL_S 30 +/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31)) +#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S) +#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_UART_CLK_SEL_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36720768; + * need_des + */ +#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) +#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_S 0 +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_struct.h b/components/soc/esp32c5/include/soc/lp_clkrst_struct.h new file mode 100644 index 0000000000..71c539b8eb --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_clkrst_struct.h @@ -0,0 +1,354 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_clk_conf register + * need_des + */ +typedef union { + struct { + /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t slow_clk_sel:2; + /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1; + * need_des + */ + uint32_t fast_clk_sel:2; + /** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0; + * need_des + */ + uint32_t lp_peri_div_num:8; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_clkrst_lp_clk_conf_reg_t; + +/** Type of lp_clk_po_en register + * need_des + */ +typedef union { + struct { + /** aon_slow_oen : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t aon_slow_oen:1; + /** aon_fast_oen : R/W; bitpos: [1]; default: 1; + * need_des + */ + uint32_t aon_fast_oen:1; + /** sosc_oen : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t sosc_oen:1; + /** fosc_oen : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t fosc_oen:1; + /** osc32k_oen : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t osc32k_oen:1; + /** xtal32k_oen : R/W; bitpos: [5]; default: 1; + * need_des + */ + uint32_t xtal32k_oen:1; + /** core_efuse_oen : R/W; bitpos: [6]; default: 1; + * need_des + */ + uint32_t core_efuse_oen:1; + /** slow_oen : R/W; bitpos: [7]; default: 1; + * need_des + */ + uint32_t slow_oen:1; + /** fast_oen : R/W; bitpos: [8]; default: 1; + * need_des + */ + uint32_t fast_oen:1; + /** rng_oen : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t rng_oen:1; + /** lpbus_oen : R/W; bitpos: [10]; default: 1; + * need_des + */ + uint32_t lpbus_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_po_en_reg_t; + +/** Type of lp_clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** fast_ori_gate : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t fast_ori_gate:1; + }; + uint32_t val; +} lp_clkrst_lp_clk_en_reg_t; + +/** Type of lp_rst_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** huk_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t huk_reset_en:1; + /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t aon_efuse_core_reset_en:1; + /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_timer_reset_en:1; + /** wdt_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_reset_en:1; + /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_peri_reset_en:1; + }; + uint32_t val; +} lp_clkrst_lp_rst_en_reg_t; + +/** Type of reset_cause register + * need_des + */ +typedef union { + struct { + /** reset_cause : RO; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t reset_cause:5; + /** core0_reset_flag : RO; bitpos: [5]; default: 1; + * need_des + */ + uint32_t core0_reset_flag:1; + uint32_t reserved_6:23; + /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t core0_reset_cause_clr:1; + /** core0_reset_flag_set : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t core0_reset_flag_set:1; + /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t core0_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_cause_reg_t; + +/** Type of cpu_reset register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1; + * write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup + * reset feature + */ + uint32_t hpcore0_lockup_reset_en:1; + /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; + * need_des + */ + uint32_t rtc_wdt_cpu_reset_length:3; + /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t rtc_wdt_cpu_reset_en:1; + /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; + * need_des + */ + uint32_t cpu_stall_wait:5; + /** cpu_stall_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_reset_reg_t; + +/** Type of fosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172; + * need_des + */ + uint32_t fosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_fosc_cntl_reg_t; + +/** Type of rc32k_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172; + * need_des + */ + uint32_t rc32k_dfreq:10; + }; + uint32_t val; +} lp_clkrst_rc32k_cntl_reg_t; + +/** Type of clk_to_hp register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t icg_hp_xtal32k:1; + /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t icg_hp_sosc:1; + /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t icg_hp_osc32k:1; + /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t icg_hp_fosc:1; + }; + uint32_t val; +} lp_clkrst_clk_to_hp_reg_t; + +/** Type of lpmem_force register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_clkrst_lpmem_force_reg_t; + +/** Type of lpperi register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** huk_clk_sel : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t huk_clk_sel:1; + /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_i2c_clk_sel:1; + /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_uart_clk_sel:1; + }; + uint32_t val; +} lp_clkrst_lpperi_reg_t; + +/** Type of xtal32k register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * need_des + */ + uint32_t dres_xtal32k:3; + /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * need_des + */ + uint32_t dgm_xtal32k:3; + /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t dbuf_xtal32k:1; + /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * need_des + */ + uint32_t dac_xtal32k:3; + }; + uint32_t val; +} lp_clkrst_xtal32k_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** clkrst_date : R/W; bitpos: [30:0]; default: 36720768; + * need_des + */ + uint32_t clkrst_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_clkrst_date_reg_t; + + +typedef struct { + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_cause_reg_t reset_cause; + volatile lp_clkrst_cpu_reset_reg_t cpu_reset; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + volatile lp_clkrst_lpperi_reg_t lpperi; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + uint32_t reserved_030[243]; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; + +extern lp_clkrst_dev_t LP_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_i2c_reg.h b/components/soc/esp32c5/include/soc/lp_i2c_reg.h new file mode 100644 index 0000000000..fc0e24966e --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_i2c_reg.h @@ -0,0 +1,1285 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL + * Clock + */ +#define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0) +/** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock. + * Measurement unit: i2c_sclk. + */ +#define LP_I2C_SCL_LOW_PERIOD 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_M (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S) +#define LP_I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_S 0 + +/** LP_I2C_CTR_REG register + * Transmission setting + */ +#define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4) +/** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA. + * 1: Sample SDA data on the SCL low level. + * + * 0: Sample SDA data on the SCL high level. + */ +#define LP_I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define LP_I2C_SAMPLE_SCL_LEVEL_M (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S) +#define LP_I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define LP_I2C_SAMPLE_SCL_LEVEL_S 2 +/** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold. + */ +#define LP_I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define LP_I2C_RX_FULL_ACK_LEVEL_M (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S) +#define LP_I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define LP_I2C_RX_FULL_ACK_LEVEL_S 3 +/** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Configures to start sending the data in txfifo for slave. + * 0: No effect + * + * 1: Start + */ +#define LP_I2C_TRANS_START (BIT(5)) +#define LP_I2C_TRANS_START_M (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S) +#define LP_I2C_TRANS_START_V 0x00000001U +#define LP_I2C_TRANS_START_S 5 +/** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent. + * 1: send data from the least significant bit, + * + * 0: send data from the most significant bit. + */ +#define LP_I2C_TX_LSB_FIRST (BIT(6)) +#define LP_I2C_TX_LSB_FIRST_M (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S) +#define LP_I2C_TX_LSB_FIRST_V 0x00000001U +#define LP_I2C_TX_LSB_FIRST_S 6 +/** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data. + * 1: receive data from the least significant bit + * + * 0: receive data from the most significant bit. + */ +#define LP_I2C_RX_LSB_FIRST (BIT(7)) +#define LP_I2C_RX_LSB_FIRST_M (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S) +#define LP_I2C_RX_LSB_FIRST_V 0x00000001U +#define LP_I2C_RX_LSB_FIRST_S 7 +/** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers. + * + * 0: Force clock on for registers + * + * 1: Support clock only when registers are read or written to by software. + */ +#define LP_I2C_CLK_EN (BIT(8)) +#define LP_I2C_CLK_EN_M (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S) +#define LP_I2C_CLK_EN_V 0x00000001U +#define LP_I2C_CLK_EN_S 8 +/** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * + * 1: Enable + */ +#define LP_I2C_ARBITRATION_EN (BIT(9)) +#define LP_I2C_ARBITRATION_EN_M (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S) +#define LP_I2C_ARBITRATION_EN_V 0x00000001U +#define LP_I2C_ARBITRATION_EN_S 9 +/** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM. + * 0: No effect + * + * 1: Reset + */ +#define LP_I2C_FSM_RST (BIT(10)) +#define LP_I2C_FSM_RST_M (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S) +#define LP_I2C_FSM_RST_V 0x00000001U +#define LP_I2C_FSM_RST_S 10 +/** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization + * 0: No effect + * + * 1: Synchronize + */ +#define LP_I2C_CONF_UPGATE (BIT(11)) +#define LP_I2C_CONF_UPGATE_M (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S) +#define LP_I2C_CONF_UPGATE_V 0x00000001U +#define LP_I2C_CONF_UPGATE_S 11 + +/** LP_I2C_SR_REG register + * Describe I2C work status. + */ +#define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8) +/** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode. + * 0: ACK, + * + * 1: NACK. + */ +#define LP_I2C_RESP_REC (BIT(0)) +#define LP_I2C_RESP_REC_M (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S) +#define LP_I2C_RESP_REC_V 0x00000001U +#define LP_I2C_RESP_REC_S 0 +/** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * + * 1: Arbitration lost + */ +#define LP_I2C_ARB_LOST (BIT(3)) +#define LP_I2C_ARB_LOST_M (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S) +#define LP_I2C_ARB_LOST_V 0x00000001U +#define LP_I2C_ARB_LOST_S 3 +/** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data, + * + * 0: The I2C bus is in idle state. + */ +#define LP_I2C_BUS_BUSY (BIT(4)) +#define LP_I2C_BUS_BUSY_M (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S) +#define LP_I2C_BUS_BUSY_V 0x00000001U +#define LP_I2C_BUS_BUSY_S 4 +/** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; + * Represents the number of data bytes to be sent. + */ +#define LP_I2C_RXFIFO_CNT 0x0000001FU +#define LP_I2C_RXFIFO_CNT_M (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S) +#define LP_I2C_RXFIFO_CNT_V 0x0000001FU +#define LP_I2C_RXFIFO_CNT_S 8 +/** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; + * Represents the number of data bytes received in RAM. + */ +#define LP_I2C_TXFIFO_CNT 0x0000001FU +#define LP_I2C_TXFIFO_CNT_M (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S) +#define LP_I2C_TXFIFO_CNT_V 0x0000001FU +#define LP_I2C_TXFIFO_CNT_S 18 +/** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine. + * 0: Idle, + * + * 1: Address shift, + * + * 2: ACK address, + * + * 3: Rx data, + * + * 4: Tx data, + * + * 5: Send ACK, + * + * 6: Wait ACK + */ +#define LP_I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_M (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S) +#define LP_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_S 24 +/** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL. + * 0: Idle, + * + * 1: Start, + * + * 2: Negative edge, + * + * 3: Low, + * + * 4: Positive edge, + * + * 5: High, + * + * 6: Stop + */ +#define LP_I2C_SCL_STATE_LAST 0x00000007U +#define LP_I2C_SCL_STATE_LAST_M (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S) +#define LP_I2C_SCL_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_STATE_LAST_S 28 + +/** LP_I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc) +/** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2^(reg_time_out_value). + * Measurement unit: i2c_sclk. + */ +#define LP_I2C_TIME_OUT_VALUE 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_M (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S) +#define LP_I2C_TIME_OUT_VALUE_V 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_S 0 +/** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control. + * 0: No effect + * + * 1: Enable + */ +#define LP_I2C_TIME_OUT_EN (BIT(5)) +#define LP_I2C_TIME_OUT_EN_M (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S) +#define LP_I2C_TIME_OUT_EN_V 0x00000001U +#define LP_I2C_TIME_OUT_EN_S 5 + +/** LP_I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14) +/** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO + */ +#define LP_I2C_RXFIFO_RADDR 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_M (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S) +#define LP_I2C_RXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_S 0 +/** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ +#define LP_I2C_RXFIFO_WADDR 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_M (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S) +#define LP_I2C_RXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_S 5 +/** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ +#define LP_I2C_TXFIFO_RADDR 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_M (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S) +#define LP_I2C_TXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_S 10 +/** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ +#define LP_I2C_TXFIFO_WADDR 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_M (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S) +#define LP_I2C_TXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_S 15 + +/** LP_I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18) +/** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define LP_I2C_RXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_M (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S) +#define LP_I2C_RXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_S 0 +/** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define LP_I2C_TXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_M (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S) +#define LP_I2C_TXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_S 5 +/** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ +#define LP_I2C_NONFIFO_EN (BIT(10)) +#define LP_I2C_NONFIFO_EN_M (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S) +#define LP_I2C_NONFIFO_EN_V 0x00000001U +#define LP_I2C_NONFIFO_EN_S 10 +/** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO. + * 0: No effect + * + * 1: Reset + */ +#define LP_I2C_RX_FIFO_RST (BIT(12)) +#define LP_I2C_RX_FIFO_RST_M (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S) +#define LP_I2C_RX_FIFO_RST_V 0x00000001U +#define LP_I2C_RX_FIFO_RST_S 12 +/** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO. + * 0: No effect + * + * 1: Reset + */ +#define LP_I2C_TX_FIFO_RST (BIT(13)) +#define LP_I2C_TX_FIFO_RST_M (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S) +#define LP_I2C_TX_FIFO_RST_V 0x00000001U +#define LP_I2C_TX_FIFO_RST_S 13 +/** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * + * 1: Enable + */ +#define LP_I2C_FIFO_PRT_EN (BIT(14)) +#define LP_I2C_FIFO_PRT_EN_M (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S) +#define LP_I2C_FIFO_PRT_EN_V 0x00000001U +#define LP_I2C_FIFO_PRT_EN_S 14 + +/** LP_I2C_DATA_REG register + * Rx FIFO read data. + */ +#define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c) +/** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ +#define LP_I2C_FIFO_RDATA 0x000000FFU +#define LP_I2C_FIFO_RDATA_M (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S) +#define LP_I2C_FIFO_RDATA_V 0x000000FFU +#define LP_I2C_FIFO_RDATA_S 0 + +/** LP_I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20) +/** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_RAW_M (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S) +#define LP_I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_RAW_S 0 +/** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_RAW_M (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S) +#define LP_I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_RAW_S 1 +/** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_RAW_M (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S) +#define LP_I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_RAW_S 2 +/** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_RAW (BIT(3)) +#define LP_I2C_END_DETECT_INT_RAW_M (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S) +#define LP_I2C_END_DETECT_INT_RAW_V 0x00000001U +#define LP_I2C_END_DETECT_INT_RAW_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_M (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_M (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_RAW (BIT(8)) +#define LP_I2C_TIME_OUT_INT_RAW_M (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S) +#define LP_I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_RAW_S 8 +/** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_RAW (BIT(9)) +#define LP_I2C_TRANS_START_INT_RAW_M (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S) +#define LP_I2C_TRANS_START_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_START_INT_RAW_S 9 +/** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_RAW (BIT(10)) +#define LP_I2C_NACK_INT_RAW_M (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S) +#define LP_I2C_NACK_INT_RAW_V 0x00000001U +#define LP_I2C_NACK_INT_RAW_S 10 +/** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_RAW_M (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S) +#define LP_I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_RAW_S 11 +/** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_RAW_M (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S) +#define LP_I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_RAW_S 12 +/** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_RAW_M (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_RAW_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_RAW (BIT(15)) +#define LP_I2C_DET_START_INT_RAW_M (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S) +#define LP_I2C_DET_START_INT_RAW_V 0x00000001U +#define LP_I2C_DET_START_INT_RAW_S 15 + +/** LP_I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24) +/** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_CLR_M (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S) +#define LP_I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_CLR_S 0 +/** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_CLR_M (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S) +#define LP_I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_CLR_S 1 +/** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_CLR_M (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S) +#define LP_I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_CLR_S 2 +/** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_CLR (BIT(3)) +#define LP_I2C_END_DETECT_INT_CLR_M (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S) +#define LP_I2C_END_DETECT_INT_CLR_V 0x00000001U +#define LP_I2C_END_DETECT_INT_CLR_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_M (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_M (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_CLR (BIT(8)) +#define LP_I2C_TIME_OUT_INT_CLR_M (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S) +#define LP_I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_CLR_S 8 +/** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_CLR (BIT(9)) +#define LP_I2C_TRANS_START_INT_CLR_M (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S) +#define LP_I2C_TRANS_START_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_START_INT_CLR_S 9 +/** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_CLR (BIT(10)) +#define LP_I2C_NACK_INT_CLR_M (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S) +#define LP_I2C_NACK_INT_CLR_V 0x00000001U +#define LP_I2C_NACK_INT_CLR_S 10 +/** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_CLR_M (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S) +#define LP_I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_CLR_S 11 +/** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_CLR_M (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S) +#define LP_I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_CLR_S 12 +/** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_CLR_M (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_CLR_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_CLR (BIT(15)) +#define LP_I2C_DET_START_INT_CLR_M (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S) +#define LP_I2C_DET_START_INT_CLR_V 0x00000001U +#define LP_I2C_DET_START_INT_CLR_S 15 + +/** LP_I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28) +/** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to anable I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ENA_M (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S) +#define LP_I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ENA_S 0 +/** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to anable I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ENA_M (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S) +#define LP_I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ENA_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ENA_M (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S) +#define LP_I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ENA_S 2 +/** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * Write 1 to anable the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ENA (BIT(3)) +#define LP_I2C_END_DETECT_INT_ENA_M (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S) +#define LP_I2C_END_DETECT_INT_ENA_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ENA_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * Write 1 to anable the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_M (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_M (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * Write 1 to anable the I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ENA (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ENA_M (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S) +#define LP_I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ENA_S 8 +/** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * Write 1 to anable the I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ENA (BIT(9)) +#define LP_I2C_TRANS_START_INT_ENA_M (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S) +#define LP_I2C_TRANS_START_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ENA_S 9 +/** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ENA (BIT(10)) +#define LP_I2C_NACK_INT_ENA_M (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S) +#define LP_I2C_NACK_INT_ENA_V 0x00000001U +#define LP_I2C_NACK_INT_ENA_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ENA_M (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S) +#define LP_I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ENA_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ENA_M (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S) +#define LP_I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ENA_S 12 +/** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * Write 1 to anable I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ENA_M (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ENA_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * Write 1 to anable I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ENA (BIT(15)) +#define LP_I2C_DET_START_INT_ENA_M (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S) +#define LP_I2C_DET_START_INT_ENA_V 0x00000001U +#define LP_I2C_DET_START_INT_ENA_S 15 + +/** LP_I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c) +/** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ +#define LP_I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ST_M (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S) +#define LP_I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ST_S 0 +/** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ +#define LP_I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ST_M (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S) +#define LP_I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ST_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ST_M (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S) +#define LP_I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ST_S 2 +/** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_END_DETECT_INT_ST (BIT(3)) +#define LP_I2C_END_DETECT_INT_ST_M (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S) +#define LP_I2C_END_DETECT_INT_ST_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ST_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ +#define LP_I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_M (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define LP_I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ST_M (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S) +#define LP_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ST_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_M (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define LP_I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ST_M (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S) +#define LP_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ST_S 7 +/** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ +#define LP_I2C_TIME_OUT_INT_ST (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ST_M (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S) +#define LP_I2C_TIME_OUT_INT_ST_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ST_S 8 +/** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ +#define LP_I2C_TRANS_START_INT_ST (BIT(9)) +#define LP_I2C_TRANS_START_INT_ST_M (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S) +#define LP_I2C_TRANS_START_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ST_S 9 +/** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ +#define LP_I2C_NACK_INT_ST (BIT(10)) +#define LP_I2C_NACK_INT_ST_M (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S) +#define LP_I2C_NACK_INT_ST_V 0x00000001U +#define LP_I2C_NACK_INT_ST_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ +#define LP_I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ST_M (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S) +#define LP_I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ST_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ +#define LP_I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ST_M (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S) +#define LP_I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ST_S 12 +/** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ST_M (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S) +#define LP_I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ST_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ +#define LP_I2C_DET_START_INT_ST (BIT(15)) +#define LP_I2C_DET_START_INT_ST_M (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S) +#define LP_I2C_DET_START_INT_ST_V 0x00000001U +#define LP_I2C_DET_START_INT_ST_S 15 + +/** LP_I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30) +/** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SDA_HOLD_TIME 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_M (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S) +#define LP_I2C_SDA_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_S 0 + +/** LP_I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34) +/** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * Configures the sample time after a positive SCL edge. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SDA_SAMPLE_TIME 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_M (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S) +#define LP_I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_S 0 + +/** LP_I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38) +/** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_HIGH_PERIOD 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_M (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S) +#define LP_I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_S 0 +/** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_M (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S) +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/** LP_I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40) +/** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: i2c_sclk. + */ +#define LP_I2C_SCL_START_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_M (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S) +#define LP_I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_S 0 + +/** LP_I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +#define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44) +/** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_M (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S) +#define LP_I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_S 0 + +/** LP_I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +#define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48) +/** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_M (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S) +#define LP_I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_S 0 + +/** LP_I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +#define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c) +/** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_M (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S) +#define LP_I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_S 0 + +/** LP_I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50) +/** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_FILTER_THRES 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_M (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S) +#define LP_I2C_SCL_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_S 0 +/** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SDA_FILTER_THRES 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_M (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S) +#define LP_I2C_SDA_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_S 4 +/** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. + */ +#define LP_I2C_SCL_FILTER_EN (BIT(8)) +#define LP_I2C_SCL_FILTER_EN_M (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S) +#define LP_I2C_SCL_FILTER_EN_V 0x00000001U +#define LP_I2C_SCL_FILTER_EN_S 8 +/** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. + */ +#define LP_I2C_SDA_FILTER_EN (BIT(9)) +#define LP_I2C_SDA_FILTER_EN_M (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S) +#define LP_I2C_SDA_FILTER_EN_V 0x00000001U +#define LP_I2C_SDA_FILTER_EN_S 9 + +/** LP_I2C_CLK_CONF_REG register + * I2C CLK configuration register + */ +#define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54) +/** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_NUM 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_M (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S) +#define LP_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_S 0 +/** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_A 0x0000003FU +#define LP_I2C_SCLK_DIV_A_M (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S) +#define LP_I2C_SCLK_DIV_A_V 0x0000003FU +#define LP_I2C_SCLK_DIV_A_S 8 +/** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ +#define LP_I2C_SCLK_DIV_B 0x0000003FU +#define LP_I2C_SCLK_DIV_B_M (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S) +#define LP_I2C_SCLK_DIV_B_V 0x0000003FU +#define LP_I2C_SCLK_DIV_B_S 14 +/** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ +#define LP_I2C_SCLK_SEL (BIT(20)) +#define LP_I2C_SCLK_SEL_M (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S) +#define LP_I2C_SCLK_SEL_V 0x00000001U +#define LP_I2C_SCLK_SEL_S 20 +/** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ +#define LP_I2C_SCLK_ACTIVE (BIT(21)) +#define LP_I2C_SCLK_ACTIVE_M (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S) +#define LP_I2C_SCLK_ACTIVE_V 0x00000001U +#define LP_I2C_SCLK_ACTIVE_S 21 + +/** LP_I2C_COMD0_REG register + * I2C command register 0 + */ +#define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58) +/** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + */ +#define LP_I2C_COMMAND0 0x00003FFFU +#define LP_I2C_COMMAND0_M (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S) +#define LP_I2C_COMMAND0_V 0x00003FFFU +#define LP_I2C_COMMAND0_S 0 +/** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND0_DONE (BIT(31)) +#define LP_I2C_COMMAND0_DONE_M (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S) +#define LP_I2C_COMMAND0_DONE_V 0x00000001U +#define LP_I2C_COMMAND0_DONE_S 31 + +/** LP_I2C_COMD1_REG register + * I2C command register 1 + */ +#define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c) +/** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * Configures command 1. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND1 0x00003FFFU +#define LP_I2C_COMMAND1_M (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S) +#define LP_I2C_COMMAND1_V 0x00003FFFU +#define LP_I2C_COMMAND1_S 0 +/** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND1_DONE (BIT(31)) +#define LP_I2C_COMMAND1_DONE_M (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S) +#define LP_I2C_COMMAND1_DONE_V 0x00000001U +#define LP_I2C_COMMAND1_DONE_S 31 + +/** LP_I2C_COMD2_REG register + * I2C command register 2 + */ +#define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60) +/** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * Configures command 2. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND2 0x00003FFFU +#define LP_I2C_COMMAND2_M (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S) +#define LP_I2C_COMMAND2_V 0x00003FFFU +#define LP_I2C_COMMAND2_S 0 +/** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND2_DONE (BIT(31)) +#define LP_I2C_COMMAND2_DONE_M (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S) +#define LP_I2C_COMMAND2_DONE_V 0x00000001U +#define LP_I2C_COMMAND2_DONE_S 31 + +/** LP_I2C_COMD3_REG register + * I2C command register 3 + */ +#define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64) +/** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * Configures command 3. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND3 0x00003FFFU +#define LP_I2C_COMMAND3_M (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S) +#define LP_I2C_COMMAND3_V 0x00003FFFU +#define LP_I2C_COMMAND3_S 0 +/** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND3_DONE (BIT(31)) +#define LP_I2C_COMMAND3_DONE_M (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S) +#define LP_I2C_COMMAND3_DONE_V 0x00000001U +#define LP_I2C_COMMAND3_DONE_S 31 + +/** LP_I2C_COMD4_REG register + * I2C command register 4 + */ +#define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68) +/** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * Configures command 4. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND4 0x00003FFFU +#define LP_I2C_COMMAND4_M (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S) +#define LP_I2C_COMMAND4_V 0x00003FFFU +#define LP_I2C_COMMAND4_S 0 +/** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND4_DONE (BIT(31)) +#define LP_I2C_COMMAND4_DONE_M (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S) +#define LP_I2C_COMMAND4_DONE_V 0x00000001U +#define LP_I2C_COMMAND4_DONE_S 31 + +/** LP_I2C_COMD5_REG register + * I2C command register 5 + */ +#define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c) +/** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * Configures command 5. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND5 0x00003FFFU +#define LP_I2C_COMMAND5_M (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S) +#define LP_I2C_COMMAND5_V 0x00003FFFU +#define LP_I2C_COMMAND5_S 0 +/** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND5_DONE (BIT(31)) +#define LP_I2C_COMMAND5_DONE_M (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S) +#define LP_I2C_COMMAND5_DONE_V 0x00000001U +#define LP_I2C_COMMAND5_DONE_S 31 + +/** LP_I2C_COMD6_REG register + * I2C command register 6 + */ +#define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70) +/** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * Configures command 6. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND6 0x00003FFFU +#define LP_I2C_COMMAND6_M (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S) +#define LP_I2C_COMMAND6_V 0x00003FFFU +#define LP_I2C_COMMAND6_S 0 +/** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND6_DONE (BIT(31)) +#define LP_I2C_COMMAND6_DONE_M (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S) +#define LP_I2C_COMMAND6_DONE_V 0x00000001U +#define LP_I2C_COMMAND6_DONE_S 31 + +/** LP_I2C_COMD7_REG register + * I2C command register 7 + */ +#define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74) +/** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * Configures command 7. See details in I2C_CMD0_REG[13:0]. + */ +#define LP_I2C_COMMAND7 0x00003FFFU +#define LP_I2C_COMMAND7_M (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S) +#define LP_I2C_COMMAND7_V 0x00003FFFU +#define LP_I2C_COMMAND7_S 0 +/** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ +#define LP_I2C_COMMAND7_DONE (BIT(31)) +#define LP_I2C_COMMAND7_DONE_M (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S) +#define LP_I2C_COMMAND7_DONE_V 0x00000001U +#define LP_I2C_COMMAND7_DONE_S 31 + +/** LP_I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78) +/** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_ST_TO_I2C_M (LP_I2C_SCL_ST_TO_I2C_V << LP_I2C_SCL_ST_TO_I2C_S) +#define LP_I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define LP_I2C_SCL_ST_TO_I2C_S 0 + +/** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c) +/** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be + * no more than 23. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_I2C_M (LP_I2C_SCL_MAIN_ST_TO_I2C_V << LP_I2C_SCL_MAIN_ST_TO_I2C_S) +#define LP_I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_I2C_S 0 + +/** LP_I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80) +/** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define LP_I2C_SCL_RST_SLV_EN (BIT(0)) +#define LP_I2C_SCL_RST_SLV_EN_M (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S) +#define LP_I2C_SCL_RST_SLV_EN_V 0x00000001U +#define LP_I2C_SCL_RST_SLV_EN_S 0 +/** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ +#define LP_I2C_SCL_RST_SLV_NUM 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_M (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S) +#define LP_I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_S 1 +/** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. + * Valid when reg_scl_rst_slv_en is 1. + * Measurement unit: i2c_sclk + */ +#define LP_I2C_SCL_PD_EN (BIT(6)) +#define LP_I2C_SCL_PD_EN_M (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S) +#define LP_I2C_SCL_PD_EN_V 0x00000001U +#define LP_I2C_SCL_PD_EN_S 6 +/** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_scl_force_out is 1. + */ +#define LP_I2C_SDA_PD_EN (BIT(7)) +#define LP_I2C_SDA_PD_EN_M (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S) +#define LP_I2C_SDA_PD_EN_V 0x00000001U +#define LP_I2C_SDA_PD_EN_S 7 + +/** LP_I2C_DATE_REG register + * Version register + */ +#define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8) +/** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 35656003; + * Version control register. + */ +#define LP_I2C_DATE 0xFFFFFFFFU +#define LP_I2C_DATE_M (LP_I2C_DATE_V << LP_I2C_DATE_S) +#define LP_I2C_DATE_V 0xFFFFFFFFU +#define LP_I2C_DATE_S 0 + +/** LP_I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100) +/** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ +#define LP_I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_M (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S) +#define LP_I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_S 0 + +/** LP_I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180) +/** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ +#define LP_I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_M (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S) +#define LP_I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_i2c_struct.h b/components/soc/esp32c5/include/soc/lp_i2c_struct.h new file mode 100644 index 0000000000..c548c282a1 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_i2c_struct.h @@ -0,0 +1,1118 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * Configures the low level width of the SCL Clock. + * Measurement unit: i2c_sclk. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * Configures the sample time after a positive SCL edge. + * Measurement unit: i2c_sclk + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the falling edge of SDA and the falling edge of SCL for + * a START condition. + * Measurement unit: i2c_sclk. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the positive edge of SCL and the negative edge of SDA + * for a RESTART condition. + * Measurement unit: i2c_sclk + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * Configures the time between the rising edge of SCL and the rising edge of SDA. + * Measurement unit: i2c_sclk + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_FSM state unchanged period. It should be no + * more than 23. + * Measurement unit: i2c_sclk + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be + * no more than 23. + * Measurement unit: i2c_sclk + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} lp_i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * Configures the sample mode for SDA. + * 1: Sample SDA data on the SCL low level. + * + * 0: Sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has + * reached the threshold. + */ + uint32_t rx_full_ack_level:1; + uint32_t reserved_4:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Configures to start sending the data in txfifo for slave. + * 0: No effect + * + * 1: Start + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * Configures to control the sending order for data needing to be sent. + * 1: send data from the least significant bit, + * + * 0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * Configures to control the storage order for received data. + * 1: receive data from the least significant bit + * + * 0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Configures whether to gate clock signal for registers. + * + * 0: Force clock on for registers + * + * 1: Support clock only when registers are read or written to by software. + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * + * 1: Enable + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * Configures to reset the SCL_FSM. + * 0: No effect + * + * 1: Reset + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * Configures this bit for synchronization + * 0: No effect + * + * 1: Synchronize + */ + uint32_t conf_upgate:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * Configures the timeout threshold period for SCL stucking at high or low level. The + * actual period is 2^(reg_time_out_value). + * Measurement unit: i2c_sclk. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * Configures to enable time out control. + * 0: No effect + * + * 1: Enable + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} lp_i2c_to_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6; + * Configures the water mark threshold of RXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:4; + uint32_t reserved_4:1; + /** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2; + * Configures the water mark threshold of TXFIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:4; + uint32_t reserved_9:1; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Configures to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + uint32_t reserved_11:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Configures to reset RXFIFO. + * 0: No effect + * + * 1: Reset + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Configures to reset TXFIFO. + * 0: No effect + * + * 1: Reset + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * + * 1: Enable + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA + * input has smaller width than this register value, the I2C controller will ignore + * that pulse. + * Measurement unit: i2c_sclk + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * Configures to enable the filter function for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * Configures to enable the filter function for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} lp_i2c_filter_cfg_reg_t; + +/** Type of clk_conf register + * I2C CLK configuration register + */ +typedef union { + struct { + /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + */ + uint32_t sclk_sel:1; + /** sclk_active : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ + uint32_t sclk_active:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} lp_i2c_clk_conf_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configures to send out SCL pulses when I2C master is IDLE. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. + * Valid when reg_scl_rst_slv_en is 1. + * Measurement unit: i2c_sclk + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * + * 1: Power down. + * Valid only when reg_scl_force_out is 1. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_i2c_scl_sp_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * Represents the received ACK value in master mode or slave mode. + * 0: ACK, + * + * 1: NACK. + */ + uint32_t resp_rec:1; + uint32_t reserved_1:2; + /** arb_lost : RO; bitpos: [3]; default: 0; + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * + * 1: Arbitration lost + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data, + * + * 0: The I2C bus is in idle state. + */ + uint32_t bus_busy:1; + uint32_t reserved_5:3; + /** rxfifo_cnt : RO; bitpos: [12:8]; default: 0; + * Represents the number of data bytes to be sent. + */ + uint32_t rxfifo_cnt:5; + uint32_t reserved_13:5; + /** txfifo_cnt : RO; bitpos: [22:18]; default: 0; + * Represents the number of data bytes received in RAM. + */ + uint32_t txfifo_cnt:5; + uint32_t reserved_23:1; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * Represents the states of the I2C module state machine. + * 0: Idle, + * + * 1: Address shift, + * + * 2: ACK address, + * + * 3: Rx data, + * + * 4: Tx data, + * + * 5: Send ACK, + * + * 6: Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * Represents the states of the state machine used to produce SCL. + * 0: Idle, + * + * 1: Start, + * + * 2: Negative edge, + * + * 3: Low, + * + * 4: Positive edge, + * + * 5: High, + * + * 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} lp_i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [3:0]; default: 0; + * Represents the offset address of the APB reading from RXFIFO + */ + uint32_t rxfifo_raddr:4; + uint32_t reserved_4:1; + /** rxfifo_waddr : RO; bitpos: [8:5]; default: 0; + * Represents the offset address of i2c module receiving data and writing to RXFIFO. + */ + uint32_t rxfifo_waddr:4; + uint32_t reserved_9:1; + /** txfifo_raddr : RO; bitpos: [13:10]; default: 0; + * Represents the offset address of i2c module reading from TXFIFO. + */ + uint32_t txfifo_raddr:4; + uint32_t reserved_14:1; + /** txfifo_waddr : RO; bitpos: [18:15]; default: 0; + * Represents the offset address of APB bus writing to TXFIFO. + */ + uint32_t txfifo_waddr:4; + uint32_t reserved_19:13; + }; + uint32_t val; +} lp_i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : RO; bitpos: [7:0]; default: 0; + * Represents the value of RXFIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Write 1 to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Write 1 to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Write 1 to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to anable I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to anable I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * Write 1 to anable the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * Write 1 to anable the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * Write 1 to anable the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * Write 1 to anable the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * Write 1 to anable I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * Write 1 to anable I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status status of I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd0 register + * I2C command register 0 + */ +typedef union { + struct { + /** command0 : R/W; bitpos: [13:0]; default: 0; + * Configures command 0. It consists of three parts: + * op_code is the command, + * 0: RSTART, + * 1: WRITE, + * 2: READ, + * 3: STOP, + * 4: END. + * + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more information. + */ + uint32_t command0:14; + uint32_t reserved_14:17; + /** command0_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command0_done:1; + }; + uint32_t val; +} lp_i2c_comd0_reg_t; + +/** Type of comd1 register + * I2C command register 1 + */ +typedef union { + struct { + /** command1 : R/W; bitpos: [13:0]; default: 0; + * Configures command 1. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command1:14; + uint32_t reserved_14:17; + /** command1_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command1_done:1; + }; + uint32_t val; +} lp_i2c_comd1_reg_t; + +/** Type of comd2 register + * I2C command register 2 + */ +typedef union { + struct { + /** command2 : R/W; bitpos: [13:0]; default: 0; + * Configures command 2. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command2:14; + uint32_t reserved_14:17; + /** command2_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command2_done:1; + }; + uint32_t val; +} lp_i2c_comd2_reg_t; + +/** Type of comd3 register + * I2C command register 3 + */ +typedef union { + struct { + /** command3 : R/W; bitpos: [13:0]; default: 0; + * Configures command 3. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command3:14; + uint32_t reserved_14:17; + /** command3_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command3_done:1; + }; + uint32_t val; +} lp_i2c_comd3_reg_t; + +/** Type of comd4 register + * I2C command register 4 + */ +typedef union { + struct { + /** command4 : R/W; bitpos: [13:0]; default: 0; + * Configures command 4. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command4:14; + uint32_t reserved_14:17; + /** command4_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command4_done:1; + }; + uint32_t val; +} lp_i2c_comd4_reg_t; + +/** Type of comd5 register + * I2C command register 5 + */ +typedef union { + struct { + /** command5 : R/W; bitpos: [13:0]; default: 0; + * Configures command 5. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command5:14; + uint32_t reserved_14:17; + /** command5_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command5_done:1; + }; + uint32_t val; +} lp_i2c_comd5_reg_t; + +/** Type of comd6 register + * I2C command register 6 + */ +typedef union { + struct { + /** command6 : R/W; bitpos: [13:0]; default: 0; + * Configures command 6. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command6:14; + uint32_t reserved_14:17; + /** command6_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command6_done:1; + }; + uint32_t val; +} lp_i2c_comd6_reg_t; + +/** Type of comd7 register + * I2C command register 7 + */ +typedef union { + struct { + /** command7 : R/W; bitpos: [13:0]; default: 0; + * Configures command 7. See details in I2C_CMD0_REG[13:0]. + */ + uint32_t command7:14; + uint32_t reserved_14:17; + /** command7_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * + * 1: Done + */ + uint32_t command7_done:1; + }; + uint32_t val; +} lp_i2c_comd7_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656003; + * Version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} lp_i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} lp_i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} lp_i2c_rxfifo_start_addr_reg_t; + + +typedef struct { + volatile lp_i2c_scl_low_period_reg_t scl_low_period; + volatile lp_i2c_ctr_reg_t ctr; + volatile lp_i2c_sr_reg_t sr; + volatile lp_i2c_to_reg_t to; + uint32_t reserved_010; + volatile lp_i2c_fifo_st_reg_t fifo_st; + volatile lp_i2c_fifo_conf_reg_t fifo_conf; + volatile lp_i2c_data_reg_t data; + volatile lp_i2c_int_raw_reg_t int_raw; + volatile lp_i2c_int_clr_reg_t int_clr; + volatile lp_i2c_int_ena_reg_t int_ena; + volatile lp_i2c_int_status_reg_t int_status; + volatile lp_i2c_sda_hold_reg_t sda_hold; + volatile lp_i2c_sda_sample_reg_t sda_sample; + volatile lp_i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile lp_i2c_scl_start_hold_reg_t scl_start_hold; + volatile lp_i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile lp_i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile lp_i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile lp_i2c_filter_cfg_reg_t filter_cfg; + volatile lp_i2c_clk_conf_reg_t clk_conf; + volatile lp_i2c_comd0_reg_t comd0; + volatile lp_i2c_comd1_reg_t comd1; + volatile lp_i2c_comd2_reg_t comd2; + volatile lp_i2c_comd3_reg_t comd3; + volatile lp_i2c_comd4_reg_t comd4; + volatile lp_i2c_comd5_reg_t comd5; + volatile lp_i2c_comd6_reg_t comd6; + volatile lp_i2c_comd7_reg_t comd7; + volatile lp_i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile lp_i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile lp_i2c_scl_sp_conf_reg_t scl_sp_conf; + uint32_t reserved_084[29]; + volatile lp_i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile lp_i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile lp_i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; +} lp_i2c_dev_t; + +extern lp_i2c_dev_t LP_I2C; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_i2c_dev_t) == 0x184, "Invalid size of lp_i2c_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_io_reg.h b/components/soc/esp32c5/include/soc/lp_io_reg.h new file mode 100644 index 0000000000..6382de6eed --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_io_reg.h @@ -0,0 +1,1263 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_IO_OUT_DATA_REG register + * need des + */ +#define LP_IO_OUT_DATA_REG (DR_REG_LP_IO_BASE + 0x0) +/** LP_IO_LP_GPIO_OUT_DATA : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_OUT_DATA 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_M (LP_IO_LP_GPIO_OUT_DATA_V << LP_IO_LP_GPIO_OUT_DATA_S) +#define LP_IO_LP_GPIO_OUT_DATA_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_S 0 + +/** LP_IO_OUT_DATA_W1TS_REG register + * need des + */ +#define LP_IO_OUT_DATA_W1TS_REG (DR_REG_LP_IO_BASE + 0x4) +/** LP_IO_LP_GPIO_OUT_DATA_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_OUT_DATA_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_M (LP_IO_LP_GPIO_OUT_DATA_W1TS_V << LP_IO_LP_GPIO_OUT_DATA_W1TS_S) +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TS_S 0 + +/** LP_IO_OUT_DATA_W1TC_REG register + * need des + */ +#define LP_IO_OUT_DATA_W1TC_REG (DR_REG_LP_IO_BASE + 0x8) +/** LP_IO_LP_GPIO_OUT_DATA_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_OUT_DATA_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_M (LP_IO_LP_GPIO_OUT_DATA_W1TC_V << LP_IO_LP_GPIO_OUT_DATA_W1TC_S) +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_OUT_DATA_W1TC_S 0 + +/** LP_IO_OUT_ENABLE_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_REG (DR_REG_LP_IO_BASE + 0xc) +/** LP_IO_LP_GPIO_ENABLE : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_ENABLE 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_M (LP_IO_LP_GPIO_ENABLE_V << LP_IO_LP_GPIO_ENABLE_S) +#define LP_IO_LP_GPIO_ENABLE_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_S 0 + +/** LP_IO_OUT_ENABLE_W1TS_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_W1TS_REG (DR_REG_LP_IO_BASE + 0x10) +/** LP_IO_LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_ENABLE_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TS_M (LP_IO_LP_GPIO_ENABLE_W1TS_V << LP_IO_LP_GPIO_ENABLE_W1TS_S) +#define LP_IO_LP_GPIO_ENABLE_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TS_S 0 + +/** LP_IO_OUT_ENABLE_W1TC_REG register + * need des + */ +#define LP_IO_OUT_ENABLE_W1TC_REG (DR_REG_LP_IO_BASE + 0x14) +/** LP_IO_LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_ENABLE_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TC_M (LP_IO_LP_GPIO_ENABLE_W1TC_V << LP_IO_LP_GPIO_ENABLE_W1TC_S) +#define LP_IO_LP_GPIO_ENABLE_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_ENABLE_W1TC_S 0 + +/** LP_IO_STATUS_REG register + * need des + */ +#define LP_IO_STATUS_REG (DR_REG_LP_IO_BASE + 0x18) +/** LP_IO_LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ +#define LP_IO_LP_GPIO_STATUS_INTERRUPT 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_M (LP_IO_LP_GPIO_STATUS_INTERRUPT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_S) +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_INTERRUPT_S 0 + +/** LP_IO_STATUS_W1TS_REG register + * need des + */ +#define LP_IO_STATUS_W1TS_REG (DR_REG_LP_IO_BASE + 0x1c) +/** LP_IO_LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ +#define LP_IO_LP_GPIO_STATUS_W1TS 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TS_M (LP_IO_LP_GPIO_STATUS_W1TS_V << LP_IO_LP_GPIO_STATUS_W1TS_S) +#define LP_IO_LP_GPIO_STATUS_W1TS_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TS_S 0 + +/** LP_IO_STATUS_W1TC_REG register + * need des + */ +#define LP_IO_STATUS_W1TC_REG (DR_REG_LP_IO_BASE + 0x20) +/** LP_IO_LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ +#define LP_IO_LP_GPIO_STATUS_W1TC 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TC_M (LP_IO_LP_GPIO_STATUS_W1TC_V << LP_IO_LP_GPIO_STATUS_W1TC_S) +#define LP_IO_LP_GPIO_STATUS_W1TC_V 0x000000FFU +#define LP_IO_LP_GPIO_STATUS_W1TC_S 0 + +/** LP_IO_IN_REG register + * need des + */ +#define LP_IO_IN_REG (DR_REG_LP_IO_BASE + 0x24) +/** LP_IO_LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO_IN_DATA_NEXT 0x000000FFU +#define LP_IO_LP_GPIO_IN_DATA_NEXT_M (LP_IO_LP_GPIO_IN_DATA_NEXT_V << LP_IO_LP_GPIO_IN_DATA_NEXT_S) +#define LP_IO_LP_GPIO_IN_DATA_NEXT_V 0x000000FFU +#define LP_IO_LP_GPIO_IN_DATA_NEXT_S 0 + +/** LP_IO_PIN0_REG register + * need des + */ +#define LP_IO_PIN0_REG (DR_REG_LP_IO_BASE + 0x28) +/** LP_IO_LP_GPIO0_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO0_SYNC_BYPASS_M (LP_IO_LP_GPIO0_SYNC_BYPASS_V << LP_IO_LP_GPIO0_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO0_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO0_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO0_PAD_DRIVER_M (LP_IO_LP_GPIO0_PAD_DRIVER_V << LP_IO_LP_GPIO0_PAD_DRIVER_S) +#define LP_IO_LP_GPIO0_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO0_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO0_INT_TYPE_M (LP_IO_LP_GPIO0_INT_TYPE_V << LP_IO_LP_GPIO0_INT_TYPE_S) +#define LP_IO_LP_GPIO0_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO0_INT_TYPE_S 7 +/** LP_IO_LP_GPIO0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_M (LP_IO_LP_GPIO0_WAKEUP_ENABLE_V << LP_IO_LP_GPIO0_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO0_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO0_FILTER_EN_M (LP_IO_LP_GPIO0_FILTER_EN_V << LP_IO_LP_GPIO0_FILTER_EN_S) +#define LP_IO_LP_GPIO0_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO0_FILTER_EN_S 11 + +/** LP_IO_PIN1_REG register + * need des + */ +#define LP_IO_PIN1_REG (DR_REG_LP_IO_BASE + 0x2c) +/** LP_IO_LP_GPIO1_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO1_SYNC_BYPASS_M (LP_IO_LP_GPIO1_SYNC_BYPASS_V << LP_IO_LP_GPIO1_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO1_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO1_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO1_PAD_DRIVER_M (LP_IO_LP_GPIO1_PAD_DRIVER_V << LP_IO_LP_GPIO1_PAD_DRIVER_S) +#define LP_IO_LP_GPIO1_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO1_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO1_INT_TYPE_M (LP_IO_LP_GPIO1_INT_TYPE_V << LP_IO_LP_GPIO1_INT_TYPE_S) +#define LP_IO_LP_GPIO1_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO1_INT_TYPE_S 7 +/** LP_IO_LP_GPIO1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_M (LP_IO_LP_GPIO1_WAKEUP_ENABLE_V << LP_IO_LP_GPIO1_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO1_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO1_FILTER_EN_M (LP_IO_LP_GPIO1_FILTER_EN_V << LP_IO_LP_GPIO1_FILTER_EN_S) +#define LP_IO_LP_GPIO1_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO1_FILTER_EN_S 11 + +/** LP_IO_PIN2_REG register + * need des + */ +#define LP_IO_PIN2_REG (DR_REG_LP_IO_BASE + 0x30) +/** LP_IO_LP_GPIO2_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO2_SYNC_BYPASS_M (LP_IO_LP_GPIO2_SYNC_BYPASS_V << LP_IO_LP_GPIO2_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO2_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO2_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO2_PAD_DRIVER_M (LP_IO_LP_GPIO2_PAD_DRIVER_V << LP_IO_LP_GPIO2_PAD_DRIVER_S) +#define LP_IO_LP_GPIO2_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO2_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO2_INT_TYPE_M (LP_IO_LP_GPIO2_INT_TYPE_V << LP_IO_LP_GPIO2_INT_TYPE_S) +#define LP_IO_LP_GPIO2_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO2_INT_TYPE_S 7 +/** LP_IO_LP_GPIO2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_M (LP_IO_LP_GPIO2_WAKEUP_ENABLE_V << LP_IO_LP_GPIO2_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO2_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO2_FILTER_EN_M (LP_IO_LP_GPIO2_FILTER_EN_V << LP_IO_LP_GPIO2_FILTER_EN_S) +#define LP_IO_LP_GPIO2_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO2_FILTER_EN_S 11 + +/** LP_IO_PIN3_REG register + * need des + */ +#define LP_IO_PIN3_REG (DR_REG_LP_IO_BASE + 0x34) +/** LP_IO_LP_GPIO3_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO3_SYNC_BYPASS_M (LP_IO_LP_GPIO3_SYNC_BYPASS_V << LP_IO_LP_GPIO3_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO3_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO3_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO3_PAD_DRIVER_M (LP_IO_LP_GPIO3_PAD_DRIVER_V << LP_IO_LP_GPIO3_PAD_DRIVER_S) +#define LP_IO_LP_GPIO3_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO3_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO3_INT_TYPE_M (LP_IO_LP_GPIO3_INT_TYPE_V << LP_IO_LP_GPIO3_INT_TYPE_S) +#define LP_IO_LP_GPIO3_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO3_INT_TYPE_S 7 +/** LP_IO_LP_GPIO3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_M (LP_IO_LP_GPIO3_WAKEUP_ENABLE_V << LP_IO_LP_GPIO3_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO3_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO3_FILTER_EN_M (LP_IO_LP_GPIO3_FILTER_EN_V << LP_IO_LP_GPIO3_FILTER_EN_S) +#define LP_IO_LP_GPIO3_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO3_FILTER_EN_S 11 + +/** LP_IO_PIN4_REG register + * need des + */ +#define LP_IO_PIN4_REG (DR_REG_LP_IO_BASE + 0x38) +/** LP_IO_LP_GPIO4_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO4_SYNC_BYPASS_M (LP_IO_LP_GPIO4_SYNC_BYPASS_V << LP_IO_LP_GPIO4_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO4_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO4_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO4_PAD_DRIVER_M (LP_IO_LP_GPIO4_PAD_DRIVER_V << LP_IO_LP_GPIO4_PAD_DRIVER_S) +#define LP_IO_LP_GPIO4_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO4_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO4_INT_TYPE_M (LP_IO_LP_GPIO4_INT_TYPE_V << LP_IO_LP_GPIO4_INT_TYPE_S) +#define LP_IO_LP_GPIO4_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO4_INT_TYPE_S 7 +/** LP_IO_LP_GPIO4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_M (LP_IO_LP_GPIO4_WAKEUP_ENABLE_V << LP_IO_LP_GPIO4_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO4_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO4_FILTER_EN_M (LP_IO_LP_GPIO4_FILTER_EN_V << LP_IO_LP_GPIO4_FILTER_EN_S) +#define LP_IO_LP_GPIO4_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO4_FILTER_EN_S 11 + +/** LP_IO_PIN5_REG register + * need des + */ +#define LP_IO_PIN5_REG (DR_REG_LP_IO_BASE + 0x3c) +/** LP_IO_LP_GPIO5_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO5_SYNC_BYPASS_M (LP_IO_LP_GPIO5_SYNC_BYPASS_V << LP_IO_LP_GPIO5_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO5_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO5_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO5_PAD_DRIVER_M (LP_IO_LP_GPIO5_PAD_DRIVER_V << LP_IO_LP_GPIO5_PAD_DRIVER_S) +#define LP_IO_LP_GPIO5_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO5_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO5_INT_TYPE_M (LP_IO_LP_GPIO5_INT_TYPE_V << LP_IO_LP_GPIO5_INT_TYPE_S) +#define LP_IO_LP_GPIO5_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO5_INT_TYPE_S 7 +/** LP_IO_LP_GPIO5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_M (LP_IO_LP_GPIO5_WAKEUP_ENABLE_V << LP_IO_LP_GPIO5_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO5_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO5_FILTER_EN_M (LP_IO_LP_GPIO5_FILTER_EN_V << LP_IO_LP_GPIO5_FILTER_EN_S) +#define LP_IO_LP_GPIO5_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO5_FILTER_EN_S 11 + +/** LP_IO_PIN6_REG register + * need des + */ +#define LP_IO_PIN6_REG (DR_REG_LP_IO_BASE + 0x40) +/** LP_IO_LP_GPIO6_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO6_SYNC_BYPASS_M (LP_IO_LP_GPIO6_SYNC_BYPASS_V << LP_IO_LP_GPIO6_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO6_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO6_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO6_PAD_DRIVER_M (LP_IO_LP_GPIO6_PAD_DRIVER_V << LP_IO_LP_GPIO6_PAD_DRIVER_S) +#define LP_IO_LP_GPIO6_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO6_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO6_INT_TYPE_M (LP_IO_LP_GPIO6_INT_TYPE_V << LP_IO_LP_GPIO6_INT_TYPE_S) +#define LP_IO_LP_GPIO6_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO6_INT_TYPE_S 7 +/** LP_IO_LP_GPIO6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_M (LP_IO_LP_GPIO6_WAKEUP_ENABLE_V << LP_IO_LP_GPIO6_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO6_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO6_FILTER_EN_M (LP_IO_LP_GPIO6_FILTER_EN_V << LP_IO_LP_GPIO6_FILTER_EN_S) +#define LP_IO_LP_GPIO6_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO6_FILTER_EN_S 11 + +/** LP_IO_PIN7_REG register + * need des + */ +#define LP_IO_PIN7_REG (DR_REG_LP_IO_BASE + 0x44) +/** LP_IO_LP_GPIO7_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_SYNC_BYPASS 0x00000003U +#define LP_IO_LP_GPIO7_SYNC_BYPASS_M (LP_IO_LP_GPIO7_SYNC_BYPASS_V << LP_IO_LP_GPIO7_SYNC_BYPASS_S) +#define LP_IO_LP_GPIO7_SYNC_BYPASS_V 0x00000003U +#define LP_IO_LP_GPIO7_SYNC_BYPASS_S 0 +/** LP_IO_LP_GPIO7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_PAD_DRIVER (BIT(2)) +#define LP_IO_LP_GPIO7_PAD_DRIVER_M (LP_IO_LP_GPIO7_PAD_DRIVER_V << LP_IO_LP_GPIO7_PAD_DRIVER_S) +#define LP_IO_LP_GPIO7_PAD_DRIVER_V 0x00000001U +#define LP_IO_LP_GPIO7_PAD_DRIVER_S 2 +/** LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR (BIT(3)) +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_M (LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S) +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S 3 +/** LP_IO_LP_GPIO7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_INT_TYPE 0x00000007U +#define LP_IO_LP_GPIO7_INT_TYPE_M (LP_IO_LP_GPIO7_INT_TYPE_V << LP_IO_LP_GPIO7_INT_TYPE_S) +#define LP_IO_LP_GPIO7_INT_TYPE_V 0x00000007U +#define LP_IO_LP_GPIO7_INT_TYPE_S 7 +/** LP_IO_LP_GPIO7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE (BIT(10)) +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_M (LP_IO_LP_GPIO7_WAKEUP_ENABLE_V << LP_IO_LP_GPIO7_WAKEUP_ENABLE_S) +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_V 0x00000001U +#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_S 10 +/** LP_IO_LP_GPIO7_FILTER_EN : R/W; bitpos: [11]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FILTER_EN (BIT(11)) +#define LP_IO_LP_GPIO7_FILTER_EN_M (LP_IO_LP_GPIO7_FILTER_EN_V << LP_IO_LP_GPIO7_FILTER_EN_S) +#define LP_IO_LP_GPIO7_FILTER_EN_V 0x00000001U +#define LP_IO_LP_GPIO7_FILTER_EN_S 11 + +/** LP_IO_GPIO0_REG register + * need des + */ +#define LP_IO_GPIO0_REG (DR_REG_LP_IO_BASE + 0x48) +/** LP_IO_LP_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO0_MCU_OE_M (LP_IO_LP_GPIO0_MCU_OE_V << LP_IO_LP_GPIO0_MCU_OE_S) +#define LP_IO_LP_GPIO0_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_OE_S 0 +/** LP_IO_LP_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO0_SLP_SEL_M (LP_IO_LP_GPIO0_SLP_SEL_V << LP_IO_LP_GPIO0_SLP_SEL_S) +#define LP_IO_LP_GPIO0_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO0_SLP_SEL_S 1 +/** LP_IO_LP_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO0_MCU_WPD_M (LP_IO_LP_GPIO0_MCU_WPD_V << LP_IO_LP_GPIO0_MCU_WPD_S) +#define LP_IO_LP_GPIO0_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_WPD_S 2 +/** LP_IO_LP_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO0_MCU_WPU_M (LP_IO_LP_GPIO0_MCU_WPU_V << LP_IO_LP_GPIO0_MCU_WPU_S) +#define LP_IO_LP_GPIO0_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_WPU_S 3 +/** LP_IO_LP_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO0_MCU_IE_M (LP_IO_LP_GPIO0_MCU_IE_V << LP_IO_LP_GPIO0_MCU_IE_S) +#define LP_IO_LP_GPIO0_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO0_MCU_IE_S 4 +/** LP_IO_LP_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO0_MCU_DRV_M (LP_IO_LP_GPIO0_MCU_DRV_V << LP_IO_LP_GPIO0_MCU_DRV_S) +#define LP_IO_LP_GPIO0_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO0_MCU_DRV_S 5 +/** LP_IO_LP_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO0_FUN_WPD_M (LP_IO_LP_GPIO0_FUN_WPD_V << LP_IO_LP_GPIO0_FUN_WPD_S) +#define LP_IO_LP_GPIO0_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_WPD_S 7 +/** LP_IO_LP_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO0_FUN_WPU_M (LP_IO_LP_GPIO0_FUN_WPU_V << LP_IO_LP_GPIO0_FUN_WPU_S) +#define LP_IO_LP_GPIO0_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_WPU_S 8 +/** LP_IO_LP_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO0_FUN_IE_M (LP_IO_LP_GPIO0_FUN_IE_V << LP_IO_LP_GPIO0_FUN_IE_S) +#define LP_IO_LP_GPIO0_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO0_FUN_IE_S 9 +/** LP_IO_LP_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO0_FUN_DRV_M (LP_IO_LP_GPIO0_FUN_DRV_V << LP_IO_LP_GPIO0_FUN_DRV_S) +#define LP_IO_LP_GPIO0_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO0_FUN_DRV_S 10 +/** LP_IO_LP_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO0_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO0_MCU_SEL_M (LP_IO_LP_GPIO0_MCU_SEL_V << LP_IO_LP_GPIO0_MCU_SEL_S) +#define LP_IO_LP_GPIO0_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO0_MCU_SEL_S 12 + +/** LP_IO_GPIO1_REG register + * need des + */ +#define LP_IO_GPIO1_REG (DR_REG_LP_IO_BASE + 0x4c) +/** LP_IO_LP_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO1_MCU_OE_M (LP_IO_LP_GPIO1_MCU_OE_V << LP_IO_LP_GPIO1_MCU_OE_S) +#define LP_IO_LP_GPIO1_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_OE_S 0 +/** LP_IO_LP_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO1_SLP_SEL_M (LP_IO_LP_GPIO1_SLP_SEL_V << LP_IO_LP_GPIO1_SLP_SEL_S) +#define LP_IO_LP_GPIO1_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO1_SLP_SEL_S 1 +/** LP_IO_LP_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO1_MCU_WPD_M (LP_IO_LP_GPIO1_MCU_WPD_V << LP_IO_LP_GPIO1_MCU_WPD_S) +#define LP_IO_LP_GPIO1_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_WPD_S 2 +/** LP_IO_LP_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO1_MCU_WPU_M (LP_IO_LP_GPIO1_MCU_WPU_V << LP_IO_LP_GPIO1_MCU_WPU_S) +#define LP_IO_LP_GPIO1_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_WPU_S 3 +/** LP_IO_LP_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO1_MCU_IE_M (LP_IO_LP_GPIO1_MCU_IE_V << LP_IO_LP_GPIO1_MCU_IE_S) +#define LP_IO_LP_GPIO1_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO1_MCU_IE_S 4 +/** LP_IO_LP_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO1_MCU_DRV_M (LP_IO_LP_GPIO1_MCU_DRV_V << LP_IO_LP_GPIO1_MCU_DRV_S) +#define LP_IO_LP_GPIO1_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO1_MCU_DRV_S 5 +/** LP_IO_LP_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO1_FUN_WPD_M (LP_IO_LP_GPIO1_FUN_WPD_V << LP_IO_LP_GPIO1_FUN_WPD_S) +#define LP_IO_LP_GPIO1_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_WPD_S 7 +/** LP_IO_LP_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO1_FUN_WPU_M (LP_IO_LP_GPIO1_FUN_WPU_V << LP_IO_LP_GPIO1_FUN_WPU_S) +#define LP_IO_LP_GPIO1_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_WPU_S 8 +/** LP_IO_LP_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO1_FUN_IE_M (LP_IO_LP_GPIO1_FUN_IE_V << LP_IO_LP_GPIO1_FUN_IE_S) +#define LP_IO_LP_GPIO1_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO1_FUN_IE_S 9 +/** LP_IO_LP_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO1_FUN_DRV_M (LP_IO_LP_GPIO1_FUN_DRV_V << LP_IO_LP_GPIO1_FUN_DRV_S) +#define LP_IO_LP_GPIO1_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO1_FUN_DRV_S 10 +/** LP_IO_LP_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO1_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO1_MCU_SEL_M (LP_IO_LP_GPIO1_MCU_SEL_V << LP_IO_LP_GPIO1_MCU_SEL_S) +#define LP_IO_LP_GPIO1_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO1_MCU_SEL_S 12 + +/** LP_IO_GPIO2_REG register + * need des + */ +#define LP_IO_GPIO2_REG (DR_REG_LP_IO_BASE + 0x50) +/** LP_IO_LP_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO2_MCU_OE_M (LP_IO_LP_GPIO2_MCU_OE_V << LP_IO_LP_GPIO2_MCU_OE_S) +#define LP_IO_LP_GPIO2_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_OE_S 0 +/** LP_IO_LP_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO2_SLP_SEL_M (LP_IO_LP_GPIO2_SLP_SEL_V << LP_IO_LP_GPIO2_SLP_SEL_S) +#define LP_IO_LP_GPIO2_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO2_SLP_SEL_S 1 +/** LP_IO_LP_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO2_MCU_WPD_M (LP_IO_LP_GPIO2_MCU_WPD_V << LP_IO_LP_GPIO2_MCU_WPD_S) +#define LP_IO_LP_GPIO2_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_WPD_S 2 +/** LP_IO_LP_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO2_MCU_WPU_M (LP_IO_LP_GPIO2_MCU_WPU_V << LP_IO_LP_GPIO2_MCU_WPU_S) +#define LP_IO_LP_GPIO2_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_WPU_S 3 +/** LP_IO_LP_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO2_MCU_IE_M (LP_IO_LP_GPIO2_MCU_IE_V << LP_IO_LP_GPIO2_MCU_IE_S) +#define LP_IO_LP_GPIO2_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO2_MCU_IE_S 4 +/** LP_IO_LP_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO2_MCU_DRV_M (LP_IO_LP_GPIO2_MCU_DRV_V << LP_IO_LP_GPIO2_MCU_DRV_S) +#define LP_IO_LP_GPIO2_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO2_MCU_DRV_S 5 +/** LP_IO_LP_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO2_FUN_WPD_M (LP_IO_LP_GPIO2_FUN_WPD_V << LP_IO_LP_GPIO2_FUN_WPD_S) +#define LP_IO_LP_GPIO2_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_WPD_S 7 +/** LP_IO_LP_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO2_FUN_WPU_M (LP_IO_LP_GPIO2_FUN_WPU_V << LP_IO_LP_GPIO2_FUN_WPU_S) +#define LP_IO_LP_GPIO2_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_WPU_S 8 +/** LP_IO_LP_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO2_FUN_IE_M (LP_IO_LP_GPIO2_FUN_IE_V << LP_IO_LP_GPIO2_FUN_IE_S) +#define LP_IO_LP_GPIO2_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO2_FUN_IE_S 9 +/** LP_IO_LP_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO2_FUN_DRV_M (LP_IO_LP_GPIO2_FUN_DRV_V << LP_IO_LP_GPIO2_FUN_DRV_S) +#define LP_IO_LP_GPIO2_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO2_FUN_DRV_S 10 +/** LP_IO_LP_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO2_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO2_MCU_SEL_M (LP_IO_LP_GPIO2_MCU_SEL_V << LP_IO_LP_GPIO2_MCU_SEL_S) +#define LP_IO_LP_GPIO2_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO2_MCU_SEL_S 12 + +/** LP_IO_GPIO3_REG register + * need des + */ +#define LP_IO_GPIO3_REG (DR_REG_LP_IO_BASE + 0x54) +/** LP_IO_LP_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO3_MCU_OE_M (LP_IO_LP_GPIO3_MCU_OE_V << LP_IO_LP_GPIO3_MCU_OE_S) +#define LP_IO_LP_GPIO3_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_OE_S 0 +/** LP_IO_LP_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO3_SLP_SEL_M (LP_IO_LP_GPIO3_SLP_SEL_V << LP_IO_LP_GPIO3_SLP_SEL_S) +#define LP_IO_LP_GPIO3_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO3_SLP_SEL_S 1 +/** LP_IO_LP_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO3_MCU_WPD_M (LP_IO_LP_GPIO3_MCU_WPD_V << LP_IO_LP_GPIO3_MCU_WPD_S) +#define LP_IO_LP_GPIO3_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_WPD_S 2 +/** LP_IO_LP_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO3_MCU_WPU_M (LP_IO_LP_GPIO3_MCU_WPU_V << LP_IO_LP_GPIO3_MCU_WPU_S) +#define LP_IO_LP_GPIO3_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_WPU_S 3 +/** LP_IO_LP_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO3_MCU_IE_M (LP_IO_LP_GPIO3_MCU_IE_V << LP_IO_LP_GPIO3_MCU_IE_S) +#define LP_IO_LP_GPIO3_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO3_MCU_IE_S 4 +/** LP_IO_LP_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO3_MCU_DRV_M (LP_IO_LP_GPIO3_MCU_DRV_V << LP_IO_LP_GPIO3_MCU_DRV_S) +#define LP_IO_LP_GPIO3_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO3_MCU_DRV_S 5 +/** LP_IO_LP_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO3_FUN_WPD_M (LP_IO_LP_GPIO3_FUN_WPD_V << LP_IO_LP_GPIO3_FUN_WPD_S) +#define LP_IO_LP_GPIO3_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_WPD_S 7 +/** LP_IO_LP_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO3_FUN_WPU_M (LP_IO_LP_GPIO3_FUN_WPU_V << LP_IO_LP_GPIO3_FUN_WPU_S) +#define LP_IO_LP_GPIO3_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_WPU_S 8 +/** LP_IO_LP_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO3_FUN_IE_M (LP_IO_LP_GPIO3_FUN_IE_V << LP_IO_LP_GPIO3_FUN_IE_S) +#define LP_IO_LP_GPIO3_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO3_FUN_IE_S 9 +/** LP_IO_LP_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO3_FUN_DRV_M (LP_IO_LP_GPIO3_FUN_DRV_V << LP_IO_LP_GPIO3_FUN_DRV_S) +#define LP_IO_LP_GPIO3_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO3_FUN_DRV_S 10 +/** LP_IO_LP_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO3_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO3_MCU_SEL_M (LP_IO_LP_GPIO3_MCU_SEL_V << LP_IO_LP_GPIO3_MCU_SEL_S) +#define LP_IO_LP_GPIO3_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO3_MCU_SEL_S 12 + +/** LP_IO_GPIO4_REG register + * need des + */ +#define LP_IO_GPIO4_REG (DR_REG_LP_IO_BASE + 0x58) +/** LP_IO_LP_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO4_MCU_OE_M (LP_IO_LP_GPIO4_MCU_OE_V << LP_IO_LP_GPIO4_MCU_OE_S) +#define LP_IO_LP_GPIO4_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_OE_S 0 +/** LP_IO_LP_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO4_SLP_SEL_M (LP_IO_LP_GPIO4_SLP_SEL_V << LP_IO_LP_GPIO4_SLP_SEL_S) +#define LP_IO_LP_GPIO4_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO4_SLP_SEL_S 1 +/** LP_IO_LP_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO4_MCU_WPD_M (LP_IO_LP_GPIO4_MCU_WPD_V << LP_IO_LP_GPIO4_MCU_WPD_S) +#define LP_IO_LP_GPIO4_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_WPD_S 2 +/** LP_IO_LP_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO4_MCU_WPU_M (LP_IO_LP_GPIO4_MCU_WPU_V << LP_IO_LP_GPIO4_MCU_WPU_S) +#define LP_IO_LP_GPIO4_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_WPU_S 3 +/** LP_IO_LP_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO4_MCU_IE_M (LP_IO_LP_GPIO4_MCU_IE_V << LP_IO_LP_GPIO4_MCU_IE_S) +#define LP_IO_LP_GPIO4_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO4_MCU_IE_S 4 +/** LP_IO_LP_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO4_MCU_DRV_M (LP_IO_LP_GPIO4_MCU_DRV_V << LP_IO_LP_GPIO4_MCU_DRV_S) +#define LP_IO_LP_GPIO4_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO4_MCU_DRV_S 5 +/** LP_IO_LP_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO4_FUN_WPD_M (LP_IO_LP_GPIO4_FUN_WPD_V << LP_IO_LP_GPIO4_FUN_WPD_S) +#define LP_IO_LP_GPIO4_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_WPD_S 7 +/** LP_IO_LP_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO4_FUN_WPU_M (LP_IO_LP_GPIO4_FUN_WPU_V << LP_IO_LP_GPIO4_FUN_WPU_S) +#define LP_IO_LP_GPIO4_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_WPU_S 8 +/** LP_IO_LP_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO4_FUN_IE_M (LP_IO_LP_GPIO4_FUN_IE_V << LP_IO_LP_GPIO4_FUN_IE_S) +#define LP_IO_LP_GPIO4_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO4_FUN_IE_S 9 +/** LP_IO_LP_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO4_FUN_DRV_M (LP_IO_LP_GPIO4_FUN_DRV_V << LP_IO_LP_GPIO4_FUN_DRV_S) +#define LP_IO_LP_GPIO4_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO4_FUN_DRV_S 10 +/** LP_IO_LP_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO4_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO4_MCU_SEL_M (LP_IO_LP_GPIO4_MCU_SEL_V << LP_IO_LP_GPIO4_MCU_SEL_S) +#define LP_IO_LP_GPIO4_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO4_MCU_SEL_S 12 + +/** LP_IO_GPIO5_REG register + * need des + */ +#define LP_IO_GPIO5_REG (DR_REG_LP_IO_BASE + 0x5c) +/** LP_IO_LP_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO5_MCU_OE_M (LP_IO_LP_GPIO5_MCU_OE_V << LP_IO_LP_GPIO5_MCU_OE_S) +#define LP_IO_LP_GPIO5_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_OE_S 0 +/** LP_IO_LP_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO5_SLP_SEL_M (LP_IO_LP_GPIO5_SLP_SEL_V << LP_IO_LP_GPIO5_SLP_SEL_S) +#define LP_IO_LP_GPIO5_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO5_SLP_SEL_S 1 +/** LP_IO_LP_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO5_MCU_WPD_M (LP_IO_LP_GPIO5_MCU_WPD_V << LP_IO_LP_GPIO5_MCU_WPD_S) +#define LP_IO_LP_GPIO5_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_WPD_S 2 +/** LP_IO_LP_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO5_MCU_WPU_M (LP_IO_LP_GPIO5_MCU_WPU_V << LP_IO_LP_GPIO5_MCU_WPU_S) +#define LP_IO_LP_GPIO5_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_WPU_S 3 +/** LP_IO_LP_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO5_MCU_IE_M (LP_IO_LP_GPIO5_MCU_IE_V << LP_IO_LP_GPIO5_MCU_IE_S) +#define LP_IO_LP_GPIO5_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO5_MCU_IE_S 4 +/** LP_IO_LP_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO5_MCU_DRV_M (LP_IO_LP_GPIO5_MCU_DRV_V << LP_IO_LP_GPIO5_MCU_DRV_S) +#define LP_IO_LP_GPIO5_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO5_MCU_DRV_S 5 +/** LP_IO_LP_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO5_FUN_WPD_M (LP_IO_LP_GPIO5_FUN_WPD_V << LP_IO_LP_GPIO5_FUN_WPD_S) +#define LP_IO_LP_GPIO5_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_WPD_S 7 +/** LP_IO_LP_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO5_FUN_WPU_M (LP_IO_LP_GPIO5_FUN_WPU_V << LP_IO_LP_GPIO5_FUN_WPU_S) +#define LP_IO_LP_GPIO5_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_WPU_S 8 +/** LP_IO_LP_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO5_FUN_IE_M (LP_IO_LP_GPIO5_FUN_IE_V << LP_IO_LP_GPIO5_FUN_IE_S) +#define LP_IO_LP_GPIO5_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO5_FUN_IE_S 9 +/** LP_IO_LP_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO5_FUN_DRV_M (LP_IO_LP_GPIO5_FUN_DRV_V << LP_IO_LP_GPIO5_FUN_DRV_S) +#define LP_IO_LP_GPIO5_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO5_FUN_DRV_S 10 +/** LP_IO_LP_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO5_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO5_MCU_SEL_M (LP_IO_LP_GPIO5_MCU_SEL_V << LP_IO_LP_GPIO5_MCU_SEL_S) +#define LP_IO_LP_GPIO5_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO5_MCU_SEL_S 12 + +/** LP_IO_GPIO6_REG register + * need des + */ +#define LP_IO_GPIO6_REG (DR_REG_LP_IO_BASE + 0x60) +/** LP_IO_LP_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO6_MCU_OE_M (LP_IO_LP_GPIO6_MCU_OE_V << LP_IO_LP_GPIO6_MCU_OE_S) +#define LP_IO_LP_GPIO6_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_OE_S 0 +/** LP_IO_LP_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO6_SLP_SEL_M (LP_IO_LP_GPIO6_SLP_SEL_V << LP_IO_LP_GPIO6_SLP_SEL_S) +#define LP_IO_LP_GPIO6_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO6_SLP_SEL_S 1 +/** LP_IO_LP_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO6_MCU_WPD_M (LP_IO_LP_GPIO6_MCU_WPD_V << LP_IO_LP_GPIO6_MCU_WPD_S) +#define LP_IO_LP_GPIO6_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_WPD_S 2 +/** LP_IO_LP_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO6_MCU_WPU_M (LP_IO_LP_GPIO6_MCU_WPU_V << LP_IO_LP_GPIO6_MCU_WPU_S) +#define LP_IO_LP_GPIO6_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_WPU_S 3 +/** LP_IO_LP_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO6_MCU_IE_M (LP_IO_LP_GPIO6_MCU_IE_V << LP_IO_LP_GPIO6_MCU_IE_S) +#define LP_IO_LP_GPIO6_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO6_MCU_IE_S 4 +/** LP_IO_LP_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO6_MCU_DRV_M (LP_IO_LP_GPIO6_MCU_DRV_V << LP_IO_LP_GPIO6_MCU_DRV_S) +#define LP_IO_LP_GPIO6_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO6_MCU_DRV_S 5 +/** LP_IO_LP_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO6_FUN_WPD_M (LP_IO_LP_GPIO6_FUN_WPD_V << LP_IO_LP_GPIO6_FUN_WPD_S) +#define LP_IO_LP_GPIO6_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_WPD_S 7 +/** LP_IO_LP_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO6_FUN_WPU_M (LP_IO_LP_GPIO6_FUN_WPU_V << LP_IO_LP_GPIO6_FUN_WPU_S) +#define LP_IO_LP_GPIO6_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_WPU_S 8 +/** LP_IO_LP_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO6_FUN_IE_M (LP_IO_LP_GPIO6_FUN_IE_V << LP_IO_LP_GPIO6_FUN_IE_S) +#define LP_IO_LP_GPIO6_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO6_FUN_IE_S 9 +/** LP_IO_LP_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO6_FUN_DRV_M (LP_IO_LP_GPIO6_FUN_DRV_V << LP_IO_LP_GPIO6_FUN_DRV_S) +#define LP_IO_LP_GPIO6_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO6_FUN_DRV_S 10 +/** LP_IO_LP_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO6_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO6_MCU_SEL_M (LP_IO_LP_GPIO6_MCU_SEL_V << LP_IO_LP_GPIO6_MCU_SEL_S) +#define LP_IO_LP_GPIO6_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO6_MCU_SEL_S 12 + +/** LP_IO_GPIO7_REG register + * need des + */ +#define LP_IO_GPIO7_REG (DR_REG_LP_IO_BASE + 0x64) +/** LP_IO_LP_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_OE (BIT(0)) +#define LP_IO_LP_GPIO7_MCU_OE_M (LP_IO_LP_GPIO7_MCU_OE_V << LP_IO_LP_GPIO7_MCU_OE_S) +#define LP_IO_LP_GPIO7_MCU_OE_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_OE_S 0 +/** LP_IO_LP_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_SLP_SEL (BIT(1)) +#define LP_IO_LP_GPIO7_SLP_SEL_M (LP_IO_LP_GPIO7_SLP_SEL_V << LP_IO_LP_GPIO7_SLP_SEL_S) +#define LP_IO_LP_GPIO7_SLP_SEL_V 0x00000001U +#define LP_IO_LP_GPIO7_SLP_SEL_S 1 +/** LP_IO_LP_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_WPD (BIT(2)) +#define LP_IO_LP_GPIO7_MCU_WPD_M (LP_IO_LP_GPIO7_MCU_WPD_V << LP_IO_LP_GPIO7_MCU_WPD_S) +#define LP_IO_LP_GPIO7_MCU_WPD_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_WPD_S 2 +/** LP_IO_LP_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_WPU (BIT(3)) +#define LP_IO_LP_GPIO7_MCU_WPU_M (LP_IO_LP_GPIO7_MCU_WPU_V << LP_IO_LP_GPIO7_MCU_WPU_S) +#define LP_IO_LP_GPIO7_MCU_WPU_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_WPU_S 3 +/** LP_IO_LP_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_IE (BIT(4)) +#define LP_IO_LP_GPIO7_MCU_IE_M (LP_IO_LP_GPIO7_MCU_IE_V << LP_IO_LP_GPIO7_MCU_IE_S) +#define LP_IO_LP_GPIO7_MCU_IE_V 0x00000001U +#define LP_IO_LP_GPIO7_MCU_IE_S 4 +/** LP_IO_LP_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_DRV 0x00000003U +#define LP_IO_LP_GPIO7_MCU_DRV_M (LP_IO_LP_GPIO7_MCU_DRV_V << LP_IO_LP_GPIO7_MCU_DRV_S) +#define LP_IO_LP_GPIO7_MCU_DRV_V 0x00000003U +#define LP_IO_LP_GPIO7_MCU_DRV_S 5 +/** LP_IO_LP_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_WPD (BIT(7)) +#define LP_IO_LP_GPIO7_FUN_WPD_M (LP_IO_LP_GPIO7_FUN_WPD_V << LP_IO_LP_GPIO7_FUN_WPD_S) +#define LP_IO_LP_GPIO7_FUN_WPD_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_WPD_S 7 +/** LP_IO_LP_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_WPU (BIT(8)) +#define LP_IO_LP_GPIO7_FUN_WPU_M (LP_IO_LP_GPIO7_FUN_WPU_V << LP_IO_LP_GPIO7_FUN_WPU_S) +#define LP_IO_LP_GPIO7_FUN_WPU_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_WPU_S 8 +/** LP_IO_LP_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_IE (BIT(9)) +#define LP_IO_LP_GPIO7_FUN_IE_M (LP_IO_LP_GPIO7_FUN_IE_V << LP_IO_LP_GPIO7_FUN_IE_S) +#define LP_IO_LP_GPIO7_FUN_IE_V 0x00000001U +#define LP_IO_LP_GPIO7_FUN_IE_S 9 +/** LP_IO_LP_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_FUN_DRV 0x00000003U +#define LP_IO_LP_GPIO7_FUN_DRV_M (LP_IO_LP_GPIO7_FUN_DRV_V << LP_IO_LP_GPIO7_FUN_DRV_S) +#define LP_IO_LP_GPIO7_FUN_DRV_V 0x00000003U +#define LP_IO_LP_GPIO7_FUN_DRV_S 10 +/** LP_IO_LP_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * need des + */ +#define LP_IO_LP_GPIO7_MCU_SEL 0x00000007U +#define LP_IO_LP_GPIO7_MCU_SEL_M (LP_IO_LP_GPIO7_MCU_SEL_V << LP_IO_LP_GPIO7_MCU_SEL_S) +#define LP_IO_LP_GPIO7_MCU_SEL_V 0x00000007U +#define LP_IO_LP_GPIO7_MCU_SEL_S 12 + +/** LP_IO_STATUS_INTERRUPT_REG register + * need des + */ +#define LP_IO_STATUS_INTERRUPT_REG (DR_REG_LP_IO_BASE + 0x68) +/** LP_IO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0; + * need des + */ +#define LP_IO_STATUS_INTERRUPT_NEXT 0x000000FFU +#define LP_IO_STATUS_INTERRUPT_NEXT_M (LP_IO_STATUS_INTERRUPT_NEXT_V << LP_IO_STATUS_INTERRUPT_NEXT_S) +#define LP_IO_STATUS_INTERRUPT_NEXT_V 0x000000FFU +#define LP_IO_STATUS_INTERRUPT_NEXT_S 0 + +/** LP_IO_DEBUG_SEL0_REG register + * need des + */ +#define LP_IO_DEBUG_SEL0_REG (DR_REG_LP_IO_BASE + 0x6c) +/** LP_IO_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL0 0x0000007FU +#define LP_IO_LP_DEBUG_SEL0_M (LP_IO_LP_DEBUG_SEL0_V << LP_IO_LP_DEBUG_SEL0_S) +#define LP_IO_LP_DEBUG_SEL0_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL0_S 0 +/** LP_IO_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL1 0x0000007FU +#define LP_IO_LP_DEBUG_SEL1_M (LP_IO_LP_DEBUG_SEL1_V << LP_IO_LP_DEBUG_SEL1_S) +#define LP_IO_LP_DEBUG_SEL1_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL1_S 7 +/** LP_IO_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL2 0x0000007FU +#define LP_IO_LP_DEBUG_SEL2_M (LP_IO_LP_DEBUG_SEL2_V << LP_IO_LP_DEBUG_SEL2_S) +#define LP_IO_LP_DEBUG_SEL2_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL2_S 14 +/** LP_IO_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL3 0x0000007FU +#define LP_IO_LP_DEBUG_SEL3_M (LP_IO_LP_DEBUG_SEL3_V << LP_IO_LP_DEBUG_SEL3_S) +#define LP_IO_LP_DEBUG_SEL3_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL3_S 21 + +/** LP_IO_DEBUG_SEL1_REG register + * need des + */ +#define LP_IO_DEBUG_SEL1_REG (DR_REG_LP_IO_BASE + 0x70) +/** LP_IO_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LP_IO_LP_DEBUG_SEL4 0x0000007FU +#define LP_IO_LP_DEBUG_SEL4_M (LP_IO_LP_DEBUG_SEL4_V << LP_IO_LP_DEBUG_SEL4_S) +#define LP_IO_LP_DEBUG_SEL4_V 0x0000007FU +#define LP_IO_LP_DEBUG_SEL4_S 0 + +/** LP_IO_LPI2C_REG register + * need des + */ +#define LP_IO_LPI2C_REG (DR_REG_LP_IO_BASE + 0x74) +/** LP_IO_LP_I2C_SDA_IE : R/W; bitpos: [30]; default: 1; + * need des + */ +#define LP_IO_LP_I2C_SDA_IE (BIT(30)) +#define LP_IO_LP_I2C_SDA_IE_M (LP_IO_LP_I2C_SDA_IE_V << LP_IO_LP_I2C_SDA_IE_S) +#define LP_IO_LP_I2C_SDA_IE_V 0x00000001U +#define LP_IO_LP_I2C_SDA_IE_S 30 +/** LP_IO_LP_I2C_SCL_IE : R/W; bitpos: [31]; default: 1; + * need des + */ +#define LP_IO_LP_I2C_SCL_IE (BIT(31)) +#define LP_IO_LP_I2C_SCL_IE_M (LP_IO_LP_I2C_SCL_IE_V << LP_IO_LP_I2C_SCL_IE_S) +#define LP_IO_LP_I2C_SCL_IE_V 0x00000001U +#define LP_IO_LP_I2C_SCL_IE_S 31 + +/** LP_IO_DATE_REG register + * need des + */ +#define LP_IO_DATE_REG (DR_REG_LP_IO_BASE + 0x3fc) +/** LP_IO_LP_IO_DATE : R/W; bitpos: [30:0]; default: 35660032; + * need des + */ +#define LP_IO_LP_IO_DATE 0x7FFFFFFFU +#define LP_IO_LP_IO_DATE_M (LP_IO_LP_IO_DATE_V << LP_IO_LP_IO_DATE_S) +#define LP_IO_LP_IO_DATE_V 0x7FFFFFFFU +#define LP_IO_LP_IO_DATE_S 0 +/** LP_IO_CLK_EN : R/W; bitpos: [31]; default: 0; + * need des + */ +#define LP_IO_CLK_EN (BIT(31)) +#define LP_IO_CLK_EN_M (LP_IO_CLK_EN_V << LP_IO_CLK_EN_S) +#define LP_IO_CLK_EN_V 0x00000001U +#define LP_IO_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_io_struct.h b/components/soc/esp32c5/include/soc/lp_io_struct.h new file mode 100644 index 0000000000..bcc0ad2c05 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_io_struct.h @@ -0,0 +1,999 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of out_data register + * need des + */ +typedef union { + struct { + /** lp_gpio_out_data : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t lp_gpio_out_data:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_reg_t; + +/** Type of out_data_w1ts register + * need des + */ +typedef union { + struct { + /** lp_gpio_out_data_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t lp_gpio_out_data_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_w1ts_reg_t; + +/** Type of out_data_w1tc register + * need des + */ +typedef union { + struct { + /** lp_gpio_out_data_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t lp_gpio_out_data_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_data_w1tc_reg_t; + +/** Type of out_enable register + * need des + */ +typedef union { + struct { + /** lp_gpio_enable : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t lp_gpio_enable:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_reg_t; + +/** Type of out_enable_w1ts register + * need des + */ +typedef union { + struct { + /** lp_gpio_enable_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t lp_gpio_enable_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_w1ts_reg_t; + +/** Type of out_enable_w1tc register + * need des + */ +typedef union { + struct { + /** lp_gpio_enable_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t lp_gpio_enable_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_out_enable_w1tc_reg_t; + +/** Type of status register + * need des + */ +typedef union { + struct { + /** lp_gpio_status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0; + * set lp gpio output data + */ + uint32_t lp_gpio_status_interrupt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_reg_t; + +/** Type of status_w1ts register + * need des + */ +typedef union { + struct { + /** lp_gpio_status_w1ts : WT; bitpos: [7:0]; default: 0; + * set one time output data + */ + uint32_t lp_gpio_status_w1ts:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_w1ts_reg_t; + +/** Type of status_w1tc register + * need des + */ +typedef union { + struct { + /** lp_gpio_status_w1tc : WT; bitpos: [7:0]; default: 0; + * clear one time output data + */ + uint32_t lp_gpio_status_w1tc:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_w1tc_reg_t; + +/** Type of in register + * need des + */ +typedef union { + struct { + /** lp_gpio_in_data_next : RO; bitpos: [7:0]; default: 0; + * need des + */ + uint32_t lp_gpio_in_data_next:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_in_reg_t; + +/** Type of pin0 register + * need des + */ +typedef union { + struct { + /** lp_gpio0_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio0_sync_bypass:2; + /** lp_gpio0_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio0_pad_driver:1; + /** lp_gpio0_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio0_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio0_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio0_int_type:3; + /** lp_gpio0_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio0_wakeup_enable:1; + /** lp_gpio0_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio0_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin0_reg_t; + +/** Type of pin1 register + * need des + */ +typedef union { + struct { + /** lp_gpio1_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio1_sync_bypass:2; + /** lp_gpio1_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio1_pad_driver:1; + /** lp_gpio1_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio1_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio1_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio1_int_type:3; + /** lp_gpio1_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio1_wakeup_enable:1; + /** lp_gpio1_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio1_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin1_reg_t; + +/** Type of pin2 register + * need des + */ +typedef union { + struct { + /** lp_gpio2_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio2_sync_bypass:2; + /** lp_gpio2_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio2_pad_driver:1; + /** lp_gpio2_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio2_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio2_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio2_int_type:3; + /** lp_gpio2_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio2_wakeup_enable:1; + /** lp_gpio2_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio2_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin2_reg_t; + +/** Type of pin3 register + * need des + */ +typedef union { + struct { + /** lp_gpio3_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio3_sync_bypass:2; + /** lp_gpio3_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio3_pad_driver:1; + /** lp_gpio3_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio3_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio3_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio3_int_type:3; + /** lp_gpio3_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio3_wakeup_enable:1; + /** lp_gpio3_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio3_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin3_reg_t; + +/** Type of pin4 register + * need des + */ +typedef union { + struct { + /** lp_gpio4_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio4_sync_bypass:2; + /** lp_gpio4_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio4_pad_driver:1; + /** lp_gpio4_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio4_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio4_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio4_int_type:3; + /** lp_gpio4_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio4_wakeup_enable:1; + /** lp_gpio4_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio4_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin4_reg_t; + +/** Type of pin5 register + * need des + */ +typedef union { + struct { + /** lp_gpio5_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio5_sync_bypass:2; + /** lp_gpio5_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio5_pad_driver:1; + /** lp_gpio5_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio5_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio5_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio5_int_type:3; + /** lp_gpio5_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio5_wakeup_enable:1; + /** lp_gpio5_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio5_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin5_reg_t; + +/** Type of pin6 register + * need des + */ +typedef union { + struct { + /** lp_gpio6_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio6_sync_bypass:2; + /** lp_gpio6_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio6_pad_driver:1; + /** lp_gpio6_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio6_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio6_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio6_int_type:3; + /** lp_gpio6_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio6_wakeup_enable:1; + /** lp_gpio6_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio6_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin6_reg_t; + +/** Type of pin7 register + * need des + */ +typedef union { + struct { + /** lp_gpio7_sync_bypass : R/W; bitpos: [1:0]; default: 0; + * need des + */ + uint32_t lp_gpio7_sync_bypass:2; + /** lp_gpio7_pad_driver : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio7_pad_driver:1; + /** lp_gpio7_edge_wakeup_clr : WT; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio7_edge_wakeup_clr:1; + uint32_t reserved_4:3; + /** lp_gpio7_int_type : R/W; bitpos: [9:7]; default: 0; + * need des + */ + uint32_t lp_gpio7_int_type:3; + /** lp_gpio7_wakeup_enable : R/W; bitpos: [10]; default: 0; + * need des + */ + uint32_t lp_gpio7_wakeup_enable:1; + /** lp_gpio7_filter_en : R/W; bitpos: [11]; default: 0; + * need des + */ + uint32_t lp_gpio7_filter_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_io_pin7_reg_t; + +/** Type of gpio0 register + * need des + */ +typedef union { + struct { + /** lp_gpio0_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio0_mcu_oe:1; + /** lp_gpio0_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio0_slp_sel:1; + /** lp_gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio0_mcu_wpd:1; + /** lp_gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio0_mcu_wpu:1; + /** lp_gpio0_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio0_mcu_ie:1; + /** lp_gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio0_mcu_drv:2; + /** lp_gpio0_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio0_fun_wpd:1; + /** lp_gpio0_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio0_fun_wpu:1; + /** lp_gpio0_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio0_fun_ie:1; + /** lp_gpio0_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio0_fun_drv:2; + /** lp_gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio0_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio0_reg_t; + +/** Type of gpio1 register + * need des + */ +typedef union { + struct { + /** lp_gpio1_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_oe:1; + /** lp_gpio1_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio1_slp_sel:1; + /** lp_gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_wpd:1; + /** lp_gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_wpu:1; + /** lp_gpio1_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_ie:1; + /** lp_gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_drv:2; + /** lp_gpio1_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio1_fun_wpd:1; + /** lp_gpio1_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio1_fun_wpu:1; + /** lp_gpio1_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio1_fun_ie:1; + /** lp_gpio1_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio1_fun_drv:2; + /** lp_gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio1_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio1_reg_t; + +/** Type of gpio2 register + * need des + */ +typedef union { + struct { + /** lp_gpio2_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_oe:1; + /** lp_gpio2_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio2_slp_sel:1; + /** lp_gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_wpd:1; + /** lp_gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_wpu:1; + /** lp_gpio2_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_ie:1; + /** lp_gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_drv:2; + /** lp_gpio2_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio2_fun_wpd:1; + /** lp_gpio2_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio2_fun_wpu:1; + /** lp_gpio2_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio2_fun_ie:1; + /** lp_gpio2_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio2_fun_drv:2; + /** lp_gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio2_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio2_reg_t; + +/** Type of gpio3 register + * need des + */ +typedef union { + struct { + /** lp_gpio3_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_oe:1; + /** lp_gpio3_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio3_slp_sel:1; + /** lp_gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_wpd:1; + /** lp_gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_wpu:1; + /** lp_gpio3_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_ie:1; + /** lp_gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_drv:2; + /** lp_gpio3_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio3_fun_wpd:1; + /** lp_gpio3_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio3_fun_wpu:1; + /** lp_gpio3_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio3_fun_ie:1; + /** lp_gpio3_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio3_fun_drv:2; + /** lp_gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio3_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio3_reg_t; + +/** Type of gpio4 register + * need des + */ +typedef union { + struct { + /** lp_gpio4_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_oe:1; + /** lp_gpio4_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio4_slp_sel:1; + /** lp_gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_wpd:1; + /** lp_gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_wpu:1; + /** lp_gpio4_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_ie:1; + /** lp_gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_drv:2; + /** lp_gpio4_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio4_fun_wpd:1; + /** lp_gpio4_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio4_fun_wpu:1; + /** lp_gpio4_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio4_fun_ie:1; + /** lp_gpio4_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio4_fun_drv:2; + /** lp_gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio4_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio4_reg_t; + +/** Type of gpio5 register + * need des + */ +typedef union { + struct { + /** lp_gpio5_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_oe:1; + /** lp_gpio5_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio5_slp_sel:1; + /** lp_gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_wpd:1; + /** lp_gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_wpu:1; + /** lp_gpio5_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_ie:1; + /** lp_gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_drv:2; + /** lp_gpio5_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio5_fun_wpd:1; + /** lp_gpio5_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio5_fun_wpu:1; + /** lp_gpio5_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio5_fun_ie:1; + /** lp_gpio5_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio5_fun_drv:2; + /** lp_gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio5_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio5_reg_t; + +/** Type of gpio6 register + * need des + */ +typedef union { + struct { + /** lp_gpio6_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_oe:1; + /** lp_gpio6_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio6_slp_sel:1; + /** lp_gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_wpd:1; + /** lp_gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_wpu:1; + /** lp_gpio6_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_ie:1; + /** lp_gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_drv:2; + /** lp_gpio6_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio6_fun_wpd:1; + /** lp_gpio6_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio6_fun_wpu:1; + /** lp_gpio6_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio6_fun_ie:1; + /** lp_gpio6_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio6_fun_drv:2; + /** lp_gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio6_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio6_reg_t; + +/** Type of gpio7 register + * need des + */ +typedef union { + struct { + /** lp_gpio7_mcu_oe : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_oe:1; + /** lp_gpio7_slp_sel : R/W; bitpos: [1]; default: 0; + * need des + */ + uint32_t lp_gpio7_slp_sel:1; + /** lp_gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_wpd:1; + /** lp_gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_wpu:1; + /** lp_gpio7_mcu_ie : R/W; bitpos: [4]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_ie:1; + /** lp_gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_drv:2; + /** lp_gpio7_fun_wpd : R/W; bitpos: [7]; default: 0; + * need des + */ + uint32_t lp_gpio7_fun_wpd:1; + /** lp_gpio7_fun_wpu : R/W; bitpos: [8]; default: 0; + * need des + */ + uint32_t lp_gpio7_fun_wpu:1; + /** lp_gpio7_fun_ie : R/W; bitpos: [9]; default: 0; + * need des + */ + uint32_t lp_gpio7_fun_ie:1; + /** lp_gpio7_fun_drv : R/W; bitpos: [11:10]; default: 0; + * need des + */ + uint32_t lp_gpio7_fun_drv:2; + /** lp_gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * need des + */ + uint32_t lp_gpio7_mcu_sel:3; + uint32_t reserved_15:17; + }; + uint32_t val; +} lp_io_gpio7_reg_t; + +/** Type of status_interrupt register + * need des + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [7:0]; default: 0; + * need des + */ + uint32_t status_interrupt_next:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_io_status_interrupt_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t lp_debug_sel0:7; + /** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t lp_debug_sel1:7; + /** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t lp_debug_sel2:7; + /** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t lp_debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_io_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t lp_debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_io_debug_sel1_reg_t; + +/** Type of lpi2c register + * need des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1; + * need des + */ + uint32_t lp_i2c_sda_ie:1; + /** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1; + * need des + */ + uint32_t lp_i2c_scl_ie:1; + }; + uint32_t val; +} lp_io_lpi2c_reg_t; + +/** Type of date register + * need des + */ +typedef union { + struct { + /** lp_io_date : R/W; bitpos: [30:0]; default: 35660032; + * need des + */ + uint32_t lp_io_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_io_date_reg_t; + + +typedef struct { + volatile lp_io_out_data_reg_t out_data; + volatile lp_io_out_data_w1ts_reg_t out_data_w1ts; + volatile lp_io_out_data_w1tc_reg_t out_data_w1tc; + volatile lp_io_out_enable_reg_t out_enable; + volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts; + volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc; + volatile lp_io_status_reg_t status; + volatile lp_io_status_w1ts_reg_t status_w1ts; + volatile lp_io_status_w1tc_reg_t status_w1tc; + volatile lp_io_in_reg_t in; + volatile lp_io_pin0_reg_t pin0; + volatile lp_io_pin1_reg_t pin1; + volatile lp_io_pin2_reg_t pin2; + volatile lp_io_pin3_reg_t pin3; + volatile lp_io_pin4_reg_t pin4; + volatile lp_io_pin5_reg_t pin5; + volatile lp_io_pin6_reg_t pin6; + volatile lp_io_pin7_reg_t pin7; + volatile lp_io_gpio0_reg_t gpio0; + volatile lp_io_gpio1_reg_t gpio1; + volatile lp_io_gpio2_reg_t gpio2; + volatile lp_io_gpio3_reg_t gpio3; + volatile lp_io_gpio4_reg_t gpio4; + volatile lp_io_gpio5_reg_t gpio5; + volatile lp_io_gpio6_reg_t gpio6; + volatile lp_io_gpio7_reg_t gpio7; + volatile lp_io_status_interrupt_reg_t status_interrupt; + volatile lp_io_debug_sel0_reg_t debug_sel0; + volatile lp_io_debug_sel1_reg_t debug_sel1; + volatile lp_io_lpi2c_reg_t lpi2c; + uint32_t reserved_078[225]; + volatile lp_io_date_reg_t date; +} lp_io_dev_t; + +extern lp_io_dev_t LP_IO; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_tee_reg.h b/components/soc/esp32c5/include/soc/lp_tee_reg.h new file mode 100644 index 0000000000..872bfbbfe1 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_tee_reg.h @@ -0,0 +1,72 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TEE_M0_MODE_CTRL_REG register + * Tee mode control register + */ +#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) +/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define LP_TEE_M0_MODE 0x00000003U +#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) +#define LP_TEE_M0_MODE_V 0x00000003U +#define LP_TEE_M0_MODE_S 0 +/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define LP_TEE_M0_LOCK (BIT(2)) +#define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S) +#define LP_TEE_M0_LOCK_V 0x00000001U +#define LP_TEE_M0_LOCK_S 2 + +/** LP_TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4) +/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_TEE_CLK_EN (BIT(0)) +#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) +#define LP_TEE_CLK_EN_V 0x00000001U +#define LP_TEE_CLK_EN_S 0 + +/** LP_TEE_FORCE_ACC_HP_REG register + * need_des + */ +#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) +/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) +#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) +#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U +#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 + +/** LP_TEE_DATE_REG register + * Version register + */ +#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) +/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664; + * reg_tee_date + */ +#define LP_TEE_DATE_REG 0x0FFFFFFFU +#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S) +#define LP_TEE_DATE_REG_V 0x0FFFFFFFU +#define LP_TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_tee_struct.h b/components/soc/esp32c5/include/soc/lp_tee_struct.h new file mode 100644 index 0000000000..5b23b3217d --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_tee_struct.h @@ -0,0 +1,98 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of m0_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m0_mode : R/W; bitpos: [1:0]; default: 3; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m0_mode:2; + /** m0_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ + uint32_t m0_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_tee_m0_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_clock_gate_reg_t; + + +/** Group: configure_register */ +/** Type of force_acc_hp register + * need_des + */ +typedef union { + struct { + /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_acc_hpmem_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_force_acc_hp_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35725664; + * reg_tee_date + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_tee_date_reg_t; + + +typedef struct { + volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl; + volatile lp_tee_clock_gate_reg_t clock_gate; + uint32_t reserved_008[34]; + volatile lp_tee_force_acc_hp_reg_t force_acc_hp; + uint32_t reserved_094[26]; + volatile lp_tee_date_reg_t date; +} lp_tee_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_timer_reg.h b/components/soc/esp32c5/include/soc/lp_timer_reg.h new file mode 100644 index 0000000000..7628cbf7e0 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_timer_reg.h @@ -0,0 +1,342 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_TAR1_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 + +/** LP_TIMER_TAR1_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 + +/** LP_TIMER_UPDATE_REG register + * need_des + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_MAIN_OVERFLOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** LP_TIMER_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * need_des + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_LP_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 + +/** LP_TIMER_LP_INT_ST_REG register + * need_des + */ +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 + +/** LP_TIMER_LP_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 + +/** LP_TIMER_LP_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * need_des + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_timer_struct.h b/components/soc/esp32c5/include/soc/lp_timer_struct.h new file mode 100644 index 0000000000..e5372939b5 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_timer_struct.h @@ -0,0 +1,363 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of tar0_low register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_low0:32; + }; + uint32_t val; +} lp_timer_tar0_low_reg_t; + +/** Type of tar0_high register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_high0:16; + uint32_t reserved_16:15; + /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_tar_en0:1; + }; + uint32_t val; +} lp_timer_tar0_high_reg_t; + +/** Type of tar1_low register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_low1:32; + }; + uint32_t val; +} lp_timer_tar1_low_reg_t; + +/** Type of tar1_high register + * need_des + */ +typedef union { + struct { + /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_tar_high1:16; + uint32_t reserved_16:15; + /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_tar_en1:1; + }; + uint32_t val; +} lp_timer_tar1_high_reg_t; + +/** Type of update register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** main_timer_update : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t main_timer_update:1; + /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t main_timer_xtal_off:1; + /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_sys_stall:1; + /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of main_buf0_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf0_low:32; + }; + uint32_t val; +} lp_timer_main_buf0_low_reg_t; + +/** Type of main_buf0_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf0_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf0_high_reg_t; + +/** Type of main_buf1_low register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of main_buf1_high register + * need_des + */ +typedef union { + struct { + /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of main_overflow register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** main_timer_alarm_load : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t overflow_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_raw:1; + /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_raw:1; + }; + uint32_t val; +} lp_timer_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_st:1; + /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_st:1; + }; + uint32_t val; +} lp_timer_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_ena:1; + /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_ena:1; + }; + uint32_t val; +} lp_timer_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t main_timer_overflow_lp_int_clr:1; + /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t main_timer_lp_int_clr:1; + }; + uint32_t val; +} lp_timer_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 34672976; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct { + volatile lp_timer_tar0_low_reg_t tar0_low; + volatile lp_timer_tar0_high_reg_t tar0_high; + volatile lp_timer_tar1_low_reg_t tar1_low; + volatile lp_timer_tar1_high_reg_t tar1_high; + volatile lp_timer_update_reg_t update; + volatile lp_timer_main_buf0_low_reg_t main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t main_buf1_high; + volatile lp_timer_main_overflow_reg_t main_overflow; + volatile lp_timer_int_raw_reg_t int_raw; + volatile lp_timer_int_st_reg_t int_st; + volatile lp_timer_int_ena_reg_t int_ena; + volatile lp_timer_int_clr_reg_t int_clr; + volatile lp_timer_lp_int_raw_reg_t lp_int_raw; + volatile lp_timer_lp_int_st_reg_t lp_int_st; + volatile lp_timer_lp_int_ena_reg_t lp_int_ena; + volatile lp_timer_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_048[237]; + volatile lp_timer_date_reg_t date; +} lp_timer_dev_t; + +extern lp_timer_dev_t LP_TIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_uart_reg.h b/components/soc/esp32c5/include/soc/lp_uart_reg.h new file mode 100644 index 0000000000..a23d7aeb7b --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_uart_reg.h @@ -0,0 +1,1381 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_UART_FIFO_REG register + * FIFO data register + */ +#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0) +/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ +#define LP_UART_RXFIFO_RD_BYTE 0x000000FFU +#define LP_UART_RXFIFO_RD_BYTE_M (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S) +#define LP_UART_RXFIFO_RD_BYTE_V 0x000000FFU +#define LP_UART_RXFIFO_RD_BYTE_S 0 + +/** LP_UART_INT_RAW_REG register + * Raw interrupt status + */ +#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4) +/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ +#define LP_UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_RAW_M (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S) +#define LP_UART_RXFIFO_FULL_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_RAW_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ +#define LP_UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_RAW_M (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S) +#define LP_UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_RAW_S 1 +/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ +#define LP_UART_PARITY_ERR_INT_RAW (BIT(2)) +#define LP_UART_PARITY_ERR_INT_RAW_M (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S) +#define LP_UART_PARITY_ERR_INT_RAW_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_RAW_S 2 +/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ +#define LP_UART_FRM_ERR_INT_RAW (BIT(3)) +#define LP_UART_FRM_ERR_INT_RAW_M (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S) +#define LP_UART_FRM_ERR_INT_RAW_V 0x00000001U +#define LP_UART_FRM_ERR_INT_RAW_S 3 +/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ +#define LP_UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_RAW_M (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S) +#define LP_UART_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_RAW_S 4 +/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ +#define LP_UART_DSR_CHG_INT_RAW (BIT(5)) +#define LP_UART_DSR_CHG_INT_RAW_M (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S) +#define LP_UART_DSR_CHG_INT_RAW_V 0x00000001U +#define LP_UART_DSR_CHG_INT_RAW_S 5 +/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ +#define LP_UART_CTS_CHG_INT_RAW (BIT(6)) +#define LP_UART_CTS_CHG_INT_RAW_M (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S) +#define LP_UART_CTS_CHG_INT_RAW_V 0x00000001U +#define LP_UART_CTS_CHG_INT_RAW_S 6 +/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ +#define LP_UART_BRK_DET_INT_RAW (BIT(7)) +#define LP_UART_BRK_DET_INT_RAW_M (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S) +#define LP_UART_BRK_DET_INT_RAW_V 0x00000001U +#define LP_UART_BRK_DET_INT_RAW_S 7 +/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ +#define LP_UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_RAW_M (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S) +#define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_RAW_S 8 +/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ +#define LP_UART_SW_XON_INT_RAW (BIT(9)) +#define LP_UART_SW_XON_INT_RAW_M (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S) +#define LP_UART_SW_XON_INT_RAW_V 0x00000001U +#define LP_UART_SW_XON_INT_RAW_S 9 +/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ +#define LP_UART_SW_XOFF_INT_RAW (BIT(10)) +#define LP_UART_SW_XOFF_INT_RAW_M (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S) +#define LP_UART_SW_XOFF_INT_RAW_V 0x00000001U +#define LP_UART_SW_XOFF_INT_RAW_S 10 +/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ +#define LP_UART_GLITCH_DET_INT_RAW (BIT(11)) +#define LP_UART_GLITCH_DET_INT_RAW_M (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S) +#define LP_UART_GLITCH_DET_INT_RAW_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_RAW_S 11 +/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ +#define LP_UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_RAW_M (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S) +#define LP_UART_TX_BRK_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_RAW_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ +#define LP_UART_TX_DONE_INT_RAW (BIT(14)) +#define LP_UART_TX_DONE_INT_RAW_M (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S) +#define LP_UART_TX_DONE_INT_RAW_V 0x00000001U +#define LP_UART_TX_DONE_INT_RAW_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ +#define LP_UART_WAKEUP_INT_RAW (BIT(19)) +#define LP_UART_WAKEUP_INT_RAW_M (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S) +#define LP_UART_WAKEUP_INT_RAW_V 0x00000001U +#define LP_UART_WAKEUP_INT_RAW_S 19 + +/** LP_UART_INT_ST_REG register + * Masked interrupt status + */ +#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8) +/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_ST_M (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S) +#define LP_UART_RXFIFO_FULL_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_ST_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ +#define LP_UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_ST_M (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S) +#define LP_UART_TXFIFO_EMPTY_INT_ST_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_ST_S 1 +/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ +#define LP_UART_PARITY_ERR_INT_ST (BIT(2)) +#define LP_UART_PARITY_ERR_INT_ST_M (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S) +#define LP_UART_PARITY_ERR_INT_ST_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_ST_S 2 +/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ +#define LP_UART_FRM_ERR_INT_ST (BIT(3)) +#define LP_UART_FRM_ERR_INT_ST_M (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S) +#define LP_UART_FRM_ERR_INT_ST_V 0x00000001U +#define LP_UART_FRM_ERR_INT_ST_S 3 +/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_ST_M (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S) +#define LP_UART_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_ST_S 4 +/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ +#define LP_UART_DSR_CHG_INT_ST (BIT(5)) +#define LP_UART_DSR_CHG_INT_ST_M (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S) +#define LP_UART_DSR_CHG_INT_ST_V 0x00000001U +#define LP_UART_DSR_CHG_INT_ST_S 5 +/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ +#define LP_UART_CTS_CHG_INT_ST (BIT(6)) +#define LP_UART_CTS_CHG_INT_ST_M (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S) +#define LP_UART_CTS_CHG_INT_ST_V 0x00000001U +#define LP_UART_CTS_CHG_INT_ST_S 6 +/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ +#define LP_UART_BRK_DET_INT_ST (BIT(7)) +#define LP_UART_BRK_DET_INT_ST_M (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S) +#define LP_UART_BRK_DET_INT_ST_V 0x00000001U +#define LP_UART_BRK_DET_INT_ST_S 7 +/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ +#define LP_UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_ST_M (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S) +#define LP_UART_RXFIFO_TOUT_INT_ST_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_ST_S 8 +/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ +#define LP_UART_SW_XON_INT_ST (BIT(9)) +#define LP_UART_SW_XON_INT_ST_M (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S) +#define LP_UART_SW_XON_INT_ST_V 0x00000001U +#define LP_UART_SW_XON_INT_ST_S 9 +/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ +#define LP_UART_SW_XOFF_INT_ST (BIT(10)) +#define LP_UART_SW_XOFF_INT_ST_M (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S) +#define LP_UART_SW_XOFF_INT_ST_V 0x00000001U +#define LP_UART_SW_XOFF_INT_ST_S 10 +/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ +#define LP_UART_GLITCH_DET_INT_ST (BIT(11)) +#define LP_UART_GLITCH_DET_INT_ST_M (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S) +#define LP_UART_GLITCH_DET_INT_ST_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_ST_S 11 +/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ +#define LP_UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_ST_M (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S) +#define LP_UART_TX_BRK_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_ST_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ +#define LP_UART_TX_DONE_INT_ST (BIT(14)) +#define LP_UART_TX_DONE_INT_ST_M (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S) +#define LP_UART_TX_DONE_INT_ST_V 0x00000001U +#define LP_UART_TX_DONE_INT_ST_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ +#define LP_UART_WAKEUP_INT_ST (BIT(19)) +#define LP_UART_WAKEUP_INT_ST_M (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S) +#define LP_UART_WAKEUP_INT_ST_V 0x00000001U +#define LP_UART_WAKEUP_INT_ST_S 19 + +/** LP_UART_INT_ENA_REG register + * Interrupt enable bits + */ +#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc) +/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ +#define LP_UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_ENA_M (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S) +#define LP_UART_RXFIFO_FULL_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_ENA_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ +#define LP_UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_ENA_M (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S) +#define LP_UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_ENA_S 1 +/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ +#define LP_UART_PARITY_ERR_INT_ENA (BIT(2)) +#define LP_UART_PARITY_ERR_INT_ENA_M (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S) +#define LP_UART_PARITY_ERR_INT_ENA_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_ENA_S 2 +/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ +#define LP_UART_FRM_ERR_INT_ENA (BIT(3)) +#define LP_UART_FRM_ERR_INT_ENA_M (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S) +#define LP_UART_FRM_ERR_INT_ENA_V 0x00000001U +#define LP_UART_FRM_ERR_INT_ENA_S 3 +/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ +#define LP_UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_ENA_M (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S) +#define LP_UART_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_ENA_S 4 +/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ +#define LP_UART_DSR_CHG_INT_ENA (BIT(5)) +#define LP_UART_DSR_CHG_INT_ENA_M (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S) +#define LP_UART_DSR_CHG_INT_ENA_V 0x00000001U +#define LP_UART_DSR_CHG_INT_ENA_S 5 +/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ +#define LP_UART_CTS_CHG_INT_ENA (BIT(6)) +#define LP_UART_CTS_CHG_INT_ENA_M (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S) +#define LP_UART_CTS_CHG_INT_ENA_V 0x00000001U +#define LP_UART_CTS_CHG_INT_ENA_S 6 +/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ +#define LP_UART_BRK_DET_INT_ENA (BIT(7)) +#define LP_UART_BRK_DET_INT_ENA_M (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S) +#define LP_UART_BRK_DET_INT_ENA_V 0x00000001U +#define LP_UART_BRK_DET_INT_ENA_S 7 +/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ +#define LP_UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_ENA_M (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S) +#define LP_UART_RXFIFO_TOUT_INT_ENA_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_ENA_S 8 +/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ +#define LP_UART_SW_XON_INT_ENA (BIT(9)) +#define LP_UART_SW_XON_INT_ENA_M (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S) +#define LP_UART_SW_XON_INT_ENA_V 0x00000001U +#define LP_UART_SW_XON_INT_ENA_S 9 +/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ +#define LP_UART_SW_XOFF_INT_ENA (BIT(10)) +#define LP_UART_SW_XOFF_INT_ENA_M (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S) +#define LP_UART_SW_XOFF_INT_ENA_V 0x00000001U +#define LP_UART_SW_XOFF_INT_ENA_S 10 +/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ +#define LP_UART_GLITCH_DET_INT_ENA (BIT(11)) +#define LP_UART_GLITCH_DET_INT_ENA_M (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S) +#define LP_UART_GLITCH_DET_INT_ENA_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_ENA_S 11 +/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ +#define LP_UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_ENA_M (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S) +#define LP_UART_TX_BRK_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_ENA_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ +#define LP_UART_TX_DONE_INT_ENA (BIT(14)) +#define LP_UART_TX_DONE_INT_ENA_M (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S) +#define LP_UART_TX_DONE_INT_ENA_V 0x00000001U +#define LP_UART_TX_DONE_INT_ENA_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ +#define LP_UART_WAKEUP_INT_ENA (BIT(19)) +#define LP_UART_WAKEUP_INT_ENA_M (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S) +#define LP_UART_WAKEUP_INT_ENA_V 0x00000001U +#define LP_UART_WAKEUP_INT_ENA_S 19 + +/** LP_UART_INT_CLR_REG register + * Interrupt clear bits + */ +#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10) +/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ +#define LP_UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define LP_UART_RXFIFO_FULL_INT_CLR_M (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S) +#define LP_UART_RXFIFO_FULL_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_FULL_INT_CLR_S 0 +/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ +#define LP_UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define LP_UART_TXFIFO_EMPTY_INT_CLR_M (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S) +#define LP_UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001U +#define LP_UART_TXFIFO_EMPTY_INT_CLR_S 1 +/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ +#define LP_UART_PARITY_ERR_INT_CLR (BIT(2)) +#define LP_UART_PARITY_ERR_INT_CLR_M (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S) +#define LP_UART_PARITY_ERR_INT_CLR_V 0x00000001U +#define LP_UART_PARITY_ERR_INT_CLR_S 2 +/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ +#define LP_UART_FRM_ERR_INT_CLR (BIT(3)) +#define LP_UART_FRM_ERR_INT_CLR_M (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S) +#define LP_UART_FRM_ERR_INT_CLR_V 0x00000001U +#define LP_UART_FRM_ERR_INT_CLR_S 3 +/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ +#define LP_UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define LP_UART_RXFIFO_OVF_INT_CLR_M (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S) +#define LP_UART_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_OVF_INT_CLR_S 4 +/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ +#define LP_UART_DSR_CHG_INT_CLR (BIT(5)) +#define LP_UART_DSR_CHG_INT_CLR_M (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S) +#define LP_UART_DSR_CHG_INT_CLR_V 0x00000001U +#define LP_UART_DSR_CHG_INT_CLR_S 5 +/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ +#define LP_UART_CTS_CHG_INT_CLR (BIT(6)) +#define LP_UART_CTS_CHG_INT_CLR_M (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S) +#define LP_UART_CTS_CHG_INT_CLR_V 0x00000001U +#define LP_UART_CTS_CHG_INT_CLR_S 6 +/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ +#define LP_UART_BRK_DET_INT_CLR (BIT(7)) +#define LP_UART_BRK_DET_INT_CLR_M (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S) +#define LP_UART_BRK_DET_INT_CLR_V 0x00000001U +#define LP_UART_BRK_DET_INT_CLR_S 7 +/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ +#define LP_UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define LP_UART_RXFIFO_TOUT_INT_CLR_M (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S) +#define LP_UART_RXFIFO_TOUT_INT_CLR_V 0x00000001U +#define LP_UART_RXFIFO_TOUT_INT_CLR_S 8 +/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ +#define LP_UART_SW_XON_INT_CLR (BIT(9)) +#define LP_UART_SW_XON_INT_CLR_M (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S) +#define LP_UART_SW_XON_INT_CLR_V 0x00000001U +#define LP_UART_SW_XON_INT_CLR_S 9 +/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ +#define LP_UART_SW_XOFF_INT_CLR (BIT(10)) +#define LP_UART_SW_XOFF_INT_CLR_M (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S) +#define LP_UART_SW_XOFF_INT_CLR_V 0x00000001U +#define LP_UART_SW_XOFF_INT_CLR_S 10 +/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ +#define LP_UART_GLITCH_DET_INT_CLR (BIT(11)) +#define LP_UART_GLITCH_DET_INT_CLR_M (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S) +#define LP_UART_GLITCH_DET_INT_CLR_V 0x00000001U +#define LP_UART_GLITCH_DET_INT_CLR_S 11 +/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ +#define LP_UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define LP_UART_TX_BRK_DONE_INT_CLR_M (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S) +#define LP_UART_TX_BRK_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_BRK_DONE_INT_CLR_S 12 +/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ +#define LP_UART_TX_DONE_INT_CLR (BIT(14)) +#define LP_UART_TX_DONE_INT_CLR_M (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S) +#define LP_UART_TX_DONE_INT_CLR_V 0x00000001U +#define LP_UART_TX_DONE_INT_CLR_S 14 +/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001U +#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ +#define LP_UART_WAKEUP_INT_CLR (BIT(19)) +#define LP_UART_WAKEUP_INT_CLR_M (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S) +#define LP_UART_WAKEUP_INT_CLR_V 0x00000001U +#define LP_UART_WAKEUP_INT_CLR_S 19 + +/** LP_UART_CLKDIV_SYNC_REG register + * Clock divider configuration + */ +#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14) +/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ +#define LP_UART_CLKDIV 0x00000FFFU +#define LP_UART_CLKDIV_M (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S) +#define LP_UART_CLKDIV_V 0x00000FFFU +#define LP_UART_CLKDIV_S 0 +/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ +#define LP_UART_CLKDIV_FRAG 0x0000000FU +#define LP_UART_CLKDIV_FRAG_M (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S) +#define LP_UART_CLKDIV_FRAG_V 0x0000000FU +#define LP_UART_CLKDIV_FRAG_S 20 + +/** LP_UART_RX_FILT_REG register + * Rx Filter configuration + */ +#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18) +/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ +#define LP_UART_GLITCH_FILT 0x000000FFU +#define LP_UART_GLITCH_FILT_M (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S) +#define LP_UART_GLITCH_FILT_V 0x000000FFU +#define LP_UART_GLITCH_FILT_S 0 +/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ +#define LP_UART_GLITCH_FILT_EN (BIT(8)) +#define LP_UART_GLITCH_FILT_EN_M (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S) +#define LP_UART_GLITCH_FILT_EN_V 0x00000001U +#define LP_UART_GLITCH_FILT_EN_S 8 + +/** LP_UART_STATUS_REG register + * UART status register + */ +#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c) +/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ +#define LP_UART_RXFIFO_CNT 0x0000001FU +#define LP_UART_RXFIFO_CNT_M (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S) +#define LP_UART_RXFIFO_CNT_V 0x0000001FU +#define LP_UART_RXFIFO_CNT_S 3 +/** LP_UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ +#define LP_UART_DSRN (BIT(13)) +#define LP_UART_DSRN_M (LP_UART_DSRN_V << LP_UART_DSRN_S) +#define LP_UART_DSRN_V 0x00000001U +#define LP_UART_DSRN_S 13 +/** LP_UART_CTSN : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ +#define LP_UART_CTSN (BIT(14)) +#define LP_UART_CTSN_M (LP_UART_CTSN_V << LP_UART_CTSN_S) +#define LP_UART_CTSN_V 0x00000001U +#define LP_UART_CTSN_S 14 +/** LP_UART_RXD : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ +#define LP_UART_RXD (BIT(15)) +#define LP_UART_RXD_M (LP_UART_RXD_V << LP_UART_RXD_S) +#define LP_UART_RXD_V 0x00000001U +#define LP_UART_RXD_S 15 +/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ +#define LP_UART_TXFIFO_CNT 0x0000001FU +#define LP_UART_TXFIFO_CNT_M (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S) +#define LP_UART_TXFIFO_CNT_V 0x0000001FU +#define LP_UART_TXFIFO_CNT_S 19 +/** LP_UART_DTRN : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ +#define LP_UART_DTRN (BIT(29)) +#define LP_UART_DTRN_M (LP_UART_DTRN_V << LP_UART_DTRN_S) +#define LP_UART_DTRN_V 0x00000001U +#define LP_UART_DTRN_S 29 +/** LP_UART_RTSN : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ +#define LP_UART_RTSN (BIT(30)) +#define LP_UART_RTSN_M (LP_UART_RTSN_V << LP_UART_RTSN_S) +#define LP_UART_RTSN_V 0x00000001U +#define LP_UART_RTSN_S 30 +/** LP_UART_TXD : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ +#define LP_UART_TXD (BIT(31)) +#define LP_UART_TXD_M (LP_UART_TXD_V << LP_UART_TXD_S) +#define LP_UART_TXD_V 0x00000001U +#define LP_UART_TXD_S 31 + +/** LP_UART_CONF0_SYNC_REG register + * Configuration register 0 + */ +#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20) +/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ +#define LP_UART_PARITY (BIT(0)) +#define LP_UART_PARITY_M (LP_UART_PARITY_V << LP_UART_PARITY_S) +#define LP_UART_PARITY_V 0x00000001U +#define LP_UART_PARITY_S 0 +/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ +#define LP_UART_PARITY_EN (BIT(1)) +#define LP_UART_PARITY_EN_M (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S) +#define LP_UART_PARITY_EN_V 0x00000001U +#define LP_UART_PARITY_EN_S 1 +/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ +#define LP_UART_BIT_NUM 0x00000003U +#define LP_UART_BIT_NUM_M (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S) +#define LP_UART_BIT_NUM_V 0x00000003U +#define LP_UART_BIT_NUM_S 2 +/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ +#define LP_UART_STOP_BIT_NUM 0x00000003U +#define LP_UART_STOP_BIT_NUM_M (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S) +#define LP_UART_STOP_BIT_NUM_V 0x00000003U +#define LP_UART_STOP_BIT_NUM_S 4 +/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ +#define LP_UART_TXD_BRK (BIT(6)) +#define LP_UART_TXD_BRK_M (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S) +#define LP_UART_TXD_BRK_V 0x00000001U +#define LP_UART_TXD_BRK_S 6 +/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ +#define LP_UART_LOOPBACK (BIT(12)) +#define LP_UART_LOOPBACK_M (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S) +#define LP_UART_LOOPBACK_V 0x00000001U +#define LP_UART_LOOPBACK_S 12 +/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ +#define LP_UART_TX_FLOW_EN (BIT(13)) +#define LP_UART_TX_FLOW_EN_M (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S) +#define LP_UART_TX_FLOW_EN_V 0x00000001U +#define LP_UART_TX_FLOW_EN_S 13 +/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ +#define LP_UART_RXD_INV (BIT(15)) +#define LP_UART_RXD_INV_M (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S) +#define LP_UART_RXD_INV_V 0x00000001U +#define LP_UART_RXD_INV_S 15 +/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ +#define LP_UART_TXD_INV (BIT(16)) +#define LP_UART_TXD_INV_M (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S) +#define LP_UART_TXD_INV_V 0x00000001U +#define LP_UART_TXD_INV_S 16 +/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ +#define LP_UART_DIS_RX_DAT_OVF (BIT(17)) +#define LP_UART_DIS_RX_DAT_OVF_M (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S) +#define LP_UART_DIS_RX_DAT_OVF_V 0x00000001U +#define LP_UART_DIS_RX_DAT_OVF_S 17 +/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ +#define LP_UART_ERR_WR_MASK (BIT(18)) +#define LP_UART_ERR_WR_MASK_M (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S) +#define LP_UART_ERR_WR_MASK_V 0x00000001U +#define LP_UART_ERR_WR_MASK_S 18 +/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ +#define LP_UART_MEM_CLK_EN (BIT(20)) +#define LP_UART_MEM_CLK_EN_M (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S) +#define LP_UART_MEM_CLK_EN_V 0x00000001U +#define LP_UART_MEM_CLK_EN_S 20 +/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ +#define LP_UART_SW_RTS (BIT(21)) +#define LP_UART_SW_RTS_M (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S) +#define LP_UART_SW_RTS_V 0x00000001U +#define LP_UART_SW_RTS_S 21 +/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ +#define LP_UART_RXFIFO_RST (BIT(22)) +#define LP_UART_RXFIFO_RST_M (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S) +#define LP_UART_RXFIFO_RST_V 0x00000001U +#define LP_UART_RXFIFO_RST_S 22 +/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ +#define LP_UART_TXFIFO_RST (BIT(23)) +#define LP_UART_TXFIFO_RST_M (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S) +#define LP_UART_TXFIFO_RST_V 0x00000001U +#define LP_UART_TXFIFO_RST_S 23 + +/** LP_UART_CONF1_REG register + * Configuration register 1 + */ +#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24) +/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ +#define LP_UART_RXFIFO_FULL_THRHD 0x0000001FU +#define LP_UART_RXFIFO_FULL_THRHD_M (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S) +#define LP_UART_RXFIFO_FULL_THRHD_V 0x0000001FU +#define LP_UART_RXFIFO_FULL_THRHD_S 3 +/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ +#define LP_UART_TXFIFO_EMPTY_THRHD 0x0000001FU +#define LP_UART_TXFIFO_EMPTY_THRHD_M (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S) +#define LP_UART_TXFIFO_EMPTY_THRHD_V 0x0000001FU +#define LP_UART_TXFIFO_EMPTY_THRHD_S 11 +/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ +#define LP_UART_CTS_INV (BIT(16)) +#define LP_UART_CTS_INV_M (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S) +#define LP_UART_CTS_INV_V 0x00000001U +#define LP_UART_CTS_INV_S 16 +/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ +#define LP_UART_DSR_INV (BIT(17)) +#define LP_UART_DSR_INV_M (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S) +#define LP_UART_DSR_INV_V 0x00000001U +#define LP_UART_DSR_INV_S 17 +/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ +#define LP_UART_RTS_INV (BIT(18)) +#define LP_UART_RTS_INV_M (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S) +#define LP_UART_RTS_INV_V 0x00000001U +#define LP_UART_RTS_INV_S 18 +/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ +#define LP_UART_DTR_INV (BIT(19)) +#define LP_UART_DTR_INV_M (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S) +#define LP_UART_DTR_INV_V 0x00000001U +#define LP_UART_DTR_INV_S 19 +/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ +#define LP_UART_SW_DTR (BIT(20)) +#define LP_UART_SW_DTR_M (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S) +#define LP_UART_SW_DTR_V 0x00000001U +#define LP_UART_SW_DTR_S 20 +/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define LP_UART_CLK_EN (BIT(21)) +#define LP_UART_CLK_EN_M (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S) +#define LP_UART_CLK_EN_V 0x00000001U +#define LP_UART_CLK_EN_S 21 + +/** LP_UART_HWFC_CONF_SYNC_REG register + * Hardware flow-control configuration + */ +#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c) +/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ +#define LP_UART_RX_FLOW_THRHD 0x0000001FU +#define LP_UART_RX_FLOW_THRHD_M (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S) +#define LP_UART_RX_FLOW_THRHD_V 0x0000001FU +#define LP_UART_RX_FLOW_THRHD_S 3 +/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ +#define LP_UART_RX_FLOW_EN (BIT(8)) +#define LP_UART_RX_FLOW_EN_M (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S) +#define LP_UART_RX_FLOW_EN_V 0x00000001U +#define LP_UART_RX_FLOW_EN_S 8 + +/** LP_UART_SLEEP_CONF0_REG register + * UART sleep configure register 0 + */ +#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30) +/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ +#define LP_UART_WK_CHAR1 0x000000FFU +#define LP_UART_WK_CHAR1_M (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S) +#define LP_UART_WK_CHAR1_V 0x000000FFU +#define LP_UART_WK_CHAR1_S 0 +/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ +#define LP_UART_WK_CHAR2 0x000000FFU +#define LP_UART_WK_CHAR2_M (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S) +#define LP_UART_WK_CHAR2_V 0x000000FFU +#define LP_UART_WK_CHAR2_S 8 +/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ +#define LP_UART_WK_CHAR3 0x000000FFU +#define LP_UART_WK_CHAR3_M (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S) +#define LP_UART_WK_CHAR3_V 0x000000FFU +#define LP_UART_WK_CHAR3_S 16 +/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ +#define LP_UART_WK_CHAR4 0x000000FFU +#define LP_UART_WK_CHAR4_M (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S) +#define LP_UART_WK_CHAR4_V 0x000000FFU +#define LP_UART_WK_CHAR4_S 24 + +/** LP_UART_SLEEP_CONF1_REG register + * UART sleep configure register 1 + */ +#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34) +/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ +#define LP_UART_WK_CHAR0 0x000000FFU +#define LP_UART_WK_CHAR0_M (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S) +#define LP_UART_WK_CHAR0_V 0x000000FFU +#define LP_UART_WK_CHAR0_S 0 + +/** LP_UART_SLEEP_CONF2_REG register + * UART sleep configure register 2 + */ +#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38) +/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ +#define LP_UART_ACTIVE_THRESHOLD 0x000003FFU +#define LP_UART_ACTIVE_THRESHOLD_M (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S) +#define LP_UART_ACTIVE_THRESHOLD_V 0x000003FFU +#define LP_UART_ACTIVE_THRESHOLD_S 0 +/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ +#define LP_UART_RX_WAKE_UP_THRHD 0x0000001FU +#define LP_UART_RX_WAKE_UP_THRHD_M (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S) +#define LP_UART_RX_WAKE_UP_THRHD_V 0x0000001FU +#define LP_UART_RX_WAKE_UP_THRHD_S 13 +/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ +#define LP_UART_WK_CHAR_NUM 0x00000007U +#define LP_UART_WK_CHAR_NUM_M (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S) +#define LP_UART_WK_CHAR_NUM_V 0x00000007U +#define LP_UART_WK_CHAR_NUM_S 18 +/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ +#define LP_UART_WK_CHAR_MASK 0x0000001FU +#define LP_UART_WK_CHAR_MASK_M (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S) +#define LP_UART_WK_CHAR_MASK_V 0x0000001FU +#define LP_UART_WK_CHAR_MASK_S 21 +/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ +#define LP_UART_WK_MODE_SEL 0x00000003U +#define LP_UART_WK_MODE_SEL_M (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S) +#define LP_UART_WK_MODE_SEL_V 0x00000003U +#define LP_UART_WK_MODE_SEL_S 26 + +/** LP_UART_SWFC_CONF0_SYNC_REG register + * Software flow-control character configuration + */ +#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c) +/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ +#define LP_UART_XON_CHAR 0x000000FFU +#define LP_UART_XON_CHAR_M (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S) +#define LP_UART_XON_CHAR_V 0x000000FFU +#define LP_UART_XON_CHAR_S 0 +/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ +#define LP_UART_XOFF_CHAR 0x000000FFU +#define LP_UART_XOFF_CHAR_M (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S) +#define LP_UART_XOFF_CHAR_V 0x000000FFU +#define LP_UART_XOFF_CHAR_S 8 +/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ +#define LP_UART_XON_XOFF_STILL_SEND (BIT(16)) +#define LP_UART_XON_XOFF_STILL_SEND_M (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S) +#define LP_UART_XON_XOFF_STILL_SEND_V 0x00000001U +#define LP_UART_XON_XOFF_STILL_SEND_S 16 +/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ +#define LP_UART_SW_FLOW_CON_EN (BIT(17)) +#define LP_UART_SW_FLOW_CON_EN_M (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S) +#define LP_UART_SW_FLOW_CON_EN_V 0x00000001U +#define LP_UART_SW_FLOW_CON_EN_S 17 +/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ +#define LP_UART_XONOFF_DEL (BIT(18)) +#define LP_UART_XONOFF_DEL_M (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S) +#define LP_UART_XONOFF_DEL_V 0x00000001U +#define LP_UART_XONOFF_DEL_S 18 +/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ +#define LP_UART_FORCE_XON (BIT(19)) +#define LP_UART_FORCE_XON_M (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S) +#define LP_UART_FORCE_XON_V 0x00000001U +#define LP_UART_FORCE_XON_S 19 +/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ +#define LP_UART_FORCE_XOFF (BIT(20)) +#define LP_UART_FORCE_XOFF_M (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S) +#define LP_UART_FORCE_XOFF_V 0x00000001U +#define LP_UART_FORCE_XOFF_S 20 +/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ +#define LP_UART_SEND_XON (BIT(21)) +#define LP_UART_SEND_XON_M (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S) +#define LP_UART_SEND_XON_V 0x00000001U +#define LP_UART_SEND_XON_S 21 +/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ +#define LP_UART_SEND_XOFF (BIT(22)) +#define LP_UART_SEND_XOFF_M (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S) +#define LP_UART_SEND_XOFF_V 0x00000001U +#define LP_UART_SEND_XOFF_S 22 + +/** LP_UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ +#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40) +/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ +#define LP_UART_XON_THRESHOLD 0x0000001FU +#define LP_UART_XON_THRESHOLD_M (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S) +#define LP_UART_XON_THRESHOLD_V 0x0000001FU +#define LP_UART_XON_THRESHOLD_S 3 +/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ +#define LP_UART_XOFF_THRESHOLD 0x0000001FU +#define LP_UART_XOFF_THRESHOLD_M (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S) +#define LP_UART_XOFF_THRESHOLD_V 0x0000001FU +#define LP_UART_XOFF_THRESHOLD_S 11 + +/** LP_UART_TXBRK_CONF_SYNC_REG register + * Tx Break character configuration + */ +#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44) +/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ +#define LP_UART_TX_BRK_NUM 0x000000FFU +#define LP_UART_TX_BRK_NUM_M (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S) +#define LP_UART_TX_BRK_NUM_V 0x000000FFU +#define LP_UART_TX_BRK_NUM_S 0 + +/** LP_UART_IDLE_CONF_SYNC_REG register + * Frame-end idle configuration + */ +#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48) +/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ +#define LP_UART_RX_IDLE_THRHD 0x000003FFU +#define LP_UART_RX_IDLE_THRHD_M (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S) +#define LP_UART_RX_IDLE_THRHD_V 0x000003FFU +#define LP_UART_RX_IDLE_THRHD_S 0 +/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ +#define LP_UART_TX_IDLE_NUM 0x000003FFU +#define LP_UART_TX_IDLE_NUM_M (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S) +#define LP_UART_TX_IDLE_NUM_V 0x000003FFU +#define LP_UART_TX_IDLE_NUM_S 10 + +/** LP_UART_RS485_CONF_SYNC_REG register + * RS485 mode configuration + */ +#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c) +/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define LP_UART_DL0_EN (BIT(1)) +#define LP_UART_DL0_EN_M (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S) +#define LP_UART_DL0_EN_V 0x00000001U +#define LP_UART_DL0_EN_S 1 +/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ +#define LP_UART_DL1_EN (BIT(2)) +#define LP_UART_DL1_EN_M (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S) +#define LP_UART_DL1_EN_V 0x00000001U +#define LP_UART_DL1_EN_S 2 + +/** LP_UART_AT_CMD_PRECNT_SYNC_REG register + * Pre-sequence timing configuration + */ +#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50) +/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ +#define LP_UART_PRE_IDLE_NUM 0x0000FFFFU +#define LP_UART_PRE_IDLE_NUM_M (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S) +#define LP_UART_PRE_IDLE_NUM_V 0x0000FFFFU +#define LP_UART_PRE_IDLE_NUM_S 0 + +/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register + * Post-sequence timing configuration + */ +#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54) +/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ +#define LP_UART_POST_IDLE_NUM 0x0000FFFFU +#define LP_UART_POST_IDLE_NUM_M (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S) +#define LP_UART_POST_IDLE_NUM_V 0x0000FFFFU +#define LP_UART_POST_IDLE_NUM_S 0 + +/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register + * Timeout configuration + */ +#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58) +/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ +#define LP_UART_RX_GAP_TOUT 0x0000FFFFU +#define LP_UART_RX_GAP_TOUT_M (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S) +#define LP_UART_RX_GAP_TOUT_V 0x0000FFFFU +#define LP_UART_RX_GAP_TOUT_S 0 + +/** LP_UART_AT_CMD_CHAR_SYNC_REG register + * AT escape sequence detection configuration + */ +#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c) +/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ +#define LP_UART_AT_CMD_CHAR 0x000000FFU +#define LP_UART_AT_CMD_CHAR_M (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S) +#define LP_UART_AT_CMD_CHAR_V 0x000000FFU +#define LP_UART_AT_CMD_CHAR_S 0 +/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ +#define LP_UART_CHAR_NUM 0x000000FFU +#define LP_UART_CHAR_NUM_M (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S) +#define LP_UART_CHAR_NUM_V 0x000000FFU +#define LP_UART_CHAR_NUM_S 8 + +/** LP_UART_MEM_CONF_REG register + * UART memory power configuration + */ +#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60) +/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ +#define LP_UART_MEM_FORCE_PD (BIT(25)) +#define LP_UART_MEM_FORCE_PD_M (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S) +#define LP_UART_MEM_FORCE_PD_V 0x00000001U +#define LP_UART_MEM_FORCE_PD_S 25 +/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ +#define LP_UART_MEM_FORCE_PU (BIT(26)) +#define LP_UART_MEM_FORCE_PU_M (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S) +#define LP_UART_MEM_FORCE_PU_V 0x00000001U +#define LP_UART_MEM_FORCE_PU_S 26 + +/** LP_UART_TOUT_CONF_SYNC_REG register + * UART threshold and allocation configuration + */ +#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64) +/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ +#define LP_UART_RX_TOUT_EN (BIT(0)) +#define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S) +#define LP_UART_RX_TOUT_EN_V 0x00000001U +#define LP_UART_RX_TOUT_EN_S 0 +/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ +#define LP_UART_RX_TOUT_FLOW_DIS (BIT(1)) +#define LP_UART_RX_TOUT_FLOW_DIS_M (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S) +#define LP_UART_RX_TOUT_FLOW_DIS_V 0x00000001U +#define LP_UART_RX_TOUT_FLOW_DIS_S 1 +/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ +#define LP_UART_RX_TOUT_THRHD 0x000003FFU +#define LP_UART_RX_TOUT_THRHD_M (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S) +#define LP_UART_RX_TOUT_THRHD_V 0x000003FFU +#define LP_UART_RX_TOUT_THRHD_S 2 + +/** LP_UART_MEM_TX_STATUS_REG register + * Tx-SRAM write and read offset address. + */ +#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68) +/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ +#define LP_UART_TX_SRAM_WADDR 0x0000001FU +#define LP_UART_TX_SRAM_WADDR_M (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S) +#define LP_UART_TX_SRAM_WADDR_V 0x0000001FU +#define LP_UART_TX_SRAM_WADDR_S 3 +/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ +#define LP_UART_TX_SRAM_RADDR 0x0000001FU +#define LP_UART_TX_SRAM_RADDR_M (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S) +#define LP_UART_TX_SRAM_RADDR_V 0x0000001FU +#define LP_UART_TX_SRAM_RADDR_S 12 + +/** LP_UART_MEM_RX_STATUS_REG register + * Rx-SRAM write and read offset address. + */ +#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c) +/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16; + * This register stores the offset read address in RX-SRAM. + */ +#define LP_UART_RX_SRAM_RADDR 0x0000001FU +#define LP_UART_RX_SRAM_RADDR_M (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S) +#define LP_UART_RX_SRAM_RADDR_V 0x0000001FU +#define LP_UART_RX_SRAM_RADDR_S 3 +/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16; + * This register stores the offset write address in Rx-SRAM. + */ +#define LP_UART_RX_SRAM_WADDR 0x0000001FU +#define LP_UART_RX_SRAM_WADDR_M (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S) +#define LP_UART_RX_SRAM_WADDR_V 0x0000001FU +#define LP_UART_RX_SRAM_WADDR_S 12 + +/** LP_UART_FSM_STATUS_REG register + * UART transmit and receive status. + */ +#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70) +/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ +#define LP_UART_ST_URX_OUT 0x0000000FU +#define LP_UART_ST_URX_OUT_M (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S) +#define LP_UART_ST_URX_OUT_V 0x0000000FU +#define LP_UART_ST_URX_OUT_S 0 +/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ +#define LP_UART_ST_UTX_OUT 0x0000000FU +#define LP_UART_ST_UTX_OUT_M (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S) +#define LP_UART_ST_UTX_OUT_V 0x0000000FU +#define LP_UART_ST_UTX_OUT_S 4 + +/** LP_UART_CLK_CONF_REG register + * UART core clock configuration + */ +#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88) +/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_B 0x0000003FU +#define LP_UART_SCLK_DIV_B_M (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S) +#define LP_UART_SCLK_DIV_B_V 0x0000003FU +#define LP_UART_SCLK_DIV_B_S 0 +/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_A 0x0000003FU +#define LP_UART_SCLK_DIV_A_M (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S) +#define LP_UART_SCLK_DIV_A_V 0x0000003FU +#define LP_UART_SCLK_DIV_A_S 6 +/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ +#define LP_UART_SCLK_DIV_NUM 0x000000FFU +#define LP_UART_SCLK_DIV_NUM_M (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S) +#define LP_UART_SCLK_DIV_NUM_V 0x000000FFU +#define LP_UART_SCLK_DIV_NUM_S 12 +/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ +#define LP_UART_SCLK_SEL 0x00000003U +#define LP_UART_SCLK_SEL_M (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S) +#define LP_UART_SCLK_SEL_V 0x00000003U +#define LP_UART_SCLK_SEL_S 20 +/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ +#define LP_UART_SCLK_EN (BIT(22)) +#define LP_UART_SCLK_EN_M (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S) +#define LP_UART_SCLK_EN_V 0x00000001U +#define LP_UART_SCLK_EN_S 22 +/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ +#define LP_UART_RST_CORE (BIT(23)) +#define LP_UART_RST_CORE_M (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S) +#define LP_UART_RST_CORE_V 0x00000001U +#define LP_UART_RST_CORE_S 23 +/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ +#define LP_UART_TX_SCLK_EN (BIT(24)) +#define LP_UART_TX_SCLK_EN_M (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S) +#define LP_UART_TX_SCLK_EN_V 0x00000001U +#define LP_UART_TX_SCLK_EN_S 24 +/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ +#define LP_UART_RX_SCLK_EN (BIT(25)) +#define LP_UART_RX_SCLK_EN_M (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S) +#define LP_UART_RX_SCLK_EN_V 0x00000001U +#define LP_UART_RX_SCLK_EN_S 25 +/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ +#define LP_UART_TX_RST_CORE (BIT(26)) +#define LP_UART_TX_RST_CORE_M (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S) +#define LP_UART_TX_RST_CORE_V 0x00000001U +#define LP_UART_TX_RST_CORE_S 26 +/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ +#define LP_UART_RX_RST_CORE (BIT(27)) +#define LP_UART_RX_RST_CORE_M (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S) +#define LP_UART_RX_RST_CORE_V 0x00000001U +#define LP_UART_RX_RST_CORE_S 27 + +/** LP_UART_DATE_REG register + * UART Version register + */ +#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c) +/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ +#define LP_UART_DATE 0xFFFFFFFFU +#define LP_UART_DATE_M (LP_UART_DATE_V << LP_UART_DATE_S) +#define LP_UART_DATE_V 0xFFFFFFFFU +#define LP_UART_DATE_S 0 + +/** LP_UART_AFIFO_STATUS_REG register + * UART AFIFO Status + */ +#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90) +/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ +#define LP_UART_TX_AFIFO_FULL (BIT(0)) +#define LP_UART_TX_AFIFO_FULL_M (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S) +#define LP_UART_TX_AFIFO_FULL_V 0x00000001U +#define LP_UART_TX_AFIFO_FULL_S 0 +/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ +#define LP_UART_TX_AFIFO_EMPTY (BIT(1)) +#define LP_UART_TX_AFIFO_EMPTY_M (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S) +#define LP_UART_TX_AFIFO_EMPTY_V 0x00000001U +#define LP_UART_TX_AFIFO_EMPTY_S 1 +/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ +#define LP_UART_RX_AFIFO_FULL (BIT(2)) +#define LP_UART_RX_AFIFO_FULL_M (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S) +#define LP_UART_RX_AFIFO_FULL_V 0x00000001U +#define LP_UART_RX_AFIFO_FULL_S 2 +/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ +#define LP_UART_RX_AFIFO_EMPTY (BIT(3)) +#define LP_UART_RX_AFIFO_EMPTY_M (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S) +#define LP_UART_RX_AFIFO_EMPTY_V 0x00000001U +#define LP_UART_RX_AFIFO_EMPTY_S 3 + +/** LP_UART_REG_UPDATE_REG register + * UART Registers Configuration Update register + */ +#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98) +/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ +#define LP_UART_REG_UPDATE (BIT(0)) +#define LP_UART_REG_UPDATE_M (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S) +#define LP_UART_REG_UPDATE_V 0x00000001U +#define LP_UART_REG_UPDATE_S 0 + +/** LP_UART_ID_REG register + * UART ID register + */ +#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c) +/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ +#define LP_UART_ID 0xFFFFFFFFU +#define LP_UART_ID_M (LP_UART_ID_V << LP_UART_ID_S) +#define LP_UART_ID_V 0xFFFFFFFFU +#define LP_UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lp_uart_struct.h b/components/soc/esp32c5/include/soc/lp_uart_struct.h new file mode 100644 index 0000000000..e47a691f22 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lp_uart_struct.h @@ -0,0 +1,1127 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO Configuration */ +/** Type of fifo register + * FIFO data register + */ +typedef union { + struct { + /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; + * UART $n accesses FIFO via this register. + */ + uint32_t rxfifo_rd_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_fifo_reg_t; + +/** Type of mem_conf register + * UART memory power configuration + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** mem_force_pd : R/W; bitpos: [25]; default: 0; + * Set this bit to force power down UART memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [26]; default: 0; + * Set this bit to force power up UART memory. + */ + uint32_t mem_force_pu:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} lp_uart_mem_conf_reg_t; + +/** Type of tout_conf_sync register + * UART threshold and allocation configuration + */ +typedef union { + struct { + /** rx_tout_en : R/W; bitpos: [0]; default: 0; + * This is the enble bit for uart receiver's timeout function. + */ + uint32_t rx_tout_en:1; + /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control works. + */ + uint32_t rx_tout_flow_dis:1; + /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10; + * This register is used to configure the threshold time that receiver takes to + * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver + * takes more time to receive one byte with rx_tout_en set to 1. + */ + uint32_t rx_tout_thrhd:10; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_uart_tout_conf_sync_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * what rxfifo_full_thrhd specifies. + */ + uint32_t rxfifo_full_int_raw:1; + /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; + * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is + * less than what txfifo_empty_thrhd specifies . + */ + uint32_t txfifo_empty_int_raw:1; + /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity error in + * the data. + */ + uint32_t parity_err_int_raw:1; + /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data frame error + * . + */ + uint32_t frm_err_int_raw:1; + /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more data than + * the FIFO can store. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * DSRn signal. + */ + uint32_t dsr_chg_int_raw:1; + /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge change of + * CTSn signal. + */ + uint32_t cts_chg_int_raw:1; + /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 after the stop + * bit. + */ + uint32_t brk_det_int_raw:1; + /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time than + * rx_tout_thrhd to receive a byte. + */ + uint32_t rxfifo_tout_int_raw:1; + /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver recevies Xon char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xon_int_raw:1; + /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives Xoff char when + * uart_sw_flow_con_en is set to 1. + */ + uint32_t sw_xoff_int_raw:1; + /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch in the + * middle of a start bit. + */ + uint32_t glitch_det_int_raw:1; + /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes sending + * NULL characters after all data in Tx-FIFO are sent. + */ + uint32_t tx_brk_done_int_raw:1; + /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the shortest + * duration after sending the last data. + */ + uint32_t tx_brk_idle_done_int_raw:1; + /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has send out all data + * in FIFO. + */ + uint32_t tx_done_int_raw:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the configured + * at_cmd char. + */ + uint32_t at_cmd_char_det_int_raw:1; + /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes more times + * than what reg_active_threshold specifies in light sleeping mode. + */ + uint32_t wakeup_int_raw:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; + * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + */ + uint32_t rxfifo_full_int_st:1; + /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; + * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set + * to 1. + */ + uint32_t txfifo_empty_int_st:1; + /** parity_err_int_st : RO; bitpos: [2]; default: 0; + * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + */ + uint32_t parity_err_int_st:1; + /** frm_err_int_st : RO; bitpos: [3]; default: 0; + * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + */ + uint32_t frm_err_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; + * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + */ + uint32_t rxfifo_ovf_int_st:1; + /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; + * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + */ + uint32_t dsr_chg_int_st:1; + /** cts_chg_int_st : RO; bitpos: [6]; default: 0; + * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + */ + uint32_t cts_chg_int_st:1; + /** brk_det_int_st : RO; bitpos: [7]; default: 0; + * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + */ + uint32_t brk_det_int_st:1; + /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; + * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + */ + uint32_t rxfifo_tout_int_st:1; + /** sw_xon_int_st : RO; bitpos: [9]; default: 0; + * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + */ + uint32_t sw_xon_int_st:1; + /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; + * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + */ + uint32_t sw_xoff_int_st:1; + /** glitch_det_int_st : RO; bitpos: [11]; default: 0; + * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + */ + uint32_t glitch_det_int_st:1; + /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; + * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + */ + uint32_t tx_brk_done_int_st:1; + /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; + * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena + * is set to 1. + */ + uint32_t tx_brk_idle_done_int_st:1; + /** tx_done_int_st : RO; bitpos: [14]; default: 0; + * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + */ + uint32_t tx_done_int_st:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; + * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set + * to 1. + */ + uint32_t at_cmd_char_det_int_st:1; + /** wakeup_int_st : RO; bitpos: [19]; default: 0; + * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + */ + uint32_t wakeup_int_st:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; + * This is the enable bit for rxfifo_full_int_st register. + */ + uint32_t rxfifo_full_int_ena:1; + /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; + * This is the enable bit for txfifo_empty_int_st register. + */ + uint32_t txfifo_empty_int_ena:1; + /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; + * This is the enable bit for parity_err_int_st register. + */ + uint32_t parity_err_int_ena:1; + /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; + * This is the enable bit for frm_err_int_st register. + */ + uint32_t frm_err_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; + * This is the enable bit for rxfifo_ovf_int_st register. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; + * This is the enable bit for dsr_chg_int_st register. + */ + uint32_t dsr_chg_int_ena:1; + /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; + * This is the enable bit for cts_chg_int_st register. + */ + uint32_t cts_chg_int_ena:1; + /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; + * This is the enable bit for brk_det_int_st register. + */ + uint32_t brk_det_int_ena:1; + /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; + * This is the enable bit for rxfifo_tout_int_st register. + */ + uint32_t rxfifo_tout_int_ena:1; + /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; + * This is the enable bit for sw_xon_int_st register. + */ + uint32_t sw_xon_int_ena:1; + /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; + * This is the enable bit for sw_xoff_int_st register. + */ + uint32_t sw_xoff_int_ena:1; + /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; + * This is the enable bit for glitch_det_int_st register. + */ + uint32_t glitch_det_int_ena:1; + /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; + * This is the enable bit for tx_brk_done_int_st register. + */ + uint32_t tx_brk_done_int_ena:1; + /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; + * This is the enable bit for tx_brk_idle_done_int_st register. + */ + uint32_t tx_brk_idle_done_int_ena:1; + /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * This is the enable bit for tx_done_int_st register. + */ + uint32_t tx_done_int_ena:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; + * This is the enable bit for at_cmd_char_det_int_st register. + */ + uint32_t at_cmd_char_det_int_ena:1; + /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; + * This is the enable bit for uart_wakeup_int_st register. + */ + uint32_t wakeup_int_ena:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the rxfifo_full_int_raw interrupt. + */ + uint32_t rxfifo_full_int_clr:1; + /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear txfifo_empty_int_raw interrupt. + */ + uint32_t txfifo_empty_int_clr:1; + /** parity_err_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear parity_err_int_raw interrupt. + */ + uint32_t parity_err_int_clr:1; + /** frm_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear frm_err_int_raw interrupt. + */ + uint32_t frm_err_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear rxfifo_ovf_int_raw interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the dsr_chg_int_raw interrupt. + */ + uint32_t dsr_chg_int_clr:1; + /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the cts_chg_int_raw interrupt. + */ + uint32_t cts_chg_int_clr:1; + /** brk_det_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the brk_det_int_raw interrupt. + */ + uint32_t brk_det_int_clr:1; + /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the rxfifo_tout_int_raw interrupt. + */ + uint32_t rxfifo_tout_int_clr:1; + /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the sw_xon_int_raw interrupt. + */ + uint32_t sw_xon_int_clr:1; + /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the sw_xoff_int_raw interrupt. + */ + uint32_t sw_xoff_int_clr:1; + /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the glitch_det_int_raw interrupt. + */ + uint32_t glitch_det_int_clr:1; + /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the tx_brk_done_int_raw interrupt.. + */ + uint32_t tx_brk_done_int_clr:1; + /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + */ + uint32_t tx_brk_idle_done_int_clr:1; + /** tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the tx_done_int_raw interrupt. + */ + uint32_t tx_done_int_clr:1; + uint32_t reserved_15:3; + /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear the at_cmd_char_det_int_raw interrupt. + */ + uint32_t at_cmd_char_det_int_clr:1; + /** wakeup_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear the uart_wakeup_int_raw interrupt. + */ + uint32_t wakeup_int_clr:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_int_clr_reg_t; + + +/** Group: Configuration Register */ +/** Type of clkdiv_sync register + * Clock divider configuration + */ +typedef union { + struct { + /** clkdiv : R/W; bitpos: [11:0]; default: 694; + * The integral part of the frequency divider factor. + */ + uint32_t clkdiv:12; + uint32_t reserved_12:8; + /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divider factor. + */ + uint32_t clkdiv_frag:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_uart_clkdiv_sync_reg_t; + +/** Type of rx_filt register + * Rx Filter configuration + */ +typedef union { + struct { + /** glitch_filt : R/W; bitpos: [7:0]; default: 8; + * when input pulse width is lower than this value the pulse is ignored. + */ + uint32_t glitch_filt:8; + /** glitch_filt_en : R/W; bitpos: [8]; default: 0; + * Set this bit to enable Rx signal filter. + */ + uint32_t glitch_filt_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_uart_rx_filt_reg_t; + +/** Type of conf0_sync register + * Configuration register 0 + */ +typedef union { + struct { + /** parity : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + */ + uint32_t parity:1; + /** parity_en : R/W; bitpos: [1]; default: 0; + * Set this bit to enable uart parity check. + */ + uint32_t parity_en:1; + /** bit_num : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + */ + uint32_t bit_num:2; + /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + */ + uint32_t stop_bit_num:2; + /** txd_brk : R/W; bitpos: [6]; default: 0; + * Set this bit to enbale transmitter to send NULL when the process of sending data + * is done. + */ + uint32_t txd_brk:1; + uint32_t reserved_7:5; + /** loopback : R/W; bitpos: [12]; default: 0; + * Set this bit to enable uart loopback test mode. + */ + uint32_t loopback:1; + /** tx_flow_en : R/W; bitpos: [13]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + uint32_t tx_flow_en:1; + uint32_t reserved_14:1; + /** rxd_inv : R/W; bitpos: [15]; default: 0; + * Set this bit to inverse the level value of uart rxd signal. + */ + uint32_t rxd_inv:1; + /** txd_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart txd signal. + */ + uint32_t txd_inv:1; + /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0; + * Disable UART Rx data overflow detect. + */ + uint32_t dis_rx_dat_ovf:1; + /** err_wr_mask : R/W; bitpos: [18]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver + * stores the data even if the received data is wrong. + */ + uint32_t err_wr_mask:1; + uint32_t reserved_19:1; + /** mem_clk_en : R/W; bitpos: [20]; default: 1; + * UART memory clock gate enable signal. + */ + uint32_t mem_clk_en:1; + /** sw_rts : R/W; bitpos: [21]; default: 0; + * This register is used to configure the software rts signal which is used in + * software flow control. + */ + uint32_t sw_rts:1; + /** rxfifo_rst : R/W; bitpos: [22]; default: 0; + * Set this bit to reset the uart receive-FIFO. + */ + uint32_t rxfifo_rst:1; + /** txfifo_rst : R/W; bitpos: [23]; default: 0; + * Set this bit to reset the uart transmit-FIFO. + */ + uint32_t txfifo_rst:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_uart_conf0_sync_reg_t; + +/** Type of conf1 register + * Configuration register 1 + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12; + * It will produce rxfifo_full_int interrupt when receiver receives more data than + * this register value. + */ + uint32_t rxfifo_full_thrhd:5; + uint32_t reserved_8:3; + /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12; + * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less + * than this register value. + */ + uint32_t txfifo_empty_thrhd:5; + /** cts_inv : R/W; bitpos: [16]; default: 0; + * Set this bit to inverse the level value of uart cts signal. + */ + uint32_t cts_inv:1; + /** dsr_inv : R/W; bitpos: [17]; default: 0; + * Set this bit to inverse the level value of uart dsr signal. + */ + uint32_t dsr_inv:1; + /** rts_inv : R/W; bitpos: [18]; default: 0; + * Set this bit to inverse the level value of uart rts signal. + */ + uint32_t rts_inv:1; + /** dtr_inv : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of uart dtr signal. + */ + uint32_t dtr_inv:1; + /** sw_dtr : R/W; bitpos: [20]; default: 0; + * This register is used to configure the software dtr signal which is used in + * software flow control. + */ + uint32_t sw_dtr:1; + /** clk_en : R/W; bitpos: [21]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} lp_uart_conf1_reg_t; + +/** Type of hwfc_conf_sync register + * Hardware flow-control configuration + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0; + * This register is used to configure the maximum amount of data that can be received + * when hardware flow control works. + */ + uint32_t rx_flow_thrhd:5; + /** rx_flow_en : R/W; bitpos: [8]; default: 0; + * This is the flow enable bit for UART receiver. + */ + uint32_t rx_flow_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} lp_uart_hwfc_conf_sync_reg_t; + +/** Type of sleep_conf0 register + * UART sleep configure register 0 + */ +typedef union { + struct { + /** wk_char1 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified wake up char1 to wake up + */ + uint32_t wk_char1:8; + /** wk_char2 : R/W; bitpos: [15:8]; default: 0; + * This register restores the specified wake up char2 to wake up + */ + uint32_t wk_char2:8; + /** wk_char3 : R/W; bitpos: [23:16]; default: 0; + * This register restores the specified wake up char3 to wake up + */ + uint32_t wk_char3:8; + /** wk_char4 : R/W; bitpos: [31:24]; default: 0; + * This register restores the specified wake up char4 to wake up + */ + uint32_t wk_char4:8; + }; + uint32_t val; +} lp_uart_sleep_conf0_reg_t; + +/** Type of sleep_conf1 register + * UART sleep configure register 1 + */ +typedef union { + struct { + /** wk_char0 : R/W; bitpos: [7:0]; default: 0; + * This register restores the specified char0 to wake up + */ + uint32_t wk_char0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_sleep_conf1_reg_t; + +/** Type of sleep_conf2 register + * UART sleep configure register 2 + */ +typedef union { + struct { + /** active_threshold : R/W; bitpos: [9:0]; default: 240; + * The uart is activated from light sleeping mode when the input rxd edge changes more + * times than this register value. + */ + uint32_t active_threshold:10; + uint32_t reserved_10:3; + /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1; + * In wake up mode 1 this field is used to set the received data number threshold to + * wake up chip. + */ + uint32_t rx_wake_up_thrhd:5; + /** wk_char_num : R/W; bitpos: [20:18]; default: 5; + * This register is used to select number of wake up char. + */ + uint32_t wk_char_num:3; + /** wk_char_mask : R/W; bitpos: [25:21]; default: 0; + * This register is used to mask wake up char. + */ + uint32_t wk_char_mask:5; + /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0; + * This register is used to select wake up mode. 0: RXD toggling to wake up. 1: + * received data number larger than + */ + uint32_t wk_mode_sel:2; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_uart_sleep_conf2_reg_t; + +/** Type of swfc_conf0_sync register + * Software flow-control character configuration + */ +typedef union { + struct { + /** xon_char : R/W; bitpos: [7:0]; default: 17; + * This register stores the Xon flow control char. + */ + uint32_t xon_char:8; + /** xoff_char : R/W; bitpos: [15:8]; default: 19; + * This register stores the Xoff flow control char. + */ + uint32_t xoff_char:8; + /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0; + * In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In + * this status, UART Tx can not transmit XOFF even the received data number is larger + * than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when + * UART Tx is disabled. + */ + uint32_t xon_xoff_still_send:1; + /** sw_flow_con_en : R/W; bitpos: [17]; default: 0; + * Set this bit to enable software flow control. It is used with register sw_xon or + * sw_xoff. + */ + uint32_t sw_flow_con_en:1; + /** xonoff_del : R/W; bitpos: [18]; default: 0; + * Set this bit to remove flow control char from the received data. + */ + uint32_t xonoff_del:1; + /** force_xon : R/W; bitpos: [19]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + uint32_t force_xon:1; + /** force_xoff : R/W; bitpos: [20]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + uint32_t force_xoff:1; + /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0; + * Set this bit to send Xon char. It is cleared by hardware automatically. + */ + uint32_t send_xon:1; + /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0; + * Set this bit to send Xoff char. It is cleared by hardware automatically. + */ + uint32_t send_xoff:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_uart_swfc_conf0_sync_reg_t; + +/** Type of swfc_conf1 register + * Software flow-control character configuration + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** xon_threshold : R/W; bitpos: [7:3]; default: 0; + * When the data amount in Rx-FIFO is less than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xon char. + */ + uint32_t xon_threshold:5; + uint32_t reserved_8:3; + /** xoff_threshold : R/W; bitpos: [15:11]; default: 12; + * When the data amount in Rx-FIFO is more than this register value with + * uart_sw_flow_con_en set to 1 it will send a Xoff char. + */ + uint32_t xoff_threshold:5; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_swfc_conf1_reg_t; + +/** Type of txbrk_conf_sync register + * Tx Break character configuration + */ +typedef union { + struct { + /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; + * This register is used to configure the number of 0 to be sent after the process of + * sending data is done. It is active when txd_brk is set to 1. + */ + uint32_t tx_brk_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_txbrk_conf_sync_reg_t; + +/** Type of idle_conf_sync register + * Frame-end idle configuration + */ +typedef union { + struct { + /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive one byte + * data than this register value. + */ + uint32_t rx_idle_thrhd:10; + /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + uint32_t tx_idle_num:10; + uint32_t reserved_20:12; + }; + uint32_t val; +} lp_uart_idle_conf_sync_reg_t; + +/** Type of rs485_conf_sync register + * RS485 mode configuration + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** dl0_en : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl0_en:1; + /** dl1_en : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + uint32_t dl1_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_uart_rs485_conf_sync_reg_t; + +/** Type of clk_conf register + * UART core clock configuration + */ +typedef union { + struct { + /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor. + */ + uint32_t sclk_div_b:6; + /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor. + */ + uint32_t sclk_div_a:6; + /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor. + */ + uint32_t sclk_div_num:8; + /** sclk_sel : R/W; bitpos: [21:20]; default: 3; + * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. + */ + uint32_t sclk_sel:2; + /** sclk_en : R/W; bitpos: [22]; default: 1; + * Set this bit to enable UART Tx/Rx clock. + */ + uint32_t sclk_en:1; + /** rst_core : R/W; bitpos: [23]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx/Rx. + */ + uint32_t rst_core:1; + /** tx_sclk_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable UART Tx clock. + */ + uint32_t tx_sclk_en:1; + /** rx_sclk_en : R/W; bitpos: [25]; default: 1; + * Set this bit to enable UART Rx clock. + */ + uint32_t rx_sclk_en:1; + /** tx_rst_core : R/W; bitpos: [26]; default: 0; + * Write 1 then write 0 to this bit to reset UART Tx. + */ + uint32_t tx_rst_core:1; + /** rx_rst_core : R/W; bitpos: [27]; default: 0; + * Write 1 then write 0 to this bit to reset UART Rx. + */ + uint32_t rx_rst_core:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_uart_clk_conf_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * UART status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0; + * Stores the byte number of valid data in Rx-FIFO. + */ + uint32_t rxfifo_cnt:5; + uint32_t reserved_8:5; + /** dsrn : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal uart dsr signal. + */ + uint32_t dsrn:1; + /** ctsn : RO; bitpos: [14]; default: 1; + * This register represent the level value of the internal uart cts signal. + */ + uint32_t ctsn:1; + /** rxd : RO; bitpos: [15]; default: 1; + * This register represent the level value of the internal uart rxd signal. + */ + uint32_t rxd:1; + uint32_t reserved_16:3; + /** txfifo_cnt : RO; bitpos: [23:19]; default: 0; + * Stores the byte number of data in Tx-FIFO. + */ + uint32_t txfifo_cnt:5; + uint32_t reserved_24:5; + /** dtrn : RO; bitpos: [29]; default: 1; + * This bit represents the level of the internal uart dtr signal. + */ + uint32_t dtrn:1; + /** rtsn : RO; bitpos: [30]; default: 1; + * This bit represents the level of the internal uart rts signal. + */ + uint32_t rtsn:1; + /** txd : RO; bitpos: [31]; default: 1; + * This bit represents the level of the internal uart txd signal. + */ + uint32_t txd:1; + }; + uint32_t val; +} lp_uart_status_reg_t; + +/** Type of mem_tx_status register + * Tx-SRAM write and read offset address. + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0; + * This register stores the offset write address in Tx-SRAM. + */ + uint32_t tx_sram_waddr:5; + uint32_t reserved_8:4; + /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0; + * This register stores the offset read address in Tx-SRAM. + */ + uint32_t tx_sram_raddr:5; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_uart_mem_tx_status_reg_t; + +/** Type of mem_rx_status register + * Rx-SRAM write and read offset address. + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16; + * This register stores the offset read address in RX-SRAM. + */ + uint32_t rx_sram_raddr:5; + uint32_t reserved_8:4; + /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16; + * This register stores the offset write address in Rx-SRAM. + */ + uint32_t rx_sram_waddr:5; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_uart_mem_rx_status_reg_t; + +/** Type of fsm_status register + * UART transmit and receive status. + */ +typedef union { + struct { + /** st_urx_out : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + uint32_t st_urx_out:4; + /** st_utx_out : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + uint32_t st_utx_out:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_uart_fsm_status_reg_t; + +/** Type of afifo_status register + * UART AFIFO Status + */ +typedef union { + struct { + /** tx_afifo_full : RO; bitpos: [0]; default: 0; + * Full signal of APB TX AFIFO. + */ + uint32_t tx_afifo_full:1; + /** tx_afifo_empty : RO; bitpos: [1]; default: 1; + * Empty signal of APB TX AFIFO. + */ + uint32_t tx_afifo_empty:1; + /** rx_afifo_full : RO; bitpos: [2]; default: 0; + * Full signal of APB RX AFIFO. + */ + uint32_t rx_afifo_full:1; + /** rx_afifo_empty : RO; bitpos: [3]; default: 1; + * Empty signal of APB RX AFIFO. + */ + uint32_t rx_afifo_empty:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_uart_afifo_status_reg_t; + + +/** Group: AT Escape Sequence Selection Configuration */ +/** Type of at_cmd_precnt_sync register + * Pre-sequence timing configuration + */ +typedef union { + struct { + /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the first at_cmd + * is received by receiver. + */ + uint32_t pre_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_precnt_sync_reg_t; + +/** Type of at_cmd_postcnt_sync register + * Post-sequence timing configuration + */ +typedef union { + struct { + /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last at_cmd and + * the next data. + */ + uint32_t post_idle_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_postcnt_sync_reg_t; + +/** Type of at_cmd_gaptout_sync register + * Timeout configuration + */ +typedef union { + struct { + /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the at_cmd chars. + */ + uint32_t rx_gap_tout:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_gaptout_sync_reg_t; + +/** Type of at_cmd_char_sync register + * AT escape sequence detection configuration + */ +typedef union { + struct { + /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of at_cmd char. + */ + uint32_t at_cmd_char:8; + /** char_num : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the num of continuous at_cmd chars received by + * receiver. + */ + uint32_t char_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_uart_at_cmd_char_sync_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * UART Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35656288; + * This is the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} lp_uart_date_reg_t; + +/** Type of reg_update register + * UART Registers Configuration Update register + */ +typedef union { + struct { + /** reg_update : R/W/SC; bitpos: [0]; default: 0; + * Software write 1 would synchronize registers into UART Core clock domain and would + * be cleared by hardware after synchronization is done. + */ + uint32_t reg_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_uart_reg_update_reg_t; + +/** Type of id register + * UART ID register + */ +typedef union { + struct { + /** id : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the uart_id. + */ + uint32_t id:32; + }; + uint32_t val; +} lp_uart_id_reg_t; + + +typedef struct { + volatile lp_uart_fifo_reg_t fifo; + volatile lp_uart_int_raw_reg_t int_raw; + volatile lp_uart_int_st_reg_t int_st; + volatile lp_uart_int_ena_reg_t int_ena; + volatile lp_uart_int_clr_reg_t int_clr; + volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync; + volatile lp_uart_rx_filt_reg_t rx_filt; + volatile lp_uart_status_reg_t status; + volatile lp_uart_conf0_sync_reg_t conf0_sync; + volatile lp_uart_conf1_reg_t conf1; + uint32_t reserved_028; + volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync; + volatile lp_uart_sleep_conf0_reg_t sleep_conf0; + volatile lp_uart_sleep_conf1_reg_t sleep_conf1; + volatile lp_uart_sleep_conf2_reg_t sleep_conf2; + volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync; + volatile lp_uart_swfc_conf1_reg_t swfc_conf1; + volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync; + volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync; + volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync; + volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync; + volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync; + volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync; + volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync; + volatile lp_uart_mem_conf_reg_t mem_conf; + volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync; + volatile lp_uart_mem_tx_status_reg_t mem_tx_status; + volatile lp_uart_mem_rx_status_reg_t mem_rx_status; + volatile lp_uart_fsm_status_reg_t fsm_status; + uint32_t reserved_074[5]; + volatile lp_uart_clk_conf_reg_t clk_conf; + volatile lp_uart_date_reg_t date; + volatile lp_uart_afifo_status_reg_t afifo_status; + uint32_t reserved_094; + volatile lp_uart_reg_update_reg_t reg_update; + volatile lp_uart_id_reg_t id; +} lp_uart_dev_t; + +extern lp_uart_dev_t LP_UART; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lpperi_reg.h b/components/soc/esp32c5/include/soc/lpperi_reg.h new file mode 100644 index 0000000000..d3d5d79bc3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/lpperi_reg.h @@ -0,0 +1,317 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_CK_EN (BIT(26)) +#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) +#define LPPERI_LP_UART_CK_EN_V 0x00000001U +#define LPPERI_LP_UART_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) +#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_CK_EN_S 28 +/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) +#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_CK_EN_S 29 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_RESET_EN (BIT(26)) +#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) +#define LPPERI_LP_UART_RESET_EN_V 0x00000001U +#define LPPERI_LP_UART_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) +#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 +/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) +#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c) +/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) +#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_S 1 +/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) +#define LPPERI_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_UART_WAKEUP_EN_S 29 +/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) +#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PD_S 30 +/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) +#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_RNG_CFG_REG register + * need_des + */ +#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x24) +/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0)) +#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S) +#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U +#define LPPERI_RNG_SAMPLE_ENABLE_S 0 +/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * need des + */ +#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S) +#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_S 1 +/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * need des + */ +#define LPPERI_RNG_TIMER_EN (BIT(9)) +#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S) +#define LPPERI_RNG_TIMER_EN_V 0x00000001U +#define LPPERI_RNG_TIMER_EN_S 9 +/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S) +#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_S 24 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36720720; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/lpperi_struct.h b/components/soc/esp32c5/include/soc/lpperi_struct.h new file mode 100644 index 0000000000..767d0f981f --- /dev/null +++ b/components/soc/esp32c5/include/soc/lpperi_struct.h @@ -0,0 +1,289 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + uint32_t reserved_24:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of rng_cfg register + * need_des + */ +typedef union { + struct { + /** rng_sample_enable : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t rng_sample_enable:1; + /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255; + * need des + */ + uint32_t rng_timer_pscale:8; + /** rng_timer_en : R/W; bitpos: [9]; default: 1; + * need des + */ + uint32_t rng_timer_en:1; + uint32_t reserved_10:14; + /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0; + * need des + */ + uint32_t rng_sample_cnt:8; + }; + uint32_t val; +} lpperi_rng_cfg_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 36720720; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_rng_cfg_reg_t rng_cfg; + uint32_t reserved_028[245]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/mem_monitor_reg.h b/components/soc/esp32c5/include/soc/mem_monitor_reg.h new file mode 100644 index 0000000000..acda025df2 --- /dev/null +++ b/components/soc/esp32c5/include/soc/mem_monitor_reg.h @@ -0,0 +1,184 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** MEM_MONITOR_LOG_SETTING_REG register + * log config regsiter + */ +#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0) +/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0; + * enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA + */ +#define MEM_MONITOR_LOG_ENA 0x00000007U +#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S) +#define MEM_MONITOR_LOG_ENA_V 0x00000007U +#define MEM_MONITOR_LOG_ENA_S 0 +/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0; + * Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE + * monitor + */ +#define MEM_MONITOR_LOG_MODE 0x0000000FU +#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S) +#define MEM_MONITOR_LOG_MODE_V 0x0000000FU +#define MEM_MONITOR_LOG_MODE_S 3 +/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7)) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S) +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7 + +/** MEM_MONITOR_LOG_CHECK_DATA_REG register + * check data regsiter + */ +#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4) +/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ +#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S) +#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_CHECK_DATA_S 0 + +/** MEM_MONITOR_LOG_DATA_MASK_REG register + * check data mask register + */ +#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8) +/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ +#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S) +#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU +#define MEM_MONITOR_LOG_DATA_MASK_S 0 + +/** MEM_MONITOR_LOG_MIN_REG register + * log boundary regsiter + */ +#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc) +/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ +#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S) +#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MIN_S 0 + +/** MEM_MONITOR_LOG_MAX_REG register + * log boundary regsiter + */ +#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10) +/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ +#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S) +#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MAX_S 0 + +/** MEM_MONITOR_LOG_MEM_START_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14) +/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S) +#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_START_S 0 + +/** MEM_MONITOR_LOG_MEM_END_REG register + * log message store range register + */ +#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18) +/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ +#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S) +#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_END_S 0 + +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register + * current writing address. + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c) +/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S) +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0 + +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register + * writing address update + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20) +/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0)) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S) +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0 + +/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register + * full flag status register + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24) +/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ +#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0)) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0 +/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1)) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S) +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U +#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1 + +/** MEM_MONITOR_CLOCK_GATE_REG register + * clock gate force on register + */ +#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28) +/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ +#define MEM_MONITOR_CLK_EN (BIT(0)) +#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S) +#define MEM_MONITOR_CLK_EN_V 0x00000001U +#define MEM_MONITOR_CLK_EN_S 0 + +/** MEM_MONITOR_DATE_REG register + * version register + */ +#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc) +/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34632336; + * version register + */ +#define MEM_MONITOR_DATE 0x0FFFFFFFU +#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S) +#define MEM_MONITOR_DATE_V 0x0FFFFFFFU +#define MEM_MONITOR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/mem_monitor_struct.h b/components/soc/esp32c5/include/soc/mem_monitor_struct.h new file mode 100644 index 0000000000..f8c3240762 --- /dev/null +++ b/components/soc/esp32c5/include/soc/mem_monitor_struct.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configuration registers */ +/** Type of log_setting register + * log config regsiter + */ +typedef union { + struct { + /** log_ena : R/W; bitpos: [2:0]; default: 0; + * enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA + */ + uint32_t log_ena:3; + /** log_mode : R/W; bitpos: [6:3]; default: 0; + * Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE + * monitor + */ + uint32_t log_mode:4; + /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1; + * Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END + */ + uint32_t log_mem_loop_enable:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} mem_monitor_log_setting_reg_t; + +/** Type of log_check_data register + * check data regsiter + */ +typedef union { + struct { + /** log_check_data : R/W; bitpos: [31:0]; default: 0; + * The special check data, when write this special data, it will trigger logging. + */ + uint32_t log_check_data:32; + }; + uint32_t val; +} mem_monitor_log_check_data_reg_t; + +/** Type of log_data_mask register + * check data mask register + */ +typedef union { + struct { + /** log_data_mask : R/W; bitpos: [3:0]; default: 0; + * byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 + * mask second byte, and so on. + */ + uint32_t log_data_mask:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} mem_monitor_log_data_mask_reg_t; + +/** Type of log_min register + * log boundary regsiter + */ +typedef union { + struct { + /** log_min : R/W; bitpos: [31:0]; default: 0; + * the min address of log range + */ + uint32_t log_min:32; + }; + uint32_t val; +} mem_monitor_log_min_reg_t; + +/** Type of log_max register + * log boundary regsiter + */ +typedef union { + struct { + /** log_max : R/W; bitpos: [31:0]; default: 0; + * the max address of log range + */ + uint32_t log_max:32; + }; + uint32_t val; +} mem_monitor_log_max_reg_t; + +/** Type of log_mem_start register + * log message store range register + */ +typedef union { + struct { + /** log_mem_start : R/W; bitpos: [31:0]; default: 0; + * the start address of writing logging message + */ + uint32_t log_mem_start:32; + }; + uint32_t val; +} mem_monitor_log_mem_start_reg_t; + +/** Type of log_mem_end register + * log message store range register + */ +typedef union { + struct { + /** log_mem_end : R/W; bitpos: [31:0]; default: 0; + * the end address of writing logging message + */ + uint32_t log_mem_end:32; + }; + uint32_t val; +} mem_monitor_log_mem_end_reg_t; + +/** Type of log_mem_current_addr register + * current writing address. + */ +typedef union { + struct { + /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0; + * means next writing address + */ + uint32_t log_mem_current_addr:32; + }; + uint32_t val; +} mem_monitor_log_mem_current_addr_reg_t; + +/** Type of log_mem_addr_update register + * writing address update + */ +typedef union { + struct { + /** log_mem_addr_update : WT; bitpos: [0]; default: 0; + * Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, + * MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START + */ + uint32_t log_mem_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_log_mem_addr_update_reg_t; + +/** Type of log_mem_full_flag register + * full flag status register + */ +typedef union { + struct { + /** log_mem_full_flag : RO; bitpos: [0]; default: 0; + * 1 means memory write loop at least one time at the range of MEM_START and MEM_END + */ + uint32_t log_mem_full_flag:1; + /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0; + * Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + */ + uint32_t clr_log_mem_full_flag:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} mem_monitor_log_mem_full_flag_reg_t; + + +/** Group: clk register */ +/** Type of clock_gate register + * clock gate force on register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to force on the clk of mem_monitor register + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} mem_monitor_clock_gate_reg_t; + + +/** Group: version register */ +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34632336; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} mem_monitor_date_reg_t; + + +typedef struct { + volatile mem_monitor_log_setting_reg_t log_setting; + volatile mem_monitor_log_check_data_reg_t log_check_data; + volatile mem_monitor_log_data_mask_reg_t log_data_mask; + volatile mem_monitor_log_min_reg_t log_min; + volatile mem_monitor_log_max_reg_t log_max; + volatile mem_monitor_log_mem_start_reg_t log_mem_start; + volatile mem_monitor_log_mem_end_reg_t log_mem_end; + volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr; + volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update; + volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag; + volatile mem_monitor_clock_gate_reg_t clock_gate; + uint32_t reserved_02c[244]; + volatile mem_monitor_date_reg_t date; +} mem_monitor_dev_t; + +extern mem_monitor_dev_t MEM_MONITOR; + +#ifndef __cplusplus +_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/otp_debug_reg.h b/components/soc/esp32c5/include/soc/otp_debug_reg.h new file mode 100644 index 0000000000..7dfe5342f8 --- /dev/null +++ b/components/soc/esp32c5/include/soc/otp_debug_reg.h @@ -0,0 +1,1600 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** OTP_DEBUG_WR_DIS_REG register + * Otp debuger block0 data register1. + */ +#define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0) +/** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ +#define OTP_DEBUG_BLOCK0_WR_DIS 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_WR_DIS_M (OTP_DEBUG_BLOCK0_WR_DIS_V << OTP_DEBUG_BLOCK0_WR_DIS_S) +#define OTP_DEBUG_BLOCK0_WR_DIS_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_WR_DIS_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W1_REG register + * Otp debuger block0 data register2. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4) +/** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_M (OTP_DEBUG_BLOCK0_BACKUP1_W1_V << OTP_DEBUG_BLOCK0_BACKUP1_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W2_REG register + * Otp debuger block0 data register3. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8) +/** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_M (OTP_DEBUG_BLOCK0_BACKUP1_W2_V << OTP_DEBUG_BLOCK0_BACKUP1_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W3_REG register + * Otp debuger block0 data register4. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc) +/** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_M (OTP_DEBUG_BLOCK0_BACKUP1_W3_V << OTP_DEBUG_BLOCK0_BACKUP1_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W4_REG register + * Otp debuger block0 data register5. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10) +/** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_M (OTP_DEBUG_BLOCK0_BACKUP1_W4_V << OTP_DEBUG_BLOCK0_BACKUP1_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP1_W5_REG register + * Otp debuger block0 data register6. + */ +#define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14) +/** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP1_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_M (OTP_DEBUG_BLOCK0_BACKUP1_W5_V << OTP_DEBUG_BLOCK0_BACKUP1_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP1_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W1_REG register + * Otp debuger block0 data register7. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18) +/** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_M (OTP_DEBUG_BLOCK0_BACKUP2_W1_V << OTP_DEBUG_BLOCK0_BACKUP2_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W2_REG register + * Otp debuger block0 data register8. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c) +/** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_M (OTP_DEBUG_BLOCK0_BACKUP2_W2_V << OTP_DEBUG_BLOCK0_BACKUP2_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W3_REG register + * Otp debuger block0 data register9. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20) +/** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_M (OTP_DEBUG_BLOCK0_BACKUP2_W3_V << OTP_DEBUG_BLOCK0_BACKUP2_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W4_REG register + * Otp debuger block0 data register10. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24) +/** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_M (OTP_DEBUG_BLOCK0_BACKUP2_W4_V << OTP_DEBUG_BLOCK0_BACKUP2_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP2_W5_REG register + * Otp debuger block0 data register11. + */ +#define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28) +/** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP2_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_M (OTP_DEBUG_BLOCK0_BACKUP2_W5_V << OTP_DEBUG_BLOCK0_BACKUP2_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP2_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W1_REG register + * Otp debuger block0 data register12. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c) +/** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_M (OTP_DEBUG_BLOCK0_BACKUP3_W1_V << OTP_DEBUG_BLOCK0_BACKUP3_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W2_REG register + * Otp debuger block0 data register13. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30) +/** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_M (OTP_DEBUG_BLOCK0_BACKUP3_W2_V << OTP_DEBUG_BLOCK0_BACKUP3_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W3_REG register + * Otp debuger block0 data register14. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34) +/** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_M (OTP_DEBUG_BLOCK0_BACKUP3_W3_V << OTP_DEBUG_BLOCK0_BACKUP3_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W4_REG register + * Otp debuger block0 data register15. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38) +/** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_M (OTP_DEBUG_BLOCK0_BACKUP3_W4_V << OTP_DEBUG_BLOCK0_BACKUP3_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP3_W5_REG register + * Otp debuger block0 data register16. + */ +#define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c) +/** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP3_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_M (OTP_DEBUG_BLOCK0_BACKUP3_W5_V << OTP_DEBUG_BLOCK0_BACKUP3_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP3_W5_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W1_REG register + * Otp debuger block0 data register17. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40) +/** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_M (OTP_DEBUG_BLOCK0_BACKUP4_W1_V << OTP_DEBUG_BLOCK0_BACKUP4_W1_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W1_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W2_REG register + * Otp debuger block0 data register18. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44) +/** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_M (OTP_DEBUG_BLOCK0_BACKUP4_W2_V << OTP_DEBUG_BLOCK0_BACKUP4_W2_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W2_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W3_REG register + * Otp debuger block0 data register19. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48) +/** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_M (OTP_DEBUG_BLOCK0_BACKUP4_W3_V << OTP_DEBUG_BLOCK0_BACKUP4_W3_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W3_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W4_REG register + * Otp debuger block0 data register20. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c) +/** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_M (OTP_DEBUG_BLOCK0_BACKUP4_W4_V << OTP_DEBUG_BLOCK0_BACKUP4_W4_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W4_S 0 + +/** OTP_DEBUG_BLK0_BACKUP4_W5_REG register + * Otp debuger block0 data register21. + */ +#define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50) +/** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ +#define OTP_DEBUG_BLOCK0_BACKUP4_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_M (OTP_DEBUG_BLOCK0_BACKUP4_W5_V << OTP_DEBUG_BLOCK0_BACKUP4_W5_S) +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK0_BACKUP4_W5_S 0 + +/** OTP_DEBUG_BLK1_W1_REG register + * Otp debuger block1 data register1. + */ +#define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54) +/** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ +#define OTP_DEBUG_BLOCK1_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W1_M (OTP_DEBUG_BLOCK1_W1_V << OTP_DEBUG_BLOCK1_W1_S) +#define OTP_DEBUG_BLOCK1_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W1_S 0 + +/** OTP_DEBUG_BLK1_W2_REG register + * Otp debuger block1 data register2. + */ +#define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58) +/** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ +#define OTP_DEBUG_BLOCK1_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W2_M (OTP_DEBUG_BLOCK1_W2_V << OTP_DEBUG_BLOCK1_W2_S) +#define OTP_DEBUG_BLOCK1_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W2_S 0 + +/** OTP_DEBUG_BLK1_W3_REG register + * Otp debuger block1 data register3. + */ +#define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c) +/** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ +#define OTP_DEBUG_BLOCK1_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W3_M (OTP_DEBUG_BLOCK1_W3_V << OTP_DEBUG_BLOCK1_W3_S) +#define OTP_DEBUG_BLOCK1_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W3_S 0 + +/** OTP_DEBUG_BLK1_W4_REG register + * Otp debuger block1 data register4. + */ +#define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60) +/** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ +#define OTP_DEBUG_BLOCK1_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W4_M (OTP_DEBUG_BLOCK1_W4_V << OTP_DEBUG_BLOCK1_W4_S) +#define OTP_DEBUG_BLOCK1_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W4_S 0 + +/** OTP_DEBUG_BLK1_W5_REG register + * Otp debuger block1 data register5. + */ +#define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64) +/** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ +#define OTP_DEBUG_BLOCK1_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W5_M (OTP_DEBUG_BLOCK1_W5_V << OTP_DEBUG_BLOCK1_W5_S) +#define OTP_DEBUG_BLOCK1_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W5_S 0 + +/** OTP_DEBUG_BLK1_W6_REG register + * Otp debuger block1 data register6. + */ +#define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68) +/** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ +#define OTP_DEBUG_BLOCK1_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W6_M (OTP_DEBUG_BLOCK1_W6_V << OTP_DEBUG_BLOCK1_W6_S) +#define OTP_DEBUG_BLOCK1_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W6_S 0 + +/** OTP_DEBUG_BLK1_W7_REG register + * Otp debuger block1 data register7. + */ +#define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c) +/** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ +#define OTP_DEBUG_BLOCK1_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W7_M (OTP_DEBUG_BLOCK1_W7_V << OTP_DEBUG_BLOCK1_W7_S) +#define OTP_DEBUG_BLOCK1_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W7_S 0 + +/** OTP_DEBUG_BLK1_W8_REG register + * Otp debuger block1 data register8. + */ +#define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70) +/** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ +#define OTP_DEBUG_BLOCK1_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W8_M (OTP_DEBUG_BLOCK1_W8_V << OTP_DEBUG_BLOCK1_W8_S) +#define OTP_DEBUG_BLOCK1_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W8_S 0 + +/** OTP_DEBUG_BLK1_W9_REG register + * Otp debuger block1 data register9. + */ +#define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74) +/** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ +#define OTP_DEBUG_BLOCK1_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W9_M (OTP_DEBUG_BLOCK1_W9_V << OTP_DEBUG_BLOCK1_W9_S) +#define OTP_DEBUG_BLOCK1_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK1_W9_S 0 + +/** OTP_DEBUG_BLK2_W1_REG register + * Otp debuger block2 data register1. + */ +#define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78) +/** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ +#define OTP_DEBUG_BLOCK2_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W1_M (OTP_DEBUG_BLOCK2_W1_V << OTP_DEBUG_BLOCK2_W1_S) +#define OTP_DEBUG_BLOCK2_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W1_S 0 + +/** OTP_DEBUG_BLK2_W2_REG register + * Otp debuger block2 data register2. + */ +#define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c) +/** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ +#define OTP_DEBUG_BLOCK2_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W2_M (OTP_DEBUG_BLOCK2_W2_V << OTP_DEBUG_BLOCK2_W2_S) +#define OTP_DEBUG_BLOCK2_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W2_S 0 + +/** OTP_DEBUG_BLK2_W3_REG register + * Otp debuger block2 data register3. + */ +#define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80) +/** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ +#define OTP_DEBUG_BLOCK2_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W3_M (OTP_DEBUG_BLOCK2_W3_V << OTP_DEBUG_BLOCK2_W3_S) +#define OTP_DEBUG_BLOCK2_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W3_S 0 + +/** OTP_DEBUG_BLK2_W4_REG register + * Otp debuger block2 data register4. + */ +#define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84) +/** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ +#define OTP_DEBUG_BLOCK2_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W4_M (OTP_DEBUG_BLOCK2_W4_V << OTP_DEBUG_BLOCK2_W4_S) +#define OTP_DEBUG_BLOCK2_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W4_S 0 + +/** OTP_DEBUG_BLK2_W5_REG register + * Otp debuger block2 data register5. + */ +#define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88) +/** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ +#define OTP_DEBUG_BLOCK2_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W5_M (OTP_DEBUG_BLOCK2_W5_V << OTP_DEBUG_BLOCK2_W5_S) +#define OTP_DEBUG_BLOCK2_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W5_S 0 + +/** OTP_DEBUG_BLK2_W6_REG register + * Otp debuger block2 data register6. + */ +#define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c) +/** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ +#define OTP_DEBUG_BLOCK2_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W6_M (OTP_DEBUG_BLOCK2_W6_V << OTP_DEBUG_BLOCK2_W6_S) +#define OTP_DEBUG_BLOCK2_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W6_S 0 + +/** OTP_DEBUG_BLK2_W7_REG register + * Otp debuger block2 data register7. + */ +#define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90) +/** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ +#define OTP_DEBUG_BLOCK2_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W7_M (OTP_DEBUG_BLOCK2_W7_V << OTP_DEBUG_BLOCK2_W7_S) +#define OTP_DEBUG_BLOCK2_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W7_S 0 + +/** OTP_DEBUG_BLK2_W8_REG register + * Otp debuger block2 data register8. + */ +#define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94) +/** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ +#define OTP_DEBUG_BLOCK2_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W8_M (OTP_DEBUG_BLOCK2_W8_V << OTP_DEBUG_BLOCK2_W8_S) +#define OTP_DEBUG_BLOCK2_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W8_S 0 + +/** OTP_DEBUG_BLK2_W9_REG register + * Otp debuger block2 data register9. + */ +#define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98) +/** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ +#define OTP_DEBUG_BLOCK2_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W9_M (OTP_DEBUG_BLOCK2_W9_V << OTP_DEBUG_BLOCK2_W9_S) +#define OTP_DEBUG_BLOCK2_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W9_S 0 + +/** OTP_DEBUG_BLK2_W10_REG register + * Otp debuger block2 data register10. + */ +#define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c) +/** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ +#define OTP_DEBUG_BLOCK2_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W10_M (OTP_DEBUG_BLOCK2_W10_V << OTP_DEBUG_BLOCK2_W10_S) +#define OTP_DEBUG_BLOCK2_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W10_S 0 + +/** OTP_DEBUG_BLK2_W11_REG register + * Otp debuger block2 data register11. + */ +#define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0) +/** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ +#define OTP_DEBUG_BLOCK2_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W11_M (OTP_DEBUG_BLOCK2_W11_V << OTP_DEBUG_BLOCK2_W11_S) +#define OTP_DEBUG_BLOCK2_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK2_W11_S 0 + +/** OTP_DEBUG_BLK3_W1_REG register + * Otp debuger block3 data register1. + */ +#define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4) +/** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ +#define OTP_DEBUG_BLOCK3_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W1_M (OTP_DEBUG_BLOCK3_W1_V << OTP_DEBUG_BLOCK3_W1_S) +#define OTP_DEBUG_BLOCK3_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W1_S 0 + +/** OTP_DEBUG_BLK3_W2_REG register + * Otp debuger block3 data register2. + */ +#define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8) +/** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ +#define OTP_DEBUG_BLOCK3_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W2_M (OTP_DEBUG_BLOCK3_W2_V << OTP_DEBUG_BLOCK3_W2_S) +#define OTP_DEBUG_BLOCK3_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W2_S 0 + +/** OTP_DEBUG_BLK3_W3_REG register + * Otp debuger block3 data register3. + */ +#define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac) +/** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ +#define OTP_DEBUG_BLOCK3_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W3_M (OTP_DEBUG_BLOCK3_W3_V << OTP_DEBUG_BLOCK3_W3_S) +#define OTP_DEBUG_BLOCK3_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W3_S 0 + +/** OTP_DEBUG_BLK3_W4_REG register + * Otp debuger block3 data register4. + */ +#define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0) +/** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ +#define OTP_DEBUG_BLOCK3_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W4_M (OTP_DEBUG_BLOCK3_W4_V << OTP_DEBUG_BLOCK3_W4_S) +#define OTP_DEBUG_BLOCK3_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W4_S 0 + +/** OTP_DEBUG_BLK3_W5_REG register + * Otp debuger block3 data register5. + */ +#define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4) +/** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ +#define OTP_DEBUG_BLOCK3_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W5_M (OTP_DEBUG_BLOCK3_W5_V << OTP_DEBUG_BLOCK3_W5_S) +#define OTP_DEBUG_BLOCK3_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W5_S 0 + +/** OTP_DEBUG_BLK3_W6_REG register + * Otp debuger block3 data register6. + */ +#define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8) +/** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ +#define OTP_DEBUG_BLOCK3_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W6_M (OTP_DEBUG_BLOCK3_W6_V << OTP_DEBUG_BLOCK3_W6_S) +#define OTP_DEBUG_BLOCK3_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W6_S 0 + +/** OTP_DEBUG_BLK3_W7_REG register + * Otp debuger block3 data register7. + */ +#define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc) +/** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ +#define OTP_DEBUG_BLOCK3_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W7_M (OTP_DEBUG_BLOCK3_W7_V << OTP_DEBUG_BLOCK3_W7_S) +#define OTP_DEBUG_BLOCK3_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W7_S 0 + +/** OTP_DEBUG_BLK3_W8_REG register + * Otp debuger block3 data register8. + */ +#define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0) +/** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ +#define OTP_DEBUG_BLOCK3_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W8_M (OTP_DEBUG_BLOCK3_W8_V << OTP_DEBUG_BLOCK3_W8_S) +#define OTP_DEBUG_BLOCK3_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W8_S 0 + +/** OTP_DEBUG_BLK3_W9_REG register + * Otp debuger block3 data register9. + */ +#define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4) +/** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ +#define OTP_DEBUG_BLOCK3_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W9_M (OTP_DEBUG_BLOCK3_W9_V << OTP_DEBUG_BLOCK3_W9_S) +#define OTP_DEBUG_BLOCK3_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W9_S 0 + +/** OTP_DEBUG_BLK3_W10_REG register + * Otp debuger block3 data register10. + */ +#define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8) +/** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ +#define OTP_DEBUG_BLOCK3_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W10_M (OTP_DEBUG_BLOCK3_W10_V << OTP_DEBUG_BLOCK3_W10_S) +#define OTP_DEBUG_BLOCK3_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W10_S 0 + +/** OTP_DEBUG_BLK3_W11_REG register + * Otp debuger block3 data register11. + */ +#define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc) +/** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ +#define OTP_DEBUG_BLOCK3_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W11_M (OTP_DEBUG_BLOCK3_W11_V << OTP_DEBUG_BLOCK3_W11_S) +#define OTP_DEBUG_BLOCK3_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK3_W11_S 0 + +/** OTP_DEBUG_BLK4_W1_REG register + * Otp debuger block4 data register1. + */ +#define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0) +/** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ +#define OTP_DEBUG_BLOCK4_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W1_M (OTP_DEBUG_BLOCK4_W1_V << OTP_DEBUG_BLOCK4_W1_S) +#define OTP_DEBUG_BLOCK4_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W1_S 0 + +/** OTP_DEBUG_BLK4_W2_REG register + * Otp debuger block4 data register2. + */ +#define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4) +/** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ +#define OTP_DEBUG_BLOCK4_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W2_M (OTP_DEBUG_BLOCK4_W2_V << OTP_DEBUG_BLOCK4_W2_S) +#define OTP_DEBUG_BLOCK4_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W2_S 0 + +/** OTP_DEBUG_BLK4_W3_REG register + * Otp debuger block4 data register3. + */ +#define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8) +/** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ +#define OTP_DEBUG_BLOCK4_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W3_M (OTP_DEBUG_BLOCK4_W3_V << OTP_DEBUG_BLOCK4_W3_S) +#define OTP_DEBUG_BLOCK4_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W3_S 0 + +/** OTP_DEBUG_BLK4_W4_REG register + * Otp debuger block4 data register4. + */ +#define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc) +/** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ +#define OTP_DEBUG_BLOCK4_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W4_M (OTP_DEBUG_BLOCK4_W4_V << OTP_DEBUG_BLOCK4_W4_S) +#define OTP_DEBUG_BLOCK4_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W4_S 0 + +/** OTP_DEBUG_BLK4_W5_REG register + * Otp debuger block4 data register5. + */ +#define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0) +/** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ +#define OTP_DEBUG_BLOCK4_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W5_M (OTP_DEBUG_BLOCK4_W5_V << OTP_DEBUG_BLOCK4_W5_S) +#define OTP_DEBUG_BLOCK4_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W5_S 0 + +/** OTP_DEBUG_BLK4_W6_REG register + * Otp debuger block4 data register6. + */ +#define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4) +/** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ +#define OTP_DEBUG_BLOCK4_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W6_M (OTP_DEBUG_BLOCK4_W6_V << OTP_DEBUG_BLOCK4_W6_S) +#define OTP_DEBUG_BLOCK4_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W6_S 0 + +/** OTP_DEBUG_BLK4_W7_REG register + * Otp debuger block4 data register7. + */ +#define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8) +/** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ +#define OTP_DEBUG_BLOCK4_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W7_M (OTP_DEBUG_BLOCK4_W7_V << OTP_DEBUG_BLOCK4_W7_S) +#define OTP_DEBUG_BLOCK4_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W7_S 0 + +/** OTP_DEBUG_BLK4_W8_REG register + * Otp debuger block4 data register8. + */ +#define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec) +/** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ +#define OTP_DEBUG_BLOCK4_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W8_M (OTP_DEBUG_BLOCK4_W8_V << OTP_DEBUG_BLOCK4_W8_S) +#define OTP_DEBUG_BLOCK4_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W8_S 0 + +/** OTP_DEBUG_BLK4_W9_REG register + * Otp debuger block4 data register9. + */ +#define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0) +/** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ +#define OTP_DEBUG_BLOCK4_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W9_M (OTP_DEBUG_BLOCK4_W9_V << OTP_DEBUG_BLOCK4_W9_S) +#define OTP_DEBUG_BLOCK4_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W9_S 0 + +/** OTP_DEBUG_BLK4_W10_REG register + * Otp debuger block4 data registe10. + */ +#define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4) +/** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ +#define OTP_DEBUG_BLOCK4_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W10_M (OTP_DEBUG_BLOCK4_W10_V << OTP_DEBUG_BLOCK4_W10_S) +#define OTP_DEBUG_BLOCK4_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W10_S 0 + +/** OTP_DEBUG_BLK4_W11_REG register + * Otp debuger block4 data register11. + */ +#define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8) +/** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ +#define OTP_DEBUG_BLOCK4_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W11_M (OTP_DEBUG_BLOCK4_W11_V << OTP_DEBUG_BLOCK4_W11_S) +#define OTP_DEBUG_BLOCK4_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK4_W11_S 0 + +/** OTP_DEBUG_BLK5_W1_REG register + * Otp debuger block5 data register1. + */ +#define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc) +/** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ +#define OTP_DEBUG_BLOCK5_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W1_M (OTP_DEBUG_BLOCK5_W1_V << OTP_DEBUG_BLOCK5_W1_S) +#define OTP_DEBUG_BLOCK5_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W1_S 0 + +/** OTP_DEBUG_BLK5_W2_REG register + * Otp debuger block5 data register2. + */ +#define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100) +/** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ +#define OTP_DEBUG_BLOCK5_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W2_M (OTP_DEBUG_BLOCK5_W2_V << OTP_DEBUG_BLOCK5_W2_S) +#define OTP_DEBUG_BLOCK5_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W2_S 0 + +/** OTP_DEBUG_BLK5_W3_REG register + * Otp debuger block5 data register3. + */ +#define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104) +/** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ +#define OTP_DEBUG_BLOCK5_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W3_M (OTP_DEBUG_BLOCK5_W3_V << OTP_DEBUG_BLOCK5_W3_S) +#define OTP_DEBUG_BLOCK5_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W3_S 0 + +/** OTP_DEBUG_BLK5_W4_REG register + * Otp debuger block5 data register4. + */ +#define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108) +/** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ +#define OTP_DEBUG_BLOCK5_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W4_M (OTP_DEBUG_BLOCK5_W4_V << OTP_DEBUG_BLOCK5_W4_S) +#define OTP_DEBUG_BLOCK5_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W4_S 0 + +/** OTP_DEBUG_BLK5_W5_REG register + * Otp debuger block5 data register5. + */ +#define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c) +/** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ +#define OTP_DEBUG_BLOCK5_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W5_M (OTP_DEBUG_BLOCK5_W5_V << OTP_DEBUG_BLOCK5_W5_S) +#define OTP_DEBUG_BLOCK5_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W5_S 0 + +/** OTP_DEBUG_BLK5_W6_REG register + * Otp debuger block5 data register6. + */ +#define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110) +/** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ +#define OTP_DEBUG_BLOCK5_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W6_M (OTP_DEBUG_BLOCK5_W6_V << OTP_DEBUG_BLOCK5_W6_S) +#define OTP_DEBUG_BLOCK5_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W6_S 0 + +/** OTP_DEBUG_BLK5_W7_REG register + * Otp debuger block5 data register7. + */ +#define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114) +/** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ +#define OTP_DEBUG_BLOCK5_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W7_M (OTP_DEBUG_BLOCK5_W7_V << OTP_DEBUG_BLOCK5_W7_S) +#define OTP_DEBUG_BLOCK5_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W7_S 0 + +/** OTP_DEBUG_BLK5_W8_REG register + * Otp debuger block5 data register8. + */ +#define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118) +/** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ +#define OTP_DEBUG_BLOCK5_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W8_M (OTP_DEBUG_BLOCK5_W8_V << OTP_DEBUG_BLOCK5_W8_S) +#define OTP_DEBUG_BLOCK5_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W8_S 0 + +/** OTP_DEBUG_BLK5_W9_REG register + * Otp debuger block5 data register9. + */ +#define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c) +/** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ +#define OTP_DEBUG_BLOCK5_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W9_M (OTP_DEBUG_BLOCK5_W9_V << OTP_DEBUG_BLOCK5_W9_S) +#define OTP_DEBUG_BLOCK5_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W9_S 0 + +/** OTP_DEBUG_BLK5_W10_REG register + * Otp debuger block5 data register10. + */ +#define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120) +/** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ +#define OTP_DEBUG_BLOCK5_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W10_M (OTP_DEBUG_BLOCK5_W10_V << OTP_DEBUG_BLOCK5_W10_S) +#define OTP_DEBUG_BLOCK5_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W10_S 0 + +/** OTP_DEBUG_BLK5_W11_REG register + * Otp debuger block5 data register11. + */ +#define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124) +/** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ +#define OTP_DEBUG_BLOCK5_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W11_M (OTP_DEBUG_BLOCK5_W11_V << OTP_DEBUG_BLOCK5_W11_S) +#define OTP_DEBUG_BLOCK5_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK5_W11_S 0 + +/** OTP_DEBUG_BLK6_W1_REG register + * Otp debuger block6 data register1. + */ +#define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128) +/** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ +#define OTP_DEBUG_BLOCK6_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W1_M (OTP_DEBUG_BLOCK6_W1_V << OTP_DEBUG_BLOCK6_W1_S) +#define OTP_DEBUG_BLOCK6_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W1_S 0 + +/** OTP_DEBUG_BLK6_W2_REG register + * Otp debuger block6 data register2. + */ +#define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c) +/** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ +#define OTP_DEBUG_BLOCK6_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W2_M (OTP_DEBUG_BLOCK6_W2_V << OTP_DEBUG_BLOCK6_W2_S) +#define OTP_DEBUG_BLOCK6_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W2_S 0 + +/** OTP_DEBUG_BLK6_W3_REG register + * Otp debuger block6 data register3. + */ +#define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130) +/** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ +#define OTP_DEBUG_BLOCK6_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W3_M (OTP_DEBUG_BLOCK6_W3_V << OTP_DEBUG_BLOCK6_W3_S) +#define OTP_DEBUG_BLOCK6_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W3_S 0 + +/** OTP_DEBUG_BLK6_W4_REG register + * Otp debuger block6 data register4. + */ +#define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134) +/** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ +#define OTP_DEBUG_BLOCK6_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W4_M (OTP_DEBUG_BLOCK6_W4_V << OTP_DEBUG_BLOCK6_W4_S) +#define OTP_DEBUG_BLOCK6_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W4_S 0 + +/** OTP_DEBUG_BLK6_W5_REG register + * Otp debuger block6 data register5. + */ +#define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138) +/** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ +#define OTP_DEBUG_BLOCK6_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W5_M (OTP_DEBUG_BLOCK6_W5_V << OTP_DEBUG_BLOCK6_W5_S) +#define OTP_DEBUG_BLOCK6_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W5_S 0 + +/** OTP_DEBUG_BLK6_W6_REG register + * Otp debuger block6 data register6. + */ +#define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c) +/** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ +#define OTP_DEBUG_BLOCK6_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W6_M (OTP_DEBUG_BLOCK6_W6_V << OTP_DEBUG_BLOCK6_W6_S) +#define OTP_DEBUG_BLOCK6_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W6_S 0 + +/** OTP_DEBUG_BLK6_W7_REG register + * Otp debuger block6 data register7. + */ +#define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140) +/** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ +#define OTP_DEBUG_BLOCK6_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W7_M (OTP_DEBUG_BLOCK6_W7_V << OTP_DEBUG_BLOCK6_W7_S) +#define OTP_DEBUG_BLOCK6_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W7_S 0 + +/** OTP_DEBUG_BLK6_W8_REG register + * Otp debuger block6 data register8. + */ +#define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144) +/** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ +#define OTP_DEBUG_BLOCK6_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W8_M (OTP_DEBUG_BLOCK6_W8_V << OTP_DEBUG_BLOCK6_W8_S) +#define OTP_DEBUG_BLOCK6_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W8_S 0 + +/** OTP_DEBUG_BLK6_W9_REG register + * Otp debuger block6 data register9. + */ +#define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148) +/** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ +#define OTP_DEBUG_BLOCK6_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W9_M (OTP_DEBUG_BLOCK6_W9_V << OTP_DEBUG_BLOCK6_W9_S) +#define OTP_DEBUG_BLOCK6_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W9_S 0 + +/** OTP_DEBUG_BLK6_W10_REG register + * Otp debuger block6 data register10. + */ +#define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c) +/** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ +#define OTP_DEBUG_BLOCK6_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W10_M (OTP_DEBUG_BLOCK6_W10_V << OTP_DEBUG_BLOCK6_W10_S) +#define OTP_DEBUG_BLOCK6_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W10_S 0 + +/** OTP_DEBUG_BLK6_W11_REG register + * Otp debuger block6 data register11. + */ +#define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150) +/** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ +#define OTP_DEBUG_BLOCK6_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W11_M (OTP_DEBUG_BLOCK6_W11_V << OTP_DEBUG_BLOCK6_W11_S) +#define OTP_DEBUG_BLOCK6_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK6_W11_S 0 + +/** OTP_DEBUG_BLK7_W1_REG register + * Otp debuger block7 data register1. + */ +#define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154) +/** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ +#define OTP_DEBUG_BLOCK7_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W1_M (OTP_DEBUG_BLOCK7_W1_V << OTP_DEBUG_BLOCK7_W1_S) +#define OTP_DEBUG_BLOCK7_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W1_S 0 + +/** OTP_DEBUG_BLK7_W2_REG register + * Otp debuger block7 data register2. + */ +#define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158) +/** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ +#define OTP_DEBUG_BLOCK7_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W2_M (OTP_DEBUG_BLOCK7_W2_V << OTP_DEBUG_BLOCK7_W2_S) +#define OTP_DEBUG_BLOCK7_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W2_S 0 + +/** OTP_DEBUG_BLK7_W3_REG register + * Otp debuger block7 data register3. + */ +#define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c) +/** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ +#define OTP_DEBUG_BLOCK7_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W3_M (OTP_DEBUG_BLOCK7_W3_V << OTP_DEBUG_BLOCK7_W3_S) +#define OTP_DEBUG_BLOCK7_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W3_S 0 + +/** OTP_DEBUG_BLK7_W4_REG register + * Otp debuger block7 data register4. + */ +#define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160) +/** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ +#define OTP_DEBUG_BLOCK7_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W4_M (OTP_DEBUG_BLOCK7_W4_V << OTP_DEBUG_BLOCK7_W4_S) +#define OTP_DEBUG_BLOCK7_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W4_S 0 + +/** OTP_DEBUG_BLK7_W5_REG register + * Otp debuger block7 data register5. + */ +#define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164) +/** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ +#define OTP_DEBUG_BLOCK7_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W5_M (OTP_DEBUG_BLOCK7_W5_V << OTP_DEBUG_BLOCK7_W5_S) +#define OTP_DEBUG_BLOCK7_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W5_S 0 + +/** OTP_DEBUG_BLK7_W6_REG register + * Otp debuger block7 data register6. + */ +#define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168) +/** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ +#define OTP_DEBUG_BLOCK7_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W6_M (OTP_DEBUG_BLOCK7_W6_V << OTP_DEBUG_BLOCK7_W6_S) +#define OTP_DEBUG_BLOCK7_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W6_S 0 + +/** OTP_DEBUG_BLK7_W7_REG register + * Otp debuger block7 data register7. + */ +#define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c) +/** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ +#define OTP_DEBUG_BLOCK7_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W7_M (OTP_DEBUG_BLOCK7_W7_V << OTP_DEBUG_BLOCK7_W7_S) +#define OTP_DEBUG_BLOCK7_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W7_S 0 + +/** OTP_DEBUG_BLK7_W8_REG register + * Otp debuger block7 data register8. + */ +#define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170) +/** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ +#define OTP_DEBUG_BLOCK7_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W8_M (OTP_DEBUG_BLOCK7_W8_V << OTP_DEBUG_BLOCK7_W8_S) +#define OTP_DEBUG_BLOCK7_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W8_S 0 + +/** OTP_DEBUG_BLK7_W9_REG register + * Otp debuger block7 data register9. + */ +#define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174) +/** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ +#define OTP_DEBUG_BLOCK7_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W9_M (OTP_DEBUG_BLOCK7_W9_V << OTP_DEBUG_BLOCK7_W9_S) +#define OTP_DEBUG_BLOCK7_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W9_S 0 + +/** OTP_DEBUG_BLK7_W10_REG register + * Otp debuger block7 data register10. + */ +#define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178) +/** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ +#define OTP_DEBUG_BLOCK7_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W10_M (OTP_DEBUG_BLOCK7_W10_V << OTP_DEBUG_BLOCK7_W10_S) +#define OTP_DEBUG_BLOCK7_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W10_S 0 + +/** OTP_DEBUG_BLK7_W11_REG register + * Otp debuger block7 data register11. + */ +#define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c) +/** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ +#define OTP_DEBUG_BLOCK7_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W11_M (OTP_DEBUG_BLOCK7_W11_V << OTP_DEBUG_BLOCK7_W11_S) +#define OTP_DEBUG_BLOCK7_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK7_W11_S 0 + +/** OTP_DEBUG_BLK8_W1_REG register + * Otp debuger block8 data register1. + */ +#define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180) +/** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ +#define OTP_DEBUG_BLOCK8_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W1_M (OTP_DEBUG_BLOCK8_W1_V << OTP_DEBUG_BLOCK8_W1_S) +#define OTP_DEBUG_BLOCK8_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W1_S 0 + +/** OTP_DEBUG_BLK8_W2_REG register + * Otp debuger block8 data register2. + */ +#define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184) +/** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ +#define OTP_DEBUG_BLOCK8_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W2_M (OTP_DEBUG_BLOCK8_W2_V << OTP_DEBUG_BLOCK8_W2_S) +#define OTP_DEBUG_BLOCK8_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W2_S 0 + +/** OTP_DEBUG_BLK8_W3_REG register + * Otp debuger block8 data register3. + */ +#define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188) +/** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ +#define OTP_DEBUG_BLOCK8_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W3_M (OTP_DEBUG_BLOCK8_W3_V << OTP_DEBUG_BLOCK8_W3_S) +#define OTP_DEBUG_BLOCK8_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W3_S 0 + +/** OTP_DEBUG_BLK8_W4_REG register + * Otp debuger block8 data register4. + */ +#define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c) +/** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ +#define OTP_DEBUG_BLOCK8_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W4_M (OTP_DEBUG_BLOCK8_W4_V << OTP_DEBUG_BLOCK8_W4_S) +#define OTP_DEBUG_BLOCK8_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W4_S 0 + +/** OTP_DEBUG_BLK8_W5_REG register + * Otp debuger block8 data register5. + */ +#define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190) +/** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ +#define OTP_DEBUG_BLOCK8_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W5_M (OTP_DEBUG_BLOCK8_W5_V << OTP_DEBUG_BLOCK8_W5_S) +#define OTP_DEBUG_BLOCK8_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W5_S 0 + +/** OTP_DEBUG_BLK8_W6_REG register + * Otp debuger block8 data register6. + */ +#define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194) +/** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ +#define OTP_DEBUG_BLOCK8_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W6_M (OTP_DEBUG_BLOCK8_W6_V << OTP_DEBUG_BLOCK8_W6_S) +#define OTP_DEBUG_BLOCK8_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W6_S 0 + +/** OTP_DEBUG_BLK8_W7_REG register + * Otp debuger block8 data register7. + */ +#define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198) +/** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ +#define OTP_DEBUG_BLOCK8_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W7_M (OTP_DEBUG_BLOCK8_W7_V << OTP_DEBUG_BLOCK8_W7_S) +#define OTP_DEBUG_BLOCK8_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W7_S 0 + +/** OTP_DEBUG_BLK8_W8_REG register + * Otp debuger block8 data register8. + */ +#define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c) +/** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ +#define OTP_DEBUG_BLOCK8_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W8_M (OTP_DEBUG_BLOCK8_W8_V << OTP_DEBUG_BLOCK8_W8_S) +#define OTP_DEBUG_BLOCK8_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W8_S 0 + +/** OTP_DEBUG_BLK8_W9_REG register + * Otp debuger block8 data register9. + */ +#define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0) +/** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ +#define OTP_DEBUG_BLOCK8_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W9_M (OTP_DEBUG_BLOCK8_W9_V << OTP_DEBUG_BLOCK8_W9_S) +#define OTP_DEBUG_BLOCK8_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W9_S 0 + +/** OTP_DEBUG_BLK8_W10_REG register + * Otp debuger block8 data register10. + */ +#define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4) +/** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ +#define OTP_DEBUG_BLOCK8_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W10_M (OTP_DEBUG_BLOCK8_W10_V << OTP_DEBUG_BLOCK8_W10_S) +#define OTP_DEBUG_BLOCK8_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W10_S 0 + +/** OTP_DEBUG_BLK8_W11_REG register + * Otp debuger block8 data register11. + */ +#define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8) +/** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ +#define OTP_DEBUG_BLOCK8_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W11_M (OTP_DEBUG_BLOCK8_W11_V << OTP_DEBUG_BLOCK8_W11_S) +#define OTP_DEBUG_BLOCK8_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK8_W11_S 0 + +/** OTP_DEBUG_BLK9_W1_REG register + * Otp debuger block9 data register1. + */ +#define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac) +/** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ +#define OTP_DEBUG_BLOCK9_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W1_M (OTP_DEBUG_BLOCK9_W1_V << OTP_DEBUG_BLOCK9_W1_S) +#define OTP_DEBUG_BLOCK9_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W1_S 0 + +/** OTP_DEBUG_BLK9_W2_REG register + * Otp debuger block9 data register2. + */ +#define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0) +/** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ +#define OTP_DEBUG_BLOCK9_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W2_M (OTP_DEBUG_BLOCK9_W2_V << OTP_DEBUG_BLOCK9_W2_S) +#define OTP_DEBUG_BLOCK9_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W2_S 0 + +/** OTP_DEBUG_BLK9_W3_REG register + * Otp debuger block9 data register3. + */ +#define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4) +/** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ +#define OTP_DEBUG_BLOCK9_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W3_M (OTP_DEBUG_BLOCK9_W3_V << OTP_DEBUG_BLOCK9_W3_S) +#define OTP_DEBUG_BLOCK9_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W3_S 0 + +/** OTP_DEBUG_BLK9_W4_REG register + * Otp debuger block9 data register4. + */ +#define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8) +/** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ +#define OTP_DEBUG_BLOCK9_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W4_M (OTP_DEBUG_BLOCK9_W4_V << OTP_DEBUG_BLOCK9_W4_S) +#define OTP_DEBUG_BLOCK9_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W4_S 0 + +/** OTP_DEBUG_BLK9_W5_REG register + * Otp debuger block9 data register5. + */ +#define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc) +/** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ +#define OTP_DEBUG_BLOCK9_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W5_M (OTP_DEBUG_BLOCK9_W5_V << OTP_DEBUG_BLOCK9_W5_S) +#define OTP_DEBUG_BLOCK9_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W5_S 0 + +/** OTP_DEBUG_BLK9_W6_REG register + * Otp debuger block9 data register6. + */ +#define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0) +/** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ +#define OTP_DEBUG_BLOCK9_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W6_M (OTP_DEBUG_BLOCK9_W6_V << OTP_DEBUG_BLOCK9_W6_S) +#define OTP_DEBUG_BLOCK9_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W6_S 0 + +/** OTP_DEBUG_BLK9_W7_REG register + * Otp debuger block9 data register7. + */ +#define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4) +/** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ +#define OTP_DEBUG_BLOCK9_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W7_M (OTP_DEBUG_BLOCK9_W7_V << OTP_DEBUG_BLOCK9_W7_S) +#define OTP_DEBUG_BLOCK9_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W7_S 0 + +/** OTP_DEBUG_BLK9_W8_REG register + * Otp debuger block9 data register8. + */ +#define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8) +/** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ +#define OTP_DEBUG_BLOCK9_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W8_M (OTP_DEBUG_BLOCK9_W8_V << OTP_DEBUG_BLOCK9_W8_S) +#define OTP_DEBUG_BLOCK9_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W8_S 0 + +/** OTP_DEBUG_BLK9_W9_REG register + * Otp debuger block9 data register9. + */ +#define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc) +/** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ +#define OTP_DEBUG_BLOCK9_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W9_M (OTP_DEBUG_BLOCK9_W9_V << OTP_DEBUG_BLOCK9_W9_S) +#define OTP_DEBUG_BLOCK9_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W9_S 0 + +/** OTP_DEBUG_BLK9_W10_REG register + * Otp debuger block9 data register10. + */ +#define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0) +/** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ +#define OTP_DEBUG_BLOCK9_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W10_M (OTP_DEBUG_BLOCK9_W10_V << OTP_DEBUG_BLOCK9_W10_S) +#define OTP_DEBUG_BLOCK9_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W10_S 0 + +/** OTP_DEBUG_BLK9_W11_REG register + * Otp debuger block9 data register11. + */ +#define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4) +/** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ +#define OTP_DEBUG_BLOCK9_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W11_M (OTP_DEBUG_BLOCK9_W11_V << OTP_DEBUG_BLOCK9_W11_S) +#define OTP_DEBUG_BLOCK9_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK9_W11_S 0 + +/** OTP_DEBUG_BLK10_W1_REG register + * Otp debuger block10 data register1. + */ +#define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8) +/** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ +#define OTP_DEBUG_BLOCK10_W1 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W1_M (OTP_DEBUG_BLOCK10_W1_V << OTP_DEBUG_BLOCK10_W1_S) +#define OTP_DEBUG_BLOCK10_W1_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W1_S 0 + +/** OTP_DEBUG_BLK10_W2_REG register + * Otp debuger block10 data register2. + */ +#define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc) +/** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ +#define OTP_DEBUG_BLOCK10_W2 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W2_M (OTP_DEBUG_BLOCK10_W2_V << OTP_DEBUG_BLOCK10_W2_S) +#define OTP_DEBUG_BLOCK10_W2_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W2_S 0 + +/** OTP_DEBUG_BLK10_W3_REG register + * Otp debuger block10 data register3. + */ +#define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0) +/** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ +#define OTP_DEBUG_BLOCK10_W3 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W3_M (OTP_DEBUG_BLOCK10_W3_V << OTP_DEBUG_BLOCK10_W3_S) +#define OTP_DEBUG_BLOCK10_W3_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W3_S 0 + +/** OTP_DEBUG_BLK10_W4_REG register + * Otp debuger block10 data register4. + */ +#define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4) +/** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ +#define OTP_DEBUG_BLOCK10_W4 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W4_M (OTP_DEBUG_BLOCK10_W4_V << OTP_DEBUG_BLOCK10_W4_S) +#define OTP_DEBUG_BLOCK10_W4_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W4_S 0 + +/** OTP_DEBUG_BLK10_W5_REG register + * Otp debuger block10 data register5. + */ +#define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8) +/** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ +#define OTP_DEBUG_BLOCK10_W5 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W5_M (OTP_DEBUG_BLOCK10_W5_V << OTP_DEBUG_BLOCK10_W5_S) +#define OTP_DEBUG_BLOCK10_W5_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W5_S 0 + +/** OTP_DEBUG_BLK10_W6_REG register + * Otp debuger block10 data register6. + */ +#define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec) +/** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ +#define OTP_DEBUG_BLOCK10_W6 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W6_M (OTP_DEBUG_BLOCK10_W6_V << OTP_DEBUG_BLOCK10_W6_S) +#define OTP_DEBUG_BLOCK10_W6_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W6_S 0 + +/** OTP_DEBUG_BLK10_W7_REG register + * Otp debuger block10 data register7. + */ +#define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0) +/** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ +#define OTP_DEBUG_BLOCK10_W7 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W7_M (OTP_DEBUG_BLOCK10_W7_V << OTP_DEBUG_BLOCK10_W7_S) +#define OTP_DEBUG_BLOCK10_W7_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W7_S 0 + +/** OTP_DEBUG_BLK10_W8_REG register + * Otp debuger block10 data register8. + */ +#define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4) +/** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ +#define OTP_DEBUG_BLOCK10_W8 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W8_M (OTP_DEBUG_BLOCK10_W8_V << OTP_DEBUG_BLOCK10_W8_S) +#define OTP_DEBUG_BLOCK10_W8_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W8_S 0 + +/** OTP_DEBUG_BLK10_W9_REG register + * Otp debuger block10 data register9. + */ +#define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8) +/** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ +#define OTP_DEBUG_BLOCK10_W9 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W9_M (OTP_DEBUG_BLOCK10_W9_V << OTP_DEBUG_BLOCK10_W9_S) +#define OTP_DEBUG_BLOCK10_W9_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W9_S 0 + +/** OTP_DEBUG_BLK10_W10_REG register + * Otp debuger block10 data register10. + */ +#define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc) +/** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ +#define OTP_DEBUG_BLOCK19_W10 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK19_W10_M (OTP_DEBUG_BLOCK19_W10_V << OTP_DEBUG_BLOCK19_W10_S) +#define OTP_DEBUG_BLOCK19_W10_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK19_W10_S 0 + +/** OTP_DEBUG_BLK10_W11_REG register + * Otp debuger block10 data register11. + */ +#define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200) +/** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ +#define OTP_DEBUG_BLOCK10_W11 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W11_M (OTP_DEBUG_BLOCK10_W11_V << OTP_DEBUG_BLOCK10_W11_S) +#define OTP_DEBUG_BLOCK10_W11_V 0xFFFFFFFFU +#define OTP_DEBUG_BLOCK10_W11_S 0 + +/** OTP_DEBUG_CLK_REG register + * Otp debuger clk_en configuration register. + */ +#define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204) +/** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file. + */ +#define OTP_DEBUG_CLK_EN (BIT(0)) +#define OTP_DEBUG_CLK_EN_M (OTP_DEBUG_CLK_EN_V << OTP_DEBUG_CLK_EN_S) +#define OTP_DEBUG_CLK_EN_V 0x00000001U +#define OTP_DEBUG_CLK_EN_S 0 + +/** OTP_DEBUG_APB2OTP_EN_REG register + * Otp_debuger apb2otp enable configuration register. + */ +#define OTP_DEBUG_APB2OTP_EN_REG (DR_REG_OTP_DEBUG_BASE + 0x208) +/** OTP_DEBUG_APB2OTP_EN : R/W; bitpos: [0]; default: 0; + * Debug mode enable signal. + */ +#define OTP_DEBUG_APB2OTP_EN (BIT(0)) +#define OTP_DEBUG_APB2OTP_EN_M (OTP_DEBUG_APB2OTP_EN_V << OTP_DEBUG_APB2OTP_EN_S) +#define OTP_DEBUG_APB2OTP_EN_V 0x00000001U +#define OTP_DEBUG_APB2OTP_EN_S 0 + +/** OTP_DEBUG_DATE_REG register + * eFuse version register. + */ +#define OTP_DEBUG_DATE_REG (DR_REG_OTP_DEBUG_BASE + 0x20c) +/** OTP_DEBUG_DATE : R/W; bitpos: [27:0]; default: 539037736; + * Stores otp_debug version. + */ +#define OTP_DEBUG_DATE 0x0FFFFFFFU +#define OTP_DEBUG_DATE_M (OTP_DEBUG_DATE_V << OTP_DEBUG_DATE_S) +#define OTP_DEBUG_DATE_V 0x0FFFFFFFU +#define OTP_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/otp_debug_struct.h b/components/soc/esp32c5/include/soc/otp_debug_struct.h new file mode 100644 index 0000000000..ff4c13921e --- /dev/null +++ b/components/soc/esp32c5/include/soc/otp_debug_struct.h @@ -0,0 +1,2137 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: OTP_DEBUG Block0 Write Disable Data */ +/** Type of wr_dis register + * Otp debuger block0 data register1. + */ +typedef union { + struct { + /** block0_wr_dis : RO; bitpos: [31:0]; default: 0; + * Otp block0 write disable data. + */ + uint32_t block0_wr_dis:32; + }; + uint32_t val; +} otp_debug_wr_dis_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word1 Data */ +/** Type of blk0_backup1_w1 register + * Otp debuger block0 data register2. + */ +typedef union { + struct { + /** block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word1 data. + */ + uint32_t block0_backup1_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word2 Data */ +/** Type of blk0_backup1_w2 register + * Otp debuger block0 data register3. + */ +typedef union { + struct { + /** block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word2 data. + */ + uint32_t block0_backup1_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word3 Data */ +/** Type of blk0_backup1_w3 register + * Otp debuger block0 data register4. + */ +typedef union { + struct { + /** block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word3 data. + */ + uint32_t block0_backup1_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word4 Data */ +/** Type of blk0_backup1_w4 register + * Otp debuger block0 data register5. + */ +typedef union { + struct { + /** block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word4 data. + */ + uint32_t block0_backup1_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup1 Word5 Data */ +/** Type of blk0_backup1_w5 register + * Otp debuger block0 data register6. + */ +typedef union { + struct { + /** block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup1 word5 data. + */ + uint32_t block0_backup1_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup1_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word1 Data */ +/** Type of blk0_backup2_w1 register + * Otp debuger block0 data register7. + */ +typedef union { + struct { + /** block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word1 data. + */ + uint32_t block0_backup2_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word2 Data */ +/** Type of blk0_backup2_w2 register + * Otp debuger block0 data register8. + */ +typedef union { + struct { + /** block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word2 data. + */ + uint32_t block0_backup2_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word3 Data */ +/** Type of blk0_backup2_w3 register + * Otp debuger block0 data register9. + */ +typedef union { + struct { + /** block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word3 data. + */ + uint32_t block0_backup2_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word4 Data */ +/** Type of blk0_backup2_w4 register + * Otp debuger block0 data register10. + */ +typedef union { + struct { + /** block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word4 data. + */ + uint32_t block0_backup2_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup2 Word5 Data */ +/** Type of blk0_backup2_w5 register + * Otp debuger block0 data register11. + */ +typedef union { + struct { + /** block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup2 word5 data. + */ + uint32_t block0_backup2_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup2_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word1 Data */ +/** Type of blk0_backup3_w1 register + * Otp debuger block0 data register12. + */ +typedef union { + struct { + /** block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word1 data. + */ + uint32_t block0_backup3_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word2 Data */ +/** Type of blk0_backup3_w2 register + * Otp debuger block0 data register13. + */ +typedef union { + struct { + /** block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word2 data. + */ + uint32_t block0_backup3_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word3 Data */ +/** Type of blk0_backup3_w3 register + * Otp debuger block0 data register14. + */ +typedef union { + struct { + /** block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word3 data. + */ + uint32_t block0_backup3_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word4 Data */ +/** Type of blk0_backup3_w4 register + * Otp debuger block0 data register15. + */ +typedef union { + struct { + /** block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word4 data. + */ + uint32_t block0_backup3_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup3 Word5 Data */ +/** Type of blk0_backup3_w5 register + * Otp debuger block0 data register16. + */ +typedef union { + struct { + /** block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup3 word5 data. + */ + uint32_t block0_backup3_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup3_w5_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word1 Data */ +/** Type of blk0_backup4_w1 register + * Otp debuger block0 data register17. + */ +typedef union { + struct { + /** block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word1 data. + */ + uint32_t block0_backup4_w1:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w1_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word2 Data */ +/** Type of blk0_backup4_w2 register + * Otp debuger block0 data register18. + */ +typedef union { + struct { + /** block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word2 data. + */ + uint32_t block0_backup4_w2:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w2_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word3 Data */ +/** Type of blk0_backup4_w3 register + * Otp debuger block0 data register19. + */ +typedef union { + struct { + /** block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word3 data. + */ + uint32_t block0_backup4_w3:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w3_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word4 Data */ +/** Type of blk0_backup4_w4 register + * Otp debuger block0 data register20. + */ +typedef union { + struct { + /** block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word4 data. + */ + uint32_t block0_backup4_w4:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w4_reg_t; + + +/** Group: OTP_DEBUG Block0 Backup4 Word5 Data */ +/** Type of blk0_backup4_w5 register + * Otp debuger block0 data register21. + */ +typedef union { + struct { + /** block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block0 backup4 word5 data. + */ + uint32_t block0_backup4_w5:32; + }; + uint32_t val; +} otp_debug_blk0_backup4_w5_reg_t; + + +/** Group: OTP_DEBUG Block1 Word1 Data */ +/** Type of blk1_w1 register + * Otp debuger block1 data register1. + */ +typedef union { + struct { + /** block1_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word1 data. + */ + uint32_t block1_w1:32; + }; + uint32_t val; +} otp_debug_blk1_w1_reg_t; + + +/** Group: OTP_DEBUG Block1 Word2 Data */ +/** Type of blk1_w2 register + * Otp debuger block1 data register2. + */ +typedef union { + struct { + /** block1_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word2 data. + */ + uint32_t block1_w2:32; + }; + uint32_t val; +} otp_debug_blk1_w2_reg_t; + + +/** Group: OTP_DEBUG Block1 Word3 Data */ +/** Type of blk1_w3 register + * Otp debuger block1 data register3. + */ +typedef union { + struct { + /** block1_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word3 data. + */ + uint32_t block1_w3:32; + }; + uint32_t val; +} otp_debug_blk1_w3_reg_t; + + +/** Group: OTP_DEBUG Block1 Word4 Data */ +/** Type of blk1_w4 register + * Otp debuger block1 data register4. + */ +typedef union { + struct { + /** block1_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word4 data. + */ + uint32_t block1_w4:32; + }; + uint32_t val; +} otp_debug_blk1_w4_reg_t; + + +/** Group: OTP_DEBUG Block1 Word5 Data */ +/** Type of blk1_w5 register + * Otp debuger block1 data register5. + */ +typedef union { + struct { + /** block1_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word5 data. + */ + uint32_t block1_w5:32; + }; + uint32_t val; +} otp_debug_blk1_w5_reg_t; + + +/** Group: OTP_DEBUG Block1 Word6 Data */ +/** Type of blk1_w6 register + * Otp debuger block1 data register6. + */ +typedef union { + struct { + /** block1_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word6 data. + */ + uint32_t block1_w6:32; + }; + uint32_t val; +} otp_debug_blk1_w6_reg_t; + + +/** Group: OTP_DEBUG Block1 Word7 Data */ +/** Type of blk1_w7 register + * Otp debuger block1 data register7. + */ +typedef union { + struct { + /** block1_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word7 data. + */ + uint32_t block1_w7:32; + }; + uint32_t val; +} otp_debug_blk1_w7_reg_t; + + +/** Group: OTP_DEBUG Block1 Word8 Data */ +/** Type of blk1_w8 register + * Otp debuger block1 data register8. + */ +typedef union { + struct { + /** block1_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word8 data. + */ + uint32_t block1_w8:32; + }; + uint32_t val; +} otp_debug_blk1_w8_reg_t; + + +/** Group: OTP_DEBUG Block1 Word9 Data */ +/** Type of blk1_w9 register + * Otp debuger block1 data register9. + */ +typedef union { + struct { + /** block1_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block1 word9 data. + */ + uint32_t block1_w9:32; + }; + uint32_t val; +} otp_debug_blk1_w9_reg_t; + + +/** Group: OTP_DEBUG Block2 Word1 Data */ +/** Type of blk2_w1 register + * Otp debuger block2 data register1. + */ +typedef union { + struct { + /** block2_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word1 data. + */ + uint32_t block2_w1:32; + }; + uint32_t val; +} otp_debug_blk2_w1_reg_t; + + +/** Group: OTP_DEBUG Block2 Word2 Data */ +/** Type of blk2_w2 register + * Otp debuger block2 data register2. + */ +typedef union { + struct { + /** block2_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word2 data. + */ + uint32_t block2_w2:32; + }; + uint32_t val; +} otp_debug_blk2_w2_reg_t; + + +/** Group: OTP_DEBUG Block2 Word3 Data */ +/** Type of blk2_w3 register + * Otp debuger block2 data register3. + */ +typedef union { + struct { + /** block2_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word3 data. + */ + uint32_t block2_w3:32; + }; + uint32_t val; +} otp_debug_blk2_w3_reg_t; + + +/** Group: OTP_DEBUG Block2 Word4 Data */ +/** Type of blk2_w4 register + * Otp debuger block2 data register4. + */ +typedef union { + struct { + /** block2_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word4 data. + */ + uint32_t block2_w4:32; + }; + uint32_t val; +} otp_debug_blk2_w4_reg_t; + + +/** Group: OTP_DEBUG Block2 Word5 Data */ +/** Type of blk2_w5 register + * Otp debuger block2 data register5. + */ +typedef union { + struct { + /** block2_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word5 data. + */ + uint32_t block2_w5:32; + }; + uint32_t val; +} otp_debug_blk2_w5_reg_t; + + +/** Group: OTP_DEBUG Block2 Word6 Data */ +/** Type of blk2_w6 register + * Otp debuger block2 data register6. + */ +typedef union { + struct { + /** block2_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word6 data. + */ + uint32_t block2_w6:32; + }; + uint32_t val; +} otp_debug_blk2_w6_reg_t; + + +/** Group: OTP_DEBUG Block2 Word7 Data */ +/** Type of blk2_w7 register + * Otp debuger block2 data register7. + */ +typedef union { + struct { + /** block2_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word7 data. + */ + uint32_t block2_w7:32; + }; + uint32_t val; +} otp_debug_blk2_w7_reg_t; + + +/** Group: OTP_DEBUG Block2 Word8 Data */ +/** Type of blk2_w8 register + * Otp debuger block2 data register8. + */ +typedef union { + struct { + /** block2_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word8 data. + */ + uint32_t block2_w8:32; + }; + uint32_t val; +} otp_debug_blk2_w8_reg_t; + + +/** Group: OTP_DEBUG Block2 Word9 Data */ +/** Type of blk2_w9 register + * Otp debuger block2 data register9. + */ +typedef union { + struct { + /** block2_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word9 data. + */ + uint32_t block2_w9:32; + }; + uint32_t val; +} otp_debug_blk2_w9_reg_t; + + +/** Group: OTP_DEBUG Block2 Word10 Data */ +/** Type of blk2_w10 register + * Otp debuger block2 data register10. + */ +typedef union { + struct { + /** block2_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word10 data. + */ + uint32_t block2_w10:32; + }; + uint32_t val; +} otp_debug_blk2_w10_reg_t; + + +/** Group: OTP_DEBUG Block2 Word11 Data */ +/** Type of blk2_w11 register + * Otp debuger block2 data register11. + */ +typedef union { + struct { + /** block2_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block2 word11 data. + */ + uint32_t block2_w11:32; + }; + uint32_t val; +} otp_debug_blk2_w11_reg_t; + +/** Type of blk10_w11 register + * Otp debuger block10 data register11. + */ +typedef union { + struct { + /** block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t block10_w11:32; + }; + uint32_t val; +} otp_debug_blk10_w11_reg_t; + + +/** Group: OTP_DEBUG Block3 Word1 Data */ +/** Type of blk3_w1 register + * Otp debuger block3 data register1. + */ +typedef union { + struct { + /** block3_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word1 data. + */ + uint32_t block3_w1:32; + }; + uint32_t val; +} otp_debug_blk3_w1_reg_t; + + +/** Group: OTP_DEBUG Block3 Word2 Data */ +/** Type of blk3_w2 register + * Otp debuger block3 data register2. + */ +typedef union { + struct { + /** block3_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word2 data. + */ + uint32_t block3_w2:32; + }; + uint32_t val; +} otp_debug_blk3_w2_reg_t; + + +/** Group: OTP_DEBUG Block3 Word3 Data */ +/** Type of blk3_w3 register + * Otp debuger block3 data register3. + */ +typedef union { + struct { + /** block3_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word3 data. + */ + uint32_t block3_w3:32; + }; + uint32_t val; +} otp_debug_blk3_w3_reg_t; + + +/** Group: OTP_DEBUG Block3 Word4 Data */ +/** Type of blk3_w4 register + * Otp debuger block3 data register4. + */ +typedef union { + struct { + /** block3_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word4 data. + */ + uint32_t block3_w4:32; + }; + uint32_t val; +} otp_debug_blk3_w4_reg_t; + + +/** Group: OTP_DEBUG Block3 Word5 Data */ +/** Type of blk3_w5 register + * Otp debuger block3 data register5. + */ +typedef union { + struct { + /** block3_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word5 data. + */ + uint32_t block3_w5:32; + }; + uint32_t val; +} otp_debug_blk3_w5_reg_t; + + +/** Group: OTP_DEBUG Block3 Word6 Data */ +/** Type of blk3_w6 register + * Otp debuger block3 data register6. + */ +typedef union { + struct { + /** block3_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word6 data. + */ + uint32_t block3_w6:32; + }; + uint32_t val; +} otp_debug_blk3_w6_reg_t; + + +/** Group: OTP_DEBUG Block3 Word7 Data */ +/** Type of blk3_w7 register + * Otp debuger block3 data register7. + */ +typedef union { + struct { + /** block3_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word7 data. + */ + uint32_t block3_w7:32; + }; + uint32_t val; +} otp_debug_blk3_w7_reg_t; + + +/** Group: OTP_DEBUG Block3 Word8 Data */ +/** Type of blk3_w8 register + * Otp debuger block3 data register8. + */ +typedef union { + struct { + /** block3_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word8 data. + */ + uint32_t block3_w8:32; + }; + uint32_t val; +} otp_debug_blk3_w8_reg_t; + + +/** Group: OTP_DEBUG Block3 Word9 Data */ +/** Type of blk3_w9 register + * Otp debuger block3 data register9. + */ +typedef union { + struct { + /** block3_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word9 data. + */ + uint32_t block3_w9:32; + }; + uint32_t val; +} otp_debug_blk3_w9_reg_t; + + +/** Group: OTP_DEBUG Block3 Word10 Data */ +/** Type of blk3_w10 register + * Otp debuger block3 data register10. + */ +typedef union { + struct { + /** block3_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word10 data. + */ + uint32_t block3_w10:32; + }; + uint32_t val; +} otp_debug_blk3_w10_reg_t; + + +/** Group: OTP_DEBUG Block3 Word11 Data */ +/** Type of blk3_w11 register + * Otp debuger block3 data register11. + */ +typedef union { + struct { + /** block3_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block3 word11 data. + */ + uint32_t block3_w11:32; + }; + uint32_t val; +} otp_debug_blk3_w11_reg_t; + + +/** Group: OTP_DEBUG Block4 Word1 Data */ +/** Type of blk4_w1 register + * Otp debuger block4 data register1. + */ +typedef union { + struct { + /** block4_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word1 data. + */ + uint32_t block4_w1:32; + }; + uint32_t val; +} otp_debug_blk4_w1_reg_t; + + +/** Group: OTP_DEBUG Block4 Word2 Data */ +/** Type of blk4_w2 register + * Otp debuger block4 data register2. + */ +typedef union { + struct { + /** block4_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word2 data. + */ + uint32_t block4_w2:32; + }; + uint32_t val; +} otp_debug_blk4_w2_reg_t; + + +/** Group: OTP_DEBUG Block4 Word3 Data */ +/** Type of blk4_w3 register + * Otp debuger block4 data register3. + */ +typedef union { + struct { + /** block4_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word3 data. + */ + uint32_t block4_w3:32; + }; + uint32_t val; +} otp_debug_blk4_w3_reg_t; + + +/** Group: OTP_DEBUG Block4 Word4 Data */ +/** Type of blk4_w4 register + * Otp debuger block4 data register4. + */ +typedef union { + struct { + /** block4_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word4 data. + */ + uint32_t block4_w4:32; + }; + uint32_t val; +} otp_debug_blk4_w4_reg_t; + + +/** Group: OTP_DEBUG Block4 Word5 Data */ +/** Type of blk4_w5 register + * Otp debuger block4 data register5. + */ +typedef union { + struct { + /** block4_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word5 data. + */ + uint32_t block4_w5:32; + }; + uint32_t val; +} otp_debug_blk4_w5_reg_t; + + +/** Group: OTP_DEBUG Block4 Word6 Data */ +/** Type of blk4_w6 register + * Otp debuger block4 data register6. + */ +typedef union { + struct { + /** block4_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word6 data. + */ + uint32_t block4_w6:32; + }; + uint32_t val; +} otp_debug_blk4_w6_reg_t; + + +/** Group: OTP_DEBUG Block4 Word7 Data */ +/** Type of blk4_w7 register + * Otp debuger block4 data register7. + */ +typedef union { + struct { + /** block4_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word7 data. + */ + uint32_t block4_w7:32; + }; + uint32_t val; +} otp_debug_blk4_w7_reg_t; + + +/** Group: OTP_DEBUG Block4 Word8 Data */ +/** Type of blk4_w8 register + * Otp debuger block4 data register8. + */ +typedef union { + struct { + /** block4_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word8 data. + */ + uint32_t block4_w8:32; + }; + uint32_t val; +} otp_debug_blk4_w8_reg_t; + + +/** Group: OTP_DEBUG Block4 Word9 Data */ +/** Type of blk4_w9 register + * Otp debuger block4 data register9. + */ +typedef union { + struct { + /** block4_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word9 data. + */ + uint32_t block4_w9:32; + }; + uint32_t val; +} otp_debug_blk4_w9_reg_t; + + +/** Group: OTP_DEBUG Block4 Word10 Data */ +/** Type of blk4_w10 register + * Otp debuger block4 data registe10. + */ +typedef union { + struct { + /** block4_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word10 data. + */ + uint32_t block4_w10:32; + }; + uint32_t val; +} otp_debug_blk4_w10_reg_t; + + +/** Group: OTP_DEBUG Block4 Word11 Data */ +/** Type of blk4_w11 register + * Otp debuger block4 data register11. + */ +typedef union { + struct { + /** block4_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block4 word11 data. + */ + uint32_t block4_w11:32; + }; + uint32_t val; +} otp_debug_blk4_w11_reg_t; + + +/** Group: OTP_DEBUG Block5 Word1 Data */ +/** Type of blk5_w1 register + * Otp debuger block5 data register1. + */ +typedef union { + struct { + /** block5_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word1 data. + */ + uint32_t block5_w1:32; + }; + uint32_t val; +} otp_debug_blk5_w1_reg_t; + + +/** Group: OTP_DEBUG Block5 Word2 Data */ +/** Type of blk5_w2 register + * Otp debuger block5 data register2. + */ +typedef union { + struct { + /** block5_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word2 data. + */ + uint32_t block5_w2:32; + }; + uint32_t val; +} otp_debug_blk5_w2_reg_t; + + +/** Group: OTP_DEBUG Block5 Word3 Data */ +/** Type of blk5_w3 register + * Otp debuger block5 data register3. + */ +typedef union { + struct { + /** block5_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word3 data. + */ + uint32_t block5_w3:32; + }; + uint32_t val; +} otp_debug_blk5_w3_reg_t; + + +/** Group: OTP_DEBUG Block5 Word4 Data */ +/** Type of blk5_w4 register + * Otp debuger block5 data register4. + */ +typedef union { + struct { + /** block5_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word4 data. + */ + uint32_t block5_w4:32; + }; + uint32_t val; +} otp_debug_blk5_w4_reg_t; + + +/** Group: OTP_DEBUG Block5 Word5 Data */ +/** Type of blk5_w5 register + * Otp debuger block5 data register5. + */ +typedef union { + struct { + /** block5_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word5 data. + */ + uint32_t block5_w5:32; + }; + uint32_t val; +} otp_debug_blk5_w5_reg_t; + + +/** Group: OTP_DEBUG Block5 Word6 Data */ +/** Type of blk5_w6 register + * Otp debuger block5 data register6. + */ +typedef union { + struct { + /** block5_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word6 data. + */ + uint32_t block5_w6:32; + }; + uint32_t val; +} otp_debug_blk5_w6_reg_t; + + +/** Group: OTP_DEBUG Block5 Word7 Data */ +/** Type of blk5_w7 register + * Otp debuger block5 data register7. + */ +typedef union { + struct { + /** block5_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word7 data. + */ + uint32_t block5_w7:32; + }; + uint32_t val; +} otp_debug_blk5_w7_reg_t; + + +/** Group: OTP_DEBUG Block5 Word8 Data */ +/** Type of blk5_w8 register + * Otp debuger block5 data register8. + */ +typedef union { + struct { + /** block5_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word8 data. + */ + uint32_t block5_w8:32; + }; + uint32_t val; +} otp_debug_blk5_w8_reg_t; + + +/** Group: OTP_DEBUG Block5 Word9 Data */ +/** Type of blk5_w9 register + * Otp debuger block5 data register9. + */ +typedef union { + struct { + /** block5_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word9 data. + */ + uint32_t block5_w9:32; + }; + uint32_t val; +} otp_debug_blk5_w9_reg_t; + + +/** Group: OTP_DEBUG Block5 Word10 Data */ +/** Type of blk5_w10 register + * Otp debuger block5 data register10. + */ +typedef union { + struct { + /** block5_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word10 data. + */ + uint32_t block5_w10:32; + }; + uint32_t val; +} otp_debug_blk5_w10_reg_t; + + +/** Group: OTP_DEBUG Block5 Word11 Data */ +/** Type of blk5_w11 register + * Otp debuger block5 data register11. + */ +typedef union { + struct { + /** block5_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block5 word11 data. + */ + uint32_t block5_w11:32; + }; + uint32_t val; +} otp_debug_blk5_w11_reg_t; + + +/** Group: OTP_DEBUG Block6 Word1 Data */ +/** Type of blk6_w1 register + * Otp debuger block6 data register1. + */ +typedef union { + struct { + /** block6_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word1 data. + */ + uint32_t block6_w1:32; + }; + uint32_t val; +} otp_debug_blk6_w1_reg_t; + + +/** Group: OTP_DEBUG Block6 Word2 Data */ +/** Type of blk6_w2 register + * Otp debuger block6 data register2. + */ +typedef union { + struct { + /** block6_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word2 data. + */ + uint32_t block6_w2:32; + }; + uint32_t val; +} otp_debug_blk6_w2_reg_t; + + +/** Group: OTP_DEBUG Block6 Word3 Data */ +/** Type of blk6_w3 register + * Otp debuger block6 data register3. + */ +typedef union { + struct { + /** block6_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word3 data. + */ + uint32_t block6_w3:32; + }; + uint32_t val; +} otp_debug_blk6_w3_reg_t; + + +/** Group: OTP_DEBUG Block6 Word4 Data */ +/** Type of blk6_w4 register + * Otp debuger block6 data register4. + */ +typedef union { + struct { + /** block6_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word4 data. + */ + uint32_t block6_w4:32; + }; + uint32_t val; +} otp_debug_blk6_w4_reg_t; + + +/** Group: OTP_DEBUG Block6 Word5 Data */ +/** Type of blk6_w5 register + * Otp debuger block6 data register5. + */ +typedef union { + struct { + /** block6_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word5 data. + */ + uint32_t block6_w5:32; + }; + uint32_t val; +} otp_debug_blk6_w5_reg_t; + + +/** Group: OTP_DEBUG Block6 Word6 Data */ +/** Type of blk6_w6 register + * Otp debuger block6 data register6. + */ +typedef union { + struct { + /** block6_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word6 data. + */ + uint32_t block6_w6:32; + }; + uint32_t val; +} otp_debug_blk6_w6_reg_t; + + +/** Group: OTP_DEBUG Block6 Word7 Data */ +/** Type of blk6_w7 register + * Otp debuger block6 data register7. + */ +typedef union { + struct { + /** block6_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word7 data. + */ + uint32_t block6_w7:32; + }; + uint32_t val; +} otp_debug_blk6_w7_reg_t; + + +/** Group: OTP_DEBUG Block6 Word8 Data */ +/** Type of blk6_w8 register + * Otp debuger block6 data register8. + */ +typedef union { + struct { + /** block6_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word8 data. + */ + uint32_t block6_w8:32; + }; + uint32_t val; +} otp_debug_blk6_w8_reg_t; + + +/** Group: OTP_DEBUG Block6 Word9 Data */ +/** Type of blk6_w9 register + * Otp debuger block6 data register9. + */ +typedef union { + struct { + /** block6_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word9 data. + */ + uint32_t block6_w9:32; + }; + uint32_t val; +} otp_debug_blk6_w9_reg_t; + + +/** Group: OTP_DEBUG Block6 Word10 Data */ +/** Type of blk6_w10 register + * Otp debuger block6 data register10. + */ +typedef union { + struct { + /** block6_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word10 data. + */ + uint32_t block6_w10:32; + }; + uint32_t val; +} otp_debug_blk6_w10_reg_t; + + +/** Group: OTP_DEBUG Block6 Word11 Data */ +/** Type of blk6_w11 register + * Otp debuger block6 data register11. + */ +typedef union { + struct { + /** block6_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block6 word11 data. + */ + uint32_t block6_w11:32; + }; + uint32_t val; +} otp_debug_blk6_w11_reg_t; + + +/** Group: OTP_DEBUG Block7 Word1 Data */ +/** Type of blk7_w1 register + * Otp debuger block7 data register1. + */ +typedef union { + struct { + /** block7_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word1 data. + */ + uint32_t block7_w1:32; + }; + uint32_t val; +} otp_debug_blk7_w1_reg_t; + + +/** Group: OTP_DEBUG Block7 Word2 Data */ +/** Type of blk7_w2 register + * Otp debuger block7 data register2. + */ +typedef union { + struct { + /** block7_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word2 data. + */ + uint32_t block7_w2:32; + }; + uint32_t val; +} otp_debug_blk7_w2_reg_t; + + +/** Group: OTP_DEBUG Block7 Word3 Data */ +/** Type of blk7_w3 register + * Otp debuger block7 data register3. + */ +typedef union { + struct { + /** block7_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word3 data. + */ + uint32_t block7_w3:32; + }; + uint32_t val; +} otp_debug_blk7_w3_reg_t; + + +/** Group: OTP_DEBUG Block7 Word4 Data */ +/** Type of blk7_w4 register + * Otp debuger block7 data register4. + */ +typedef union { + struct { + /** block7_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word4 data. + */ + uint32_t block7_w4:32; + }; + uint32_t val; +} otp_debug_blk7_w4_reg_t; + + +/** Group: OTP_DEBUG Block7 Word5 Data */ +/** Type of blk7_w5 register + * Otp debuger block7 data register5. + */ +typedef union { + struct { + /** block7_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word5 data. + */ + uint32_t block7_w5:32; + }; + uint32_t val; +} otp_debug_blk7_w5_reg_t; + + +/** Group: OTP_DEBUG Block7 Word6 Data */ +/** Type of blk7_w6 register + * Otp debuger block7 data register6. + */ +typedef union { + struct { + /** block7_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word6 data. + */ + uint32_t block7_w6:32; + }; + uint32_t val; +} otp_debug_blk7_w6_reg_t; + + +/** Group: OTP_DEBUG Block7 Word7 Data */ +/** Type of blk7_w7 register + * Otp debuger block7 data register7. + */ +typedef union { + struct { + /** block7_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word7 data. + */ + uint32_t block7_w7:32; + }; + uint32_t val; +} otp_debug_blk7_w7_reg_t; + + +/** Group: OTP_DEBUG Block7 Word8 Data */ +/** Type of blk7_w8 register + * Otp debuger block7 data register8. + */ +typedef union { + struct { + /** block7_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word8 data. + */ + uint32_t block7_w8:32; + }; + uint32_t val; +} otp_debug_blk7_w8_reg_t; + + +/** Group: OTP_DEBUG Block7 Word9 Data */ +/** Type of blk7_w9 register + * Otp debuger block7 data register9. + */ +typedef union { + struct { + /** block7_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word9 data. + */ + uint32_t block7_w9:32; + }; + uint32_t val; +} otp_debug_blk7_w9_reg_t; + + +/** Group: OTP_DEBUG Block7 Word10 Data */ +/** Type of blk7_w10 register + * Otp debuger block7 data register10. + */ +typedef union { + struct { + /** block7_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word10 data. + */ + uint32_t block7_w10:32; + }; + uint32_t val; +} otp_debug_blk7_w10_reg_t; + + +/** Group: OTP_DEBUG Block7 Word11 Data */ +/** Type of blk7_w11 register + * Otp debuger block7 data register11. + */ +typedef union { + struct { + /** block7_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block7 word11 data. + */ + uint32_t block7_w11:32; + }; + uint32_t val; +} otp_debug_blk7_w11_reg_t; + + +/** Group: OTP_DEBUG Block8 Word1 Data */ +/** Type of blk8_w1 register + * Otp debuger block8 data register1. + */ +typedef union { + struct { + /** block8_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word1 data. + */ + uint32_t block8_w1:32; + }; + uint32_t val; +} otp_debug_blk8_w1_reg_t; + + +/** Group: OTP_DEBUG Block8 Word2 Data */ +/** Type of blk8_w2 register + * Otp debuger block8 data register2. + */ +typedef union { + struct { + /** block8_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word2 data. + */ + uint32_t block8_w2:32; + }; + uint32_t val; +} otp_debug_blk8_w2_reg_t; + + +/** Group: OTP_DEBUG Block8 Word3 Data */ +/** Type of blk8_w3 register + * Otp debuger block8 data register3. + */ +typedef union { + struct { + /** block8_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word3 data. + */ + uint32_t block8_w3:32; + }; + uint32_t val; +} otp_debug_blk8_w3_reg_t; + + +/** Group: OTP_DEBUG Block8 Word4 Data */ +/** Type of blk8_w4 register + * Otp debuger block8 data register4. + */ +typedef union { + struct { + /** block8_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word4 data. + */ + uint32_t block8_w4:32; + }; + uint32_t val; +} otp_debug_blk8_w4_reg_t; + + +/** Group: OTP_DEBUG Block8 Word5 Data */ +/** Type of blk8_w5 register + * Otp debuger block8 data register5. + */ +typedef union { + struct { + /** block8_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word5 data. + */ + uint32_t block8_w5:32; + }; + uint32_t val; +} otp_debug_blk8_w5_reg_t; + + +/** Group: OTP_DEBUG Block8 Word6 Data */ +/** Type of blk8_w6 register + * Otp debuger block8 data register6. + */ +typedef union { + struct { + /** block8_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word6 data. + */ + uint32_t block8_w6:32; + }; + uint32_t val; +} otp_debug_blk8_w6_reg_t; + + +/** Group: OTP_DEBUG Block8 Word7 Data */ +/** Type of blk8_w7 register + * Otp debuger block8 data register7. + */ +typedef union { + struct { + /** block8_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word7 data. + */ + uint32_t block8_w7:32; + }; + uint32_t val; +} otp_debug_blk8_w7_reg_t; + + +/** Group: OTP_DEBUG Block8 Word8 Data */ +/** Type of blk8_w8 register + * Otp debuger block8 data register8. + */ +typedef union { + struct { + /** block8_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word8 data. + */ + uint32_t block8_w8:32; + }; + uint32_t val; +} otp_debug_blk8_w8_reg_t; + + +/** Group: OTP_DEBUG Block8 Word9 Data */ +/** Type of blk8_w9 register + * Otp debuger block8 data register9. + */ +typedef union { + struct { + /** block8_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word9 data. + */ + uint32_t block8_w9:32; + }; + uint32_t val; +} otp_debug_blk8_w9_reg_t; + + +/** Group: OTP_DEBUG Block8 Word10 Data */ +/** Type of blk8_w10 register + * Otp debuger block8 data register10. + */ +typedef union { + struct { + /** block8_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word10 data. + */ + uint32_t block8_w10:32; + }; + uint32_t val; +} otp_debug_blk8_w10_reg_t; + + +/** Group: OTP_DEBUG Block8 Word11 Data */ +/** Type of blk8_w11 register + * Otp debuger block8 data register11. + */ +typedef union { + struct { + /** block8_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block8 word11 data. + */ + uint32_t block8_w11:32; + }; + uint32_t val; +} otp_debug_blk8_w11_reg_t; + + +/** Group: OTP_DEBUG Block9 Word1 Data */ +/** Type of blk9_w1 register + * Otp debuger block9 data register1. + */ +typedef union { + struct { + /** block9_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word1 data. + */ + uint32_t block9_w1:32; + }; + uint32_t val; +} otp_debug_blk9_w1_reg_t; + + +/** Group: OTP_DEBUG Block9 Word2 Data */ +/** Type of blk9_w2 register + * Otp debuger block9 data register2. + */ +typedef union { + struct { + /** block9_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word2 data. + */ + uint32_t block9_w2:32; + }; + uint32_t val; +} otp_debug_blk9_w2_reg_t; + + +/** Group: OTP_DEBUG Block9 Word3 Data */ +/** Type of blk9_w3 register + * Otp debuger block9 data register3. + */ +typedef union { + struct { + /** block9_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word3 data. + */ + uint32_t block9_w3:32; + }; + uint32_t val; +} otp_debug_blk9_w3_reg_t; + + +/** Group: OTP_DEBUG Block9 Word4 Data */ +/** Type of blk9_w4 register + * Otp debuger block9 data register4. + */ +typedef union { + struct { + /** block9_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word4 data. + */ + uint32_t block9_w4:32; + }; + uint32_t val; +} otp_debug_blk9_w4_reg_t; + + +/** Group: OTP_DEBUG Block9 Word5 Data */ +/** Type of blk9_w5 register + * Otp debuger block9 data register5. + */ +typedef union { + struct { + /** block9_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word5 data. + */ + uint32_t block9_w5:32; + }; + uint32_t val; +} otp_debug_blk9_w5_reg_t; + + +/** Group: OTP_DEBUG Block9 Word6 Data */ +/** Type of blk9_w6 register + * Otp debuger block9 data register6. + */ +typedef union { + struct { + /** block9_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word6 data. + */ + uint32_t block9_w6:32; + }; + uint32_t val; +} otp_debug_blk9_w6_reg_t; + + +/** Group: OTP_DEBUG Block9 Word7 Data */ +/** Type of blk9_w7 register + * Otp debuger block9 data register7. + */ +typedef union { + struct { + /** block9_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word7 data. + */ + uint32_t block9_w7:32; + }; + uint32_t val; +} otp_debug_blk9_w7_reg_t; + + +/** Group: OTP_DEBUG Block9 Word8 Data */ +/** Type of blk9_w8 register + * Otp debuger block9 data register8. + */ +typedef union { + struct { + /** block9_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word8 data. + */ + uint32_t block9_w8:32; + }; + uint32_t val; +} otp_debug_blk9_w8_reg_t; + + +/** Group: OTP_DEBUG Block9 Word9 Data */ +/** Type of blk9_w9 register + * Otp debuger block9 data register9. + */ +typedef union { + struct { + /** block9_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word9 data. + */ + uint32_t block9_w9:32; + }; + uint32_t val; +} otp_debug_blk9_w9_reg_t; + + +/** Group: OTP_DEBUG Block9 Word10 Data */ +/** Type of blk9_w10 register + * Otp debuger block9 data register10. + */ +typedef union { + struct { + /** block9_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word10 data. + */ + uint32_t block9_w10:32; + }; + uint32_t val; +} otp_debug_blk9_w10_reg_t; + + +/** Group: OTP_DEBUG Block9 Word11 Data */ +/** Type of blk9_w11 register + * Otp debuger block9 data register11. + */ +typedef union { + struct { + /** block9_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block9 word11 data. + */ + uint32_t block9_w11:32; + }; + uint32_t val; +} otp_debug_blk9_w11_reg_t; + + +/** Group: OTP_DEBUG Block10 Word1 Data */ +/** Type of blk10_w1 register + * Otp debuger block10 data register1. + */ +typedef union { + struct { + /** block10_w1 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word1 data. + */ + uint32_t block10_w1:32; + }; + uint32_t val; +} otp_debug_blk10_w1_reg_t; + + +/** Group: OTP_DEBUG Block10 Word2 Data */ +/** Type of blk10_w2 register + * Otp debuger block10 data register2. + */ +typedef union { + struct { + /** block10_w2 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word2 data. + */ + uint32_t block10_w2:32; + }; + uint32_t val; +} otp_debug_blk10_w2_reg_t; + + +/** Group: OTP_DEBUG Block10 Word3 Data */ +/** Type of blk10_w3 register + * Otp debuger block10 data register3. + */ +typedef union { + struct { + /** block10_w3 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word3 data. + */ + uint32_t block10_w3:32; + }; + uint32_t val; +} otp_debug_blk10_w3_reg_t; + + +/** Group: OTP_DEBUG Block10 Word4 Data */ +/** Type of blk10_w4 register + * Otp debuger block10 data register4. + */ +typedef union { + struct { + /** block10_w4 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word4 data. + */ + uint32_t block10_w4:32; + }; + uint32_t val; +} otp_debug_blk10_w4_reg_t; + + +/** Group: OTP_DEBUG Block10 Word5 Data */ +/** Type of blk10_w5 register + * Otp debuger block10 data register5. + */ +typedef union { + struct { + /** block10_w5 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word5 data. + */ + uint32_t block10_w5:32; + }; + uint32_t val; +} otp_debug_blk10_w5_reg_t; + + +/** Group: OTP_DEBUG Block10 Word6 Data */ +/** Type of blk10_w6 register + * Otp debuger block10 data register6. + */ +typedef union { + struct { + /** block10_w6 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word6 data. + */ + uint32_t block10_w6:32; + }; + uint32_t val; +} otp_debug_blk10_w6_reg_t; + + +/** Group: OTP_DEBUG Block10 Word7 Data */ +/** Type of blk10_w7 register + * Otp debuger block10 data register7. + */ +typedef union { + struct { + /** block10_w7 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word7 data. + */ + uint32_t block10_w7:32; + }; + uint32_t val; +} otp_debug_blk10_w7_reg_t; + + +/** Group: OTP_DEBUG Block10 Word8 Data */ +/** Type of blk10_w8 register + * Otp debuger block10 data register8. + */ +typedef union { + struct { + /** block10_w8 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word8 data. + */ + uint32_t block10_w8:32; + }; + uint32_t val; +} otp_debug_blk10_w8_reg_t; + + +/** Group: OTP_DEBUG Block10 Word9 Data */ +/** Type of blk10_w9 register + * Otp debuger block10 data register9. + */ +typedef union { + struct { + /** block10_w9 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word9 data. + */ + uint32_t block10_w9:32; + }; + uint32_t val; +} otp_debug_blk10_w9_reg_t; + + +/** Group: OTP_DEBUG Block10 Word10 Data */ +/** Type of blk10_w10 register + * Otp debuger block10 data register10. + */ +typedef union { + struct { + /** block19_w10 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word10 data. + */ + uint32_t block19_w10:32; + }; + uint32_t val; +} otp_debug_blk10_w10_reg_t; + + +/** Group: OTP_DEBUG Clock_en Configuration Register */ +/** Type of clk register + * Otp debuger clk_en configuration register. + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Force clock on for this register file. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} otp_debug_clk_reg_t; + + +/** Group: OTP_DEBUG Apb2otp Enable Singal */ +/** Type of apb2otp_en register + * Otp_debuger apb2otp enable configuration register. + */ +typedef union { + struct { + /** apb2otp_en : R/W; bitpos: [0]; default: 0; + * Debug mode enable signal. + */ + uint32_t apb2otp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} otp_debug_apb2otp_en_reg_t; + + +/** Group: OTP_DEBUG Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 539037736; + * Stores otp_debug version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} otp_debug_date_reg_t; + + +typedef struct { + volatile otp_debug_wr_dis_reg_t wr_dis; + volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1; + volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2; + volatile otp_debug_blk0_backup1_w3_reg_t blk0_backup1_w3; + volatile otp_debug_blk0_backup1_w4_reg_t blk0_backup1_w4; + volatile otp_debug_blk0_backup1_w5_reg_t blk0_backup1_w5; + volatile otp_debug_blk0_backup2_w1_reg_t blk0_backup2_w1; + volatile otp_debug_blk0_backup2_w2_reg_t blk0_backup2_w2; + volatile otp_debug_blk0_backup2_w3_reg_t blk0_backup2_w3; + volatile otp_debug_blk0_backup2_w4_reg_t blk0_backup2_w4; + volatile otp_debug_blk0_backup2_w5_reg_t blk0_backup2_w5; + volatile otp_debug_blk0_backup3_w1_reg_t blk0_backup3_w1; + volatile otp_debug_blk0_backup3_w2_reg_t blk0_backup3_w2; + volatile otp_debug_blk0_backup3_w3_reg_t blk0_backup3_w3; + volatile otp_debug_blk0_backup3_w4_reg_t blk0_backup3_w4; + volatile otp_debug_blk0_backup3_w5_reg_t blk0_backup3_w5; + volatile otp_debug_blk0_backup4_w1_reg_t blk0_backup4_w1; + volatile otp_debug_blk0_backup4_w2_reg_t blk0_backup4_w2; + volatile otp_debug_blk0_backup4_w3_reg_t blk0_backup4_w3; + volatile otp_debug_blk0_backup4_w4_reg_t blk0_backup4_w4; + volatile otp_debug_blk0_backup4_w5_reg_t blk0_backup4_w5; + volatile otp_debug_blk1_w1_reg_t blk1_w1; + volatile otp_debug_blk1_w2_reg_t blk1_w2; + volatile otp_debug_blk1_w3_reg_t blk1_w3; + volatile otp_debug_blk1_w4_reg_t blk1_w4; + volatile otp_debug_blk1_w5_reg_t blk1_w5; + volatile otp_debug_blk1_w6_reg_t blk1_w6; + volatile otp_debug_blk1_w7_reg_t blk1_w7; + volatile otp_debug_blk1_w8_reg_t blk1_w8; + volatile otp_debug_blk1_w9_reg_t blk1_w9; + volatile otp_debug_blk2_w1_reg_t blk2_w1; + volatile otp_debug_blk2_w2_reg_t blk2_w2; + volatile otp_debug_blk2_w3_reg_t blk2_w3; + volatile otp_debug_blk2_w4_reg_t blk2_w4; + volatile otp_debug_blk2_w5_reg_t blk2_w5; + volatile otp_debug_blk2_w6_reg_t blk2_w6; + volatile otp_debug_blk2_w7_reg_t blk2_w7; + volatile otp_debug_blk2_w8_reg_t blk2_w8; + volatile otp_debug_blk2_w9_reg_t blk2_w9; + volatile otp_debug_blk2_w10_reg_t blk2_w10; + volatile otp_debug_blk2_w11_reg_t blk2_w11; + volatile otp_debug_blk3_w1_reg_t blk3_w1; + volatile otp_debug_blk3_w2_reg_t blk3_w2; + volatile otp_debug_blk3_w3_reg_t blk3_w3; + volatile otp_debug_blk3_w4_reg_t blk3_w4; + volatile otp_debug_blk3_w5_reg_t blk3_w5; + volatile otp_debug_blk3_w6_reg_t blk3_w6; + volatile otp_debug_blk3_w7_reg_t blk3_w7; + volatile otp_debug_blk3_w8_reg_t blk3_w8; + volatile otp_debug_blk3_w9_reg_t blk3_w9; + volatile otp_debug_blk3_w10_reg_t blk3_w10; + volatile otp_debug_blk3_w11_reg_t blk3_w11; + volatile otp_debug_blk4_w1_reg_t blk4_w1; + volatile otp_debug_blk4_w2_reg_t blk4_w2; + volatile otp_debug_blk4_w3_reg_t blk4_w3; + volatile otp_debug_blk4_w4_reg_t blk4_w4; + volatile otp_debug_blk4_w5_reg_t blk4_w5; + volatile otp_debug_blk4_w6_reg_t blk4_w6; + volatile otp_debug_blk4_w7_reg_t blk4_w7; + volatile otp_debug_blk4_w8_reg_t blk4_w8; + volatile otp_debug_blk4_w9_reg_t blk4_w9; + volatile otp_debug_blk4_w10_reg_t blk4_w10; + volatile otp_debug_blk4_w11_reg_t blk4_w11; + volatile otp_debug_blk5_w1_reg_t blk5_w1; + volatile otp_debug_blk5_w2_reg_t blk5_w2; + volatile otp_debug_blk5_w3_reg_t blk5_w3; + volatile otp_debug_blk5_w4_reg_t blk5_w4; + volatile otp_debug_blk5_w5_reg_t blk5_w5; + volatile otp_debug_blk5_w6_reg_t blk5_w6; + volatile otp_debug_blk5_w7_reg_t blk5_w7; + volatile otp_debug_blk5_w8_reg_t blk5_w8; + volatile otp_debug_blk5_w9_reg_t blk5_w9; + volatile otp_debug_blk5_w10_reg_t blk5_w10; + volatile otp_debug_blk5_w11_reg_t blk5_w11; + volatile otp_debug_blk6_w1_reg_t blk6_w1; + volatile otp_debug_blk6_w2_reg_t blk6_w2; + volatile otp_debug_blk6_w3_reg_t blk6_w3; + volatile otp_debug_blk6_w4_reg_t blk6_w4; + volatile otp_debug_blk6_w5_reg_t blk6_w5; + volatile otp_debug_blk6_w6_reg_t blk6_w6; + volatile otp_debug_blk6_w7_reg_t blk6_w7; + volatile otp_debug_blk6_w8_reg_t blk6_w8; + volatile otp_debug_blk6_w9_reg_t blk6_w9; + volatile otp_debug_blk6_w10_reg_t blk6_w10; + volatile otp_debug_blk6_w11_reg_t blk6_w11; + volatile otp_debug_blk7_w1_reg_t blk7_w1; + volatile otp_debug_blk7_w2_reg_t blk7_w2; + volatile otp_debug_blk7_w3_reg_t blk7_w3; + volatile otp_debug_blk7_w4_reg_t blk7_w4; + volatile otp_debug_blk7_w5_reg_t blk7_w5; + volatile otp_debug_blk7_w6_reg_t blk7_w6; + volatile otp_debug_blk7_w7_reg_t blk7_w7; + volatile otp_debug_blk7_w8_reg_t blk7_w8; + volatile otp_debug_blk7_w9_reg_t blk7_w9; + volatile otp_debug_blk7_w10_reg_t blk7_w10; + volatile otp_debug_blk7_w11_reg_t blk7_w11; + volatile otp_debug_blk8_w1_reg_t blk8_w1; + volatile otp_debug_blk8_w2_reg_t blk8_w2; + volatile otp_debug_blk8_w3_reg_t blk8_w3; + volatile otp_debug_blk8_w4_reg_t blk8_w4; + volatile otp_debug_blk8_w5_reg_t blk8_w5; + volatile otp_debug_blk8_w6_reg_t blk8_w6; + volatile otp_debug_blk8_w7_reg_t blk8_w7; + volatile otp_debug_blk8_w8_reg_t blk8_w8; + volatile otp_debug_blk8_w9_reg_t blk8_w9; + volatile otp_debug_blk8_w10_reg_t blk8_w10; + volatile otp_debug_blk8_w11_reg_t blk8_w11; + volatile otp_debug_blk9_w1_reg_t blk9_w1; + volatile otp_debug_blk9_w2_reg_t blk9_w2; + volatile otp_debug_blk9_w3_reg_t blk9_w3; + volatile otp_debug_blk9_w4_reg_t blk9_w4; + volatile otp_debug_blk9_w5_reg_t blk9_w5; + volatile otp_debug_blk9_w6_reg_t blk9_w6; + volatile otp_debug_blk9_w7_reg_t blk9_w7; + volatile otp_debug_blk9_w8_reg_t blk9_w8; + volatile otp_debug_blk9_w9_reg_t blk9_w9; + volatile otp_debug_blk9_w10_reg_t blk9_w10; + volatile otp_debug_blk9_w11_reg_t blk9_w11; + volatile otp_debug_blk10_w1_reg_t blk10_w1; + volatile otp_debug_blk10_w2_reg_t blk10_w2; + volatile otp_debug_blk10_w3_reg_t blk10_w3; + volatile otp_debug_blk10_w4_reg_t blk10_w4; + volatile otp_debug_blk10_w5_reg_t blk10_w5; + volatile otp_debug_blk10_w6_reg_t blk10_w6; + volatile otp_debug_blk10_w7_reg_t blk10_w7; + volatile otp_debug_blk10_w8_reg_t blk10_w8; + volatile otp_debug_blk10_w9_reg_t blk10_w9; + volatile otp_debug_blk10_w10_reg_t blk10_w10; + volatile otp_debug_blk10_w11_reg_t blk10_w11; + volatile otp_debug_clk_reg_t clk; + volatile otp_debug_apb2otp_en_reg_t apb2otp_en; + volatile otp_debug_date_reg_t date; +} otp_debug_dev_t; + +extern otp_debug_dev_t OTP_DEBUG; + +#ifndef __cplusplus +_Static_assert(sizeof(otp_debug_dev_t) == 0x210, "Invalid size of otp_debug_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pau_reg.h b/components/soc/esp32c5/include/soc/pau_reg.h new file mode 100644 index 0000000000..207f797c02 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pau_reg.h @@ -0,0 +1,332 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PAU_REGDMA_CONF_REG register + * Peri backup control register + */ +#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0) +/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0; + * backup error type + */ +#define PAU_FLOW_ERR 0x00000007U +#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S) +#define PAU_FLOW_ERR_V 0x00000007U +#define PAU_FLOW_ERR_S 0 +/** PAU_START : WT; bitpos: [3]; default: 0; + * backup start signal + */ +#define PAU_START (BIT(3)) +#define PAU_START_M (PAU_START_V << PAU_START_S) +#define PAU_START_V 0x00000001U +#define PAU_START_S 3 +/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM (BIT(4)) +#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S) +#define PAU_TO_MEM_V 0x00000001U +#define PAU_TO_MEM_S 4 +/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0; + * Link select + */ +#define PAU_LINK_SEL 0x00000003U +#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S) +#define PAU_LINK_SEL_V 0x00000003U +#define PAU_LINK_SEL_S 5 +/** PAU_START_MAC : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ +#define PAU_START_MAC (BIT(7)) +#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S) +#define PAU_START_MAC_V 0x00000001U +#define PAU_START_MAC_S 7 +/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM_MAC (BIT(8)) +#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S) +#define PAU_TO_MEM_MAC_V 0x00000001U +#define PAU_TO_MEM_MAC_S 8 +/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ +#define PAU_SEL_MAC (BIT(9)) +#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S) +#define PAU_SEL_MAC_V 0x00000001U +#define PAU_SEL_MAC_S 9 + +/** PAU_REGDMA_CLK_CONF_REG register + * Clock control register + */ +#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4) +/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0; + * clock enable + */ +#define PAU_CLK_EN (BIT(0)) +#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S) +#define PAU_CLK_EN_V 0x00000001U +#define PAU_CLK_EN_S 0 + +/** PAU_REGDMA_ETM_CTRL_REG register + * ETM start ctrl reg + */ +#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8) +/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ +#define PAU_ETM_START_0 (BIT(0)) +#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S) +#define PAU_ETM_START_0_V 0x00000001U +#define PAU_ETM_START_0_S 0 +/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ +#define PAU_ETM_START_1 (BIT(1)) +#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S) +#define PAU_ETM_START_1_V 0x00000001U +#define PAU_ETM_START_1_S 1 +/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ +#define PAU_ETM_START_2 (BIT(2)) +#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S) +#define PAU_ETM_START_2_V 0x00000001U +#define PAU_ETM_START_2_S 2 +/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ +#define PAU_ETM_START_3 (BIT(3)) +#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S) +#define PAU_ETM_START_3_V 0x00000001U +#define PAU_ETM_START_3_S 3 + +/** PAU_REGDMA_LINK_0_ADDR_REG register + * link_0_addr + */ +#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc) +/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ +#define PAU_LINK_ADDR_0 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S) +#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_S 0 + +/** PAU_REGDMA_LINK_1_ADDR_REG register + * Link_1_addr + */ +#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10) +/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ +#define PAU_LINK_ADDR_1 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S) +#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_S 0 + +/** PAU_REGDMA_LINK_2_ADDR_REG register + * Link_2_addr + */ +#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14) +/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ +#define PAU_LINK_ADDR_2 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S) +#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_S 0 + +/** PAU_REGDMA_LINK_3_ADDR_REG register + * Link_3_addr + */ +#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18) +/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ +#define PAU_LINK_ADDR_3 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S) +#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_S 0 + +/** PAU_REGDMA_LINK_MAC_ADDR_REG register + * Link_mac_addr + */ +#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c) +/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ +#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S) +#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_S 0 + +/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register + * current link addr + */ +#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20) +/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ +#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S) +#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_S 0 + +/** PAU_REGDMA_BACKUP_ADDR_REG register + * Backup addr + */ +#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24) +/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ +#define PAU_BACKUP_ADDR 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S) +#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_S 0 + +/** PAU_REGDMA_MEM_ADDR_REG register + * mem addr + */ +#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28) +/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ +#define PAU_MEM_ADDR 0xFFFFFFFFU +#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S) +#define PAU_MEM_ADDR_V 0xFFFFFFFFU +#define PAU_MEM_ADDR_S 0 + +/** PAU_REGDMA_BKP_CONF_REG register + * backup config + */ +#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c) +/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ +#define PAU_READ_INTERVAL 0x0000007FU +#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S) +#define PAU_READ_INTERVAL_V 0x0000007FU +#define PAU_READ_INTERVAL_S 0 +/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ +#define PAU_LINK_TOUT_THRES 0x000003FFU +#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S) +#define PAU_LINK_TOUT_THRES_V 0x000003FFU +#define PAU_LINK_TOUT_THRES_S 7 +/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ +#define PAU_BURST_LIMIT 0x0000001FU +#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S) +#define PAU_BURST_LIMIT_V 0x0000001FU +#define PAU_BURST_LIMIT_S 17 +/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ +#define PAU_BACKUP_TOUT_THRES 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S) +#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_S 22 + +/** PAU_INT_ENA_REG register + * Read only register for error and done + */ +#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30) +/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ENA (BIT(0)) +#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S) +#define PAU_DONE_INT_ENA_V 0x00000001U +#define PAU_DONE_INT_ENA_S 0 +/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ENA (BIT(1)) +#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S) +#define PAU_ERROR_INT_ENA_V 0x00000001U +#define PAU_ERROR_INT_ENA_S 1 + +/** PAU_INT_RAW_REG register + * Read only register for error and done + */ +#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34) +/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_RAW (BIT(0)) +#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S) +#define PAU_DONE_INT_RAW_V 0x00000001U +#define PAU_DONE_INT_RAW_S 0 +/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_RAW (BIT(1)) +#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S) +#define PAU_ERROR_INT_RAW_V 0x00000001U +#define PAU_ERROR_INT_RAW_S 1 + +/** PAU_INT_CLR_REG register + * Read only register for error and done + */ +#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38) +/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_CLR (BIT(0)) +#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S) +#define PAU_DONE_INT_CLR_V 0x00000001U +#define PAU_DONE_INT_CLR_S 0 +/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_CLR (BIT(1)) +#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S) +#define PAU_ERROR_INT_CLR_V 0x00000001U +#define PAU_ERROR_INT_CLR_S 1 + +/** PAU_INT_ST_REG register + * Read only register for error and done + */ +#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c) +/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ST (BIT(0)) +#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S) +#define PAU_DONE_INT_ST_V 0x00000001U +#define PAU_DONE_INT_ST_S 0 +/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ST (BIT(1)) +#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S) +#define PAU_ERROR_INT_ST_V 0x00000001U +#define PAU_ERROR_INT_ST_S 1 + +/** PAU_DATE_REG register + * Date register. + */ +#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc) +/** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608; + * REGDMA date information/ REGDMA version information. + */ +#define PAU_DATE 0x0FFFFFFFU +#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S) +#define PAU_DATE_V 0x0FFFFFFFU +#define PAU_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pau_struct.h b/components/soc/esp32c5/include/soc/pau_struct.h new file mode 100644 index 0000000000..4328a02144 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pau_struct.h @@ -0,0 +1,339 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of regdma_conf register + * Peri backup control register + */ +typedef union { + struct { + /** flow_err : RO; bitpos: [2:0]; default: 0; + * backup error type + */ + uint32_t flow_err:3; + /** start : WT; bitpos: [3]; default: 0; + * backup start signal + */ + uint32_t start:1; + /** to_mem : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem:1; + /** link_sel : R/W; bitpos: [6:5]; default: 0; + * Link select + */ + uint32_t link_sel:2; + /** start_mac : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ + uint32_t start_mac:1; + /** to_mem_mac : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem_mac:1; + /** sel_mac : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ + uint32_t sel_mac:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} pau_regdma_conf_reg_t; + +/** Type of regdma_clk_conf register + * Clock control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * clock enable + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pau_regdma_clk_conf_reg_t; + +/** Type of regdma_etm_ctrl register + * ETM start ctrl reg + */ +typedef union { + struct { + /** etm_start_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ + uint32_t etm_start_0:1; + /** etm_start_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ + uint32_t etm_start_1:1; + /** etm_start_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ + uint32_t etm_start_2:1; + /** etm_start_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ + uint32_t etm_start_3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pau_regdma_etm_ctrl_reg_t; + +/** Type of regdma_link_0_addr register + * link_0_addr + */ +typedef union { + struct { + /** link_addr_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ + uint32_t link_addr_0:32; + }; + uint32_t val; +} pau_regdma_link_0_addr_reg_t; + +/** Type of regdma_link_1_addr register + * Link_1_addr + */ +typedef union { + struct { + /** link_addr_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ + uint32_t link_addr_1:32; + }; + uint32_t val; +} pau_regdma_link_1_addr_reg_t; + +/** Type of regdma_link_2_addr register + * Link_2_addr + */ +typedef union { + struct { + /** link_addr_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ + uint32_t link_addr_2:32; + }; + uint32_t val; +} pau_regdma_link_2_addr_reg_t; + +/** Type of regdma_link_3_addr register + * Link_3_addr + */ +typedef union { + struct { + /** link_addr_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ + uint32_t link_addr_3:32; + }; + uint32_t val; +} pau_regdma_link_3_addr_reg_t; + +/** Type of regdma_link_mac_addr register + * Link_mac_addr + */ +typedef union { + struct { + /** link_addr_mac : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ + uint32_t link_addr_mac:32; + }; + uint32_t val; +} pau_regdma_link_mac_addr_reg_t; + +/** Type of regdma_current_link_addr register + * current link addr + */ +typedef union { + struct { + /** current_link_addr : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ + uint32_t current_link_addr:32; + }; + uint32_t val; +} pau_regdma_current_link_addr_reg_t; + +/** Type of regdma_backup_addr register + * Backup addr + */ +typedef union { + struct { + /** backup_addr : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ + uint32_t backup_addr:32; + }; + uint32_t val; +} pau_regdma_backup_addr_reg_t; + +/** Type of regdma_mem_addr register + * mem addr + */ +typedef union { + struct { + /** mem_addr : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ + uint32_t mem_addr:32; + }; + uint32_t val; +} pau_regdma_mem_addr_reg_t; + +/** Type of regdma_bkp_conf register + * backup config + */ +typedef union { + struct { + /** read_interval : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ + uint32_t read_interval:7; + /** link_tout_thres : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ + uint32_t link_tout_thres:10; + /** burst_limit : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ + uint32_t burst_limit:5; + /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ + uint32_t backup_tout_thres:10; + }; + uint32_t val; +} pau_regdma_bkp_conf_reg_t; + +/** Type of int_ena register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_ena:1; + /** error_int_ena : R/W; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_ena_reg_t; + +/** Type of int_raw register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_raw:1; + /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_raw_reg_t; + +/** Type of int_clr register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_clr : WT; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_clr:1; + /** error_int_clr : WT; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_clr_reg_t; + +/** Type of int_st register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_st : RO; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_st:1; + /** error_int_st : RO; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_st_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36708608; + * REGDMA date information/ REGDMA version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pau_date_reg_t; + + +typedef struct { + volatile pau_regdma_conf_reg_t regdma_conf; + volatile pau_regdma_clk_conf_reg_t regdma_clk_conf; + volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl; + volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr; + volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr; + volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr; + volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr; + volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr; + volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr; + volatile pau_regdma_backup_addr_reg_t regdma_backup_addr; + volatile pau_regdma_mem_addr_reg_t regdma_mem_addr; + volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf; + volatile pau_int_ena_reg_t int_ena; + volatile pau_int_raw_reg_t int_raw; + volatile pau_int_clr_reg_t int_clr; + volatile pau_int_st_reg_t int_st; + uint32_t reserved_040[239]; + volatile pau_date_reg_t date; +} pau_dev_t; + +extern pau_dev_t PAU; + +#ifndef __cplusplus +_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pcnt_reg.h b/components/soc/esp32c5/include/soc/pcnt_reg.h new file mode 100644 index 0000000000..7cbfedda60 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pcnt_reg.h @@ -0,0 +1,1346 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCNT_U0_CONF0_REG register + * Configuration register 0 for unit 0 + */ +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0) +/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U0 0x000003FFU +#define PCNT_FILTER_THRES_U0_M (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S) +#define PCNT_FILTER_THRES_U0_V 0x000003FFU +#define PCNT_FILTER_THRES_U0_S 0 +/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 0's input filter. + */ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S) +#define PCNT_FILTER_EN_U0_V 0x00000001U +#define PCNT_FILTER_EN_U0_S 10 +/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 0's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S) +#define PCNT_THR_ZERO_EN_U0_V 0x00000001U +#define PCNT_THR_ZERO_EN_U0_S 11 +/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 0's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S) +#define PCNT_THR_H_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U0_S 12 +/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 0's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S) +#define PCNT_THR_L_LIM_EN_U0_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U0_S 13 +/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 0's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S) +#define PCNT_THR_THRES0_EN_U0_V 0x00000001U +#define PCNT_THR_THRES0_EN_U0_S 14 +/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 0's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S) +#define PCNT_THR_THRES1_EN_U0_V 0x00000001U +#define PCNT_THR_THRES1_EN_U0_S 15 +/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U0 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_M (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S) +#define PCNT_CH0_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U0_S 16 +/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U0 0x00000003U +#define PCNT_CH0_POS_MODE_U0_M (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S) +#define PCNT_CH0_POS_MODE_U0_V 0x00000003U +#define PCNT_CH0_POS_MODE_U0_S 18 +/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_M (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_M (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U0 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_M (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S) +#define PCNT_CH1_NEG_MODE_U0_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U0_S 24 +/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U0 0x00000003U +#define PCNT_CH1_POS_MODE_U0_M (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S) +#define PCNT_CH1_POS_MODE_U0_V 0x00000003U +#define PCNT_CH1_POS_MODE_U0_S 26 +/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_M (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_M (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U0_S 30 + +/** PCNT_U0_CONF1_REG register + * Configuration register 1 for unit 0 + */ +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4) +/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 0. + */ +#define PCNT_CNT_THRES0_U0 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_M (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S) +#define PCNT_CNT_THRES0_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U0_S 0 +/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 0. + */ +#define PCNT_CNT_THRES1_U0 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_M (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S) +#define PCNT_CNT_THRES1_U0_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U0_S 16 + +/** PCNT_U0_CONF2_REG register + * Configuration register 2 for unit 0 + */ +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8) +/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 0. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U0 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_M (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S) +#define PCNT_CNT_H_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U0_S 0 +/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 0. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U0 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_M (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S) +#define PCNT_CNT_L_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U0_S 16 + +/** PCNT_U1_CONF0_REG register + * Configuration register 0 for unit 1 + */ +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc) +/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U1 0x000003FFU +#define PCNT_FILTER_THRES_U1_M (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S) +#define PCNT_FILTER_THRES_U1_V 0x000003FFU +#define PCNT_FILTER_THRES_U1_S 0 +/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 1's input filter. + */ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S) +#define PCNT_FILTER_EN_U1_V 0x00000001U +#define PCNT_FILTER_EN_U1_S 10 +/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 1's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S) +#define PCNT_THR_ZERO_EN_U1_V 0x00000001U +#define PCNT_THR_ZERO_EN_U1_S 11 +/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 1's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S) +#define PCNT_THR_H_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U1_S 12 +/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 1's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S) +#define PCNT_THR_L_LIM_EN_U1_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U1_S 13 +/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 1's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S) +#define PCNT_THR_THRES0_EN_U1_V 0x00000001U +#define PCNT_THR_THRES0_EN_U1_S 14 +/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 1's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S) +#define PCNT_THR_THRES1_EN_U1_V 0x00000001U +#define PCNT_THR_THRES1_EN_U1_S 15 +/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U1 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_M (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S) +#define PCNT_CH0_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U1_S 16 +/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U1 0x00000003U +#define PCNT_CH0_POS_MODE_U1_M (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S) +#define PCNT_CH0_POS_MODE_U1_V 0x00000003U +#define PCNT_CH0_POS_MODE_U1_S 18 +/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_M (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_M (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U1 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_M (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S) +#define PCNT_CH1_NEG_MODE_U1_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U1_S 24 +/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U1 0x00000003U +#define PCNT_CH1_POS_MODE_U1_M (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S) +#define PCNT_CH1_POS_MODE_U1_V 0x00000003U +#define PCNT_CH1_POS_MODE_U1_S 26 +/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_M (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_M (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U1_S 30 + +/** PCNT_U1_CONF1_REG register + * Configuration register 1 for unit 1 + */ +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10) +/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 1. + */ +#define PCNT_CNT_THRES0_U1 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_M (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S) +#define PCNT_CNT_THRES0_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U1_S 0 +/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 1. + */ +#define PCNT_CNT_THRES1_U1 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_M (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S) +#define PCNT_CNT_THRES1_U1_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U1_S 16 + +/** PCNT_U1_CONF2_REG register + * Configuration register 2 for unit 1 + */ +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14) +/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 1. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U1 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_M (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S) +#define PCNT_CNT_H_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U1_S 0 +/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 1. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U1 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_M (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S) +#define PCNT_CNT_L_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U1_S 16 + +/** PCNT_U2_CONF0_REG register + * Configuration register 0 for unit 2 + */ +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18) +/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U2 0x000003FFU +#define PCNT_FILTER_THRES_U2_M (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S) +#define PCNT_FILTER_THRES_U2_V 0x000003FFU +#define PCNT_FILTER_THRES_U2_S 0 +/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 2's input filter. + */ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S) +#define PCNT_FILTER_EN_U2_V 0x00000001U +#define PCNT_FILTER_EN_U2_S 10 +/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 2's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S) +#define PCNT_THR_ZERO_EN_U2_V 0x00000001U +#define PCNT_THR_ZERO_EN_U2_S 11 +/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 2's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S) +#define PCNT_THR_H_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U2_S 12 +/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 2's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S) +#define PCNT_THR_L_LIM_EN_U2_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U2_S 13 +/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 2's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S) +#define PCNT_THR_THRES0_EN_U2_V 0x00000001U +#define PCNT_THR_THRES0_EN_U2_S 14 +/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 2's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S) +#define PCNT_THR_THRES1_EN_U2_V 0x00000001U +#define PCNT_THR_THRES1_EN_U2_S 15 +/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U2 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_M (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S) +#define PCNT_CH0_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U2_S 16 +/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U2 0x00000003U +#define PCNT_CH0_POS_MODE_U2_M (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S) +#define PCNT_CH0_POS_MODE_U2_V 0x00000003U +#define PCNT_CH0_POS_MODE_U2_S 18 +/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_M (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_M (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U2 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_M (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S) +#define PCNT_CH1_NEG_MODE_U2_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U2_S 24 +/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U2 0x00000003U +#define PCNT_CH1_POS_MODE_U2_M (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S) +#define PCNT_CH1_POS_MODE_U2_V 0x00000003U +#define PCNT_CH1_POS_MODE_U2_S 26 +/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_M (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_M (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U2_S 30 + +/** PCNT_U2_CONF1_REG register + * Configuration register 1 for unit 2 + */ +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c) +/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 2. + */ +#define PCNT_CNT_THRES0_U2 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_M (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S) +#define PCNT_CNT_THRES0_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U2_S 0 +/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 2. + */ +#define PCNT_CNT_THRES1_U2 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_M (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S) +#define PCNT_CNT_THRES1_U2_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U2_S 16 + +/** PCNT_U2_CONF2_REG register + * Configuration register 2 for unit 2 + */ +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20) +/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 2. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U2 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_M (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S) +#define PCNT_CNT_H_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U2_S 0 +/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 2. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U2 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_M (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S) +#define PCNT_CNT_L_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U2_S 16 + +/** PCNT_U3_CONF0_REG register + * Configuration register 0 for unit 3 + */ +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24) +/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ +#define PCNT_FILTER_THRES_U3 0x000003FFU +#define PCNT_FILTER_THRES_U3_M (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S) +#define PCNT_FILTER_THRES_U3_V 0x000003FFU +#define PCNT_FILTER_THRES_U3_S 0 +/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit 3's input filter. + */ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S) +#define PCNT_FILTER_EN_U3_V 0x00000001U +#define PCNT_FILTER_EN_U3_S 10 +/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit 3's zero comparator. + */ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S) +#define PCNT_THR_ZERO_EN_U3_V 0x00000001U +#define PCNT_THR_ZERO_EN_U3_S 11 +/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit 3's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S) +#define PCNT_THR_H_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_H_LIM_EN_U3_S 12 +/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit 3's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S) +#define PCNT_THR_L_LIM_EN_U3_V 0x00000001U +#define PCNT_THR_L_LIM_EN_U3_S 13 +/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit 3's thres0 comparator. + */ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S) +#define PCNT_THR_THRES0_EN_U3_V 0x00000001U +#define PCNT_THR_THRES0_EN_U3_S 14 +/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit 3's thres1 comparator. + */ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S) +#define PCNT_THR_THRES1_EN_U3_V 0x00000001U +#define PCNT_THR_THRES1_EN_U3_S 15 +/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_NEG_MODE_U3 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_M (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S) +#define PCNT_CH0_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH0_NEG_MODE_U3_S 16 +/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ +#define PCNT_CH0_POS_MODE_U3 0x00000003U +#define PCNT_CH0_POS_MODE_U3_M (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S) +#define PCNT_CH0_POS_MODE_U3_V 0x00000003U +#define PCNT_CH0_POS_MODE_U3_S 18 +/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_M (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_M (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_NEG_MODE_U3 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_M (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S) +#define PCNT_CH1_NEG_MODE_U3_V 0x00000003U +#define PCNT_CH1_NEG_MODE_U3_S 24 +/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ +#define PCNT_CH1_POS_MODE_U3 0x00000003U +#define PCNT_CH1_POS_MODE_U3_M (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S) +#define PCNT_CH1_POS_MODE_U3_V 0x00000003U +#define PCNT_CH1_POS_MODE_U3_S 26 +/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_M (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_M (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x00000003U +#define PCNT_CH1_LCTRL_MODE_U3_S 30 + +/** PCNT_U3_CONF1_REG register + * Configuration register 1 for unit 3 + */ +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28) +/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit 3. + */ +#define PCNT_CNT_THRES0_U3 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_M (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S) +#define PCNT_CNT_THRES0_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES0_U3_S 0 +/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit 3. + */ +#define PCNT_CNT_THRES1_U3 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_M (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S) +#define PCNT_CNT_THRES1_U3_V 0x0000FFFFU +#define PCNT_CNT_THRES1_U3_S 16 + +/** PCNT_U3_CONF2_REG register + * Configuration register 2 for unit 3 + */ +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c) +/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit 3. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_H_LIM_U3 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_M (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S) +#define PCNT_CNT_H_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_H_LIM_U3_S 0 +/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit 3. When pcnt + * reaches this value, the counter will be cleared to 0. + */ +#define PCNT_CNT_L_LIM_U3 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_M (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S) +#define PCNT_CNT_L_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_L_LIM_U3_S 16 + +/** PCNT_U0_CNT_REG register + * Counter value for unit 0 + */ +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30) +/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 0. + */ +#define PCNT_PULSE_CNT_U0 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_M (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S) +#define PCNT_PULSE_CNT_U0_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U0_S 0 + +/** PCNT_U1_CNT_REG register + * Counter value for unit 1 + */ +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34) +/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 1. + */ +#define PCNT_PULSE_CNT_U1 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_M (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S) +#define PCNT_PULSE_CNT_U1_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U1_S 0 + +/** PCNT_U2_CNT_REG register + * Counter value for unit 2 + */ +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38) +/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 2. + */ +#define PCNT_PULSE_CNT_U2 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_M (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S) +#define PCNT_PULSE_CNT_U2_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U2_S 0 + +/** PCNT_U3_CNT_REG register + * Counter value for unit 3 + */ +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c) +/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit 3. + */ +#define PCNT_PULSE_CNT_U3 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_M (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S) +#define PCNT_PULSE_CNT_U3_V 0x0000FFFFU +#define PCNT_PULSE_CNT_U3_S 0 + +/** PCNT_INT_RAW_REG register + * Interrupt raw status register + */ +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40) +/** PCNT_CNT_THR_EVENT_U0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 + +/** PCNT_INT_ST_REG register + * Interrupt status register + */ +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44) +/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 + +/** PCNT_INT_ENA_REG register + * Interrupt enable register + */ +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48) +/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 + +/** PCNT_INT_CLR_REG register + * Interrupt clear register + */ +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c) +/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 +/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x00000001U +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 + +/** PCNT_U0_STATUS_REG register + * PNCT UNIT0 status register + */ +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50) +/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_M (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S) +#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_M (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S) +#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_M (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S) +#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_M (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S) +#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U0 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_M (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S) +#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U0 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_M (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S) +#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 + +/** PCNT_U1_STATUS_REG register + * PNCT UNIT1 status register + */ +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54) +/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_M (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S) +#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_M (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S) +#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_M (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S) +#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_M (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S) +#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U1 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_M (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S) +#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U1 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_M (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S) +#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 + +/** PCNT_U2_STATUS_REG register + * PNCT UNIT2 status register + */ +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58) +/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_M (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S) +#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_M (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S) +#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_M (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S) +#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_M (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S) +#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U2 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_M (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S) +#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U2 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_M (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S) +#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 + +/** PCNT_U3_STATUS_REG register + * PNCT UNIT3 status register + */ +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c) +/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ +#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_M (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S) +#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x00000003U +#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 +/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_M (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S) +#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 +/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ +#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_M (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S) +#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 +/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_M (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S) +#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 +/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_U3 when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ +#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_M (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S) +#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 +/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_U3 when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ +#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_M (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S) +#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x00000001U +#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 + +/** PCNT_CTRL_REG register + * Control register for all counters + */ +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60) +/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ +#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_M (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S) +#define PCNT_PULSE_CNT_RST_U0_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U0_S 0 +/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S) +#define PCNT_CNT_PAUSE_U0_V 0x00000001U +#define PCNT_CNT_PAUSE_U0_S 1 +/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ +#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_M (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S) +#define PCNT_PULSE_CNT_RST_U1_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U1_S 2 +/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S) +#define PCNT_CNT_PAUSE_U1_V 0x00000001U +#define PCNT_CNT_PAUSE_U1_S 3 +/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ +#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_M (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S) +#define PCNT_PULSE_CNT_RST_U2_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U2_S 4 +/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S) +#define PCNT_CNT_PAUSE_U2_V 0x00000001U +#define PCNT_CNT_PAUSE_U2_S 5 +/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ +#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_M (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S) +#define PCNT_PULSE_CNT_RST_U3_V 0x00000001U +#define PCNT_PULSE_CNT_RST_U3_S 6 +/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S) +#define PCNT_CNT_PAUSE_U3_V 0x00000001U +#define PCNT_CNT_PAUSE_U3_S 7 +/** PCNT_DALTA_CHANGE_EN_U0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U0 (BIT(8)) +#define PCNT_DALTA_CHANGE_EN_U0_M (PCNT_DALTA_CHANGE_EN_U0_V << PCNT_DALTA_CHANGE_EN_U0_S) +#define PCNT_DALTA_CHANGE_EN_U0_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U0_S 8 +/** PCNT_DALTA_CHANGE_EN_U1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U1 (BIT(9)) +#define PCNT_DALTA_CHANGE_EN_U1_M (PCNT_DALTA_CHANGE_EN_U1_V << PCNT_DALTA_CHANGE_EN_U1_S) +#define PCNT_DALTA_CHANGE_EN_U1_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U1_S 9 +/** PCNT_DALTA_CHANGE_EN_U2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U2 (BIT(10)) +#define PCNT_DALTA_CHANGE_EN_U2_M (PCNT_DALTA_CHANGE_EN_U2_V << PCNT_DALTA_CHANGE_EN_U2_S) +#define PCNT_DALTA_CHANGE_EN_U2_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U2_S 10 +/** PCNT_DALTA_CHANGE_EN_U3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ +#define PCNT_DALTA_CHANGE_EN_U3 (BIT(11)) +#define PCNT_DALTA_CHANGE_EN_U3_M (PCNT_DALTA_CHANGE_EN_U3_V << PCNT_DALTA_CHANGE_EN_U3_S) +#define PCNT_DALTA_CHANGE_EN_U3_V 0x00000001U +#define PCNT_DALTA_CHANGE_EN_U3_S 11 +/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (PCNT_CLK_EN_V << PCNT_CLK_EN_S) +#define PCNT_CLK_EN_V 0x00000001U +#define PCNT_CLK_EN_S 16 + +/** PCNT_U3_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U3_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x64) +/** PCNT_CNT_STEP_U3 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 3. + */ +#define PCNT_CNT_STEP_U3 0x0000FFFFU +#define PCNT_CNT_STEP_U3_M (PCNT_CNT_STEP_U3_V << PCNT_CNT_STEP_U3_S) +#define PCNT_CNT_STEP_U3_V 0x0000FFFFU +#define PCNT_CNT_STEP_U3_S 0 +/** PCNT_CNT_STEP_LIM_U3 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 3. + */ +#define PCNT_CNT_STEP_LIM_U3 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U3_M (PCNT_CNT_STEP_LIM_U3_V << PCNT_CNT_STEP_LIM_U3_S) +#define PCNT_CNT_STEP_LIM_U3_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U3_S 16 + +/** PCNT_U2_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U2_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x68) +/** PCNT_CNT_STEP_U2 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 2. + */ +#define PCNT_CNT_STEP_U2 0x0000FFFFU +#define PCNT_CNT_STEP_U2_M (PCNT_CNT_STEP_U2_V << PCNT_CNT_STEP_U2_S) +#define PCNT_CNT_STEP_U2_V 0x0000FFFFU +#define PCNT_CNT_STEP_U2_S 0 +/** PCNT_CNT_STEP_LIM_U2 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 2. + */ +#define PCNT_CNT_STEP_LIM_U2 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U2_M (PCNT_CNT_STEP_LIM_U2_V << PCNT_CNT_STEP_LIM_U2_S) +#define PCNT_CNT_STEP_LIM_U2_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U2_S 16 + +/** PCNT_U1_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U1_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x6c) +/** PCNT_CNT_STEP_U1 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 1. + */ +#define PCNT_CNT_STEP_U1 0x0000FFFFU +#define PCNT_CNT_STEP_U1_M (PCNT_CNT_STEP_U1_V << PCNT_CNT_STEP_U1_S) +#define PCNT_CNT_STEP_U1_V 0x0000FFFFU +#define PCNT_CNT_STEP_U1_S 0 +/** PCNT_CNT_STEP_LIM_U1 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 1. + */ +#define PCNT_CNT_STEP_LIM_U1 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U1_M (PCNT_CNT_STEP_LIM_U1_V << PCNT_CNT_STEP_LIM_U1_S) +#define PCNT_CNT_STEP_LIM_U1_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U1_S 16 + +/** PCNT_U0_CHANGE_CONF_REG register + * Configuration register for unit $n's step value. + */ +#define PCNT_U0_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x70) +/** PCNT_CNT_STEP_U0 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 0. + */ +#define PCNT_CNT_STEP_U0 0x0000FFFFU +#define PCNT_CNT_STEP_U0_M (PCNT_CNT_STEP_U0_V << PCNT_CNT_STEP_U0_S) +#define PCNT_CNT_STEP_U0_V 0x0000FFFFU +#define PCNT_CNT_STEP_U0_S 0 +/** PCNT_CNT_STEP_LIM_U0 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 0. + */ +#define PCNT_CNT_STEP_LIM_U0 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U0_M (PCNT_CNT_STEP_LIM_U0_V << PCNT_CNT_STEP_LIM_U0_S) +#define PCNT_CNT_STEP_LIM_U0_V 0x0000FFFFU +#define PCNT_CNT_STEP_LIM_U0_S 16 + +/** PCNT_DATE_REG register + * PCNT version control register + */ +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc) +/** PCNT_DATE : R/W; bitpos: [31:0]; default: 571021568; + * This is the PCNT version control register. + */ +#define PCNT_DATE 0xFFFFFFFFU +#define PCNT_DATE_M (PCNT_DATE_V << PCNT_DATE_S) +#define PCNT_DATE_V 0xFFFFFFFFU +#define PCNT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pcnt_struct.h b/components/soc/esp32c5/include/soc/pcnt_struct.h new file mode 100644 index 0000000000..abfee16732 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pcnt_struct.h @@ -0,0 +1,504 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of un_conf0 register + * Configuration register 0 for unit n + */ +typedef union { + struct { + /** filter_thres_un : R/W; bitpos: [9:0]; default: 16; + * This sets the maximum threshold, in APB_CLK cycles, for the filter. + * + * Any pulses with width less than this will be ignored when the filter is enabled. + */ + uint32_t filter_thres_un:10; + /** filter_en_un : R/W; bitpos: [10]; default: 1; + * This is the enable bit for unit n's input filter. + */ + uint32_t filter_en_un:1; + /** thr_zero_en_un : R/W; bitpos: [11]; default: 1; + * This is the enable bit for unit n's zero comparator. + */ + uint32_t thr_zero_en_un:1; + /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1; + * This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable + * the high limit interrupt. + */ + uint32_t thr_h_lim_en_un:1; + /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1; + * This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable + * the low limit interrupt. + */ + uint32_t thr_l_lim_en_un:1; + /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0; + * This is the enable bit for unit n's thres0 comparator. + */ + uint32_t thr_thres0_en_un:1; + /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0; + * This is the enable bit for unit n's thres1 comparator. + */ + uint32_t thr_thres1_en_un:1; + /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * negative edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_neg_mode_un:2; + /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0; + * This register sets the behavior when the signal input of channel 0 detects a + * positive edge. + * + * 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + */ + uint32_t ch0_pos_mode_un:2; + /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_hctrl_mode_un:2; + /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch0_lctrl_mode_un:2; + /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * negative edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_neg_mode_un:2; + /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0; + * This register sets the behavior when the signal input of channel 1 detects a + * positive edge. + * + * 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + */ + uint32_t ch1_pos_mode_un:2; + /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is high. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_hctrl_mode_un:2; + /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0; + * This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be + * modified when the control signal is low. + * + * 0: No modification.1: Invert behavior (increase -> decrease, decrease -> + * increase).2, 3: Inhibit counter modification + */ + uint32_t ch1_lctrl_mode_un:2; + }; + uint32_t val; +} pcnt_un_conf0_reg_t; + +/** Type of un_conf1 register + * Configuration register 1 for unit n + */ +typedef union { + struct { + /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thres0 value for unit n. + */ + uint32_t cnt_thres0_un:16; + /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thres1 value for unit n. + */ + uint32_t cnt_thres1_un:16; + }; + uint32_t val; +} pcnt_un_conf1_reg_t; + +/** Type of un_conf2 register + * Configuration register 2 for unit n + */ +typedef union { + struct { + /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0; + * This register is used to configure the thr_h_lim value for unit n. When pcnt + * reaches this value, the counter will be cleared to 0. + */ + uint32_t cnt_h_lim_un:16; + /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0; + * This register is used to configure the thr_l_lim value for unit n. When pcnt + * reaches this value, the counter will be cleared to 0. + */ + uint32_t cnt_l_lim_un:16; + }; + uint32_t val; +} pcnt_un_conf2_reg_t; + +/** Type of ctrl register + * Control register for all counters + */ +typedef union { + struct { + /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1; + * Set this bit to clear unit 0's counter. + */ + uint32_t pulse_cnt_rst_u0:1; + /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0; + * Set this bit to freeze unit 0's counter. + */ + uint32_t cnt_pause_u0:1; + /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1; + * Set this bit to clear unit 1's counter. + */ + uint32_t pulse_cnt_rst_u1:1; + /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0; + * Set this bit to freeze unit 1's counter. + */ + uint32_t cnt_pause_u1:1; + /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1; + * Set this bit to clear unit 2's counter. + */ + uint32_t pulse_cnt_rst_u2:1; + /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0; + * Set this bit to freeze unit 2's counter. + */ + uint32_t cnt_pause_u2:1; + /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1; + * Set this bit to clear unit 3's counter. + */ + uint32_t pulse_cnt_rst_u3:1; + /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0; + * Set this bit to freeze unit 3's counter. + */ + uint32_t cnt_pause_u3:1; + /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ + uint32_t dalta_change_en_u0:1; + /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ + uint32_t dalta_change_en_u1:1; + /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ + uint32_t dalta_change_en_u2:1; + /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ + uint32_t dalta_change_en_u3:1; + uint32_t reserved_12:4; + /** clk_en : R/W; bitpos: [16]; default: 0; + * The registers clock gate enable signal of PCNT module. 1: the registers can be read + * and written by application. 0: the registers can not be read or written by + * application + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} pcnt_ctrl_reg_t; + +/** Type of u3_change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 3. + */ + uint32_t cnt_step_u3:16; + /** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 3. + */ + uint32_t cnt_step_lim_u3:16; + }; + uint32_t val; +} pcnt_u3_change_conf_reg_t; + +/** Type of u2_change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 2. + */ + uint32_t cnt_step_u2:16; + /** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 2. + */ + uint32_t cnt_step_lim_u2:16; + }; + uint32_t val; +} pcnt_u2_change_conf_reg_t; + +/** Type of u1_change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 1. + */ + uint32_t cnt_step_u1:16; + /** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 1. + */ + uint32_t cnt_step_lim_u1:16; + }; + uint32_t val; +} pcnt_u1_change_conf_reg_t; + +/** Type of u0_change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit 0. + */ + uint32_t cnt_step_u0:16; + /** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit 0. + */ + uint32_t cnt_step_lim_u0:16; + }; + uint32_t val; +} pcnt_u0_change_conf_reg_t; + + +/** Group: Status Register */ +/** Type of un_cnt register + * Counter value for unit n + */ +typedef union { + struct { + /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0; + * This register stores the current pulse count value for unit n. + */ + uint32_t pulse_cnt_un:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcnt_un_cnt_reg_t; + +/** Type of un_status register + * PNCT UNITn status register + */ +typedef union { + struct { + /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0; + * The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases + * from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter + * is negative. 3: pulse counter is positive. + */ + uint32_t cnt_thr_zero_mode_un:2; + /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0; + * The latched value of thres1 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres1_lat_un:1; + /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0; + * The latched value of thres0 event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: + * others + */ + uint32_t cnt_thr_thres0_lat_un:1; + /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0; + * The latched value of low limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_l_lim and low limit event is + * valid. 0: others + */ + uint32_t cnt_thr_l_lim_lat_un:1; + /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0; + * The latched value of high limit event of PCNT_Un when threshold event interrupt is + * valid. 1: the current pulse counter equals to thr_h_lim and high limit event is + * valid. 0: others + */ + uint32_t cnt_thr_h_lim_lat_un:1; + /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0; + * The latched value of zero threshold event of PCNT_Un when threshold event interrupt + * is valid. 1: the current pulse counter equals to 0 and zero threshold event is + * valid. 0: others + */ + uint32_t cnt_thr_zero_lat_un:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} pcnt_un_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_raw:1; + /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_raw:1; + /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_raw:1; + /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_st:1; + /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_st:1; + /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_st:1; + /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_ena:1; + /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_ena:1; + /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_ena:1; + /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + */ + uint32_t cnt_thr_event_u0_int_clr:1; + /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + */ + uint32_t cnt_thr_event_u1_int_clr:1; + /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + */ + uint32_t cnt_thr_event_u2_int_clr:1; + /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + */ + uint32_t cnt_thr_event_u3_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcnt_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * PCNT version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 571021568; + * This is the PCNT version control register. + */ + uint32_t date:32; + }; + uint32_t val; +} pcnt_date_reg_t; + + +typedef struct { + volatile pcnt_un_conf0_reg_t u0_conf0; + volatile pcnt_un_conf1_reg_t u0_conf1; + volatile pcnt_un_conf2_reg_t u0_conf2; + volatile pcnt_un_conf0_reg_t u1_conf0; + volatile pcnt_un_conf1_reg_t u1_conf1; + volatile pcnt_un_conf2_reg_t u1_conf2; + volatile pcnt_un_conf0_reg_t u2_conf0; + volatile pcnt_un_conf1_reg_t u2_conf1; + volatile pcnt_un_conf2_reg_t u2_conf2; + volatile pcnt_un_conf0_reg_t u3_conf0; + volatile pcnt_un_conf1_reg_t u3_conf1; + volatile pcnt_un_conf2_reg_t u3_conf2; + volatile pcnt_un_cnt_reg_t un_cnt[4]; + volatile pcnt_int_raw_reg_t int_raw; + volatile pcnt_int_st_reg_t int_st; + volatile pcnt_int_ena_reg_t int_ena; + volatile pcnt_int_clr_reg_t int_clr; + volatile pcnt_un_status_reg_t un_status[4]; + volatile pcnt_ctrl_reg_t ctrl; + volatile pcnt_u3_change_conf_reg_t u3_change_conf; + volatile pcnt_u2_change_conf_reg_t u2_change_conf; + volatile pcnt_u1_change_conf_reg_t u1_change_conf; + volatile pcnt_u0_change_conf_reg_t u0_change_conf; + uint32_t reserved_074[34]; + volatile pcnt_date_reg_t date; +} pcnt_dev_t; + +extern pcnt_dev_t PCNT; + +#ifndef __cplusplus +_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pcr_reg.h b/components/soc/esp32c5/include/soc/pcr_reg.h new file mode 100644 index 0000000000..58cebfed8c --- /dev/null +++ b/components/soc/esp32c5/include/soc/pcr_reg.h @@ -0,0 +1,2462 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PCR_UART0_CONF_REG register + * UART0 configuration register + */ +#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) +/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ +#define PCR_UART0_CLK_EN (BIT(0)) +#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) +#define PCR_UART0_CLK_EN_V 0x00000001U +#define PCR_UART0_CLK_EN_S 0 +/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ +#define PCR_UART0_RST_EN (BIT(1)) +#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) +#define PCR_UART0_RST_EN_V 0x00000001U +#define PCR_UART0_RST_EN_S 1 +/** PCR_UART0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ +#define PCR_UART0_READY (BIT(2)) +#define PCR_UART0_READY_M (PCR_UART0_READY_V << PCR_UART0_READY_S) +#define PCR_UART0_READY_V 0x00000001U +#define PCR_UART0_READY_S 2 + +/** PCR_UART0_SCLK_CONF_REG register + * UART0_SCLK configuration register + */ +#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) +/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_A 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) +#define PCR_UART0_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_A_S 0 +/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_B 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) +#define PCR_UART0_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART0_SCLK_DIV_B_S 6 +/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ +#define PCR_UART0_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) +#define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART0_SCLK_DIV_NUM_S 12 +/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz + */ +#define PCR_UART0_SCLK_SEL 0x00000003U +#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) +#define PCR_UART0_SCLK_SEL_V 0x00000003U +#define PCR_UART0_SCLK_SEL_S 20 +/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART0_SCLK_EN (BIT(22)) +#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) +#define PCR_UART0_SCLK_EN_V 0x00000001U +#define PCR_UART0_SCLK_EN_S 22 + +/** PCR_UART0_PD_CTRL_REG register + * UART0 power control register + */ +#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) +/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PU (BIT(1)) +#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) +#define PCR_UART0_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PU_S 1 +/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ +#define PCR_UART0_MEM_FORCE_PD (BIT(2)) +#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) +#define PCR_UART0_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART0_MEM_FORCE_PD_S 2 + +/** PCR_UART1_CONF_REG register + * UART1 configuration register + */ +#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) +/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ +#define PCR_UART1_CLK_EN (BIT(0)) +#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) +#define PCR_UART1_CLK_EN_V 0x00000001U +#define PCR_UART1_CLK_EN_S 0 +/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ +#define PCR_UART1_RST_EN (BIT(1)) +#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) +#define PCR_UART1_RST_EN_V 0x00000001U +#define PCR_UART1_RST_EN_S 1 +/** PCR_UART1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ +#define PCR_UART1_READY (BIT(2)) +#define PCR_UART1_READY_M (PCR_UART1_READY_V << PCR_UART1_READY_S) +#define PCR_UART1_READY_V 0x00000001U +#define PCR_UART1_READY_S 2 + +/** PCR_UART1_SCLK_CONF_REG register + * UART1_SCLK configuration register + */ +#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) +/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_A 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) +#define PCR_UART1_SCLK_DIV_A_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_A_S 0 +/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_B 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) +#define PCR_UART1_SCLK_DIV_B_V 0x0000003FU +#define PCR_UART1_SCLK_DIV_B_S 6 +/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ +#define PCR_UART1_SCLK_DIV_NUM 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) +#define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_UART1_SCLK_DIV_NUM_S 12 +/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz + */ +#define PCR_UART1_SCLK_SEL 0x00000003U +#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) +#define PCR_UART1_SCLK_SEL_V 0x00000003U +#define PCR_UART1_SCLK_SEL_S 20 +/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ +#define PCR_UART1_SCLK_EN (BIT(22)) +#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) +#define PCR_UART1_SCLK_EN_V 0x00000001U +#define PCR_UART1_SCLK_EN_S 22 + +/** PCR_UART1_PD_CTRL_REG register + * UART1 power control register + */ +#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) +/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PU (BIT(1)) +#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) +#define PCR_UART1_MEM_FORCE_PU_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PU_S 1 +/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ +#define PCR_UART1_MEM_FORCE_PD (BIT(2)) +#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) +#define PCR_UART1_MEM_FORCE_PD_V 0x00000001U +#define PCR_UART1_MEM_FORCE_PD_S 2 + +/** PCR_MSPI_CONF_REG register + * MSPI configuration register + */ +#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) +/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ +#define PCR_MSPI_CLK_EN (BIT(0)) +#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) +#define PCR_MSPI_CLK_EN_V 0x00000001U +#define PCR_MSPI_CLK_EN_S 0 +/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ +#define PCR_MSPI_RST_EN (BIT(1)) +#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) +#define PCR_MSPI_RST_EN_V 0x00000001U +#define PCR_MSPI_RST_EN_S 1 +/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ +#define PCR_MSPI_PLL_CLK_EN (BIT(2)) +#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) +#define PCR_MSPI_PLL_CLK_EN_V 0x00000001U +#define PCR_MSPI_PLL_CLK_EN_S 2 +/** PCR_MSPI_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ +#define PCR_MSPI_READY (BIT(3)) +#define PCR_MSPI_READY_M (PCR_MSPI_READY_V << PCR_MSPI_READY_S) +#define PCR_MSPI_READY_V 0x00000001U +#define PCR_MSPI_READY_S 3 + +/** PCR_MSPI_CLK_CONF_REG register + * MSPI_CLK configuration register + */ +#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) +/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ +#define PCR_MSPI_FAST_DIV_NUM 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_M (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S) +#define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU +#define PCR_MSPI_FAST_DIV_NUM_S 0 +/** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; + * set this field to select clock-source. + */ +#define PCR_MSPI_FUNC_CLK_SEL 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) +#define PCR_MSPI_FUNC_CLK_SEL_V 0x00000003U +#define PCR_MSPI_FUNC_CLK_SEL_S 8 +/** PCR_MSPI_FUNC_CLK_EN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ +#define PCR_MSPI_FUNC_CLK_EN (BIT(10)) +#define PCR_MSPI_FUNC_CLK_EN_M (PCR_MSPI_FUNC_CLK_EN_V << PCR_MSPI_FUNC_CLK_EN_S) +#define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U +#define PCR_MSPI_FUNC_CLK_EN_S 10 +/** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; + * Set 0 to reset axi_clock domain of mspi module + */ +#define PCR_MSPI_AXI_RST_EN (BIT(11)) +#define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) +#define PCR_MSPI_AXI_RST_EN_V 0x00000001U +#define PCR_MSPI_AXI_RST_EN_S 11 + +/** PCR_I2C_CONF_REG register + * I2C configuration register + */ +#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20) +/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ +#define PCR_I2C_CLK_EN (BIT(0)) +#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) +#define PCR_I2C_CLK_EN_V 0x00000001U +#define PCR_I2C_CLK_EN_S 0 +/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ +#define PCR_I2C_RST_EN (BIT(1)) +#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) +#define PCR_I2C_RST_EN_V 0x00000001U +#define PCR_I2C_RST_EN_S 1 + +/** PCR_I2C_SCLK_CONF_REG register + * I2C_SCLK configuration register + */ +#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) +/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_A 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) +#define PCR_I2C_SCLK_DIV_A_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_A_S 0 +/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_B 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) +#define PCR_I2C_SCLK_DIV_B_V 0x0000003FU +#define PCR_I2C_SCLK_DIV_B_S 6 +/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ +#define PCR_I2C_SCLK_DIV_NUM 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) +#define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_I2C_SCLK_DIV_NUM_S 12 +/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_I2C_SCLK_SEL (BIT(20)) +#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) +#define PCR_I2C_SCLK_SEL_V 0x00000001U +#define PCR_I2C_SCLK_SEL_S 20 +/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ +#define PCR_I2C_SCLK_EN (BIT(22)) +#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) +#define PCR_I2C_SCLK_EN_V 0x00000001U +#define PCR_I2C_SCLK_EN_S 22 + +/** PCR_TWAI0_CONF_REG register + * TWAI0 configuration register + */ +#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x28) +/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ +#define PCR_TWAI0_CLK_EN (BIT(0)) +#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) +#define PCR_TWAI0_CLK_EN_V 0x00000001U +#define PCR_TWAI0_CLK_EN_S 0 +/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ +#define PCR_TWAI0_RST_EN (BIT(1)) +#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) +#define PCR_TWAI0_RST_EN_V 0x00000001U +#define PCR_TWAI0_RST_EN_S 1 +/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ +#define PCR_TWAI0_READY (BIT(2)) +#define PCR_TWAI0_READY_M (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S) +#define PCR_TWAI0_READY_V 0x00000001U +#define PCR_TWAI0_READY_S 2 + +/** PCR_TWAI0_FUNC_CLK_CONF_REG register + * TWAI0_FUNC_CLK configuration register + */ +#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x2c) +/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) +#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_SEL_S 20 +/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ +#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) +#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI0_FUNC_CLK_EN_S 22 + +/** PCR_TWAI1_CONF_REG register + * TWAI1 configuration register + */ +#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x30) +/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai1 apb clock + */ +#define PCR_TWAI1_CLK_EN (BIT(0)) +#define PCR_TWAI1_CLK_EN_M (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S) +#define PCR_TWAI1_CLK_EN_V 0x00000001U +#define PCR_TWAI1_CLK_EN_S 0 +/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai1 module + */ +#define PCR_TWAI1_RST_EN (BIT(1)) +#define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) +#define PCR_TWAI1_RST_EN_V 0x00000001U +#define PCR_TWAI1_RST_EN_S 1 +/** PCR_TWAI1_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset twai1 module + */ +#define PCR_TWAI1_READY (BIT(2)) +#define PCR_TWAI1_READY_M (PCR_TWAI1_READY_V << PCR_TWAI1_READY_S) +#define PCR_TWAI1_READY_V 0x00000001U +#define PCR_TWAI1_READY_S 2 + +/** PCR_TWAI1_FUNC_CLK_CONF_REG register + * TWAI1_FUNC_CLK configuration register + */ +#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x34) +/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) +#define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) +#define PCR_TWAI1_FUNC_CLK_SEL_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_SEL_S 20 +/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai1 function clock + */ +#define PCR_TWAI1_FUNC_CLK_EN (BIT(22)) +#define PCR_TWAI1_FUNC_CLK_EN_M (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S) +#define PCR_TWAI1_FUNC_CLK_EN_V 0x00000001U +#define PCR_TWAI1_FUNC_CLK_EN_S 22 + +/** PCR_UHCI_CONF_REG register + * UHCI configuration register + */ +#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x38) +/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ +#define PCR_UHCI_CLK_EN (BIT(0)) +#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) +#define PCR_UHCI_CLK_EN_V 0x00000001U +#define PCR_UHCI_CLK_EN_S 0 +/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ +#define PCR_UHCI_RST_EN (BIT(1)) +#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) +#define PCR_UHCI_RST_EN_V 0x00000001U +#define PCR_UHCI_RST_EN_S 1 +/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ +#define PCR_UHCI_READY (BIT(2)) +#define PCR_UHCI_READY_M (PCR_UHCI_READY_V << PCR_UHCI_READY_S) +#define PCR_UHCI_READY_V 0x00000001U +#define PCR_UHCI_READY_S 2 + +/** PCR_RMT_CONF_REG register + * RMT configuration register + */ +#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x3c) +/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ +#define PCR_RMT_CLK_EN (BIT(0)) +#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) +#define PCR_RMT_CLK_EN_V 0x00000001U +#define PCR_RMT_CLK_EN_S 0 +/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ +#define PCR_RMT_RST_EN (BIT(1)) +#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) +#define PCR_RMT_RST_EN_V 0x00000001U +#define PCR_RMT_RST_EN_S 1 + +/** PCR_RMT_SCLK_CONF_REG register + * RMT_SCLK configuration register + */ +#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40) +/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_A 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) +#define PCR_RMT_SCLK_DIV_A_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_A_S 0 +/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_B 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) +#define PCR_RMT_SCLK_DIV_B_V 0x0000003FU +#define PCR_RMT_SCLK_DIV_B_S 6 +/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ +#define PCR_RMT_SCLK_DIV_NUM 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) +#define PCR_RMT_SCLK_DIV_NUM_V 0x000000FFU +#define PCR_RMT_SCLK_DIV_NUM_S 12 +/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; + * set this field to select clock-source. 0: XTAL, 1(default): FOSC, 2: 80MHz + */ +#define PCR_RMT_SCLK_SEL 0x00000003U +#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) +#define PCR_RMT_SCLK_SEL_V 0x00000003U +#define PCR_RMT_SCLK_SEL_S 20 +/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable rmt function clock + */ +#define PCR_RMT_SCLK_EN (BIT(22)) +#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) +#define PCR_RMT_SCLK_EN_V 0x00000001U +#define PCR_RMT_SCLK_EN_S 22 + +/** PCR_LEDC_CONF_REG register + * LEDC configuration register + */ +#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x44) +/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ +#define PCR_LEDC_CLK_EN (BIT(0)) +#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) +#define PCR_LEDC_CLK_EN_V 0x00000001U +#define PCR_LEDC_CLK_EN_S 0 +/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ +#define PCR_LEDC_RST_EN (BIT(1)) +#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) +#define PCR_LEDC_RST_EN_V 0x00000001U +#define PCR_LEDC_RST_EN_S 1 +/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ +#define PCR_LEDC_READY (BIT(2)) +#define PCR_LEDC_READY_M (PCR_LEDC_READY_V << PCR_LEDC_READY_S) +#define PCR_LEDC_READY_V 0x00000001U +#define PCR_LEDC_READY_S 2 + +/** PCR_LEDC_SCLK_CONF_REG register + * LEDC_SCLK configuration register + */ +#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x48) +/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ +#define PCR_LEDC_SCLK_SEL 0x00000003U +#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) +#define PCR_LEDC_SCLK_SEL_V 0x00000003U +#define PCR_LEDC_SCLK_SEL_S 20 +/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ +#define PCR_LEDC_SCLK_EN (BIT(22)) +#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) +#define PCR_LEDC_SCLK_EN_V 0x00000001U +#define PCR_LEDC_SCLK_EN_S 22 + +/** PCR_TIMERGROUP0_CONF_REG register + * TIMERGROUP0 configuration register + */ +#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x4c) +/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ +#define PCR_TG0_CLK_EN (BIT(0)) +#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) +#define PCR_TG0_CLK_EN_V 0x00000001U +#define PCR_TG0_CLK_EN_S 0 +/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ +#define PCR_TG0_RST_EN (BIT(1)) +#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) +#define PCR_TG0_RST_EN_V 0x00000001U +#define PCR_TG0_RST_EN_S 1 +/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_READY (BIT(2)) +#define PCR_TG0_WDT_READY_M (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S) +#define PCR_TG0_WDT_READY_V 0x00000001U +#define PCR_TG0_WDT_READY_S 2 +/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ +#define PCR_TG0_TIMER0_READY (BIT(3)) +#define PCR_TG0_TIMER0_READY_M (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S) +#define PCR_TG0_TIMER0_READY_V 0x00000001U +#define PCR_TG0_TIMER0_READY_S 3 +/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG0_TIMER1_READY (BIT(4)) +#define PCR_TG0_TIMER1_READY_M (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S) +#define PCR_TG0_TIMER1_READY_V 0x00000001U +#define PCR_TG0_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register + * TIMERGROUP0_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) +/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_TIMER_CLK_SEL 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) +#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG0_TIMER_CLK_SEL_S 20 +/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ +#define PCR_TG0_TIMER_CLK_EN (BIT(22)) +#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) +#define PCR_TG0_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG0_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register + * TIMERGROUP0_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) +/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG0_WDT_CLK_SEL 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) +#define PCR_TG0_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG0_WDT_CLK_SEL_S 20 +/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG0_WDT_CLK_EN (BIT(22)) +#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) +#define PCR_TG0_WDT_CLK_EN_V 0x00000001U +#define PCR_TG0_WDT_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x58) +/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ +#define PCR_TG1_CLK_EN (BIT(0)) +#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) +#define PCR_TG1_CLK_EN_V 0x00000001U +#define PCR_TG1_CLK_EN_S 0 +/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ +#define PCR_TG1_RST_EN (BIT(1)) +#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) +#define PCR_TG1_RST_EN_V 0x00000001U +#define PCR_TG1_RST_EN_S 1 +/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_READY (BIT(2)) +#define PCR_TG1_WDT_READY_M (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S) +#define PCR_TG1_WDT_READY_V 0x00000001U +#define PCR_TG1_WDT_READY_S 2 +/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ +#define PCR_TG1_TIMER0_READY (BIT(3)) +#define PCR_TG1_TIMER0_READY_M (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S) +#define PCR_TG1_TIMER0_READY_V 0x00000001U +#define PCR_TG1_TIMER0_READY_S 3 +/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1; + * reserved + */ +#define PCR_TG1_TIMER1_READY (BIT(4)) +#define PCR_TG1_TIMER1_READY_M (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S) +#define PCR_TG1_TIMER1_READY_V 0x00000001U +#define PCR_TG1_TIMER1_READY_S 4 + +/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register + * TIMERGROUP1_TIMER_CLK configuration register + */ +#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) +/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_TIMER_CLK_SEL 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) +#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003U +#define PCR_TG1_TIMER_CLK_SEL_S 20 +/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ +#define PCR_TG1_TIMER_CLK_EN (BIT(22)) +#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) +#define PCR_TG1_TIMER_CLK_EN_V 0x00000001U +#define PCR_TG1_TIMER_CLK_EN_S 22 + +/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register + * TIMERGROUP1_WDT_CLK configuration register + */ +#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) +/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_TG1_WDT_CLK_SEL 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) +#define PCR_TG1_WDT_CLK_SEL_V 0x00000003U +#define PCR_TG1_WDT_CLK_SEL_S 20 +/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ +#define PCR_TG1_WDT_CLK_EN (BIT(22)) +#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) +#define PCR_TG1_WDT_CLK_EN_V 0x00000001U +#define PCR_TG1_WDT_CLK_EN_S 22 + +/** PCR_SYSTIMER_CONF_REG register + * SYSTIMER configuration register + */ +#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x64) +/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ +#define PCR_SYSTIMER_CLK_EN (BIT(0)) +#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) +#define PCR_SYSTIMER_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_CLK_EN_S 0 +/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ +#define PCR_SYSTIMER_RST_EN (BIT(1)) +#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) +#define PCR_SYSTIMER_RST_EN_V 0x00000001U +#define PCR_SYSTIMER_RST_EN_S 1 +/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ +#define PCR_SYSTIMER_READY (BIT(2)) +#define PCR_SYSTIMER_READY_M (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S) +#define PCR_SYSTIMER_READY_V 0x00000001U +#define PCR_SYSTIMER_READY_S 2 + +/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register + * SYSTIMER_FUNC_CLK configuration register + */ +#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) +/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ +#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) +#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) +#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 +/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ +#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) +#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) +#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001U +#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 + +/** PCR_I2S_CONF_REG register + * I2S configuration register + */ +#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) +/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ +#define PCR_I2S_CLK_EN (BIT(0)) +#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) +#define PCR_I2S_CLK_EN_V 0x00000001U +#define PCR_I2S_CLK_EN_S 0 +/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ +#define PCR_I2S_RST_EN (BIT(1)) +#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) +#define PCR_I2S_RST_EN_V 0x00000001U +#define PCR_I2S_RST_EN_S 1 +/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ +#define PCR_I2S_RX_READY (BIT(2)) +#define PCR_I2S_RX_READY_M (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S) +#define PCR_I2S_RX_READY_V 0x00000001U +#define PCR_I2S_RX_READY_S 2 +/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ +#define PCR_I2S_TX_READY (BIT(3)) +#define PCR_I2S_TX_READY_M (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S) +#define PCR_I2S_TX_READY_V 0x00000001U +#define PCR_I2S_TX_READY_S 3 + +/** PCR_I2S_TX_CLKM_CONF_REG register + * I2S_TX_CLKM configuration register + */ +#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) +/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ +#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) +#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ +#define PCR_I2S_TX_CLKM_SEL 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) +#define PCR_I2S_TX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_TX_CLKM_SEL_S 20 +/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ +#define PCR_I2S_TX_CLKM_EN (BIT(22)) +#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) +#define PCR_I2S_TX_CLKM_EN_V 0x00000001U +#define PCR_I2S_TX_CLKM_EN_S 22 + +/** PCR_I2S_TX_CLKM_DIV_CONF_REG register + * I2S_TX_CLKM_DIV configuration register + */ +#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) +/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_TX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) +#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Z_S 0 +/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_TX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) +#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_Y_S 9 +/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_TX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) +#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_TX_CLKM_DIV_X_S 18 +/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) +#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 + +/** PCR_I2S_RX_CLKM_CONF_REG register + * I2S_RX_CLKM configuration register + */ +#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) +/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ +#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) +#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 +/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ +#define PCR_I2S_RX_CLKM_SEL 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) +#define PCR_I2S_RX_CLKM_SEL_V 0x00000003U +#define PCR_I2S_RX_CLKM_SEL_S 20 +/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ +#define PCR_I2S_RX_CLKM_EN (BIT(22)) +#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) +#define PCR_I2S_RX_CLKM_EN_V 0x00000001U +#define PCR_I2S_RX_CLKM_EN_S 22 +/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ +#define PCR_I2S_MCLK_SEL (BIT(23)) +#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) +#define PCR_I2S_MCLK_SEL_V 0x00000001U +#define PCR_I2S_MCLK_SEL_S 23 + +/** PCR_I2S_RX_CLKM_DIV_CONF_REG register + * I2S_RX_CLKM_DIV configuration register + */ +#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) +/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ +#define PCR_I2S_RX_CLKM_DIV_Z 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) +#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Z_S 0 +/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ +#define PCR_I2S_RX_CLKM_DIV_Y 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) +#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_Y_S 9 +/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ +#define PCR_I2S_RX_CLKM_DIV_X 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) +#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001FFU +#define PCR_I2S_RX_CLKM_DIV_X_S 18 +/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ +#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) +#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001U +#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 + +/** PCR_SARADC_CONF_REG register + * SARADC configuration register + */ +#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) +/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; + * no use + */ +#define PCR_SARADC_CLK_EN (BIT(0)) +#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) +#define PCR_SARADC_CLK_EN_V 0x00000001U +#define PCR_SARADC_CLK_EN_S 0 +/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ +#define PCR_SARADC_RST_EN (BIT(1)) +#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) +#define PCR_SARADC_RST_EN_V 0x00000001U +#define PCR_SARADC_RST_EN_S 1 +/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ +#define PCR_SARADC_REG_CLK_EN (BIT(2)) +#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) +#define PCR_SARADC_REG_CLK_EN_V 0x00000001U +#define PCR_SARADC_REG_CLK_EN_S 2 +/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ +#define PCR_SARADC_REG_RST_EN (BIT(3)) +#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) +#define PCR_SARADC_REG_RST_EN_V 0x00000001U +#define PCR_SARADC_REG_RST_EN_S 3 + +/** PCR_SARADC_CLKM_CONF_REG register + * SARADC_CLKM configuration register + */ +#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) +/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_A 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) +#define PCR_SARADC_CLKM_DIV_A_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_A_S 0 +/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_B 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) +#define PCR_SARADC_CLKM_DIV_B_V 0x0000003FU +#define PCR_SARADC_CLKM_DIV_B_S 6 +/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ +#define PCR_SARADC_CLKM_DIV_NUM 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) +#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SARADC_CLKM_DIV_NUM_S 12 +/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SARADC_CLKM_SEL 0x00000003U +#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) +#define PCR_SARADC_CLKM_SEL_V 0x00000003U +#define PCR_SARADC_CLKM_SEL_S 20 +/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ +#define PCR_SARADC_CLKM_EN (BIT(22)) +#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) +#define PCR_SARADC_CLKM_EN_V 0x00000001U +#define PCR_SARADC_CLKM_EN_S 22 + +/** PCR_TSENS_CLK_CONF_REG register + * TSENS_CLK configuration register + */ +#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) +/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ +#define PCR_TSENS_CLK_SEL (BIT(20)) +#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) +#define PCR_TSENS_CLK_SEL_V 0x00000001U +#define PCR_TSENS_CLK_SEL_S 20 +/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ +#define PCR_TSENS_CLK_EN (BIT(22)) +#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) +#define PCR_TSENS_CLK_EN_V 0x00000001U +#define PCR_TSENS_CLK_EN_S 22 +/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ +#define PCR_TSENS_RST_EN (BIT(23)) +#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) +#define PCR_TSENS_RST_EN_V 0x00000001U +#define PCR_TSENS_RST_EN_S 23 + +/** PCR_USB_DEVICE_CONF_REG register + * USB_DEVICE configuration register + */ +#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) +/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ +#define PCR_USB_DEVICE_CLK_EN (BIT(0)) +#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) +#define PCR_USB_DEVICE_CLK_EN_V 0x00000001U +#define PCR_USB_DEVICE_CLK_EN_S 0 +/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ +#define PCR_USB_DEVICE_RST_EN (BIT(1)) +#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) +#define PCR_USB_DEVICE_RST_EN_V 0x00000001U +#define PCR_USB_DEVICE_RST_EN_S 1 +/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ +#define PCR_USB_DEVICE_READY (BIT(2)) +#define PCR_USB_DEVICE_READY_M (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S) +#define PCR_USB_DEVICE_READY_V 0x00000001U +#define PCR_USB_DEVICE_READY_S 2 + +/** PCR_INTMTX_CONF_REG register + * INTMTX configuration register + */ +#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) +/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ +#define PCR_INTMTX_CLK_EN (BIT(0)) +#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) +#define PCR_INTMTX_CLK_EN_V 0x00000001U +#define PCR_INTMTX_CLK_EN_S 0 +/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ +#define PCR_INTMTX_RST_EN (BIT(1)) +#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) +#define PCR_INTMTX_RST_EN_V 0x00000001U +#define PCR_INTMTX_RST_EN_S 1 +/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ +#define PCR_INTMTX_READY (BIT(2)) +#define PCR_INTMTX_READY_M (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S) +#define PCR_INTMTX_READY_V 0x00000001U +#define PCR_INTMTX_READY_S 2 + +/** PCR_PCNT_CONF_REG register + * PCNT configuration register + */ +#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) +/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ +#define PCR_PCNT_CLK_EN (BIT(0)) +#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) +#define PCR_PCNT_CLK_EN_V 0x00000001U +#define PCR_PCNT_CLK_EN_S 0 +/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ +#define PCR_PCNT_RST_EN (BIT(1)) +#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) +#define PCR_PCNT_RST_EN_V 0x00000001U +#define PCR_PCNT_RST_EN_S 1 +/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ +#define PCR_PCNT_READY (BIT(2)) +#define PCR_PCNT_READY_M (PCR_PCNT_READY_V << PCR_PCNT_READY_S) +#define PCR_PCNT_READY_V 0x00000001U +#define PCR_PCNT_READY_S 2 + +/** PCR_ETM_CONF_REG register + * ETM configuration register + */ +#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) +/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ +#define PCR_ETM_CLK_EN (BIT(0)) +#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) +#define PCR_ETM_CLK_EN_V 0x00000001U +#define PCR_ETM_CLK_EN_S 0 +/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ +#define PCR_ETM_RST_EN (BIT(1)) +#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) +#define PCR_ETM_RST_EN_V 0x00000001U +#define PCR_ETM_RST_EN_S 1 +/** PCR_ETM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ +#define PCR_ETM_READY (BIT(2)) +#define PCR_ETM_READY_M (PCR_ETM_READY_V << PCR_ETM_READY_S) +#define PCR_ETM_READY_V 0x00000001U +#define PCR_ETM_READY_S 2 + +/** PCR_PWM_CONF_REG register + * PWM configuration register + */ +#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) +/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ +#define PCR_PWM_CLK_EN (BIT(0)) +#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) +#define PCR_PWM_CLK_EN_V 0x00000001U +#define PCR_PWM_CLK_EN_S 0 +/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ +#define PCR_PWM_RST_EN (BIT(1)) +#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) +#define PCR_PWM_RST_EN_V 0x00000001U +#define PCR_PWM_RST_EN_S 1 +/** PCR_PWM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ +#define PCR_PWM_READY (BIT(2)) +#define PCR_PWM_READY_M (PCR_PWM_READY_V << PCR_PWM_READY_S) +#define PCR_PWM_READY_V 0x00000001U +#define PCR_PWM_READY_S 2 + +/** PCR_PWM_CLK_CONF_REG register + * PWM_CLK configuration register + */ +#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) +/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ +#define PCR_PWM_DIV_NUM 0x000000FFU +#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) +#define PCR_PWM_DIV_NUM_V 0x000000FFU +#define PCR_PWM_DIV_NUM_S 12 +/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ +#define PCR_PWM_CLKM_SEL 0x00000003U +#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) +#define PCR_PWM_CLKM_SEL_V 0x00000003U +#define PCR_PWM_CLKM_SEL_S 20 +/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ +#define PCR_PWM_CLKM_EN (BIT(22)) +#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) +#define PCR_PWM_CLKM_EN_V 0x00000001U +#define PCR_PWM_CLKM_EN_S 22 + +/** PCR_PARL_IO_CONF_REG register + * PARL_IO configuration register + */ +#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) +/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ +#define PCR_PARL_CLK_EN (BIT(0)) +#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) +#define PCR_PARL_CLK_EN_V 0x00000001U +#define PCR_PARL_CLK_EN_S 0 +/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ +#define PCR_PARL_RST_EN (BIT(1)) +#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) +#define PCR_PARL_RST_EN_V 0x00000001U +#define PCR_PARL_RST_EN_S 1 +/** PCR_PARL_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ +#define PCR_PARL_READY (BIT(2)) +#define PCR_PARL_READY_M (PCR_PARL_READY_V << PCR_PARL_READY_S) +#define PCR_PARL_READY_V 0x00000001U +#define PCR_PARL_READY_S 2 + +/** PCR_PARL_CLK_RX_CONF_REG register + * PARL_CLK_RX configuration register + */ +#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) +/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ +#define PCR_PARL_CLK_RX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) +#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_RX_DIV_NUM_S 0 +/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_RX_SEL 0x00000003U +#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) +#define PCR_PARL_CLK_RX_SEL_V 0x00000003U +#define PCR_PARL_CLK_RX_SEL_S 16 +/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ +#define PCR_PARL_CLK_RX_EN (BIT(18)) +#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) +#define PCR_PARL_CLK_RX_EN_V 0x00000001U +#define PCR_PARL_CLK_RX_EN_S 18 +/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ +#define PCR_PARL_RX_RST_EN (BIT(19)) +#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) +#define PCR_PARL_RX_RST_EN_V 0x00000001U +#define PCR_PARL_RX_RST_EN_S 19 + +/** PCR_PARL_CLK_TX_CONF_REG register + * PARL_CLK_TX configuration register + */ +#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) +/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ +#define PCR_PARL_CLK_TX_DIV_NUM 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) +#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000FFFFU +#define PCR_PARL_CLK_TX_DIV_NUM_S 0 +/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ +#define PCR_PARL_CLK_TX_SEL 0x00000003U +#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) +#define PCR_PARL_CLK_TX_SEL_V 0x00000003U +#define PCR_PARL_CLK_TX_SEL_S 16 +/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ +#define PCR_PARL_CLK_TX_EN (BIT(18)) +#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) +#define PCR_PARL_CLK_TX_EN_V 0x00000001U +#define PCR_PARL_CLK_TX_EN_S 18 +/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ +#define PCR_PARL_TX_RST_EN (BIT(19)) +#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) +#define PCR_PARL_TX_RST_EN_V 0x00000001U +#define PCR_PARL_TX_RST_EN_S 19 + +/** PCR_PVT_MONITOR_CONF_REG register + * PVT_MONITOR configuration register + */ +#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0) +/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ +#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) +#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) +#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_CLK_EN_S 0 +/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ +#define PCR_PVT_MONITOR_RST_EN (BIT(1)) +#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) +#define PCR_PVT_MONITOR_RST_EN_V 0x00000001U +#define PCR_PVT_MONITOR_RST_EN_S 1 +/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ +#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 +/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ +#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 +/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ +#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) +#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 + +/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register + * PVT_MONITOR function clock configuration register + */ +#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4) +/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU +#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 +/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * divided by 3. + */ +#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 +/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ +#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) +#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001U +#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 + +/** PCR_GDMA_CONF_REG register + * GDMA configuration register + */ +#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8) +/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ +#define PCR_GDMA_CLK_EN (BIT(0)) +#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) +#define PCR_GDMA_CLK_EN_V 0x00000001U +#define PCR_GDMA_CLK_EN_S 0 +/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ +#define PCR_GDMA_RST_EN (BIT(1)) +#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) +#define PCR_GDMA_RST_EN_V 0x00000001U +#define PCR_GDMA_RST_EN_S 1 + +/** PCR_SPI2_CONF_REG register + * SPI2 configuration register + */ +#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc) +/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ +#define PCR_SPI2_CLK_EN (BIT(0)) +#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) +#define PCR_SPI2_CLK_EN_V 0x00000001U +#define PCR_SPI2_CLK_EN_S 0 +/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ +#define PCR_SPI2_RST_EN (BIT(1)) +#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) +#define PCR_SPI2_RST_EN_V 0x00000001U +#define PCR_SPI2_RST_EN_S 1 +/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ +#define PCR_SPI2_READY (BIT(2)) +#define PCR_SPI2_READY_M (PCR_SPI2_READY_V << PCR_SPI2_READY_S) +#define PCR_SPI2_READY_V 0x00000001U +#define PCR_SPI2_READY_S 2 + +/** PCR_SPI2_CLKM_CONF_REG register + * SPI2_CLKM configuration register + */ +#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0) +/** PCR_SPI2_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ +#define PCR_SPI2_CLKM_DIV_NUM 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_M (PCR_SPI2_CLKM_DIV_NUM_V << PCR_SPI2_CLKM_DIV_NUM_S) +#define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU +#define PCR_SPI2_CLKM_DIV_NUM_S 12 +/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ +#define PCR_SPI2_CLKM_SEL 0x00000003U +#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) +#define PCR_SPI2_CLKM_SEL_V 0x00000003U +#define PCR_SPI2_CLKM_SEL_S 20 +/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ +#define PCR_SPI2_CLKM_EN (BIT(22)) +#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) +#define PCR_SPI2_CLKM_EN_V 0x00000001U +#define PCR_SPI2_CLKM_EN_S 22 + +/** PCR_AES_CONF_REG register + * AES configuration register + */ +#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4) +/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ +#define PCR_AES_CLK_EN (BIT(0)) +#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) +#define PCR_AES_CLK_EN_V 0x00000001U +#define PCR_AES_CLK_EN_S 0 +/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ +#define PCR_AES_RST_EN (BIT(1)) +#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) +#define PCR_AES_RST_EN_V 0x00000001U +#define PCR_AES_RST_EN_S 1 +/** PCR_AES_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ +#define PCR_AES_READY (BIT(2)) +#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S) +#define PCR_AES_READY_V 0x00000001U +#define PCR_AES_READY_S 2 + +/** PCR_SHA_CONF_REG register + * SHA configuration register + */ +#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8) +/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ +#define PCR_SHA_CLK_EN (BIT(0)) +#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) +#define PCR_SHA_CLK_EN_V 0x00000001U +#define PCR_SHA_CLK_EN_S 0 +/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ +#define PCR_SHA_RST_EN (BIT(1)) +#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) +#define PCR_SHA_RST_EN_V 0x00000001U +#define PCR_SHA_RST_EN_S 1 +/** PCR_SHA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ +#define PCR_SHA_READY (BIT(2)) +#define PCR_SHA_READY_M (PCR_SHA_READY_V << PCR_SHA_READY_S) +#define PCR_SHA_READY_V 0x00000001U +#define PCR_SHA_READY_S 2 + +/** PCR_RSA_CONF_REG register + * RSA configuration register + */ +#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc) +/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ +#define PCR_RSA_CLK_EN (BIT(0)) +#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) +#define PCR_RSA_CLK_EN_V 0x00000001U +#define PCR_RSA_CLK_EN_S 0 +/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ +#define PCR_RSA_RST_EN (BIT(1)) +#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) +#define PCR_RSA_RST_EN_V 0x00000001U +#define PCR_RSA_RST_EN_S 1 +/** PCR_RSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ +#define PCR_RSA_READY (BIT(2)) +#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S) +#define PCR_RSA_READY_V 0x00000001U +#define PCR_RSA_READY_S 2 + +/** PCR_RSA_PD_CTRL_REG register + * RSA power control register + */ +#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0) +/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ +#define PCR_RSA_MEM_PD (BIT(0)) +#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) +#define PCR_RSA_MEM_PD_V 0x00000001U +#define PCR_RSA_MEM_PD_S 0 +/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ +#define PCR_RSA_MEM_FORCE_PU (BIT(1)) +#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) +#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PU_S 1 +/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ +#define PCR_RSA_MEM_FORCE_PD (BIT(2)) +#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) +#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U +#define PCR_RSA_MEM_FORCE_PD_S 2 + +/** PCR_ECC_CONF_REG register + * ECC configuration register + */ +#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4) +/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ +#define PCR_ECC_CLK_EN (BIT(0)) +#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) +#define PCR_ECC_CLK_EN_V 0x00000001U +#define PCR_ECC_CLK_EN_S 0 +/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ +#define PCR_ECC_RST_EN (BIT(1)) +#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) +#define PCR_ECC_RST_EN_V 0x00000001U +#define PCR_ECC_RST_EN_S 1 +/** PCR_ECC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ +#define PCR_ECC_READY (BIT(2)) +#define PCR_ECC_READY_M (PCR_ECC_READY_V << PCR_ECC_READY_S) +#define PCR_ECC_READY_V 0x00000001U +#define PCR_ECC_READY_S 2 + +/** PCR_ECC_PD_CTRL_REG register + * ECC power control register + */ +#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8) +/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ +#define PCR_ECC_MEM_PD (BIT(0)) +#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) +#define PCR_ECC_MEM_PD_V 0x00000001U +#define PCR_ECC_MEM_PD_S 0 +/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ +#define PCR_ECC_MEM_FORCE_PU (BIT(1)) +#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) +#define PCR_ECC_MEM_FORCE_PU_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PU_S 1 +/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ +#define PCR_ECC_MEM_FORCE_PD (BIT(2)) +#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) +#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U +#define PCR_ECC_MEM_FORCE_PD_S 2 + +/** PCR_DS_CONF_REG register + * DS configuration register + */ +#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc) +/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ +#define PCR_DS_CLK_EN (BIT(0)) +#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) +#define PCR_DS_CLK_EN_V 0x00000001U +#define PCR_DS_CLK_EN_S 0 +/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ +#define PCR_DS_RST_EN (BIT(1)) +#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) +#define PCR_DS_RST_EN_V 0x00000001U +#define PCR_DS_RST_EN_S 1 +/** PCR_DS_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ +#define PCR_DS_READY (BIT(2)) +#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S) +#define PCR_DS_READY_V 0x00000001U +#define PCR_DS_READY_S 2 + +/** PCR_HMAC_CONF_REG register + * HMAC configuration register + */ +#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0) +/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ +#define PCR_HMAC_CLK_EN (BIT(0)) +#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) +#define PCR_HMAC_CLK_EN_V 0x00000001U +#define PCR_HMAC_CLK_EN_S 0 +/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ +#define PCR_HMAC_RST_EN (BIT(1)) +#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) +#define PCR_HMAC_RST_EN_V 0x00000001U +#define PCR_HMAC_RST_EN_S 1 +/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ +#define PCR_HMAC_READY (BIT(2)) +#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S) +#define PCR_HMAC_READY_V 0x00000001U +#define PCR_HMAC_READY_S 2 + +/** PCR_ECDSA_CONF_REG register + * ECDSA configuration register + */ +#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4) +/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ +#define PCR_ECDSA_CLK_EN (BIT(0)) +#define PCR_ECDSA_CLK_EN_M (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S) +#define PCR_ECDSA_CLK_EN_V 0x00000001U +#define PCR_ECDSA_CLK_EN_S 0 +/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ +#define PCR_ECDSA_RST_EN (BIT(1)) +#define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) +#define PCR_ECDSA_RST_EN_V 0x00000001U +#define PCR_ECDSA_RST_EN_S 1 +/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ +#define PCR_ECDSA_READY (BIT(2)) +#define PCR_ECDSA_READY_M (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S) +#define PCR_ECDSA_READY_V 0x00000001U +#define PCR_ECDSA_READY_S 2 + +/** PCR_IOMUX_CONF_REG register + * IOMUX configuration register + */ +#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ +#define PCR_IOMUX_CLK_EN (BIT(0)) +#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) +#define PCR_IOMUX_CLK_EN_V 0x00000001U +#define PCR_IOMUX_CLK_EN_S 0 +/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ +#define PCR_IOMUX_RST_EN (BIT(1)) +#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) +#define PCR_IOMUX_RST_EN_V 0x00000001U +#define PCR_IOMUX_RST_EN_S 1 + +/** PCR_IOMUX_CLK_CONF_REG register + * IOMUX_CLK configuration register + */ +#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) +/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ +#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) +#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003U +#define PCR_IOMUX_FUNC_CLK_SEL_S 20 +/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ +#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) +#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) +#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001U +#define PCR_IOMUX_FUNC_CLK_EN_S 22 + +/** PCR_MEM_MONITOR_CONF_REG register + * MEM_MONITOR configuration register + */ +#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) +/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ +#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) +#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) +#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001U +#define PCR_MEM_MONITOR_CLK_EN_S 0 +/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ +#define PCR_MEM_MONITOR_RST_EN (BIT(1)) +#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) +#define PCR_MEM_MONITOR_RST_EN_V 0x00000001U +#define PCR_MEM_MONITOR_RST_EN_S 1 +/** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset mem_monitor module + */ +#define PCR_MEM_MONITOR_READY (BIT(2)) +#define PCR_MEM_MONITOR_READY_M (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S) +#define PCR_MEM_MONITOR_READY_V 0x00000001U +#define PCR_MEM_MONITOR_READY_S 2 + +/** PCR_REGDMA_CONF_REG register + * REGDMA configuration register + */ +#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) +/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ +#define PCR_REGDMA_CLK_EN (BIT(0)) +#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) +#define PCR_REGDMA_CLK_EN_V 0x00000001U +#define PCR_REGDMA_CLK_EN_S 0 +/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ +#define PCR_REGDMA_RST_EN (BIT(1)) +#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) +#define PCR_REGDMA_RST_EN_V 0x00000001U +#define PCR_REGDMA_RST_EN_S 1 + +/** PCR_TRACE_CONF_REG register + * TRACE configuration register + */ +#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8) +/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ +#define PCR_TRACE_CLK_EN (BIT(0)) +#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) +#define PCR_TRACE_CLK_EN_V 0x00000001U +#define PCR_TRACE_CLK_EN_S 0 +/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ +#define PCR_TRACE_RST_EN (BIT(1)) +#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) +#define PCR_TRACE_RST_EN_V 0x00000001U +#define PCR_TRACE_RST_EN_S 1 + +/** PCR_ASSIST_CONF_REG register + * ASSIST configuration register + */ +#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc) +/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ +#define PCR_ASSIST_CLK_EN (BIT(0)) +#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) +#define PCR_ASSIST_CLK_EN_V 0x00000001U +#define PCR_ASSIST_CLK_EN_S 0 +/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ +#define PCR_ASSIST_RST_EN (BIT(1)) +#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) +#define PCR_ASSIST_RST_EN_V 0x00000001U +#define PCR_ASSIST_RST_EN_S 1 + +/** PCR_CACHE_CONF_REG register + * CACHE configuration register + */ +#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100) +/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ +#define PCR_CACHE_CLK_EN (BIT(0)) +#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) +#define PCR_CACHE_CLK_EN_V 0x00000001U +#define PCR_CACHE_CLK_EN_S 0 +/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ +#define PCR_CACHE_RST_EN (BIT(1)) +#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) +#define PCR_CACHE_RST_EN_V 0x00000001U +#define PCR_CACHE_RST_EN_S 1 + +/** PCR_MODEM_CONF_REG register + * MODEM_APB configuration register + */ +#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104) +/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ +#define PCR_MODEM_RST_EN (BIT(2)) +#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) +#define PCR_MODEM_RST_EN_V 0x00000001U +#define PCR_MODEM_RST_EN_S 2 + +/** PCR_TIMEOUT_CONF_REG register + * TIMEOUT configuration register + */ +#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108) +/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ +#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) +#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) +#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_CPU_TIMEOUT_RST_EN_S 1 +/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ +#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) +#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) +#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001U +#define PCR_HP_TIMEOUT_RST_EN_S 2 + +/** PCR_SYSCLK_CONF_REG register + * SYSCLK configuration register + */ +#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 +/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: FOSC, 2: 160M_PLL, 3: + * 240M_PLL. + */ +#define PCR_SOC_CLK_SEL 0x00000003U +#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) +#define PCR_SOC_CLK_SEL_V 0x00000003U +#define PCR_SOC_CLK_SEL_S 16 +/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ +#define PCR_CLK_XTAL_FREQ 0x0000007FU +#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) +#define PCR_CLK_XTAL_FREQ_V 0x0000007FU +#define PCR_CLK_XTAL_FREQ_S 24 + +/** PCR_CPU_WAITI_CONF_REG register + * CPU_WAITI configuration register + */ +#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110) +/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ +#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) +#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001U +#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 +/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ +#define PCR_CPU_WAITI_DELAY_NUM 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) +#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000FU +#define PCR_CPU_WAITI_DELAY_NUM_S 4 + +/** PCR_CPU_FREQ_CONF_REG register + * CPU_FREQ configuration register + */ +#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114) +/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ +#define PCR_CPU_DIV_NUM 0x000000FFU +#define PCR_CPU_DIV_NUM_M (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S) +#define PCR_CPU_DIV_NUM_V 0x000000FFU +#define PCR_CPU_DIV_NUM_S 0 + +/** PCR_AHB_FREQ_CONF_REG register + * AHB_FREQ configuration register + */ +#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) +/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ +#define PCR_AHB_DIV_NUM 0x000000FFU +#define PCR_AHB_DIV_NUM_M (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S) +#define PCR_AHB_DIV_NUM_V 0x000000FFU +#define PCR_AHB_DIV_NUM_S 0 + +/** PCR_APB_FREQ_CONF_REG register + * APB_FREQ configuration register + */ +#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) +/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ +#define PCR_APB_DECREASE_DIV_NUM 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) +#define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU +#define PCR_APB_DECREASE_DIV_NUM_S 0 +/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ +#define PCR_APB_DIV_NUM 0x000000FFU +#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) +#define PCR_APB_DIV_NUM_V 0x000000FFU +#define PCR_APB_DIV_NUM_S 8 + +/** PCR_SYSCLK_FREQ_QUERY_0_REG register + * SYSCLK frequency query 0 register + */ +#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120) +/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ +#define PCR_FOSC_FREQ 0x000000FFU +#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) +#define PCR_FOSC_FREQ_V 0x000000FFU +#define PCR_FOSC_FREQ_S 0 +/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ +#define PCR_PLL_FREQ 0x000003FFU +#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) +#define PCR_PLL_FREQ_V 0x000003FFU +#define PCR_PLL_FREQ_S 8 + +/** PCR_PLL_DIV_CLK_EN_REG register + * SPLL DIV clock-gating configuration register + */ +#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124) +/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; + * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_240M_CLK_EN (BIT(0)) +#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) +#define PCR_PLL_240M_CLK_EN_V 0x00000001U +#define PCR_PLL_240M_CLK_EN_S 0 +/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_160M_CLK_EN (BIT(1)) +#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) +#define PCR_PLL_160M_CLK_EN_V 0x00000001U +#define PCR_PLL_160M_CLK_EN_S 1 +/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_120M_CLK_EN (BIT(2)) +#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) +#define PCR_PLL_120M_CLK_EN_V 0x00000001U +#define PCR_PLL_120M_CLK_EN_S 2 +/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_80M_CLK_EN (BIT(3)) +#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) +#define PCR_PLL_80M_CLK_EN_V 0x00000001U +#define PCR_PLL_80M_CLK_EN_S 3 +/** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; + * This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_60M_CLK_EN (BIT(4)) +#define PCR_PLL_60M_CLK_EN_M (PCR_PLL_60M_CLK_EN_V << PCR_PLL_60M_CLK_EN_S) +#define PCR_PLL_60M_CLK_EN_V 0x00000001U +#define PCR_PLL_60M_CLK_EN_S 4 +/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_48M_CLK_EN (BIT(5)) +#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) +#define PCR_PLL_48M_CLK_EN_V 0x00000001U +#define PCR_PLL_48M_CLK_EN_S 5 +/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_40M_CLK_EN (BIT(6)) +#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) +#define PCR_PLL_40M_CLK_EN_V 0x00000001U +#define PCR_PLL_40M_CLK_EN_S 6 +/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_20M_CLK_EN (BIT(7)) +#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) +#define PCR_PLL_20M_CLK_EN_V 0x00000001U +#define PCR_PLL_20M_CLK_EN_S 7 +/** PCR_PLL_12M_CLK_EN : R/W; bitpos: [8]; default: 1; + * This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ +#define PCR_PLL_12M_CLK_EN (BIT(8)) +#define PCR_PLL_12M_CLK_EN_M (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S) +#define PCR_PLL_12M_CLK_EN_V 0x00000001U +#define PCR_PLL_12M_CLK_EN_S 8 + +/** PCR_CTRL_CLK_OUT_EN_REG register + * CLK_OUT_EN configuration register + */ +#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128) +/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ +#define PCR_CLK20_OEN (BIT(0)) +#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) +#define PCR_CLK20_OEN_V 0x00000001U +#define PCR_CLK20_OEN_S 0 +/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ +#define PCR_CLK22_OEN (BIT(1)) +#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) +#define PCR_CLK22_OEN_V 0x00000001U +#define PCR_CLK22_OEN_S 1 +/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ +#define PCR_CLK44_OEN (BIT(2)) +#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) +#define PCR_CLK44_OEN_V 0x00000001U +#define PCR_CLK44_OEN_S 2 +/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ +#define PCR_CLK_BB_OEN (BIT(3)) +#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) +#define PCR_CLK_BB_OEN_V 0x00000001U +#define PCR_CLK_BB_OEN_S 3 +/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ +#define PCR_CLK80_OEN (BIT(4)) +#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) +#define PCR_CLK80_OEN_V 0x00000001U +#define PCR_CLK80_OEN_S 4 +/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ +#define PCR_CLK160_OEN (BIT(5)) +#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) +#define PCR_CLK160_OEN_V 0x00000001U +#define PCR_CLK160_OEN_S 5 +/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ +#define PCR_CLK_320M_OEN (BIT(6)) +#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) +#define PCR_CLK_320M_OEN_V 0x00000001U +#define PCR_CLK_320M_OEN_S 6 +/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; + * Reserved + */ +#define PCR_CLK_ADC_INF_OEN (BIT(7)) +#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) +#define PCR_CLK_ADC_INF_OEN_V 0x00000001U +#define PCR_CLK_ADC_INF_OEN_S 7 +/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; + * Reserved + */ +#define PCR_CLK_DAC_CPU_OEN (BIT(8)) +#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) +#define PCR_CLK_DAC_CPU_OEN_V 0x00000001U +#define PCR_CLK_DAC_CPU_OEN_S 8 +/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; + * Reserved + */ +#define PCR_CLK40X_BB_OEN (BIT(9)) +#define PCR_CLK40X_BB_OEN_M (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S) +#define PCR_CLK40X_BB_OEN_V 0x00000001U +#define PCR_CLK40X_BB_OEN_S 9 +/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; + * Set 1 to enable xtal clock + */ +#define PCR_CLK_XTAL_OEN (BIT(10)) +#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) +#define PCR_CLK_XTAL_OEN_V 0x00000001U +#define PCR_CLK_XTAL_OEN_S 10 + +/** PCR_CTRL_TICK_CONF_REG register + * TICK configuration register + */ +#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c) +/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ +#define PCR_XTAL_TICK_NUM 0x000000FFU +#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) +#define PCR_XTAL_TICK_NUM_V 0x000000FFU +#define PCR_XTAL_TICK_NUM_S 0 +/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ +#define PCR_FOSC_TICK_NUM 0x000000FFU +#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) +#define PCR_FOSC_TICK_NUM_V 0x000000FFU +#define PCR_FOSC_TICK_NUM_S 8 +/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ +#define PCR_TICK_ENABLE (BIT(16)) +#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) +#define PCR_TICK_ENABLE_V 0x00000001U +#define PCR_TICK_ENABLE_S 16 +/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ +#define PCR_RST_TICK_CNT (BIT(17)) +#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) +#define PCR_RST_TICK_CNT_V 0x00000001U +#define PCR_RST_TICK_CNT_S 17 + +/** PCR_CTRL_32K_CONF_REG register + * 32KHz clock configuration register + */ +#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130) +/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by timergroup. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ +#define PCR_32K_SEL 0x00000003U +#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) +#define PCR_32K_SEL_V 0x00000003U +#define PCR_32K_SEL_S 0 + +/** PCR_SRAM_POWER_CONF_0_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134) +/** PCR_ROM_FORCE_PU : R/W; bitpos: [2:0]; default: 7; + * Set this bit to force power up ROM + */ +#define PCR_ROM_FORCE_PU 0x00000007U +#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) +#define PCR_ROM_FORCE_PU_V 0x00000007U +#define PCR_ROM_FORCE_PU_S 0 +/** PCR_ROM_FORCE_PD : R/W; bitpos: [5:3]; default: 0; + * Set this bit to force power down ROM. + */ +#define PCR_ROM_FORCE_PD 0x00000007U +#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) +#define PCR_ROM_FORCE_PD_V 0x00000007U +#define PCR_ROM_FORCE_PD_S 3 +/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [8:6]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ +#define PCR_ROM_CLKGATE_FORCE_ON 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) +#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000007U +#define PCR_ROM_CLKGATE_FORCE_ON_S 6 + +/** PCR_SRAM_POWER_CONF_1_REG register + * HP SRAM/ROM configuration register + */ +#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138) +/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15; + * Set this bit to force power up SRAM + */ +#define PCR_SRAM_FORCE_PU 0x0000000FU +#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) +#define PCR_SRAM_FORCE_PU_V 0x0000000FU +#define PCR_SRAM_FORCE_PU_S 0 +/** PCR_SRAM_FORCE_PD : R/W; bitpos: [13:10]; default: 0; + * Set this bit to force power down SRAM. + */ +#define PCR_SRAM_FORCE_PD 0x0000000FU +#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) +#define PCR_SRAM_FORCE_PD_V 0x0000000FU +#define PCR_SRAM_FORCE_PD_S 10 +/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [23:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ +#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) +#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000000FU +#define PCR_SRAM_CLKGATE_FORCE_ON_S 20 + +/** PCR_SEC_CONF_REG register + * xxxx + */ +#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c) +/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * xxxx + */ +#define PCR_SEC_CLK_SEL 0x00000003U +#define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) +#define PCR_SEC_CLK_SEL_V 0x00000003U +#define PCR_SEC_CLK_SEL_S 0 +/** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset sec module + */ +#define PCR_SEC_RST_EN (BIT(2)) +#define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) +#define PCR_SEC_RST_EN_V 0x00000001U +#define PCR_SEC_RST_EN_S 2 + +/** PCR_BUS_CLK_UPDATE_REG register + * xxxx + */ +#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148) +/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; + * xxxx + */ +#define PCR_BUS_CLOCK_UPDATE (BIT(0)) +#define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) +#define PCR_BUS_CLOCK_UPDATE_V 0x00000001U +#define PCR_BUS_CLOCK_UPDATE_S 0 + +/** PCR_SAR_CLK_DIV_REG register + * xxxx + */ +#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c) +/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * xxxx + */ +#define PCR_SAR2_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) +#define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR2_CLK_DIV_NUM_S 0 +/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; + * xxxx + */ +#define PCR_SAR1_CLK_DIV_NUM 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) +#define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU +#define PCR_SAR1_CLK_DIV_NUM_S 8 + +/** PCR_PWDET_SAR_CLK_CONF_REG register + * xxxx + */ +#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150) +/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) +#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU +#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 +/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1; + * xxxx + */ +#define PCR_PWDET_SAR_CLK_EN (BIT(8)) +#define PCR_PWDET_SAR_CLK_EN_M (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S) +#define PCR_PWDET_SAR_CLK_EN_V 0x00000001U +#define PCR_PWDET_SAR_CLK_EN_S 8 + +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register + */ +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x154) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock + */ +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 + +/** PCR_USB_OTG_CONF_REG register + * USB_OTG configuration register + */ +#define PCR_USB_OTG_CONF_REG (DR_REG_PCR_BASE + 0x158) +/** PCR_USB_OTG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_otg bus clock + */ +#define PCR_USB_OTG_CLK_EN (BIT(0)) +#define PCR_USB_OTG_CLK_EN_M (PCR_USB_OTG_CLK_EN_V << PCR_USB_OTG_CLK_EN_S) +#define PCR_USB_OTG_CLK_EN_V 0x00000001U +#define PCR_USB_OTG_CLK_EN_S 0 +/** PCR_USB_OTG_ADP_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_otg core adp + */ +#define PCR_USB_OTG_ADP_RST_EN (BIT(1)) +#define PCR_USB_OTG_ADP_RST_EN_M (PCR_USB_OTG_ADP_RST_EN_V << PCR_USB_OTG_ADP_RST_EN_S) +#define PCR_USB_OTG_ADP_RST_EN_V 0x00000001U +#define PCR_USB_OTG_ADP_RST_EN_S 1 +/** PCR_USB_OTG_MISC_RST_EN : R/W; bitpos: [2]; default: 0; + * Set 0 to reset usb_otg misc + */ +#define PCR_USB_OTG_MISC_RST_EN (BIT(2)) +#define PCR_USB_OTG_MISC_RST_EN_M (PCR_USB_OTG_MISC_RST_EN_V << PCR_USB_OTG_MISC_RST_EN_S) +#define PCR_USB_OTG_MISC_RST_EN_V 0x00000001U +#define PCR_USB_OTG_MISC_RST_EN_S 2 +/** PCR_USB_OTG_GLOBAL_RST_EN : R/W; bitpos: [3]; default: 0; + * Set 0 to reset usb_otg module + */ +#define PCR_USB_OTG_GLOBAL_RST_EN (BIT(3)) +#define PCR_USB_OTG_GLOBAL_RST_EN_M (PCR_USB_OTG_GLOBAL_RST_EN_V << PCR_USB_OTG_GLOBAL_RST_EN_S) +#define PCR_USB_OTG_GLOBAL_RST_EN_V 0x00000001U +#define PCR_USB_OTG_GLOBAL_RST_EN_S 3 + +/** PCR_USB_OTG_CLK_CONF_REG register + * USB_OTG func clk configuration register + */ +#define PCR_USB_OTG_CLK_CONF_REG (DR_REG_PCR_BASE + 0x15c) +/** PCR_USB_OTG_PHY_REFCLK_SEL : R/W; bitpos: [20]; default: 1; + * Set 1 to sel 12m pll clock, set 0 to sel pad clock + */ +#define PCR_USB_OTG_PHY_REFCLK_SEL (BIT(20)) +#define PCR_USB_OTG_PHY_REFCLK_SEL_M (PCR_USB_OTG_PHY_REFCLK_SEL_V << PCR_USB_OTG_PHY_REFCLK_SEL_S) +#define PCR_USB_OTG_PHY_REFCLK_SEL_V 0x00000001U +#define PCR_USB_OTG_PHY_REFCLK_SEL_S 20 +/** PCR_USB_OTG_PHY_REFCLK_EN : R/W; bitpos: [21]; default: 1; + * Set 1 to enable usb_otg_phy_refclk clock + */ +#define PCR_USB_OTG_PHY_REFCLK_EN (BIT(21)) +#define PCR_USB_OTG_PHY_REFCLK_EN_M (PCR_USB_OTG_PHY_REFCLK_EN_V << PCR_USB_OTG_PHY_REFCLK_EN_S) +#define PCR_USB_OTG_PHY_REFCLK_EN_V 0x00000001U +#define PCR_USB_OTG_PHY_REFCLK_EN_S 21 +/** PCR_USB_OTG_ADP_CLK_SEL : R/W; bitpos: [23:22]; default: 0; + * Set 0 to sel clock from gpio_matrix, set 1 to sel osc32k, set 2 to sel xtal32k, set + * 3 to sel ext32k + */ +#define PCR_USB_OTG_ADP_CLK_SEL 0x00000003U +#define PCR_USB_OTG_ADP_CLK_SEL_M (PCR_USB_OTG_ADP_CLK_SEL_V << PCR_USB_OTG_ADP_CLK_SEL_S) +#define PCR_USB_OTG_ADP_CLK_SEL_V 0x00000003U +#define PCR_USB_OTG_ADP_CLK_SEL_S 22 +/** PCR_USB_OTG_ADP_CLK_EN : R/W; bitpos: [24]; default: 1; + * Set 1 to enable usb_otg_adp_clk clock + */ +#define PCR_USB_OTG_ADP_CLK_EN (BIT(24)) +#define PCR_USB_OTG_ADP_CLK_EN_M (PCR_USB_OTG_ADP_CLK_EN_V << PCR_USB_OTG_ADP_CLK_EN_S) +#define PCR_USB_OTG_ADP_CLK_EN_V 0x00000001U +#define PCR_USB_OTG_ADP_CLK_EN_S 24 + +/** PCR_BS_CONF_REG register + * BS configuration register + */ +#define PCR_BS_CONF_REG (DR_REG_PCR_BASE + 0x160) +/** PCR_BS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable bs clock + */ +#define PCR_BS_CLK_EN (BIT(0)) +#define PCR_BS_CLK_EN_M (PCR_BS_CLK_EN_V << PCR_BS_CLK_EN_S) +#define PCR_BS_CLK_EN_V 0x00000001U +#define PCR_BS_CLK_EN_S 0 +/** PCR_BS_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset bs module + */ +#define PCR_BS_RST_EN (BIT(1)) +#define PCR_BS_RST_EN_M (PCR_BS_RST_EN_V << PCR_BS_RST_EN_S) +#define PCR_BS_RST_EN_V 0x00000001U +#define PCR_BS_RST_EN_S 1 + +/** PCR_BS_FUNC_CONF_REG register + * BS_FUNC_CLK configuration register + */ +#define PCR_BS_FUNC_CONF_REG (DR_REG_PCR_BASE + 0x164) +/** PCR_BS_TX_RST_EN : R/W; bitpos: [23]; default: 0; + * Set 0 to reset bs tx module + */ +#define PCR_BS_TX_RST_EN (BIT(23)) +#define PCR_BS_TX_RST_EN_M (PCR_BS_TX_RST_EN_V << PCR_BS_TX_RST_EN_S) +#define PCR_BS_TX_RST_EN_V 0x00000001U +#define PCR_BS_TX_RST_EN_S 23 +/** PCR_BS_RX_RST_EN : R/W; bitpos: [24]; default: 0; + * Set 0 to reset bs rx module + */ +#define PCR_BS_RX_RST_EN (BIT(24)) +#define PCR_BS_RX_RST_EN_M (PCR_BS_RX_RST_EN_V << PCR_BS_RX_RST_EN_S) +#define PCR_BS_RX_RST_EN_V 0x00000001U +#define PCR_BS_RX_RST_EN_S 24 + +/** PCR_TIMERGROUP_WDT_CONF_REG register + * TIMERGROUP_WDT configuration register + */ +#define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x168) +/** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 wdt module + */ +#define PCR_TG0_WDT_RST_EN (BIT(0)) +#define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) +#define PCR_TG0_WDT_RST_EN_V 0x00000001U +#define PCR_TG0_WDT_RST_EN_S 0 +/** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 wdt module + */ +#define PCR_TG1_WDT_RST_EN (BIT(1)) +#define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) +#define PCR_TG1_WDT_RST_EN_V 0x00000001U +#define PCR_TG1_WDT_RST_EN_S 1 + +/** PCR_TIMERGROUP_XTAL_CONF_REG register + * TIMERGROUP1 configuration register + */ +#define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x16c) +/** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 xtal clock domain + */ +#define PCR_TG0_XTAL_RST_EN (BIT(0)) +#define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) +#define PCR_TG0_XTAL_RST_EN_V 0x00000001U +#define PCR_TG0_XTAL_RST_EN_S 0 +/** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 xtal clock domain + */ +#define PCR_TG1_XTAL_RST_EN (BIT(1)) +#define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) +#define PCR_TG1_XTAL_RST_EN_V 0x00000001U +#define PCR_TG1_XTAL_RST_EN_S 1 + +/** PCR_KM_CONF_REG register + * Key Manager configuration register + */ +#define PCR_KM_CONF_REG (DR_REG_PCR_BASE + 0x170) +/** PCR_KM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable km clock + */ +#define PCR_KM_CLK_EN (BIT(0)) +#define PCR_KM_CLK_EN_M (PCR_KM_CLK_EN_V << PCR_KM_CLK_EN_S) +#define PCR_KM_CLK_EN_V 0x00000001U +#define PCR_KM_CLK_EN_S 0 +/** PCR_KM_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 0 to reset km module + */ +#define PCR_KM_RST_EN (BIT(1)) +#define PCR_KM_RST_EN_M (PCR_KM_RST_EN_V << PCR_KM_RST_EN_S) +#define PCR_KM_RST_EN_V 0x00000001U +#define PCR_KM_RST_EN_S 1 +/** PCR_KM_READY : RO; bitpos: [2]; default: 1; + * Query this field after reset km module + */ +#define PCR_KM_READY (BIT(2)) +#define PCR_KM_READY_M (PCR_KM_READY_V << PCR_KM_READY_S) +#define PCR_KM_READY_V 0x00000001U +#define PCR_KM_READY_S 2 + +/** PCR_DATE_REG register + * Date register. + */ +#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) +/** PCR_DATE : R/W; bitpos: [27:0]; default: 36720976; + * PCR version information. + */ +#define PCR_DATE 0x0FFFFFFFU +#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) +#define PCR_DATE_V 0x0FFFFFFFU +#define PCR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pcr_struct.h b/components/soc/esp32c5/include/soc/pcr_struct.h new file mode 100644 index 0000000000..5557b89f1e --- /dev/null +++ b/components/soc/esp32c5/include/soc/pcr_struct.h @@ -0,0 +1,2233 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of uart0_conf register + * UART0 configuration register + */ +typedef union { + struct { + /** uart0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart0 apb clock + */ + uint32_t uart0_clk_en:1; + /** uart0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart0 module + */ + uint32_t uart0_rst_en:1; + /** uart0_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart0 module + */ + uint32_t uart0_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_conf_reg_t; + +/** Type of uart0_sclk_conf register + * UART0_SCLK configuration register + */ +typedef union { + struct { + /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_a:6; + /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_b:6; + /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart0 function clock. + */ + uint32_t uart0_sclk_div_num:8; + /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz + */ + uint32_t uart0_sclk_sel:2; + /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart0_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart0_sclk_conf_reg_t; + +/** Type of uart0_pd_ctrl register + * UART0 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART0 memory. + */ + uint32_t uart0_mem_force_pu:1; + /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART0 memory. + */ + uint32_t uart0_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart0_pd_ctrl_reg_t; + +/** Type of uart1_conf register + * UART1 configuration register + */ +typedef union { + struct { + /** uart1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uart1 apb clock + */ + uint32_t uart1_clk_en:1; + /** uart1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uart1 module + */ + uint32_t uart1_rst_en:1; + /** uart1_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uart1 module + */ + uint32_t uart1_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_conf_reg_t; + +/** Type of uart1_sclk_conf register + * UART1_SCLK configuration register + */ +typedef union { + struct { + /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_a:6; + /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_b:6; + /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the uart1 function clock. + */ + uint32_t uart1_sclk_div_num:8; + /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz + */ + uint32_t uart1_sclk_sel:2; + /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable uart0 function clock + */ + uint32_t uart1_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_uart1_sclk_conf_reg_t; + +/** Type of uart1_pd_ctrl register + * UART1 power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down UART1 memory. + */ + uint32_t uart1_mem_force_pu:1; + /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up UART1 memory. + */ + uint32_t uart1_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uart1_pd_ctrl_reg_t; + +/** Type of mspi_conf register + * MSPI configuration register + */ +typedef union { + struct { + /** mspi_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mspi apb clock and mspi pll clock + */ + uint32_t mspi_clk_en:1; + /** mspi_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mspi module + */ + uint32_t mspi_rst_en:1; + /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable mspi pll clock + */ + uint32_t mspi_pll_clk_en:1; + /** mspi_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset mspi module + */ + uint32_t mspi_ready:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_mspi_conf_reg_t; + +/** Type of mspi_clk_conf register + * MSPI_CLK configuration register + */ +typedef union { + struct { + /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0; + * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed + * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a + * low-speed clock-source such as XTAL/FOSC. + */ + uint32_t mspi_fast_div_num:8; + /** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0; + * set this field to select clock-source. + */ + uint32_t mspi_func_clk_sel:2; + /** mspi_func_clk_en : R/W; bitpos: [10]; default: 1; + * Set 1 to enable mspi func clock + */ + uint32_t mspi_func_clk_en:1; + /** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0; + * Set 0 to reset axi_clock domain of mspi module + */ + uint32_t mspi_axi_rst_en:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} pcr_mspi_clk_conf_reg_t; + +/** Type of i2c_conf register + * I2C configuration register + */ +typedef union { + struct { + /** i2c_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2c apb clock + */ + uint32_t i2c_clk_en:1; + /** i2c_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2c module + */ + uint32_t i2c_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_i2c_conf_reg_t; + +/** Type of i2c_sclk_conf register + * I2C_SCLK configuration register + */ +typedef union { + struct { + /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_a:6; + /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_b:6; + /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the i2c function clock. + */ + uint32_t i2c_sclk_div_num:8; + /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t i2c_sclk_sel:1; + uint32_t reserved_21:1; + /** i2c_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2c function clock + */ + uint32_t i2c_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2c_sclk_conf_reg_t; + +/** Type of twai0_conf register + * TWAI0 configuration register + */ +typedef union { + struct { + /** twai0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai0 apb clock + */ + uint32_t twai0_clk_en:1; + /** twai0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai0 module + */ + uint32_t twai0_rst_en:1; + /** twai0_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset twai0 module + */ + uint32_t twai0_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_twai0_conf_reg_t; + +/** Type of twai0_func_clk_conf register + * TWAI0_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t twai0_func_clk_sel:1; + uint32_t reserved_21:1; + /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai0 function clock + */ + uint32_t twai0_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_twai0_func_clk_conf_reg_t; + +/** Type of twai1_conf register + * TWAI1 configuration register + */ +typedef union { + struct { + /** twai1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable twai1 apb clock + */ + uint32_t twai1_clk_en:1; + /** twai1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai1 module + */ + uint32_t twai1_rst_en:1; + /** twai1_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset twai1 module + */ + uint32_t twai1_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_twai1_conf_reg_t; + +/** Type of twai1_func_clk_conf register + * TWAI1_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** twai1_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t twai1_func_clk_sel:1; + uint32_t reserved_21:1; + /** twai1_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable twai1 function clock + */ + uint32_t twai1_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_twai1_func_clk_conf_reg_t; + +/** Type of uhci_conf register + * UHCI configuration register + */ +typedef union { + struct { + /** uhci_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable uhci clock + */ + uint32_t uhci_clk_en:1; + /** uhci_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset uhci module + */ + uint32_t uhci_rst_en:1; + /** uhci_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset uhci module + */ + uint32_t uhci_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_uhci_conf_reg_t; + +/** Type of rmt_conf register + * RMT configuration register + */ +typedef union { + struct { + /** rmt_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rmt apb clock + */ + uint32_t rmt_clk_en:1; + /** rmt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rmt module + */ + uint32_t rmt_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_rmt_conf_reg_t; + +/** Type of rmt_sclk_conf register + * RMT_SCLK configuration register + */ +typedef union { + struct { + /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_a:6; + /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_b:6; + /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1; + * The integral part of the frequency divider factor of the rmt function clock. + */ + uint32_t rmt_sclk_div_num:8; + /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1; + * set this field to select clock-source. 0: XTAL, 1(default): FOSC, 2: 80MHz + */ + uint32_t rmt_sclk_sel:2; + /** rmt_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable rmt function clock + */ + uint32_t rmt_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_rmt_sclk_conf_reg_t; + +/** Type of ledc_conf register + * LEDC configuration register + */ +typedef union { + struct { + /** ledc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ledc apb clock + */ + uint32_t ledc_clk_en:1; + /** ledc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ledc module + */ + uint32_t ledc_rst_en:1; + /** ledc_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ledc module + */ + uint32_t ledc_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ledc_conf_reg_t; + +/** Type of ledc_sclk_conf register + * LEDC_SCLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 80MHz, 2: FOSC, 3: XTAL. + */ + uint32_t ledc_sclk_sel:2; + /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable ledc function clock + */ + uint32_t ledc_sclk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_ledc_sclk_conf_reg_t; + +/** Type of timergroup0_conf register + * TIMERGROUP0 configuration register + */ +typedef union { + struct { + /** tg0_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group0 apb clock + */ + uint32_t tg0_clk_en:1; + /** tg0_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group0 module + */ + uint32_t tg0_rst_en:1; + /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group0 wdt module + */ + uint32_t tg0_wdt_ready:1; + /** tg0_timer0_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group0 timer0 module + */ + uint32_t tg0_timer0_ready:1; + /** tg0_timer1_ready : RO; bitpos: [4]; default: 1; + * reserved + */ + uint32_t tg0_timer1_ready:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_timergroup0_conf_reg_t; + +/** Type of timergroup0_timer_clk_conf register + * TIMERGROUP0_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg0_timer_clk_sel:2; + /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 timer clock + */ + uint32_t tg0_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_timer_clk_conf_reg_t; + +/** Type of timergroup0_wdt_clk_conf register + * TIMERGROUP0_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg0_wdt_clk_sel:2; + /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg0_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup0_wdt_clk_conf_reg_t; + +/** Type of timergroup1_conf register + * TIMERGROUP1 configuration register + */ +typedef union { + struct { + /** tg1_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable timer_group1 apb clock + */ + uint32_t tg1_clk_en:1; + /** tg1_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 module + */ + uint32_t tg1_rst_en:1; + /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset timer_group1 wdt module + */ + uint32_t tg1_wdt_ready:1; + /** tg1_timer0_ready : RO; bitpos: [3]; default: 1; + * Query this field after reset timer_group1 timer0 module + */ + uint32_t tg1_timer0_ready:1; + /** tg1_timer1_ready : RO; bitpos: [4]; default: 1; + * reserved + */ + uint32_t tg1_timer1_ready:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_timergroup1_conf_reg_t; + +/** Type of timergroup1_timer_clk_conf register + * TIMERGROUP1_TIMER_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg1_timer_clk_sel:2; + /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group1 timer clock + */ + uint32_t tg1_timer_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_timer_clk_conf_reg_t; + +/** Type of timergroup1_wdt_clk_conf register + * TIMERGROUP1_WDT_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t tg1_wdt_clk_sel:2; + /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable timer_group0 wdt clock + */ + uint32_t tg1_wdt_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_timergroup1_wdt_clk_conf_reg_t; + +/** Type of systimer_conf register + * SYSTIMER configuration register + */ +typedef union { + struct { + /** systimer_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable systimer apb clock + */ + uint32_t systimer_clk_en:1; + /** systimer_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset systimer module + */ + uint32_t systimer_rst_en:1; + /** systimer_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset systimer module + */ + uint32_t systimer_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_systimer_conf_reg_t; + +/** Type of systimer_func_clk_conf register + * SYSTIMER_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: FOSC. + */ + uint32_t systimer_func_clk_sel:1; + uint32_t reserved_21:1; + /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable systimer function clock + */ + uint32_t systimer_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_systimer_func_clk_conf_reg_t; + +/** Type of i2s_conf register + * I2S configuration register + */ +typedef union { + struct { + /** i2s_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable i2s apb clock + */ + uint32_t i2s_clk_en:1; + /** i2s_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset i2s module + */ + uint32_t i2s_rst_en:1; + /** i2s_rx_ready : RO; bitpos: [2]; default: 1; + * Query this field before using i2s rx function, after reset i2s module + */ + uint32_t i2s_rx_ready:1; + /** i2s_tx_ready : RO; bitpos: [3]; default: 1; + * Query this field before using i2s tx function, after reset i2s module + */ + uint32_t i2s_tx_ready:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_i2s_conf_reg_t; + +/** Type of i2s_tx_clkm_conf register + * I2S_TX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be + * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= + * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * + * (n+1)-div] + y * (n+1)-div. + */ + uint32_t i2s_tx_clkm_div_num:8; + /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: + * I2S_MCLK_in. + */ + uint32_t i2s_tx_clkm_sel:2; + /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_tx function clock + */ + uint32_t i2s_tx_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_i2s_tx_clkm_conf_reg_t; + +/** Type of i2s_tx_clkm_div_conf register + * I2S_TX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_TX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_tx_clkm_div_z:9; + /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_TX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_tx_clkm_div_y:9; + /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_tx_clkm_div_x:9; + /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_TX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_tx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_tx_clkm_div_conf_reg_t; + +/** Type of i2s_rx_clkm_conf register + * I2S_RX_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; + * Integral I2S clock divider value + */ + uint32_t i2s_rx_clkm_div_num:8; + /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + */ + uint32_t i2s_rx_clkm_sel:2; + /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable i2s_rx function clock + */ + uint32_t i2s_rx_clkm_en:1; + /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; + * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx + */ + uint32_t i2s_mclk_sel:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_i2s_rx_clkm_conf_reg_t; + +/** Type of i2s_rx_clkm_div_conf register + * I2S_RX_CLKM_DIV configuration register + */ +typedef union { + struct { + /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of + * I2S_RX_CLKM_DIV_Z is (a-b). + */ + uint32_t i2s_rx_clkm_div_z:9; + /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of + * I2S_RX_CLKM_DIV_Y is (a%(a-b)). + */ + uint32_t i2s_rx_clkm_div_y:9; + /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value + * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + */ + uint32_t i2s_rx_clkm_div_x:9; + /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; + * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of + * I2S_RX_CLKM_DIV_YN1 is 1. + */ + uint32_t i2s_rx_clkm_div_yn1:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_i2s_rx_clkm_div_conf_reg_t; + +/** Type of saradc_conf register + * SARADC configuration register + */ +typedef union { + struct { + /** saradc_clk_en : R/W; bitpos: [0]; default: 1; + * no use + */ + uint32_t saradc_clk_en:1; + /** saradc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset function_register of saradc module + */ + uint32_t saradc_rst_en:1; + /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable saradc apb clock + */ + uint32_t saradc_reg_clk_en:1; + /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; + * Set 0 to reset apb_register of saradc module + */ + uint32_t saradc_reg_rst_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_saradc_conf_reg_t; + +/** Type of saradc_clkm_conf register + * SARADC_CLKM configuration register + */ +typedef union { + struct { + /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0; + * The denominator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_a:6; + /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0; + * The numerator of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_b:6; + /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the saradc function clock. + */ + uint32_t saradc_clkm_div_num:8; + /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t saradc_clkm_sel:2; + /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable saradc function clock + */ + uint32_t saradc_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_saradc_clkm_conf_reg_t; + +/** Type of tsens_clk_conf register + * TSENS_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0(default): FOSC, 1: XTAL. + */ + uint32_t tsens_clk_sel:1; + uint32_t reserved_21:1; + /** tsens_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable tsens clock + */ + uint32_t tsens_clk_en:1; + /** tsens_rst_en : R/W; bitpos: [23]; default: 0; + * Set 0 to reset tsens module + */ + uint32_t tsens_rst_en:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_tsens_clk_conf_reg_t; + +/** Type of usb_device_conf register + * USB_DEVICE configuration register + */ +typedef union { + struct { + /** usb_device_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_device clock + */ + uint32_t usb_device_clk_en:1; + /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_device module + */ + uint32_t usb_device_rst_en:1; + /** usb_device_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset usb_device module + */ + uint32_t usb_device_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_usb_device_conf_reg_t; + +/** Type of intmtx_conf register + * INTMTX configuration register + */ +typedef union { + struct { + /** intmtx_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable intmtx clock + */ + uint32_t intmtx_clk_en:1; + /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset intmtx module + */ + uint32_t intmtx_rst_en:1; + /** intmtx_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset intmtx module + */ + uint32_t intmtx_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_intmtx_conf_reg_t; + +/** Type of pcnt_conf register + * PCNT configuration register + */ +typedef union { + struct { + /** pcnt_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pcnt clock + */ + uint32_t pcnt_clk_en:1; + /** pcnt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pcnt module + */ + uint32_t pcnt_rst_en:1; + /** pcnt_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset pcnt module + */ + uint32_t pcnt_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_pcnt_conf_reg_t; + +/** Type of etm_conf register + * ETM configuration register + */ +typedef union { + struct { + /** etm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable etm clock + */ + uint32_t etm_clk_en:1; + /** etm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset etm module + */ + uint32_t etm_rst_en:1; + /** etm_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset etm module + */ + uint32_t etm_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_etm_conf_reg_t; + +/** Type of pwm_conf register + * PWM configuration register + */ +typedef union { + struct { + /** pwm_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable pwm clock + */ + uint32_t pwm_clk_en:1; + /** pwm_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset pwm module + */ + uint32_t pwm_rst_en:1; + /** pwm_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset pwm module + */ + uint32_t pwm_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_pwm_conf_reg_t; + +/** Type of pwm_clk_conf register + * PWM_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** pwm_div_num : R/W; bitpos: [19:12]; default: 4; + * The integral part of the frequency divider factor of the pwm function clock. + */ + uint32_t pwm_div_num:8; + /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): do not select anyone clock, 1: + * 160MHz, 2: XTAL, 3: FOSC. + */ + uint32_t pwm_clkm_sel:2; + /** pwm_clkm_en : R/W; bitpos: [22]; default: 1; + * set this field as 1 to activate pwm clkm. + */ + uint32_t pwm_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pwm_clk_conf_reg_t; + +/** Type of parl_io_conf register + * PARL_IO configuration register + */ +typedef union { + struct { + /** parl_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable parl apb clock + */ + uint32_t parl_clk_en:1; + /** parl_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset parl apb reg + */ + uint32_t parl_rst_en:1; + /** parl_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset parl module + */ + uint32_t parl_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_parl_io_conf_reg_t; + +/** Type of parl_clk_rx_conf register + * PARL_CLK_RX configuration register + */ +typedef union { + struct { + /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl rx clock. + */ + uint32_t parl_clk_rx_div_num:16; + /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ + uint32_t parl_clk_rx_sel:2; + /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl rx clock + */ + uint32_t parl_clk_rx_en:1; + /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl rx module + */ + uint32_t parl_rx_rst_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} pcr_parl_clk_rx_conf_reg_t; + +/** Type of parl_clk_tx_conf register + * PARL_CLK_TX configuration register + */ +typedef union { + struct { + /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0; + * The integral part of the frequency divider factor of the parl tx clock. + */ + uint32_t parl_clk_tx_div_num:16; + /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: + * user clock from pad. + */ + uint32_t parl_clk_tx_sel:2; + /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1; + * Set 1 to enable parl tx clock + */ + uint32_t parl_clk_tx_en:1; + /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0; + * Set 0 to reset parl tx module + */ + uint32_t parl_tx_rst_en:1; + uint32_t reserved_20:12; + }; + uint32_t val; +} pcr_parl_clk_tx_conf_reg_t; + +/** Type of pvt_monitor_conf register + * PVT_MONITOR configuration register + */ +typedef union { + struct { + /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable apb clock of pvt module + */ + uint32_t pvt_monitor_clk_en:1; + /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset all pvt monitor module + */ + uint32_t pvt_monitor_rst_en:1; + /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1; + * Set 1 to enable function clock of modem pvt module + */ + uint32_t pvt_monitor_site1_clk_en:1; + /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1; + * Set 1 to enable function clock of cpu pvt module + */ + uint32_t pvt_monitor_site2_clk_en:1; + /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1; + * Set 1 to enable function clock of hp_peri pvt module + */ + uint32_t pvt_monitor_site3_clk_en:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} pcr_pvt_monitor_conf_reg_t; + +/** Type of pvt_monitor_func_clk_conf register + * PVT_MONITOR function clock configuration register + */ +typedef union { + struct { + /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0; + * The integral part of the frequency divider factor of the pvt_monitor function clock. + */ + uint32_t pvt_monitor_func_clk_div_num:4; + uint32_t reserved_4:16; + /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; + * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL + * divided by 3. + */ + uint32_t pvt_monitor_func_clk_sel:1; + uint32_t reserved_21:1; + /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable source clock of pvt sitex + */ + uint32_t pvt_monitor_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_pvt_monitor_func_clk_conf_reg_t; + +/** Type of gdma_conf register + * GDMA configuration register + */ +typedef union { + struct { + /** gdma_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable gdma clock + */ + uint32_t gdma_clk_en:1; + /** gdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset gdma module + */ + uint32_t gdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_gdma_conf_reg_t; + +/** Type of spi2_conf register + * SPI2 configuration register + */ +typedef union { + struct { + /** spi2_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable spi2 apb clock + */ + uint32_t spi2_clk_en:1; + /** spi2_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset spi2 module + */ + uint32_t spi2_rst_en:1; + /** spi2_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset spi2 module + */ + uint32_t spi2_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_spi2_conf_reg_t; + +/** Type of spi2_clkm_conf register + * SPI2_CLKM configuration register + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** spi2_clkm_div_num : R/W; bitpos: [19:12]; default: 0; + * The integral part of the frequency divider factor of the spi2_mst clock. + */ + uint32_t spi2_clkm_div_num:8; + /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: + * reserved. + */ + uint32_t spi2_clkm_sel:2; + /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable spi2 function clock + */ + uint32_t spi2_clkm_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_spi2_clkm_conf_reg_t; + +/** Type of aes_conf register + * AES configuration register + */ +typedef union { + struct { + /** aes_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable aes clock + */ + uint32_t aes_clk_en:1; + /** aes_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset aes module + */ + uint32_t aes_rst_en:1; + /** aes_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset aes module + */ + uint32_t aes_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_aes_conf_reg_t; + +/** Type of sha_conf register + * SHA configuration register + */ +typedef union { + struct { + /** sha_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sha clock + */ + uint32_t sha_clk_en:1; + /** sha_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sha module + */ + uint32_t sha_rst_en:1; + /** sha_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset sha module + */ + uint32_t sha_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sha_conf_reg_t; + +/** Type of rsa_conf register + * RSA configuration register + */ +typedef union { + struct { + /** rsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable rsa clock + */ + uint32_t rsa_clk_en:1; + /** rsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset rsa module + */ + uint32_t rsa_rst_en:1; + /** rsa_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset rsa module + */ + uint32_t rsa_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_conf_reg_t; + +/** Type of rsa_pd_ctrl register + * RSA power control register + */ +typedef union { + struct { + /** rsa_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down rsa internal memory. + */ + uint32_t rsa_mem_pd:1; + /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up rsa internal memory + */ + uint32_t rsa_mem_force_pu:1; + /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down rsa internal memory. + */ + uint32_t rsa_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_rsa_pd_ctrl_reg_t; + +/** Type of ecc_conf register + * ECC configuration register + */ +typedef union { + struct { + /** ecc_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecc clock + */ + uint32_t ecc_clk_en:1; + /** ecc_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecc module + */ + uint32_t ecc_rst_en:1; + /** ecc_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ecc module + */ + uint32_t ecc_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_conf_reg_t; + +/** Type of ecc_pd_ctrl register + * ECC power control register + */ +typedef union { + struct { + /** ecc_mem_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to power down ecc internal memory. + */ + uint32_t ecc_mem_pd:1; + /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power up ecc internal memory + */ + uint32_t ecc_mem_force_pu:1; + /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down ecc internal memory. + */ + uint32_t ecc_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecc_pd_ctrl_reg_t; + +/** Type of ds_conf register + * DS configuration register + */ +typedef union { + struct { + /** ds_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ds clock + */ + uint32_t ds_clk_en:1; + /** ds_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ds module + */ + uint32_t ds_rst_en:1; + /** ds_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ds module + */ + uint32_t ds_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ds_conf_reg_t; + +/** Type of hmac_conf register + * HMAC configuration register + */ +typedef union { + struct { + /** hmac_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable hmac clock + */ + uint32_t hmac_clk_en:1; + /** hmac_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset hmac module + */ + uint32_t hmac_rst_en:1; + /** hmac_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset hmac module + */ + uint32_t hmac_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_hmac_conf_reg_t; + +/** Type of ecdsa_conf register + * ECDSA configuration register + */ +typedef union { + struct { + /** ecdsa_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable ecdsa clock + */ + uint32_t ecdsa_clk_en:1; + /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset ecdsa module + */ + uint32_t ecdsa_rst_en:1; + /** ecdsa_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset ecdsa module + */ + uint32_t ecdsa_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_ecdsa_conf_reg_t; + +/** Type of iomux_conf register + * IOMUX configuration register + */ +typedef union { + struct { + /** iomux_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable iomux apb clock + */ + uint32_t iomux_clk_en:1; + /** iomux_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset iomux module + */ + uint32_t iomux_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_iomux_conf_reg_t; + +/** Type of iomux_clk_conf register + * IOMUX_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; + * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: + * FOSC, 3(default): XTAL. + */ + uint32_t iomux_func_clk_sel:2; + /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; + * Set 1 to enable iomux function clock + */ + uint32_t iomux_func_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} pcr_iomux_clk_conf_reg_t; + +/** Type of mem_monitor_conf register + * MEM_MONITOR configuration register + */ +typedef union { + struct { + /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable mem_monitor clock + */ + uint32_t mem_monitor_clk_en:1; + /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset mem_monitor module + */ + uint32_t mem_monitor_rst_en:1; + /** mem_monitor_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset mem_monitor module + */ + uint32_t mem_monitor_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_mem_monitor_conf_reg_t; + +/** Type of regdma_conf register + * REGDMA configuration register + */ +typedef union { + struct { + /** regdma_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable regdma clock + */ + uint32_t regdma_clk_en:1; + /** regdma_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset regdma module + */ + uint32_t regdma_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_regdma_conf_reg_t; + +/** Type of trace_conf register + * TRACE configuration register + */ +typedef union { + struct { + /** trace_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable trace clock + */ + uint32_t trace_clk_en:1; + /** trace_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset trace module + */ + uint32_t trace_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_trace_conf_reg_t; + +/** Type of assist_conf register + * ASSIST configuration register + */ +typedef union { + struct { + /** assist_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable assist clock + */ + uint32_t assist_clk_en:1; + /** assist_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset assist module + */ + uint32_t assist_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_assist_conf_reg_t; + +/** Type of cache_conf register + * CACHE configuration register + */ +typedef union { + struct { + /** cache_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable cache clock + */ + uint32_t cache_clk_en:1; + /** cache_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cache module + */ + uint32_t cache_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_cache_conf_reg_t; + +/** Type of modem_conf register + * MODEM_APB configuration register + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** modem_rst_en : R/W; bitpos: [2]; default: 0; + * Set this file as 1 to reset modem-subsystem. + */ + uint32_t modem_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_modem_conf_reg_t; + +/** Type of timeout_conf register + * TIMEOUT configuration register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset cpu_peri timeout module + */ + uint32_t cpu_timeout_rst_en:1; + /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset hp_peri timeout module and hp_modem timeout module + */ + uint32_t hp_timeout_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_timeout_conf_reg_t; + +/** Type of sysclk_conf register + * SYSCLK configuration register + */ +typedef union { + struct { + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; + /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; + * This field is used to select clock source. 0: XTAL, 1: FOSC, 2: 160M_PLL, 3: + * 240M_PLL. + */ + uint32_t soc_clk_sel:2; + uint32_t reserved_18:6; + /** clk_xtal_freq : RO; bitpos: [30:24]; default: 40; + * This field indicates the frequency(MHz) of XTAL. + */ + uint32_t clk_xtal_freq:7; + uint32_t reserved_31:1; + }; + uint32_t val; +} pcr_sysclk_conf_reg_t; + +/** Type of cpu_waiti_conf register + * CPU_WAITI configuration register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; + * Set 1 to force cpu_waiti_clk enable. + */ + uint32_t cpu_wait_mode_force_on:1; + /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; + * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk + * will close + */ + uint32_t cpu_waiti_delay_num:4; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_waiti_conf_reg_t; + +/** Type of cpu_freq_conf register + * CPU_FREQ configuration register + */ +typedef union { + struct { + /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is + * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed + * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. + */ + uint32_t cpu_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_cpu_freq_conf_reg_t; + +/** Type of ahb_freq_conf register + * AHB_FREQ configuration register + */ +typedef union { + struct { + /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; + * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is + * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for + * low-speed clock-source such as XTAL/FOSC, and should be used together with + * PCR_CPU_DIV_NUM. + */ + uint32_t ahb_div_num:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pcr_ahb_freq_conf_reg_t; + +/** Type of apb_freq_conf register + * APB_FREQ configuration register + */ +typedef union { + struct { + /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0; + * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be + * automatically down to clk_apb_decrease only when no access is on apb-bus, and will + * recover to the previous frequency when a new access appears on apb-bus. Set as one + * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note + * that enable this function will reduce performance. Users can set this field as zero + * to disable the auto-decrease-apb-freq function. By default, this function is + * disable. + */ + uint32_t apb_decrease_div_num:8; + /** apb_div_num : R/W; bitpos: [15:8]; default: 0; + * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is + * div1(default)/div2/div4 of clk_ahb. + */ + uint32_t apb_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_apb_freq_conf_reg_t; + +/** Type of pll_div_clk_en register + * SPLL DIV clock-gating configuration register + */ +typedef union { + struct { + /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1; + * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_240m_clk_en:1; + /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; + * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_160m_clk_en:1; + /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; + * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_120m_clk_en:1; + /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; + * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_80m_clk_en:1; + /** pll_60m_clk_en : R/W; bitpos: [4]; default: 1; + * This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_60m_clk_en:1; + /** pll_48m_clk_en : R/W; bitpos: [5]; default: 1; + * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_48m_clk_en:1; + /** pll_40m_clk_en : R/W; bitpos: [6]; default: 1; + * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_40m_clk_en:1; + /** pll_20m_clk_en : R/W; bitpos: [7]; default: 1; + * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_20m_clk_en:1; + /** pll_12m_clk_en : R/W; bitpos: [8]; default: 1; + * This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close, + * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. + */ + uint32_t pll_12m_clk_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_pll_div_clk_en_reg_t; + +/** Type of ctrl_clk_out_en register + * CLK_OUT_EN configuration register + */ +typedef union { + struct { + /** clk20_oen : R/W; bitpos: [0]; default: 1; + * Set 1 to enable 20m clock + */ + uint32_t clk20_oen:1; + /** clk22_oen : R/W; bitpos: [1]; default: 1; + * Set 1 to enable 22m clock + */ + uint32_t clk22_oen:1; + /** clk44_oen : R/W; bitpos: [2]; default: 1; + * Set 1 to enable 44m clock + */ + uint32_t clk44_oen:1; + /** clk_bb_oen : R/W; bitpos: [3]; default: 1; + * Set 1 to enable bb clock + */ + uint32_t clk_bb_oen:1; + /** clk80_oen : R/W; bitpos: [4]; default: 1; + * Set 1 to enable 80m clock + */ + uint32_t clk80_oen:1; + /** clk160_oen : R/W; bitpos: [5]; default: 1; + * Set 1 to enable 160m clock + */ + uint32_t clk160_oen:1; + /** clk_320m_oen : R/W; bitpos: [6]; default: 1; + * Set 1 to enable 320m clock + */ + uint32_t clk_320m_oen:1; + /** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1; + * Reserved + */ + uint32_t clk_adc_inf_oen:1; + /** clk_dac_cpu_oen : R/W; bitpos: [8]; default: 1; + * Reserved + */ + uint32_t clk_dac_cpu_oen:1; + /** clk40x_bb_oen : R/W; bitpos: [9]; default: 1; + * Reserved + */ + uint32_t clk40x_bb_oen:1; + /** clk_xtal_oen : R/W; bitpos: [10]; default: 1; + * Set 1 to enable xtal clock + */ + uint32_t clk_xtal_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} pcr_ctrl_clk_out_en_reg_t; + +/** Type of ctrl_tick_conf register + * TICK configuration register + */ +typedef union { + struct { + /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ + uint32_t xtal_tick_num:8; + /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ + uint32_t fosc_tick_num:8; + /** tick_enable : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ + uint32_t tick_enable:1; + /** rst_tick_cnt : R/W; bitpos: [17]; default: 0; + * ******* Description *********** + */ + uint32_t rst_tick_cnt:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_ctrl_tick_conf_reg_t; + +/** Type of ctrl_32k_conf register + * 32KHz clock configuration register + */ +typedef union { + struct { + /** 32k_sel : R/W; bitpos: [1:0]; default: 0; + * This field indicates which one 32KHz clock will be used by timergroup. 0: + * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. + */ + uint32_t 32k_sel:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_ctrl_32k_conf_reg_t; + +/** Type of sram_power_conf_0 register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + /** rom_force_pu : R/W; bitpos: [2:0]; default: 7; + * Set this bit to force power up ROM + */ + uint32_t rom_force_pu:3; + /** rom_force_pd : R/W; bitpos: [5:3]; default: 0; + * Set this bit to force power down ROM. + */ + uint32_t rom_force_pd:3; + /** rom_clkgate_force_on : R/W; bitpos: [8:6]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A + * gate-clock will be used when accessing the ROM. + */ + uint32_t rom_clkgate_force_on:3; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_sram_power_conf_0_reg_t; + +/** Type of sram_power_conf_1 register + * HP SRAM/ROM configuration register + */ +typedef union { + struct { + /** sram_force_pu : R/W; bitpos: [3:0]; default: 15; + * Set this bit to force power up SRAM + */ + uint32_t sram_force_pu:4; + uint32_t reserved_4:6; + /** sram_force_pd : R/W; bitpos: [13:10]; default: 0; + * Set this bit to force power down SRAM. + */ + uint32_t sram_force_pd:4; + uint32_t reserved_14:6; + /** sram_clkgate_force_on : R/W; bitpos: [23:20]; default: 0; + * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A + * gate-clock will be used when accessing the SRAM. + */ + uint32_t sram_clkgate_force_on:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} pcr_sram_power_conf_1_reg_t; + +/** Type of sec_conf register + * xxxx + */ +typedef union { + struct { + /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; + * xxxx + */ + uint32_t sec_clk_sel:2; + /** sec_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset sec module + */ + uint32_t sec_rst_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sec_conf_reg_t; + +/** Type of bus_clk_update register + * xxxx + */ +typedef union { + struct { + /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; + * xxxx + */ + uint32_t bus_clock_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pcr_bus_clk_update_reg_t; + +/** Type of sar_clk_div register + * xxxx + */ +typedef union { + struct { + /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; + * xxxx + */ + uint32_t sar2_clk_div_num:8; + /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; + * xxxx + */ + uint32_t sar1_clk_div_num:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pcr_sar_clk_div_reg_t; + +/** Type of pwdet_sar_clk_conf register + * xxxx + */ +typedef union { + struct { + /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; + * xxxx + */ + uint32_t pwdet_sar_clk_div_num:8; + /** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1; + * xxxx + */ + uint32_t pwdet_sar_clk_en:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} pcr_pwdet_sar_clk_conf_reg_t; + +/** Type of sdio_slave_conf register + * SDIO_SLAVE configuration register + */ +typedef union { + struct { + /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock + */ + uint32_t sdio_slave_clk_en:1; + /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset sdio_slave module + */ + uint32_t sdio_slave_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_sdio_slave_conf_reg_t; + +/** Type of usb_otg_conf register + * USB_OTG configuration register + */ +typedef union { + struct { + /** usb_otg_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable usb_otg bus clock + */ + uint32_t usb_otg_clk_en:1; + /** usb_otg_adp_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset usb_otg core adp + */ + uint32_t usb_otg_adp_rst_en:1; + /** usb_otg_misc_rst_en : R/W; bitpos: [2]; default: 0; + * Set 0 to reset usb_otg misc + */ + uint32_t usb_otg_misc_rst_en:1; + /** usb_otg_global_rst_en : R/W; bitpos: [3]; default: 0; + * Set 0 to reset usb_otg module + */ + uint32_t usb_otg_global_rst_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pcr_usb_otg_conf_reg_t; + +/** Type of usb_otg_clk_conf register + * USB_OTG func clk configuration register + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** usb_otg_phy_refclk_sel : R/W; bitpos: [20]; default: 1; + * Set 1 to sel 12m pll clock, set 0 to sel pad clock + */ + uint32_t usb_otg_phy_refclk_sel:1; + /** usb_otg_phy_refclk_en : R/W; bitpos: [21]; default: 1; + * Set 1 to enable usb_otg_phy_refclk clock + */ + uint32_t usb_otg_phy_refclk_en:1; + /** usb_otg_adp_clk_sel : R/W; bitpos: [23:22]; default: 0; + * Set 0 to sel clock from gpio_matrix, set 1 to sel osc32k, set 2 to sel xtal32k, set + * 3 to sel ext32k + */ + uint32_t usb_otg_adp_clk_sel:2; + /** usb_otg_adp_clk_en : R/W; bitpos: [24]; default: 1; + * Set 1 to enable usb_otg_adp_clk clock + */ + uint32_t usb_otg_adp_clk_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} pcr_usb_otg_clk_conf_reg_t; + +/** Type of bs_conf register + * BS configuration register + */ +typedef union { + struct { + /** bs_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable bs clock + */ + uint32_t bs_clk_en:1; + /** bs_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset bs module + */ + uint32_t bs_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_bs_conf_reg_t; + +/** Type of bs_func_conf register + * BS_FUNC_CLK configuration register + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bs_tx_rst_en : R/W; bitpos: [23]; default: 0; + * Set 0 to reset bs tx module + */ + uint32_t bs_tx_rst_en:1; + /** bs_rx_rst_en : R/W; bitpos: [24]; default: 0; + * Set 0 to reset bs rx module + */ + uint32_t bs_rx_rst_en:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} pcr_bs_func_conf_reg_t; + +/** Type of timergroup_wdt_conf register + * TIMERGROUP_WDT configuration register + */ +typedef union { + struct { + /** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 wdt module + */ + uint32_t tg0_wdt_rst_en:1; + /** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 wdt module + */ + uint32_t tg1_wdt_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_timergroup_wdt_conf_reg_t; + +/** Type of timergroup_xtal_conf register + * TIMERGROUP1 configuration register + */ +typedef union { + struct { + /** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0; + * Set 0 to reset timer_group0 xtal clock domain + */ + uint32_t tg0_xtal_rst_en:1; + /** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset timer_group1 xtal clock domain + */ + uint32_t tg1_xtal_rst_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pcr_timergroup_xtal_conf_reg_t; + +/** Type of km_conf register + * Key Manager configuration register + */ +typedef union { + struct { + /** km_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable km clock + */ + uint32_t km_clk_en:1; + /** km_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset km module + */ + uint32_t km_rst_en:1; + /** km_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset km module + */ + uint32_t km_ready:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_km_conf_reg_t; + + +/** Group: Frequency Statistics Register */ +/** Type of sysclk_freq_query_0 register + * SYSCLK frequency query 0 register + */ +typedef union { + struct { + /** fosc_freq : HRO; bitpos: [7:0]; default: 8; + * This field indicates the frequency(MHz) of FOSC. + */ + uint32_t fosc_freq:8; + /** pll_freq : HRO; bitpos: [17:8]; default: 96; + * This field indicates the frequency(MHz) of SPLL. + */ + uint32_t pll_freq:10; + uint32_t reserved_18:14; + }; + uint32_t val; +} pcr_sysclk_freq_query_0_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36720976; + * PCR version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pcr_date_reg_t; + + +typedef struct { + volatile pcr_uart0_conf_reg_t uart0_conf; + volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf; + volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl; + volatile pcr_uart1_conf_reg_t uart1_conf; + volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf; + volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl; + volatile pcr_mspi_conf_reg_t mspi_conf; + volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; + volatile pcr_i2c_conf_reg_t i2c_conf; + volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; + volatile pcr_twai0_conf_reg_t twai0_conf; + volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf; + volatile pcr_twai1_conf_reg_t twai1_conf; + volatile pcr_twai1_func_clk_conf_reg_t twai1_func_clk_conf; + volatile pcr_uhci_conf_reg_t uhci_conf; + volatile pcr_rmt_conf_reg_t rmt_conf; + volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf; + volatile pcr_ledc_conf_reg_t ledc_conf; + volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf; + volatile pcr_timergroup0_conf_reg_t timergroup0_conf; + volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf; + volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf; + volatile pcr_timergroup1_conf_reg_t timergroup1_conf; + volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf; + volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf; + volatile pcr_systimer_conf_reg_t systimer_conf; + volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf; + volatile pcr_i2s_conf_reg_t i2s_conf; + volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf; + volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf; + volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf; + volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf; + volatile pcr_saradc_conf_reg_t saradc_conf; + volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf; + volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf; + volatile pcr_usb_device_conf_reg_t usb_device_conf; + volatile pcr_intmtx_conf_reg_t intmtx_conf; + volatile pcr_pcnt_conf_reg_t pcnt_conf; + volatile pcr_etm_conf_reg_t etm_conf; + volatile pcr_pwm_conf_reg_t pwm_conf; + volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf; + volatile pcr_parl_io_conf_reg_t parl_io_conf; + volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf; + volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf; + volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf; + volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf; + volatile pcr_gdma_conf_reg_t gdma_conf; + volatile pcr_spi2_conf_reg_t spi2_conf; + volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf; + volatile pcr_aes_conf_reg_t aes_conf; + volatile pcr_sha_conf_reg_t sha_conf; + volatile pcr_rsa_conf_reg_t rsa_conf; + volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl; + volatile pcr_ecc_conf_reg_t ecc_conf; + volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl; + volatile pcr_ds_conf_reg_t ds_conf; + volatile pcr_hmac_conf_reg_t hmac_conf; + volatile pcr_ecdsa_conf_reg_t ecdsa_conf; + volatile pcr_iomux_conf_reg_t iomux_conf; + volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf; + volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf; + volatile pcr_regdma_conf_reg_t regdma_conf; + volatile pcr_trace_conf_reg_t trace_conf; + volatile pcr_assist_conf_reg_t assist_conf; + volatile pcr_cache_conf_reg_t cache_conf; + volatile pcr_modem_conf_reg_t modem_conf; + volatile pcr_timeout_conf_reg_t timeout_conf; + volatile pcr_sysclk_conf_reg_t sysclk_conf; + volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf; + volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf; + volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf; + volatile pcr_apb_freq_conf_reg_t apb_freq_conf; + volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0; + volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en; + volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en; + volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf; + volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf; + volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; + volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; + volatile pcr_sec_conf_reg_t sec_conf; + uint32_t reserved_140[2]; + volatile pcr_bus_clk_update_reg_t bus_clk_update; + volatile pcr_sar_clk_div_reg_t sar_clk_div; + volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; + volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf; + volatile pcr_usb_otg_conf_reg_t usb_otg_conf; + volatile pcr_usb_otg_clk_conf_reg_t usb_otg_clk_conf; + volatile pcr_bs_conf_reg_t bs_conf; + volatile pcr_bs_func_conf_reg_t bs_func_conf; + volatile pcr_timergroup_wdt_conf_reg_t timergroup_wdt_conf; + volatile pcr_timergroup_xtal_conf_reg_t timergroup_xtal_conf; + volatile pcr_km_conf_reg_t km_conf; + uint32_t reserved_174[930]; + volatile pcr_date_reg_t date; +} pcr_dev_t; + +extern pcr_dev_t PCR; + +#ifndef __cplusplus +_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pmu_reg.h b/components/soc/esp32c5/include/soc/pmu_reg.h new file mode 100644 index 0000000000..0713f07ed4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pmu_reg.h @@ -0,0 +1,3359 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMU_HP_ACTIVE_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) +/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 +/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 +/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 + +/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) +/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) +/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) +/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) +/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 +/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 +/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 + +/** PMU_HP_ACTIVE_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) +/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(26)) +#define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) +#define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_ISO_EN_S 26 +/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_RETENTION (BIT(27)) +#define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) +#define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_RETENTION_S 27 +/** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BB_I2C (BIT(28)) +#define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) +#define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BB_I2C_S 28 +/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 29 +/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL (BIT(30)) +#define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_S 30 + +/** PMU_HP_ACTIVE_BIAS_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) +#define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) +#define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DBG_ATTEN 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_M (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S) +#define PMU_HP_ACTIVE_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_S 26 +/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CUR (BIT(30)) +#define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) +#define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CUR_S 30 +/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) +#define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) +#define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 + +/** PMU_HP_ACTIVE_BACKUP_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 +/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 +/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 + +/** PMU_HP_ACTIVE_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) +/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_SYSCLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) +/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 +/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; + * need_des + */ +#define PMU_LP_DBIAS_VOL 0x0000001FU +#define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) +#define PMU_LP_DBIAS_VOL_V 0x0000001FU +#define PMU_LP_DBIAS_VOL_S 4 +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; + * need_des + */ +#define PMU_HP_DBIAS_VOL 0x0000001FU +#define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) +#define PMU_HP_DBIAS_VOL_V 0x0000001FU +#define PMU_HP_DBIAS_VOL_S 9 +/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U +#define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 +/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DIG_DBIAS_INIT (BIT(15)) +#define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) +#define PMU_DIG_DBIAS_INIT_V 0x00000001U +#define PMU_DIG_DBIAS_INIT_S 15 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_ACTIVE_XTAL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) +#define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) +#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTAL_S 31 + +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 26 +/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 27 +/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) +#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) +#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BB_I2C_S 28 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 30 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DBG_ATTEN 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_M (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S) +#define PMU_HP_MODEM_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_S 26 +/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) +/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 +/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) +#define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 +/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 + +/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) +/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) +/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_SLEEP_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) +/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) +/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 +/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 +/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) +#define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 + +/** PMU_HP_SLEEP_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) +/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_ISO_EN (BIT(26)) +#define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) +#define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_SLEEP_I2C_ISO_EN_S 26 +/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_RETENTION (BIT(27)) +#define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) +#define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U +#define PMU_HP_SLEEP_I2C_RETENTION_S 27 +/** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BB_I2C (BIT(28)) +#define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) +#define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BB_I2C_S 28 +/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 29 +/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL (BIT(30)) +#define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) +#define PMU_HP_SLEEP_XPD_BBPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_S 30 + +/** PMU_HP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) +#define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_M (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S) +#define PMU_HP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_S 26 +/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CUR (BIT(30)) +#define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) +#define PMU_HP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_HP_SLEEP_PD_CUR_S 30 +/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) +#define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_HP_SLEEP_BACKUP_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) +/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 +/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 + +/** PMU_HP_SLEEP_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) +/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) +/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) +#define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 +/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_SLEEP_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) +#define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) +/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) +#define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_HP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) +/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) +#define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) +#define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_RC32K_S 29 +/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) +#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_LP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) +/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_LP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) +#define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL_S 31 + +/** PMU_LP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) +#define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_LP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) +/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) +#define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) +#define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_RC32K_S 29 +/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) +#define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) +#define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_M (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S) +#define PMU_LP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_S 26 +/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_CUR (BIT(30)) +#define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) +#define PMU_LP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_LP_SLEEP_PD_CUR_S 30 +/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) +#define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_LP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_IMM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) +/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(0)) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 0 +/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(1)) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 1 +/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_RETENTION (BIT(2)) +#define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) +#define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_LOW_I2C_RETENTION_S 2 +/** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BB_I2C (BIT(3)) +#define PMU_TIE_LOW_XPD_BB_I2C_M (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S) +#define PMU_TIE_LOW_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BB_I2C_S 3 +/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(4)) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_I2C_S 4 +/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL (BIT(5)) +#define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S) +#define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_S 5 +/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTAL (BIT(6)) +#define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) +#define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTAL_S 6 +/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(25)) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 25 +/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(26)) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 26 +/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_RETENTION (BIT(27)) +#define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) +#define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_HIGH_I2C_RETENTION_S 27 +/** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BB_I2C (BIT(28)) +#define PMU_TIE_HIGH_XPD_BB_I2C_M (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S) +#define PMU_TIE_HIGH_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BB_I2C_S 28 +/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(29)) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 29 +/** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL (BIT(30)) +#define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S) +#define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_S 30 +/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) +#define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) +#define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_XTAL_S 31 + +/** PMU_IMM_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) +/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) +#define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) +#define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_SWITCH_S 28 +/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) +#define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) +#define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_ICG_SLP_SEL_S 29 +/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) +#define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) +#define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 +/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U +#define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 + +/** PMU_IMM_HP_FUNC_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) +/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 + +/** PMU_IMM_HP_APB_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) +/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) +#define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_APB_EN_S 31 + +/** PMU_IMM_MODEM_ICG_REG register + * need_des + */ +#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) +/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 + +/** PMU_IMM_LP_ICG_REG register + * need_des + */ +#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) +/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 +/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 + +/** PMU_IMM_PAD_HOLD_ALL_REG register + * need_des + */ +#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 +/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 +/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 +/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 + +/** PMU_IMM_I2C_ISO_REG register + * need_des + */ +#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) +/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) +#define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) +#define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_HIGH_I2C_ISO_EN_S 30 +/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) +#define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) +#define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_LOW_I2C_ISO_EN_S 31 + +/** PMU_POWER_WAIT_TIMER0_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) +/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) +#define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_S 5 +/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) +#define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_S 14 +/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_HP_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) +#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER1_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) +#define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_S 9 +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; + * need_des + */ +#define PMU_DG_LP_POWERUP_TIMER 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) +#define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_S 16 +/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_LP_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) +#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_S 23 + +/** PMU_POWER_PD_TOP_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_RESET (BIT(0)) +#define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) +#define PMU_FORCE_TOP_RESET_V 0x00000001U +#define PMU_FORCE_TOP_RESET_S 0 +/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_ISO (BIT(1)) +#define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) +#define PMU_FORCE_TOP_ISO_V 0x00000001U +#define PMU_FORCE_TOP_ISO_S 1 +/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_PU (BIT(2)) +#define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) +#define PMU_FORCE_TOP_PU_V 0x00000001U +#define PMU_FORCE_TOP_PU_S 2 +/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_RESET (BIT(3)) +#define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) +#define PMU_FORCE_TOP_NO_RESET_V 0x00000001U +#define PMU_FORCE_TOP_NO_RESET_S 3 +/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_ISO (BIT(4)) +#define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) +#define PMU_FORCE_TOP_NO_ISO_V 0x00000001U +#define PMU_FORCE_TOP_NO_ISO_S 4 +/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_PD (BIT(5)) +#define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) +#define PMU_FORCE_TOP_PD_V 0x00000001U +#define PMU_FORCE_TOP_PD_S 5 +/** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_TOP_MASK 0x0000001FU +#define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) +#define PMU_PD_TOP_MASK_V 0x0000001FU +#define PMU_PD_TOP_MASK_S 6 +/** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_TOP_PD_MASK 0x0000001FU +#define PMU_PD_TOP_PD_MASK_M (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S) +#define PMU_PD_TOP_PD_MASK_V 0x0000001FU +#define PMU_PD_TOP_PD_MASK_S 27 + +/** PMU_POWER_PD_HPAON_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +/** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_RESET (BIT(0)) +#define PMU_FORCE_HP_AON_RESET_M (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S) +#define PMU_FORCE_HP_AON_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_RESET_S 0 +/** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_ISO (BIT(1)) +#define PMU_FORCE_HP_AON_ISO_M (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S) +#define PMU_FORCE_HP_AON_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_ISO_S 1 +/** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_PU (BIT(2)) +#define PMU_FORCE_HP_AON_PU_M (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S) +#define PMU_FORCE_HP_AON_PU_V 0x00000001U +#define PMU_FORCE_HP_AON_PU_S 2 +/** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_AON_NO_RESET_M (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S) +#define PMU_FORCE_HP_AON_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_RESET_S 3 +/** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_AON_NO_ISO_M (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S) +#define PMU_FORCE_HP_AON_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_ISO_S 4 +/** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_PD (BIT(5)) +#define PMU_FORCE_HP_AON_PD_M (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S) +#define PMU_FORCE_HP_AON_PD_V 0x00000001U +#define PMU_FORCE_HP_AON_PD_S 5 +/** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_MASK 0x0000001FU +#define PMU_PD_HP_AON_MASK_M (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S) +#define PMU_PD_HP_AON_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_MASK_S 6 +/** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_PD_MASK 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_M (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S) +#define PMU_PD_HP_AON_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_S 27 + +/** PMU_POWER_PD_HPCPU_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_RESET (BIT(0)) +#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) +#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_RESET_S 0 +/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_ISO (BIT(1)) +#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) +#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_ISO_S 1 +/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_PU (BIT(2)) +#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) +#define PMU_FORCE_HP_CPU_PU_V 0x00000001U +#define PMU_FORCE_HP_CPU_PU_S 2 +/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) +#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_RESET_S 3 +/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) +#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_ISO_S 4 +/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_PD (BIT(5)) +#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) +#define PMU_FORCE_HP_CPU_PD_V 0x00000001U +#define PMU_FORCE_HP_CPU_PD_S 5 +/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_MASK 0x0000001FU +#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) +#define PMU_PD_HP_CPU_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_MASK_S 6 +/** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_PD_MASK 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_M (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S) +#define PMU_PD_HP_CPU_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_S 27 + +/** PMU_POWER_PD_HPWIFI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_RESET (BIT(0)) +#define PMU_FORCE_HP_WIFI_RESET_M (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S) +#define PMU_FORCE_HP_WIFI_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_RESET_S 0 +/** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_ISO (BIT(1)) +#define PMU_FORCE_HP_WIFI_ISO_M (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S) +#define PMU_FORCE_HP_WIFI_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_ISO_S 1 +/** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PU (BIT(2)) +#define PMU_FORCE_HP_WIFI_PU_M (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S) +#define PMU_FORCE_HP_WIFI_PU_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PU_S 2 +/** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_WIFI_NO_RESET_M (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S) +#define PMU_FORCE_HP_WIFI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_RESET_S 3 +/** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_WIFI_NO_ISO_M (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S) +#define PMU_FORCE_HP_WIFI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_ISO_S 4 +/** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PD (BIT(5)) +#define PMU_FORCE_HP_WIFI_PD_M (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S) +#define PMU_FORCE_HP_WIFI_PD_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PD_S 5 +/** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_M (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S) +#define PMU_PD_HP_WIFI_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_S 6 +/** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_PD_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_M (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S) +#define PMU_PD_HP_WIFI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_S 27 + +/** PMU_POWER_PD_LPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_RESET (BIT(0)) +#define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) +#define PMU_FORCE_LP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_RESET_S 0 +/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_ISO (BIT(1)) +#define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) +#define PMU_FORCE_LP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_ISO_S 1 +/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_PU (BIT(2)) +#define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) +#define PMU_FORCE_LP_PERI_PU_V 0x00000001U +#define PMU_FORCE_LP_PERI_PU_S 2 +/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) +#define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_RESET_S 3 +/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) +#define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_ISO_S 4 +/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_PD (BIT(5)) +#define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) +#define PMU_FORCE_LP_PERI_PD_V 0x00000001U +#define PMU_FORCE_LP_PERI_PD_S 5 + +/** PMU_POWER_PD_MEM_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) +#define PMU_FORCE_HP_MEM_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_S 0 +/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_PD 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) +#define PMU_FORCE_HP_MEM_PD_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_S 4 +/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) +#define PMU_FORCE_HP_MEM_NO_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_S 24 +/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_PU 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) +#define PMU_FORCE_HP_MEM_PU_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_S 28 + +/** PMU_POWER_PD_MEM_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) +/** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_M (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S) +#define PMU_PD_HP_MEM2_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_S 0 +/** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_M (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S) +#define PMU_PD_HP_MEM1_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_S 5 +/** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_M (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S) +#define PMU_PD_HP_MEM0_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_S 10 +/** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_M (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S) +#define PMU_PD_HP_MEM2_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_S 17 +/** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_M (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S) +#define PMU_PD_HP_MEM1_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_S 22 +/** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_M (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S) +#define PMU_PD_HP_MEM0_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_S 27 + +/** PMU_POWER_HP_PAD_REG register + * need_des + */ +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) +/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 +/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) +#define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_ISO_ALL_S 1 + +/** PMU_POWER_VDD_SPI_CNTL_REG register + * need_des + */ +#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; + * need_des + */ +#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) +#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_S 18 +/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; + * need_des + */ +#define PMU_VDD_SPI_PWR_SW 0x00000003U +#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) +#define PMU_VDD_SPI_PWR_SW_V 0x00000003U +#define PMU_VDD_SPI_PWR_SW_S 29 +/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) +#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) +#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U +#define PMU_VDD_SPI_PWR_SEL_SW_S 31 + +/** PMU_POWER_CK_WAIT_CNTL_REG register + * need_des + */ +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; + * need_des + */ +#define PMU_WAIT_XTL_STABLE 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_M (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S) +#define PMU_WAIT_XTL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_S 0 +/** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; + * need_des + */ +#define PMU_WAIT_PLL_STABLE 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_M (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S) +#define PMU_WAIT_PLL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_S 16 + +/** PMU_SLP_WAKEUP_CNTL0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLEEP_REQ (BIT(31)) +#define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) +#define PMU_SLEEP_REQ_V 0x00000001U +#define PMU_SLEEP_REQ_S 31 + +/** PMU_SLP_WAKEUP_CNTL1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) +#define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_S 0 +/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_EN (BIT(31)) +#define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) +#define PMU_SLP_REJECT_EN_V 0x00000001U +#define PMU_SLP_REJECT_EN_S 31 + +/** PMU_SLP_WAKEUP_CNTL2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_ENA 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) +#define PMU_WAKEUP_ENA_V 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_S 0 + +/** PMU_SLP_WAKEUP_CNTL3_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define PMU_LP_MIN_SLP_VAL 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) +#define PMU_LP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_S 0 +/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; + * need_des + */ +#define PMU_HP_MIN_SLP_VAL 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) +#define PMU_HP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_S 8 +/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SLEEP_PRT_SEL 0x00000003U +#define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) +#define PMU_SLEEP_PRT_SEL_V 0x00000003U +#define PMU_SLEEP_PRT_SEL_S 16 + +/** PMU_SLP_WAKEUP_CNTL4_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) +/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) +#define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) +#define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U +#define PMU_SLP_REJECT_CAUSE_CLR_S 31 + +/** PMU_SLP_WAKEUP_CNTL5_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) +/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_MODEM_WAIT_TARGET 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) +#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) +#define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_S 24 + +/** PMU_SLP_WAKEUP_CNTL6_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) +/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) +#define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_S 0 +/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) +#define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_S 30 + +/** PMU_SLP_WAKEUP_CNTL7_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) +/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; + * need_des + */ +#define PMU_ANA_WAIT_TARGET 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) +#define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_S 16 + +/** PMU_SLP_WAKEUP_STATUS0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) +/** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_CAUSE 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) +#define PMU_WAKEUP_CAUSE_V 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) +/** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_REJECT_CAUSE 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) +#define PMU_REJECT_CAUSE_V 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_S 0 + +/** PMU_HP_CK_POWERON_REG register + * need_des + */ +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) +/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; + * need_des + */ +#define PMU_I2C_POR_WAIT_TARGET 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) +#define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_S 0 + +/** PMU_HP_CK_CNTL_REG register + * need_des + */ +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) +/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; + * need_des + */ +#define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) +#define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_S 0 +/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; + * need_des + */ +#define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) +#define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_S 8 + +/** PMU_POR_STATUS_REG register + * need_des + */ +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_POR_DONE (BIT(31)) +#define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) +#define PMU_POR_DONE_V 0x00000001U +#define PMU_POR_DONE_S 31 + +/** PMU_RF_PWC_REG register + * need_des + */ +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) +/** PMU_XPD_TC5G_I2C : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_XPD_TC5G_I2C (BIT(24)) +#define PMU_XPD_TC5G_I2C_M (PMU_XPD_TC5G_I2C_V << PMU_XPD_TC5G_I2C_S) +#define PMU_XPD_TC5G_I2C_V 0x00000001U +#define PMU_XPD_TC5G_I2C_S 24 +/** PMU_XPD_RX5G_I2C : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_XPD_RX5G_I2C (BIT(25)) +#define PMU_XPD_RX5G_I2C_M (PMU_XPD_RX5G_I2C_V << PMU_XPD_RX5G_I2C_S) +#define PMU_XPD_RX5G_I2C_V 0x00000001U +#define PMU_XPD_RX5G_I2C_S 25 +/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_PERIF_I2C_RSTB (BIT(26)) +#define PMU_PERIF_I2C_RSTB_M (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S) +#define PMU_PERIF_I2C_RSTB_V 0x00000001U +#define PMU_PERIF_I2C_RSTB_S 26 +/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define PMU_XPD_PERIF_I2C (BIT(27)) +#define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) +#define PMU_XPD_PERIF_I2C_V 0x00000001U +#define PMU_XPD_PERIF_I2C_S 27 +/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_XPD_TXRF_I2C (BIT(28)) +#define PMU_XPD_TXRF_I2C_M (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S) +#define PMU_XPD_TXRF_I2C_V 0x00000001U +#define PMU_XPD_TXRF_I2C_S 28 +/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_XPD_RFRX_PBUS (BIT(29)) +#define PMU_XPD_RFRX_PBUS_M (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S) +#define PMU_XPD_RFRX_PBUS_V 0x00000001U +#define PMU_XPD_RFRX_PBUS_S 29 +/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_XPD_CKGEN_I2C (BIT(30)) +#define PMU_XPD_CKGEN_I2C_M (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S) +#define PMU_XPD_CKGEN_I2C_V 0x00000001U +#define PMU_XPD_CKGEN_I2C_S 30 +/** PMU_XPD_PLL_I2C : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_XPD_PLL_I2C (BIT(31)) +#define PMU_XPD_PLL_I2C_M (PMU_XPD_PLL_I2C_V << PMU_XPD_PLL_I2C_S) +#define PMU_XPD_PLL_I2C_V 0x00000001U +#define PMU_XPD_PLL_I2C_S 31 + +/** PMU_BACKUP_CFG_REG register + * need_des + */ +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x158) +/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) +#define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) +#define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 + +/** PMU_INT_RAW_REG register + * need_des + */ +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x15c) +/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) +#define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) +#define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_RAW_S 27 +/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_RAW (BIT(28)) +#define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) +#define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U +#define PMU_SDIO_IDLE_INT_RAW_S 28 +/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_RAW (BIT(29)) +#define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) +#define PMU_SW_INT_RAW_V 0x00000001U +#define PMU_SW_INT_RAW_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 +/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) +#define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) +#define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_RAW_S 31 + +/** PMU_HP_INT_ST_REG register + * need_des + */ +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x160) +/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ST (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) +#define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ST_S 27 +/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ST (BIT(28)) +#define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) +#define PMU_SDIO_IDLE_INT_ST_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ST_S 28 +/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ST (BIT(29)) +#define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) +#define PMU_SW_INT_ST_V 0x00000001U +#define PMU_SW_INT_ST_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) +#define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 +/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ST (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) +#define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ST_S 31 + +/** PMU_HP_INT_ENA_REG register + * need_des + */ +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) +#define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ENA_S 27 +/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ENA (BIT(28)) +#define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) +#define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ENA_S 28 +/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ENA (BIT(29)) +#define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) +#define PMU_SW_INT_ENA_V 0x00000001U +#define PMU_SW_INT_ENA_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 +/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) +#define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ENA_S 31 + +/** PMU_HP_INT_CLR_REG register + * need_des + */ +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) +#define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) +#define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_CLR_S 27 +/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_CLR (BIT(28)) +#define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) +#define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U +#define PMU_SDIO_IDLE_INT_CLR_S 28 +/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_CLR (BIT(29)) +#define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) +#define PMU_SW_INT_CLR_V 0x00000001U +#define PMU_SW_INT_CLR_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 +/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) +#define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) +#define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_CLR_S 31 + +/** PMU_LP_INT_RAW_REG register + * need_des + */ +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x16c) +/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) +#define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_RAW_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 +/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) +#define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_RAW_S 31 + +/** PMU_LP_INT_ST_REG register + * need_des + */ +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x170) +/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ST (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) +#define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ST_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 +/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) +#define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ST_S 31 + +/** PMU_LP_INT_ENA_REG register + * need_des + */ +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x174) +/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) +#define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ENA_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 +/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) +#define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ENA_S 31 + +/** PMU_LP_INT_CLR_REG register + * need_des + */ +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x178) +/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) +#define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_CLR_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 +/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) +#define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_CLR_S 31 + +/** PMU_LP_CPU_PWR0_REG register + * need_des + */ +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x17c) +/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAITI_RDY (BIT(0)) +#define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) +#define PMU_LP_CPU_WAITI_RDY_V 0x00000001U +#define PMU_LP_CPU_WAITI_RDY_S 0 +/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_CPU_STALL_RDY (BIT(1)) +#define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) +#define PMU_LP_CPU_STALL_RDY_V 0x00000001U +#define PMU_LP_CPU_STALL_RDY_S 1 +/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_LP_CPU_FORCE_STALL (BIT(18)) +#define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) +#define PMU_LP_CPU_FORCE_STALL_V 0x00000001U +#define PMU_LP_CPU_FORCE_STALL_S 18 +/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 +/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 +/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) +#define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_S 21 +/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) +#define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) +#define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_EN_S 29 +/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) +#define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) +#define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_RESET_EN_S 30 +/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 + +/** PMU_LP_CPU_PWR1_REG register + * need_des + */ +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x180) +/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_EN 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) +#define PMU_LP_CPU_WAKEUP_EN_V 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_S 0 +/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REQ (BIT(31)) +#define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) +#define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REQ_S 31 + +/** PMU_HP_LP_CPU_COMM_REG register + * need_des + */ +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x184) +/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_TRIGGER_HP (BIT(30)) +#define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) +#define PMU_LP_TRIGGER_HP_V 0x00000001U +#define PMU_LP_TRIGGER_HP_S 30 +/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_TRIGGER_LP (BIT(31)) +#define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) +#define PMU_HP_TRIGGER_LP_V 0x00000001U +#define PMU_HP_TRIGGER_LP_S 31 + +/** PMU_HP_REGULATOR_CFG_REG register + * need_des + */ +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x188) +/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) +#define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) +#define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U +#define PMU_DIG_REGULATOR_EN_CAL_S 31 + +/** PMU_MAIN_STATE_REG register + * need_des + */ +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x18c) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; + * need_des + */ +#define PMU_MAIN_LAST_ST_STATE 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_M (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S) +#define PMU_MAIN_LAST_ST_STATE_V 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_S 11 +/** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; + * need_des + */ +#define PMU_MAIN_TAR_ST_STATE 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) +#define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_S 18 +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; + * need_des + */ +#define PMU_MAIN_CUR_ST_STATE 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_M (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S) +#define PMU_MAIN_CUR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_S 25 + +/** PMU_PWR_STATE_REG register + * need_des + */ +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; + * need_des + */ +#define PMU_BACKUP_ST_STATE 0x0000001FU +#define PMU_BACKUP_ST_STATE_M (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S) +#define PMU_BACKUP_ST_STATE_V 0x0000001FU +#define PMU_BACKUP_ST_STATE_S 13 +/** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_LP_PWR_ST_STATE 0x0000001FU +#define PMU_LP_PWR_ST_STATE_M (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S) +#define PMU_LP_PWR_ST_STATE_V 0x0000001FU +#define PMU_LP_PWR_ST_STATE_S 18 +/** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; + * need_des + */ +#define PMU_HP_PWR_ST_STATE 0x000001FFU +#define PMU_HP_PWR_ST_STATE_M (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S) +#define PMU_HP_PWR_ST_STATE_V 0x000001FFU +#define PMU_HP_PWR_ST_STATE_S 23 + +/** PMU_CLK_STATE0_REG register + * need_des + */ +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x194) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) +#define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) +#define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_BBPLL_STATE_S 0 +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) +#define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) +#define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_XTAL_STATE_S 1 +/** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SLP_SEL_STATE (BIT(15)) +#define PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S) +#define PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U +#define PMU_SYS_CLK_SLP_SEL_STATE_S 15 +/** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SEL_STATE 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_M (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S) +#define PMU_SYS_CLK_SEL_STATE_V 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_S 16 +/** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_NO_DIV_STATE (BIT(18)) +#define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) +#define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U +#define PMU_SYS_CLK_NO_DIV_STATE_S 18 +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) +#define PMU_ICG_SYS_CLK_EN_STATE_M (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S) +#define PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U +#define PMU_ICG_SYS_CLK_EN_STATE_S 19 +/** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_SWITCH_STATE (BIT(20)) +#define PMU_ICG_MODEM_SWITCH_STATE_M (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S) +#define PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U +#define PMU_ICG_MODEM_SWITCH_STATE_S 20 +/** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_CODE_STATE 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_M (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S) +#define PMU_ICG_MODEM_CODE_STATE_V 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_S 21 +/** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_ICG_SLP_SEL_STATE (BIT(23)) +#define PMU_ICG_SLP_SEL_STATE_M (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S) +#define PMU_ICG_SLP_SEL_STATE_V 0x00000001U +#define PMU_ICG_SLP_SEL_STATE_S 23 +/** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_XTAL_STATE (BIT(24)) +#define PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S) +#define PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_XTAL_STATE_S 24 +/** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_PLL_STATE (BIT(25)) +#define PMU_ICG_GLOBAL_PLL_STATE_M (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S) +#define PMU_ICG_GLOBAL_PLL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_PLL_STATE_S 25 +/** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_ISO_EN_STATE (BIT(26)) +#define PMU_ANA_I2C_ISO_EN_STATE_M (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S) +#define PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U +#define PMU_ANA_I2C_ISO_EN_STATE_S 26 +/** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_RETENTION_STATE (BIT(27)) +#define PMU_ANA_I2C_RETENTION_STATE_M (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S) +#define PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U +#define PMU_ANA_I2C_RETENTION_STATE_S 27 +/** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BB_I2C_STATE (BIT(28)) +#define PMU_ANA_XPD_BB_I2C_STATE_M (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S) +#define PMU_ANA_XPD_BB_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BB_I2C_STATE_S 28 +/** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_I2C_STATE (BIT(29)) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_M (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_I2C_STATE_S 29 +/** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_STATE (BIT(30)) +#define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) +#define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_STATE_S 30 +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_XTAL_STATE (BIT(31)) +#define PMU_ANA_XPD_XTAL_STATE_M (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S) +#define PMU_ANA_XPD_XTAL_STATE_V 0x00000001U +#define PMU_ANA_XPD_XTAL_STATE_S 31 + +/** PMU_CLK_STATE1_REG register + * need_des + */ +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_M (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S) +#define PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_S 0 + +/** PMU_CLK_STATE2_REG register + * need_des + */ +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x19c) +/** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_APB_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_M (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S) +#define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_S 0 + +/** PMU_VDD_SPI_STATUS_REG register + * need_des + */ +#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a0) +/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) +#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) +#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U +#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 + +/** PMU_DATE_REG register + * need_des + */ +#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35664432; + * need_des + */ +#define PMU_PMU_DATE 0x7FFFFFFFU +#define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) +#define PMU_PMU_DATE_V 0x7FFFFFFFU +#define PMU_PMU_DATE_S 0 +/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_CLK_EN (BIT(31)) +#define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) +#define PMU_CLK_EN_V 0x00000001U +#define PMU_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/pmu_struct.h b/components/soc/esp32c5/include/soc/pmu_struct.h new file mode 100644 index 0000000000..65d00bd8b6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/pmu_struct.h @@ -0,0 +1,2787 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of hp_active_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_active_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_active_vdd_spi_pd_en:1; + /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_hp_mem_dslp:1; + /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_mem_pd_en:4; + /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_cpu_pd_en:1; + /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_aon_pd_en:1; + /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_active_dig_power_reg_t; + +/** Type of hp_active_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_func_reg_t; + +/** Type of hp_active_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_apb_reg_t; + +/** Type of hp_active_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_active_icg_modem_reg_t; + +/** Type of hp_active_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_active_uart_wakeup_en:1; + /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_lp_pad_hold_all:1; + /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_pad_hold_all:1; + /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pad_slp_sel:1; + /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pause_wdt:1; + /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_active_hp_sys_cntl_reg_t; + +/** Type of hp_active_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_iso_en:1; + /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_retention:1; + /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bb_i2c:1; + /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll_i2c:1; + /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_hp_ck_power_reg_t; + +/** Type of hp_active_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bias:1; + /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_active_dbg_atten:4; + /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cur:1; + /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_active_bias_reg_t; + +/** Type of hp_active_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_modem_clk_code:2; + /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_modem_clk_code:2; + uint32_t reserved_8:2; + /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_active_retention_mode:1; + /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_retention_en:1; + /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2active_retention_en:1; + uint32_t reserved_13:1; + /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_clk_sel:2; + /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_clk_sel:2; + uint32_t reserved_18:2; + /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_mode:3; + /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_mode:3; + uint32_t reserved_26:3; + /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_en:1; + /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_backup_reg_t; + +/** Type of hp_active_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_active_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_backup_clk_reg_t; + +/** Type of hp_active_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_no_div:1; + /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_icg_sys_clock_en:1; + /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_sys_clk_slp_sel:1; + /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_icg_slp_sel:1; + /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_active_sysclk_reg_t; + +/** Type of hp_active_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; + * need_des + */ + uint32_t lp_dbias_vol:5; + /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; + * need_des + */ + uint32_t hp_dbias_vol:5; + /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; + * need_des + */ + uint32_t dig_regulator0_dbias_sel:1; + /** dig_dbias_init : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dig_dbias_init:1; + /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_xpd:1; + /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_xpd:1; + /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_xpd:1; + /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_dbias:4; + /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_dbias:4; + /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_active_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_active_hp_regulator0_reg_t; + +/** Type of hp_active_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_active_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_active_hp_regulator1_reg_t; + +/** Type of hp_active_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_active_xtal_reg_t; + +/** Type of hp_modem_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_modem_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_modem_vdd_spi_pd_en:1; + /** hp_modem_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_mem_dslp:1; + /** hp_modem_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_mem_pd_en:4; + /** hp_modem_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_modem_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_cpu_pd_en:1; + /** hp_modem_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_aon_pd_en:1; + /** hp_modem_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_modem_dig_power_reg_t; + +/** Type of hp_modem_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_func_reg_t; + +/** Type of hp_modem_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_apb_reg_t; + +/** Type of hp_modem_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_modem_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_modem_icg_modem_reg_t; + +/** Type of hp_modem_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_modem_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_modem_uart_wakeup_en:1; + /** hp_modem_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_lp_pad_hold_all:1; + /** hp_modem_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_pad_hold_all:1; + /** hp_modem_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pad_slp_sel:1; + /** hp_modem_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pause_wdt:1; + /** hp_modem_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_hp_sys_cntl_reg_t; + +/** Type of hp_modem_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_iso_en:1; + /** hp_modem_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_retention:1; + /** hp_modem_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bb_i2c:1; + /** hp_modem_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll_i2c:1; + /** hp_modem_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_modem_hp_ck_power_reg_t; + +/** Type of hp_modem_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_modem_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bias:1; + /** hp_modem_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_modem_dbg_atten:4; + /** hp_modem_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_cur:1; + /** hp_modem_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_modem_bias_reg_t; + +/** Type of hp_modem_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2modem_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_modem_clk_code:2; + uint32_t reserved_6:4; + /** hp_modem_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_modem_retention_mode:1; + /** hp_sleep2modem_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_retention_en:1; + uint32_t reserved_12:2; + /** hp_sleep2modem_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_clk_sel:2; + uint32_t reserved_16:4; + /** hp_sleep2modem_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_mode:3; + uint32_t reserved_23:6; + /** hp_sleep2modem_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_backup_reg_t; + +/** Type of hp_modem_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_modem_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_modem_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_backup_clk_reg_t; + +/** Type of hp_modem_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_no_div:1; + /** hp_modem_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_sys_clock_en:1; + /** hp_modem_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_sys_clk_slp_sel:1; + /** hp_modem_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_slp_sel:1; + /** hp_modem_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_modem_sysclk_reg_t; + +/** Type of hp_modem_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hp_modem_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; + /** hp_modem_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; + /** hp_modem_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_xpd:1; + /** hp_modem_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; + /** hp_modem_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; + /** hp_modem_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_modem_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator0_reg_t; + +/** Type of hp_modem_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_modem_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator1_reg_t; + +/** Type of hp_modem_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_modem_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_modem_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_modem_xtal_reg_t; + +/** Type of hp_sleep_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_spi_pd_en:1; + /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_mem_dslp:1; + /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_mem_pd_en:4; + /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_wifi_pd_en:1; + uint32_t reserved_28:1; + /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_cpu_pd_en:1; + /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_aon_pd_en:1; + /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_dig_power_reg_t; + +/** Type of hp_sleep_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_func_reg_t; + +/** Type of hp_sleep_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_apb_reg_t; + +/** Type of hp_sleep_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_sleep_icg_modem_reg_t; + +/** Type of hp_sleep_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_sleep_uart_wakeup_en:1; + /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_hold_all:1; + /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_pad_hold_all:1; + /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pad_slp_sel:1; + /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pause_wdt:1; + /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_sleep_hp_sys_cntl_reg_t; + +/** Type of hp_sleep_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_iso_en:1; + /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_retention:1; + /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bb_i2c:1; + /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll_i2c:1; + /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_sleep_hp_ck_power_reg_t; + +/** Type of hp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bias:1; + /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dbg_atten:4; + /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cur:1; + /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_sleep_bias_reg_t; + +/** Type of hp_sleep_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_modem_clk_code:2; + /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_modem_clk_code:2; + /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_sleep_retention_mode:1; + uint32_t reserved_11:1; + /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_retention_en:1; + /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_retention_en:1; + uint32_t reserved_14:2; + /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_clk_sel:2; + /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_clk_sel:2; + uint32_t reserved_20:3; + /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_mode:3; + /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_mode:3; + uint32_t reserved_29:1; + /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_en:1; + /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_en:1; + }; + uint32_t val; +} pmu_hp_sleep_backup_reg_t; + +/** Type of hp_sleep_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_backup_clk_reg_t; + +/** Type of hp_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_no_div:1; + /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_sys_clock_en:1; + /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_sys_clk_slp_sel:1; + /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_slp_sel:1; + /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_sleep_sysclk_reg_t; + +/** Type of hp_sleep_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; + /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; + /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_xpd:1; + /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; + /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; + /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator0_reg_t; + +/** Type of hp_sleep_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator1_reg_t; + +/** Type of hp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_sleep_xtal_reg_t; + +/** Type of hp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_xpd:1; + /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_xpd:1; + /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_dbias:4; + /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator0_reg_t; + +/** Type of hp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator1_reg_t; + +/** Type of hp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_mem_dslp:1; + /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_dig_power_reg_t; + +/** Type of hp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_xtal32k:1; + /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_rc32k:1; + /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_fosc_clk:1; + /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_xpd:1; + /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_xpd:1; + /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_dbias:4; + /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t lp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator0_reg_t; + +/** Type of lp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator1_reg_t; + +/** Type of lp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_lp_sleep_xtal_reg_t; + +/** Type of lp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_mem_dslp:1; + /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_dig_power_reg_t; + +/** Type of lp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_xtal32k:1; + /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_rc32k:1; + /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_fosc_clk:1; + /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_bias:1; + /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t lp_sleep_dbg_atten:4; + /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_cur:1; + /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_lp_sleep_bias_reg_t; + +/** Type of imm_hp_ck_power register + * need_des + */ +typedef union { + struct { + /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t tie_low_global_bbpll_icg:1; + /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtal_icg:1; + /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_retention:1; + /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bb_i2c:1; + /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll_i2c:1; + /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll:1; + /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtal:1; + uint32_t reserved_7:18; + /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t tie_high_global_bbpll_icg:1; + /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtal_icg:1; + /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_retention:1; + /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bb_i2c:1; + /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll_i2c:1; + /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll:1; + /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_xtal:1; + }; + uint32_t val; +} pmu_imm_hp_ck_power_reg_t; + +/** Type of imm_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t update_dig_icg_switch:1; + /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_icg_slp_sel:1; + /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_icg_slp_sel:1; + /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_sys_clk_sel:1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +/** Type of imm_hp_func_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_func_en:1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +/** Type of imm_hp_apb_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_apb_en:1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +/** Type of imm_modem_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_modem_en:1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +/** Type of imm_lp_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_low_lp_rootclk_sel:1; + /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_lp_rootclk_sel:1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +/** Type of imm_pad_hold_all register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_lp_pad_hold_all:1; + /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_lp_pad_hold_all:1; + /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_hp_pad_hold_all:1; + /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_hp_pad_hold_all:1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +/** Type of imm_i2c_iso register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_iso_en:1; + /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_iso_en:1; + }; + uint32_t val; +} pmu_imm_i2c_iso_reg_t; + +/** Type of power_wait_timer0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_hp_powerdown_timer:9; + /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_hp_powerup_timer:9; + /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_hp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +/** Type of power_wait_timer1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 255; + * need_des + */ + uint32_t dg_lp_powerdown_timer:7; + /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 255; + * need_des + */ + uint32_t dg_lp_powerup_timer:7; + /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_lp_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +/** Type of power_pd_top_cntl register + * need_des + */ +typedef union { + struct { + /** force_top_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_top_reset:1; + /** force_top_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_top_iso:1; + /** force_top_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_top_pu:1; + /** force_top_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_top_no_reset:1; + /** force_top_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_top_no_iso:1; + /** force_top_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_top_pd:1; + /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_top_mask:5; + uint32_t reserved_11:16; + /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_top_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_top_cntl_reg_t; + +/** Type of power_pd_hpaon_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_aon_reset:1; + /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_aon_iso:1; + /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_aon_pu:1; + /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_reset:1; + /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_iso:1; + /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_aon_pd:1; + /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_mask:5; + uint32_t reserved_11:16; + /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpaon_cntl_reg_t; + +/** Type of power_pd_hpcpu_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_reset:1; + /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_iso:1; + /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_pu:1; + /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_reset:1; + /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_iso:1; + /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_pd:1; + /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_mask:5; + uint32_t reserved_11:16; + /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpcpu_cntl_reg_t; + +/** Type of power_pd_hpwifi_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_reset:1; + /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_iso:1; + /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_pu:1; + /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_reset:1; + /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_iso:1; + /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_pd:1; + /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_mask:5; + uint32_t reserved_11:16; + /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpwifi_cntl_reg_t; + +/** Type of power_pd_lpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_lp_peri_reset:1; + /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_lp_peri_iso:1; + /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_lp_peri_pu:1; + /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_reset:1; + /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_iso:1; + /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_lp_peri_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_lpperi_cntl_reg_t; + +/** Type of power_pd_mem_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; + * need_des + */ + uint32_t force_hp_mem_iso:4; + /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; + * need_des + */ + uint32_t force_hp_mem_pd:4; + uint32_t reserved_8:16; + /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; + * need_des + */ + uint32_t force_hp_mem_no_iso:4; + /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; + * need_des + */ + uint32_t force_hp_mem_pu:4; + }; + uint32_t val; +} pmu_power_pd_mem_cntl_reg_t; + +/** Type of power_pd_mem_mask register + * need_des + */ +typedef union { + struct { + /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_pd_mask:5; + /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_pd_mask:5; + /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_pd_mask:5; + uint32_t reserved_15:2; + /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_mask:5; + /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_mask:5; + /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_mask:5; + }; + uint32_t val; +} pmu_power_pd_mem_mask_reg_t; + +/** Type of power_hp_pad register + * need_des + */ +typedef union { + struct { + /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_pad_no_iso_all:1; + /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_pad_iso_all:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +/** Type of power_vdd_spi_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** vdd_spi_pwr_wait : R/W; bitpos: [28:18]; default: 255; + * need_des + */ + uint32_t vdd_spi_pwr_wait:11; + /** vdd_spi_pwr_sw : R/W; bitpos: [30:29]; default: 3; + * need_des + */ + uint32_t vdd_spi_pwr_sw:2; + /** vdd_spi_pwr_sel_sw : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vdd_spi_pwr_sel_sw:1; + }; + uint32_t val; +} pmu_power_vdd_spi_cntl_reg_t; + +/** Type of power_ck_wait_cntl register + * need_des + */ +typedef union { + struct { + /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; + * need_des + */ + uint32_t wait_xtl_stable:16; + /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; + * need_des + */ + uint32_t wait_pll_stable:16; + }; + uint32_t val; +} pmu_power_ck_wait_cntl_reg_t; + +/** Type of slp_wakeup_cntl0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t sleep_req:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +/** Type of slp_wakeup_cntl1 register + * need_des + */ +typedef union { + struct { + /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t sleep_reject_ena:31; + /** slp_reject_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_en:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +/** Type of slp_wakeup_cntl2 register + * need_des + */ +typedef union { + struct { + /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_ena:32; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +/** Type of slp_wakeup_cntl3 register + * need_des + */ +typedef union { + struct { + /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t lp_min_slp_val:8; + /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t hp_min_slp_val:8; + /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sleep_prt_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +/** Type of slp_wakeup_cntl4 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_cause_clr:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +/** Type of slp_wakeup_cntl5 register + * need_des + */ +typedef union { + struct { + /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t modem_wait_target:20; + uint32_t reserved_20:4; + /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; + * need_des + */ + uint32_t lp_ana_wait_target:8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +/** Type of slp_wakeup_cntl6 register + * need_des + */ +typedef union { + struct { + /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t soc_wakeup_wait:20; + uint32_t reserved_20:10; + /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t soc_wakeup_wait_cfg:2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +/** Type of slp_wakeup_cntl7 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; + * need_des + */ + uint32_t ana_wait_target:16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +/** Type of slp_wakeup_status0 register + * need_des + */ +typedef union { + struct { + /** wakeup_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +/** Type of slp_wakeup_status1 register + * need_des + */ +typedef union { + struct { + /** reject_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t reject_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +/** Type of hp_ck_poweron register + * need_des + */ +typedef union { + struct { + /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; + * need_des + */ + uint32_t i2c_por_wait_target:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pmu_hp_ck_poweron_reg_t; + +/** Type of hp_ck_cntl register + * need_des + */ +typedef union { + struct { + /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; + * need_des + */ + uint32_t modify_icg_cntl_wait:8; + /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; + * need_des + */ + uint32_t switch_icg_cntl_wait:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pmu_hp_ck_cntl_reg_t; + +/** Type of por_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** por_done : RO; bitpos: [31]; default: 1; + * need_des + */ + uint32_t por_done:1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +/** Type of rf_pwc register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** xpd_tc5g_i2c : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t xpd_tc5g_i2c:1; + /** xpd_rx5g_i2c : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t xpd_rx5g_i2c:1; + /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t perif_i2c_rstb:1; + /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t xpd_perif_i2c:1; + /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t xpd_txrf_i2c:1; + /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t xpd_rfrx_pbus:1; + /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xpd_ckgen_i2c:1; + /** xpd_pll_i2c : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t xpd_pll_i2c:1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +/** Type of backup_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t backup_sys_clk_no_div:1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_raw:1; + /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_raw:1; + /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_raw:1; + /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} pmu_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_st:1; + /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_st:1; + /** sw_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_st:1; + /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} pmu_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_ena:1; + /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_ena:1; + /** sw_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_ena:1; + /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} pmu_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_clr:1; + /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_clr:1; + /** sw_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_clr:1; + /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} pmu_hp_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_raw:1; + /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_raw:1; + /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_raw:1; + /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_raw:1; + /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_raw:1; + /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_raw:1; + /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_raw:1; + /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_raw:1; + /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_raw:1; + /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_raw:1; + /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_raw:1; + /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_raw:1; + }; + uint32_t val; +} pmu_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_st:1; + /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_st:1; + /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_st:1; + /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_st:1; + /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_st:1; + /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_st:1; + /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_st:1; + /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_st:1; + /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_st:1; + /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_st:1; + /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_st:1; + /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_st:1; + }; + uint32_t val; +} pmu_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_ena:1; + /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_ena:1; + /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_ena:1; + /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_ena:1; + /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_ena:1; + /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_ena:1; + /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_ena:1; + /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_ena:1; + /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_ena:1; + /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_ena:1; + /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_ena:1; + /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_ena:1; + }; + uint32_t val; +} pmu_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_clr:1; + /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_clr:1; + /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_clr:1; + /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_clr:1; + /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_clr:1; + /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_clr:1; + /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_clr:1; + /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_clr:1; + /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_clr:1; + /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_clr:1; + /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_clr:1; + /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_clr:1; + }; + uint32_t val; +} pmu_lp_int_clr_reg_t; + +/** Type of lp_cpu_pwr0 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_cpu_waiti_rdy:1; + /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_cpu_stall_rdy:1; + uint32_t reserved_2:16; + /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_cpu_force_stall:1; + /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_waiti_flag_en:1; + /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t lp_cpu_slp_stall_flag_en:1; + /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_cpu_slp_stall_wait:8; + /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_stall_en:1; + /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_reset_en:1; + /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_bypass_intr_en:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +/** Type of lp_cpu_pwr1 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_en:16; + uint32_t reserved_16:15; + /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_req:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +/** Type of hp_lp_cpu_comm register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_trigger_hp : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_trigger_hp:1; + /** hp_trigger_lp : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_trigger_lp:1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +/** Type of hp_regulator_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dig_regulator_en_cal:1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +/** Type of main_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** main_last_st_state : RO; bitpos: [17:11]; default: 1; + * need_des + */ + uint32_t main_last_st_state:7; + /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; + * need_des + */ + uint32_t main_tar_st_state:7; + /** main_cur_st_state : RO; bitpos: [31:25]; default: 4; + * need_des + */ + uint32_t main_cur_st_state:7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +/** Type of pwr_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** backup_st_state : RO; bitpos: [17:13]; default: 1; + * need_des + */ + uint32_t backup_st_state:5; + /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t lp_pwr_st_state:5; + /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; + * need_des + */ + uint32_t hp_pwr_st_state:9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** pmu_date : R/W; bitpos: [30:0]; default: 35664432; + * need_des + */ + uint32_t pmu_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} pmu_date_reg_t; + + +/** Group: status_register */ +/** Type of clk_state0 register + * need_des + */ +typedef union { + struct { + /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t stable_xpd_bbpll_state:1; + /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 1; + * need_des + */ + uint32_t stable_xpd_xtal_state:1; + uint32_t reserved_2:13; + /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t sys_clk_slp_sel_state:1; + /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sys_clk_sel_state:2; + /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t sys_clk_no_div_state:1; + /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 0; + * need_des + */ + uint32_t icg_sys_clk_en_state:1; + /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t icg_modem_switch_state:1; + /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; + * need_des + */ + uint32_t icg_modem_code_state:2; + /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t icg_slp_sel_state:1; + /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t icg_global_xtal_state:1; + /** icg_global_pll_state : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t icg_global_pll_state:1; + /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_i2c_iso_en_state:1; + /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_i2c_retention_state:1; + /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_xpd_bb_i2c_state:1; + /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_i2c_state:1; + /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_state:1; + /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_xpd_xtal_state:1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +/** Type of clk_state1 register + * need_des + */ +typedef union { + struct { + /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_func_en_state:32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +/** Type of clk_state2 register + * need_des + */ +typedef union { + struct { + /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_apb_en_state:32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +/** Type of vdd_spi_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** stable_vdd_spi_pwr_drv : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t stable_vdd_spi_pwr_drv:1; + }; + uint32_t val; +} pmu_vdd_spi_status_reg_t; + + +typedef struct { + volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; + volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; + volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; + volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; + volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; + volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; + volatile pmu_hp_active_bias_reg_t hp_active_bias; + volatile pmu_hp_active_backup_reg_t hp_active_backup; + volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; + volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; + volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; + volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; + volatile pmu_hp_active_xtal_reg_t hp_active_xtal; + volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; + volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; + volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; + volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; + volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; + volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; + volatile pmu_hp_modem_bias_reg_t hp_modem_bias; + volatile pmu_hp_modem_backup_reg_t hp_modem_backup; + volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; + volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; + volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; + volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; + volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; + volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; + volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; + volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; + volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; + volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; + volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; + volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; + volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; + volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; + volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; + volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; + volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; + volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; + volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; + volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; + uint32_t reserved_0a4; + volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; + volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; + uint32_t reserved_0b0; + volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; + volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; + volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; + volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; + volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; + volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; + volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; + volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; + volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; + volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; + volatile pmu_imm_modem_icg_reg_t imm_modem_icg; + volatile pmu_imm_lp_icg_reg_t imm_lp_icg; + volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; + volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; + volatile pmu_power_wait_timer0_reg_t power_wait_timer0; + volatile pmu_power_wait_timer1_reg_t power_wait_timer1; + volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; + volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; + volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; + uint32_t reserved_100; + volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; + volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; + volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; + volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; + volatile pmu_power_hp_pad_reg_t power_hp_pad; + volatile pmu_power_vdd_spi_cntl_reg_t power_vdd_spi_cntl; + volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; + volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; + volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; + volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; + volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; + volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; + volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; + volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; + volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; + volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; + volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; + volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; + volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; + volatile pmu_por_status_reg_t por_status; + volatile pmu_rf_pwc_reg_t rf_pwc; + volatile pmu_backup_cfg_reg_t backup_cfg; + volatile pmu_int_raw_reg_t int_raw; + volatile pmu_hp_int_st_reg_t hp_int_st; + volatile pmu_hp_int_ena_reg_t hp_int_ena; + volatile pmu_hp_int_clr_reg_t hp_int_clr; + volatile pmu_lp_int_raw_reg_t lp_int_raw; + volatile pmu_lp_int_st_reg_t lp_int_st; + volatile pmu_lp_int_ena_reg_t lp_int_ena; + volatile pmu_lp_int_clr_reg_t lp_int_clr; + volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; + volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + volatile pmu_vdd_spi_status_reg_t vdd_spi_status; + uint32_t reserved_1a4[150]; + volatile pmu_date_reg_t date; +} pmu_dev_t; + +extern pmu_dev_t PMU; + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rmt_reg.h b/components/soc/esp32c5/include/soc/rmt_reg.h new file mode 100644 index 0000000000..785086a1ef --- /dev/null +++ b/components/soc/esp32c5/include/soc/rmt_reg.h @@ -0,0 +1,1491 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** RMT_CH0DATA_REG register + * The read and write data register for CHANNEL0 by apb fifo access. + */ +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) +/** RMT_CH0DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 0 via APB FIFO. + */ +#define RMT_CH0DATA 0xFFFFFFFFU +#define RMT_CH0DATA_M (RMT_CH0DATA_V << RMT_CH0DATA_S) +#define RMT_CH0DATA_V 0xFFFFFFFFU +#define RMT_CH0DATA_S 0 + +/** RMT_CH1DATA_REG register + * The read and write data register for CHANNEL1 by apb fifo access. + */ +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) +/** RMT_CH1DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 1 via APB FIFO. + */ +#define RMT_CH1DATA 0xFFFFFFFFU +#define RMT_CH1DATA_M (RMT_CH1DATA_V << RMT_CH1DATA_S) +#define RMT_CH1DATA_V 0xFFFFFFFFU +#define RMT_CH1DATA_S 0 + +/** RMT_CH2DATA_REG register + * The read and write data register for CHANNEL2 by apb fifo access. + */ +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) +/** RMT_CH2DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 2 via APB FIFO. + */ +#define RMT_CH2DATA 0xFFFFFFFFU +#define RMT_CH2DATA_M (RMT_CH2DATA_V << RMT_CH2DATA_S) +#define RMT_CH2DATA_V 0xFFFFFFFFU +#define RMT_CH2DATA_S 0 + +/** RMT_CH3DATA_REG register + * The read and write data register for CHANNEL3 by apb fifo access. + */ +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) +/** RMT_CH3DATA : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel 3 via APB FIFO. + */ +#define RMT_CH3DATA 0xFFFFFFFFU +#define RMT_CH3DATA_M (RMT_CH3DATA_V << RMT_CH3DATA_S) +#define RMT_CH3DATA_V 0xFFFFFFFFU +#define RMT_CH3DATA_S 0 + +/** RMT_CH0CONF0_REG register + * Channel 0 configure register 0 + */ +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x10) +/** RMT_TX_START_CH0 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL0. + */ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) +#define RMT_TX_START_CH0_V 0x00000001U +#define RMT_TX_START_CH0_S 0 +/** RMT_MEM_RD_RST_CH0 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL0 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) +#define RMT_MEM_RD_RST_CH0_V 0x00000001U +#define RMT_MEM_RD_RST_CH0_S 1 +/** RMT_APB_MEM_RST_CH0 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) +#define RMT_APB_MEM_RST_CH0_V 0x00000001U +#define RMT_APB_MEM_RST_CH0_S 2 +/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL0. + */ +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) +#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH0_S 3 +/** RMT_MEM_TX_WRAP_EN_CH0 : R/W; bitpos: [4]; default: 0; + * This is the channel 0 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (RMT_MEM_TX_WRAP_EN_CH0_V << RMT_MEM_TX_WRAP_EN_CH0_S) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL0 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) +#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH0_S 5 +/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL0 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) +#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH0_S 6 +/** RMT_TX_STOP_CH0 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL0 sending data out. + */ +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) +#define RMT_TX_STOP_CH0_V 0x00000001U +#define RMT_TX_STOP_CH0_S 7 +/** RMT_DIV_CNT_CH0 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL0. + */ +#define RMT_DIV_CNT_CH0 0x000000FFU +#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) +#define RMT_DIV_CNT_CH0_V 0x000000FFU +#define RMT_DIV_CNT_CH0_S 8 +/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL0. + */ +#define RMT_MEM_SIZE_CH0 0x00000007U +#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) +#define RMT_MEM_SIZE_CH0_V 0x00000007U +#define RMT_MEM_SIZE_CH0_S 16 +/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0. + * Only valid when RMT_CARRIER_EN_CH0 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) +#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH0_S 20 +/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) +#define RMT_CARRIER_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EN_CH0_S 21 +/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL0. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) +#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH0_S 22 +/** RMT_CONF_UPDATE_CH0 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL0 + */ +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (RMT_CONF_UPDATE_CH0_V << RMT_CONF_UPDATE_CH0_S) +#define RMT_CONF_UPDATE_CH0_V 0x00000001U +#define RMT_CONF_UPDATE_CH0_S 24 + +/** RMT_CH1CONF0_REG register + * Channel 1 configure register 0 + */ +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x14) +/** RMT_TX_START_CH1 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL1. + */ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S) +#define RMT_TX_START_CH1_V 0x00000001U +#define RMT_TX_START_CH1_S 0 +/** RMT_MEM_RD_RST_CH1 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL1 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S) +#define RMT_MEM_RD_RST_CH1_V 0x00000001U +#define RMT_MEM_RD_RST_CH1_S 1 +/** RMT_APB_MEM_RST_CH1 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S) +#define RMT_APB_MEM_RST_CH1_V 0x00000001U +#define RMT_APB_MEM_RST_CH1_S 2 +/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL1. + */ +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S) +#define RMT_TX_CONTI_MODE_CH1_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH1_S 3 +/** RMT_MEM_TX_WRAP_EN_CH1 : R/W; bitpos: [4]; default: 0; + * This is the channel 1 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (RMT_MEM_TX_WRAP_EN_CH1_V << RMT_MEM_TX_WRAP_EN_CH1_S) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL1 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S) +#define RMT_IDLE_OUT_LV_CH1_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH1_S 5 +/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL1 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S) +#define RMT_IDLE_OUT_EN_CH1_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH1_S 6 +/** RMT_TX_STOP_CH1 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL1 sending data out. + */ +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S) +#define RMT_TX_STOP_CH1_V 0x00000001U +#define RMT_TX_STOP_CH1_S 7 +/** RMT_DIV_CNT_CH1 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL1. + */ +#define RMT_DIV_CNT_CH1 0x000000FFU +#define RMT_DIV_CNT_CH1_M (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S) +#define RMT_DIV_CNT_CH1_V 0x000000FFU +#define RMT_DIV_CNT_CH1_S 8 +/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL1. + */ +#define RMT_MEM_SIZE_CH1 0x00000007U +#define RMT_MEM_SIZE_CH1_M (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S) +#define RMT_MEM_SIZE_CH1_V 0x00000007U +#define RMT_MEM_SIZE_CH1_S 16 +/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1. + * Only valid when RMT_CARRIER_EN_CH1 is 1. + */ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S) +#define RMT_CARRIER_EFF_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH1_S 20 +/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S) +#define RMT_CARRIER_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EN_CH1_S 21 +/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL1. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S) +#define RMT_CARRIER_OUT_LV_CH1_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH1_S 22 +/** RMT_CONF_UPDATE_CH1 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL1 + */ +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (RMT_CONF_UPDATE_CH1_V << RMT_CONF_UPDATE_CH1_S) +#define RMT_CONF_UPDATE_CH1_V 0x00000001U +#define RMT_CONF_UPDATE_CH1_S 24 + +/** RMT_CH2CONF0_REG register + * Channel 2 configure register 0 + */ +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x18) +/** RMT_DIV_CNT_CH2 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL2. + */ +#define RMT_DIV_CNT_CH2 0x000000FFU +#define RMT_DIV_CNT_CH2_M (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S) +#define RMT_DIV_CNT_CH2_V 0x000000FFU +#define RMT_DIV_CNT_CH2_S 0 +/** RMT_IDLE_THRES_CH2 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH2 0x00007FFFU +#define RMT_IDLE_THRES_CH2_M (RMT_IDLE_THRES_CH2_V << RMT_IDLE_THRES_CH2_S) +#define RMT_IDLE_THRES_CH2_V 0x00007FFFU +#define RMT_IDLE_THRES_CH2_S 8 +/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL2. + */ +#define RMT_MEM_SIZE_CH2 0x00000007U +#define RMT_MEM_SIZE_CH2_M (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S) +#define RMT_MEM_SIZE_CH2_V 0x00000007U +#define RMT_MEM_SIZE_CH2_S 23 +/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S) +#define RMT_CARRIER_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EN_CH2_S 28 +/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL2. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S) +#define RMT_CARRIER_OUT_LV_CH2_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH2_S 29 + +/** RMT_CH2CONF1_REG register + * Channel 2 configure register 1 + */ +#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x1c) +/** RMT_RX_EN_CH2 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL2. + */ +#define RMT_RX_EN_CH2 (BIT(0)) +#define RMT_RX_EN_CH2_M (RMT_RX_EN_CH2_V << RMT_RX_EN_CH2_S) +#define RMT_RX_EN_CH2_V 0x00000001U +#define RMT_RX_EN_CH2_S 0 +/** RMT_MEM_WR_RST_CH2 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL2 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH2 (BIT(1)) +#define RMT_MEM_WR_RST_CH2_M (RMT_MEM_WR_RST_CH2_V << RMT_MEM_WR_RST_CH2_S) +#define RMT_MEM_WR_RST_CH2_V 0x00000001U +#define RMT_MEM_WR_RST_CH2_S 1 +/** RMT_APB_MEM_RST_CH2 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S) +#define RMT_APB_MEM_RST_CH2_V 0x00000001U +#define RMT_APB_MEM_RST_CH2_S 2 +/** RMT_MEM_OWNER_CH2 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL2's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH2 (BIT(3)) +#define RMT_MEM_OWNER_CH2_M (RMT_MEM_OWNER_CH2_V << RMT_MEM_OWNER_CH2_S) +#define RMT_MEM_OWNER_CH2_V 0x00000001U +#define RMT_MEM_OWNER_CH2_S 3 +/** RMT_RX_FILTER_EN_CH2 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL2. + */ +#define RMT_RX_FILTER_EN_CH2 (BIT(4)) +#define RMT_RX_FILTER_EN_CH2_M (RMT_RX_FILTER_EN_CH2_V << RMT_RX_FILTER_EN_CH2_S) +#define RMT_RX_FILTER_EN_CH2_V 0x00000001U +#define RMT_RX_FILTER_EN_CH2_S 4 +/** RMT_RX_FILTER_THRES_CH2 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH2 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_M (RMT_RX_FILTER_THRES_CH2_V << RMT_RX_FILTER_THRES_CH2_S) +#define RMT_RX_FILTER_THRES_CH2_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_S 5 +/** RMT_MEM_RX_WRAP_EN_CH2 : R/W; bitpos: [13]; default: 0; + * This is the channel 2 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH2 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH2_M (RMT_MEM_RX_WRAP_EN_CH2_V << RMT_MEM_RX_WRAP_EN_CH2_S) +#define RMT_MEM_RX_WRAP_EN_CH2_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH2_S 13 +/** RMT_CONF_UPDATE_CH2 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL2 + */ +#define RMT_CONF_UPDATE_CH2 (BIT(15)) +#define RMT_CONF_UPDATE_CH2_M (RMT_CONF_UPDATE_CH2_V << RMT_CONF_UPDATE_CH2_S) +#define RMT_CONF_UPDATE_CH2_V 0x00000001U +#define RMT_CONF_UPDATE_CH2_S 15 + +/** RMT_CH3CONF0_REG register + * Channel 3 configure register 0 + */ +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x20) +/** RMT_DIV_CNT_CH3 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL3. + */ +#define RMT_DIV_CNT_CH3 0x000000FFU +#define RMT_DIV_CNT_CH3_M (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S) +#define RMT_DIV_CNT_CH3_V 0x000000FFU +#define RMT_DIV_CNT_CH3_S 0 +/** RMT_IDLE_THRES_CH3 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_CH3 0x00007FFFU +#define RMT_IDLE_THRES_CH3_M (RMT_IDLE_THRES_CH3_V << RMT_IDLE_THRES_CH3_S) +#define RMT_IDLE_THRES_CH3_V 0x00007FFFU +#define RMT_IDLE_THRES_CH3_S 8 +/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL3. + */ +#define RMT_MEM_SIZE_CH3 0x00000007U +#define RMT_MEM_SIZE_CH3_M (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S) +#define RMT_MEM_SIZE_CH3_V 0x00000007U +#define RMT_MEM_SIZE_CH3_S 23 +/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S) +#define RMT_CARRIER_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EN_CH3_S 28 +/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL3. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S) +#define RMT_CARRIER_OUT_LV_CH3_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH3_S 29 + +/** RMT_CH3CONF1_REG register + * Channel 3 configure register 1 + */ +#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x24) +/** RMT_RX_EN_CH3 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL3. + */ +#define RMT_RX_EN_CH3 (BIT(0)) +#define RMT_RX_EN_CH3_M (RMT_RX_EN_CH3_V << RMT_RX_EN_CH3_S) +#define RMT_RX_EN_CH3_V 0x00000001U +#define RMT_RX_EN_CH3_S 0 +/** RMT_MEM_WR_RST_CH3 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL3 by accessing receiver. + */ +#define RMT_MEM_WR_RST_CH3 (BIT(1)) +#define RMT_MEM_WR_RST_CH3_M (RMT_MEM_WR_RST_CH3_V << RMT_MEM_WR_RST_CH3_S) +#define RMT_MEM_WR_RST_CH3_V 0x00000001U +#define RMT_MEM_WR_RST_CH3_S 1 +/** RMT_APB_MEM_RST_CH3 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S) +#define RMT_APB_MEM_RST_CH3_V 0x00000001U +#define RMT_APB_MEM_RST_CH3_S 2 +/** RMT_MEM_OWNER_CH3 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL3's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_CH3 (BIT(3)) +#define RMT_MEM_OWNER_CH3_M (RMT_MEM_OWNER_CH3_V << RMT_MEM_OWNER_CH3_S) +#define RMT_MEM_OWNER_CH3_V 0x00000001U +#define RMT_MEM_OWNER_CH3_S 3 +/** RMT_RX_FILTER_EN_CH3 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL3. + */ +#define RMT_RX_FILTER_EN_CH3 (BIT(4)) +#define RMT_RX_FILTER_EN_CH3_M (RMT_RX_FILTER_EN_CH3_V << RMT_RX_FILTER_EN_CH3_S) +#define RMT_RX_FILTER_EN_CH3_V 0x00000001U +#define RMT_RX_FILTER_EN_CH3_S 4 +/** RMT_RX_FILTER_THRES_CH3 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_CH3 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_M (RMT_RX_FILTER_THRES_CH3_V << RMT_RX_FILTER_THRES_CH3_S) +#define RMT_RX_FILTER_THRES_CH3_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_S 5 +/** RMT_MEM_RX_WRAP_EN_CH3 : R/W; bitpos: [13]; default: 0; + * This is the channel 3 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_CH3 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH3_M (RMT_MEM_RX_WRAP_EN_CH3_V << RMT_MEM_RX_WRAP_EN_CH3_S) +#define RMT_MEM_RX_WRAP_EN_CH3_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH3_S 13 +/** RMT_CONF_UPDATE_CH3 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL3 + */ +#define RMT_CONF_UPDATE_CH3 (BIT(15)) +#define RMT_CONF_UPDATE_CH3_M (RMT_CONF_UPDATE_CH3_V << RMT_CONF_UPDATE_CH3_S) +#define RMT_CONF_UPDATE_CH3_V 0x00000001U +#define RMT_CONF_UPDATE_CH3_S 15 + +/** RMT_CH0STATUS_REG register + * Channel 0 status register + */ +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x28) +/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL0 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH0 0x000001FFU +#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) +#define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH0_S 0 +/** RMT_STATE_CH0 : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNEL0. + */ +#define RMT_STATE_CH0 0x00000007U +#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) +#define RMT_STATE_CH0_V 0x00000007U +#define RMT_STATE_CH0_S 9 +/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH0 0x000001FFU +#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) +#define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH0_S 12 +/** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH0 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) +#define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH0_S 21 +/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH0 (BIT(22)) +#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) +#define RMT_MEM_EMPTY_CH0_V 0x00000001U +#define RMT_MEM_EMPTY_CH0_S 22 +/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH0_S 23 +/** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH0 0x000000FFU +#define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) +#define RMT_APB_MEM_RADDR_CH0_V 0x000000FFU +#define RMT_APB_MEM_RADDR_CH0_S 24 + +/** RMT_CH1STATUS_REG register + * Channel 1 status register + */ +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x2c) +/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL1 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_CH1 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_M (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S) +#define RMT_MEM_RADDR_EX_CH1_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_S 0 +/** RMT_STATE_CH1 : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNEL1. + */ +#define RMT_STATE_CH1 0x00000007U +#define RMT_STATE_CH1_M (RMT_STATE_CH1_V << RMT_STATE_CH1_S) +#define RMT_STATE_CH1_V 0x00000007U +#define RMT_STATE_CH1_S 9 +/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_CH1 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_M (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S) +#define RMT_APB_MEM_WADDR_CH1_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_S 12 +/** RMT_APB_MEM_RD_ERR_CH1 : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH1 (BIT(21)) +#define RMT_APB_MEM_RD_ERR_CH1_M (RMT_APB_MEM_RD_ERR_CH1_V << RMT_APB_MEM_RD_ERR_CH1_S) +#define RMT_APB_MEM_RD_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH1_S 21 +/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_CH1 (BIT(22)) +#define RMT_MEM_EMPTY_CH1_M (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S) +#define RMT_MEM_EMPTY_CH1_V 0x00000001U +#define RMT_MEM_EMPTY_CH1_S 22 +/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(23)) +#define RMT_APB_MEM_WR_ERR_CH1_M (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH1_S 23 +/** RMT_APB_MEM_RADDR_CH1 : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH1 0x000000FFU +#define RMT_APB_MEM_RADDR_CH1_M (RMT_APB_MEM_RADDR_CH1_V << RMT_APB_MEM_RADDR_CH1_S) +#define RMT_APB_MEM_RADDR_CH1_V 0x000000FFU +#define RMT_APB_MEM_RADDR_CH1_S 24 + +/** RMT_CH2STATUS_REG register + * Channel 2 status register + */ +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x30) +/** RMT_MEM_WADDR_EX_CH2 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNEL2 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH2 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_M (RMT_MEM_WADDR_EX_CH2_V << RMT_MEM_WADDR_EX_CH2_S) +#define RMT_MEM_WADDR_EX_CH2_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_S 0 +/** RMT_APB_MEM_RADDR_CH2 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH2 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_M (RMT_APB_MEM_RADDR_CH2_V << RMT_APB_MEM_RADDR_CH2_S) +#define RMT_APB_MEM_RADDR_CH2_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_S 12 +/** RMT_STATE_CH2 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL2. + */ +#define RMT_STATE_CH2 0x00000007U +#define RMT_STATE_CH2_M (RMT_STATE_CH2_V << RMT_STATE_CH2_S) +#define RMT_STATE_CH2_V 0x00000007U +#define RMT_STATE_CH2_S 22 +/** RMT_MEM_OWNER_ERR_CH2 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH2 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH2_M (RMT_MEM_OWNER_ERR_CH2_V << RMT_MEM_OWNER_ERR_CH2_S) +#define RMT_MEM_OWNER_ERR_CH2_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH2_S 25 +/** RMT_MEM_FULL_CH2 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH2 (BIT(26)) +#define RMT_MEM_FULL_CH2_M (RMT_MEM_FULL_CH2_V << RMT_MEM_FULL_CH2_S) +#define RMT_MEM_FULL_CH2_V 0x00000001U +#define RMT_MEM_FULL_CH2_S 26 +/** RMT_APB_MEM_RD_ERR_CH2 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH2 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH2_M (RMT_APB_MEM_RD_ERR_CH2_V << RMT_APB_MEM_RD_ERR_CH2_S) +#define RMT_APB_MEM_RD_ERR_CH2_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH2_S 27 + +/** RMT_CH3STATUS_REG register + * Channel 3 status register + */ +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x34) +/** RMT_MEM_WADDR_EX_CH3 : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNEL3 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_CH3 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_M (RMT_MEM_WADDR_EX_CH3_V << RMT_MEM_WADDR_EX_CH3_S) +#define RMT_MEM_WADDR_EX_CH3_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_S 0 +/** RMT_APB_MEM_RADDR_CH3 : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_CH3 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_M (RMT_APB_MEM_RADDR_CH3_V << RMT_APB_MEM_RADDR_CH3_S) +#define RMT_APB_MEM_RADDR_CH3_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_S 12 +/** RMT_STATE_CH3 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL3. + */ +#define RMT_STATE_CH3 0x00000007U +#define RMT_STATE_CH3_M (RMT_STATE_CH3_V << RMT_STATE_CH3_S) +#define RMT_STATE_CH3_V 0x00000007U +#define RMT_STATE_CH3_S 22 +/** RMT_MEM_OWNER_ERR_CH3 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_CH3 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH3_M (RMT_MEM_OWNER_ERR_CH3_V << RMT_MEM_OWNER_ERR_CH3_S) +#define RMT_MEM_OWNER_ERR_CH3_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH3_S 25 +/** RMT_MEM_FULL_CH3 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_CH3 (BIT(26)) +#define RMT_MEM_FULL_CH3_M (RMT_MEM_FULL_CH3_V << RMT_MEM_FULL_CH3_S) +#define RMT_MEM_FULL_CH3_V 0x00000001U +#define RMT_MEM_FULL_CH3_S 26 +/** RMT_APB_MEM_RD_ERR_CH3 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_CH3 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH3_M (RMT_APB_MEM_RD_ERR_CH3_V << RMT_APB_MEM_RD_ERR_CH3_S) +#define RMT_APB_MEM_RD_ERR_CH3_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH3_S 27 + +/** RMT_INT_RAW_REG register + * Raw interrupt status + */ +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x38) +/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S) +#define RMT_CH0_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_END_INT_RAW_S 0 +/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S) +#define RMT_CH1_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_END_INT_RAW_S 1 +/** RMT_CH2_RX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when reception done. + */ +#define RMT_CH2_RX_END_INT_RAW (BIT(2)) +#define RMT_CH2_RX_END_INT_RAW_M (RMT_CH2_RX_END_INT_RAW_V << RMT_CH2_RX_END_INT_RAW_S) +#define RMT_CH2_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH2_RX_END_INT_RAW_S 2 +/** RMT_CH3_RX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when reception done. + */ +#define RMT_CH3_RX_END_INT_RAW (BIT(3)) +#define RMT_CH3_RX_END_INT_RAW_M (RMT_CH3_RX_END_INT_RAW_V << RMT_CH3_RX_END_INT_RAW_S) +#define RMT_CH3_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH3_RX_END_INT_RAW_S 3 +/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S) +#define RMT_CH0_ERR_INT_RAW_V 0x00000001U +#define RMT_CH0_ERR_INT_RAW_S 4 +/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S) +#define RMT_CH1_ERR_INT_RAW_V 0x00000001U +#define RMT_CH1_ERR_INT_RAW_S 5 +/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S) +#define RMT_CH2_ERR_INT_RAW_V 0x00000001U +#define RMT_CH2_ERR_INT_RAW_S 6 +/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S) +#define RMT_CH3_ERR_INT_RAW_V 0x00000001U +#define RMT_CH3_ERR_INT_RAW_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH2_RX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_M (RMT_CH2_RX_THR_EVENT_INT_RAW_V << RMT_CH2_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH2_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_RAW_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH3_RX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_M (RMT_CH3_RX_THR_EVENT_INT_RAW_V << RMT_CH3_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH3_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_RAW_S 11 +/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 + +/** RMT_INT_ST_REG register + * Masked interrupt status + */ +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x3c) +/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S) +#define RMT_CH0_TX_END_INT_ST_V 0x00000001U +#define RMT_CH0_TX_END_INT_ST_S 0 +/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S) +#define RMT_CH1_TX_END_INT_ST_V 0x00000001U +#define RMT_CH1_TX_END_INT_ST_S 1 +/** RMT_CH2_RX_END_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_RX_END_INT. + */ +#define RMT_CH2_RX_END_INT_ST (BIT(2)) +#define RMT_CH2_RX_END_INT_ST_M (RMT_CH2_RX_END_INT_ST_V << RMT_CH2_RX_END_INT_ST_S) +#define RMT_CH2_RX_END_INT_ST_V 0x00000001U +#define RMT_CH2_RX_END_INT_ST_S 2 +/** RMT_CH3_RX_END_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_RX_END_INT. + */ +#define RMT_CH3_RX_END_INT_ST (BIT(3)) +#define RMT_CH3_RX_END_INT_ST_M (RMT_CH3_RX_END_INT_ST_V << RMT_CH3_RX_END_INT_ST_S) +#define RMT_CH3_RX_END_INT_ST_V 0x00000001U +#define RMT_CH3_RX_END_INT_ST_S 3 +/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S) +#define RMT_CH0_ERR_INT_ST_V 0x00000001U +#define RMT_CH0_ERR_INT_ST_S 4 +/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S) +#define RMT_CH1_ERR_INT_ST_V 0x00000001U +#define RMT_CH1_ERR_INT_ST_S 5 +/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S) +#define RMT_CH2_ERR_INT_ST_V 0x00000001U +#define RMT_CH2_ERR_INT_ST_S 6 +/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S) +#define RMT_CH3_ERR_INT_ST_V 0x00000001U +#define RMT_CH3_ERR_INT_ST_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + */ +#define RMT_CH2_RX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ST_M (RMT_CH2_RX_THR_EVENT_INT_ST_V << RMT_CH2_RX_THR_EVENT_INT_ST_S) +#define RMT_CH2_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_ST_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + */ +#define RMT_CH3_RX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ST_M (RMT_CH3_RX_THR_EVENT_INT_ST_V << RMT_CH3_RX_THR_EVENT_INT_ST_S) +#define RMT_CH3_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_ST_S 11 +/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ST_S 13 + +/** RMT_INT_ENA_REG register + * Interrupt enable bits + */ +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x40) +/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S) +#define RMT_CH0_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_END_INT_ENA_S 0 +/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S) +#define RMT_CH1_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_END_INT_ENA_S 1 +/** RMT_CH2_RX_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_RX_END_INT. + */ +#define RMT_CH2_RX_END_INT_ENA (BIT(2)) +#define RMT_CH2_RX_END_INT_ENA_M (RMT_CH2_RX_END_INT_ENA_V << RMT_CH2_RX_END_INT_ENA_S) +#define RMT_CH2_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH2_RX_END_INT_ENA_S 2 +/** RMT_CH3_RX_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_RX_END_INT. + */ +#define RMT_CH3_RX_END_INT_ENA (BIT(3)) +#define RMT_CH3_RX_END_INT_ENA_M (RMT_CH3_RX_END_INT_ENA_V << RMT_CH3_RX_END_INT_ENA_S) +#define RMT_CH3_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH3_RX_END_INT_ENA_S 3 +/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S) +#define RMT_CH0_ERR_INT_ENA_V 0x00000001U +#define RMT_CH0_ERR_INT_ENA_S 4 +/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S) +#define RMT_CH1_ERR_INT_ENA_V 0x00000001U +#define RMT_CH1_ERR_INT_ENA_S 5 +/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S) +#define RMT_CH2_ERR_INT_ENA_V 0x00000001U +#define RMT_CH2_ERR_INT_ENA_S 6 +/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S) +#define RMT_CH3_ERR_INT_ENA_V 0x00000001U +#define RMT_CH3_ERR_INT_ENA_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_RX_THR_EVENT_INT. + */ +#define RMT_CH2_RX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_M (RMT_CH2_RX_THR_EVENT_INT_ENA_V << RMT_CH2_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH2_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_ENA_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_RX_THR_EVENT_INT. + */ +#define RMT_CH3_RX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_M (RMT_CH3_RX_THR_EVENT_INT_ENA_V << RMT_CH3_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH3_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_ENA_S 11 +/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 + +/** RMT_INT_CLR_REG register + * Interrupt clear bits + */ +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x44) +/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S) +#define RMT_CH0_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_END_INT_CLR_S 0 +/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S) +#define RMT_CH1_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_END_INT_CLR_S 1 +/** RMT_CH2_RX_END_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_RX_END_INT interrupt. + */ +#define RMT_CH2_RX_END_INT_CLR (BIT(2)) +#define RMT_CH2_RX_END_INT_CLR_M (RMT_CH2_RX_END_INT_CLR_V << RMT_CH2_RX_END_INT_CLR_S) +#define RMT_CH2_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH2_RX_END_INT_CLR_S 2 +/** RMT_CH3_RX_END_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_RX_END_INT interrupt. + */ +#define RMT_CH3_RX_END_INT_CLR (BIT(3)) +#define RMT_CH3_RX_END_INT_CLR_M (RMT_CH3_RX_END_INT_CLR_V << RMT_CH3_RX_END_INT_CLR_S) +#define RMT_CH3_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH3_RX_END_INT_CLR_S 3 +/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S) +#define RMT_CH0_ERR_INT_CLR_V 0x00000001U +#define RMT_CH0_ERR_INT_CLR_S 4 +/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S) +#define RMT_CH1_ERR_INT_CLR_V 0x00000001U +#define RMT_CH1_ERR_INT_CLR_S 5 +/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S) +#define RMT_CH2_ERR_INT_CLR_V 0x00000001U +#define RMT_CH2_ERR_INT_CLR_S 6 +/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S) +#define RMT_CH3_ERR_INT_CLR_V 0x00000001U +#define RMT_CH3_ERR_INT_CLR_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/** RMT_CH2_RX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH2_RX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_M (RMT_CH2_RX_THR_EVENT_INT_CLR_V << RMT_CH2_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH2_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH2_RX_THR_EVENT_INT_CLR_S 10 +/** RMT_CH3_RX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH3_RX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_M (RMT_CH3_RX_THR_EVENT_INT_CLR_V << RMT_CH3_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH3_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH3_RX_THR_EVENT_INT_CLR_S 11 +/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 + +/** RMT_CH0CARRIER_DUTY_REG register + * Channel 0 duty cycle configuration register + */ +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x48) +/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) +#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_S 0 +/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) +#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_S 16 + +/** RMT_CH1CARRIER_DUTY_REG register + * Channel 1 duty cycle configuration register + */ +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x4c) +/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_M (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S) +#define RMT_CARRIER_LOW_CH1_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_M (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S) +#define RMT_CARRIER_HIGH_CH1_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_S 16 + +/** RMT_CH2_RX_CARRIER_RM_REG register + * Channel 2 carrier remove register + */ +#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x50) +/** RMT_CARRIER_LOW_THRES_CH2 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH2 + 1) for channel 2. + */ +#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_M (RMT_CARRIER_LOW_THRES_CH2_V << RMT_CARRIER_LOW_THRES_CH2_S) +#define RMT_CARRIER_LOW_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_S 0 +/** RMT_CARRIER_HIGH_THRES_CH2 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH2 + 1) for channel 2. + */ +#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_M (RMT_CARRIER_HIGH_THRES_CH2_V << RMT_CARRIER_HIGH_THRES_CH2_S) +#define RMT_CARRIER_HIGH_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_S 16 + +/** RMT_CH3_RX_CARRIER_RM_REG register + * Channel 3 carrier remove register + */ +#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x54) +/** RMT_CARRIER_LOW_THRES_CH3 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH3 + 1) for channel 3. + */ +#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_M (RMT_CARRIER_LOW_THRES_CH3_V << RMT_CARRIER_LOW_THRES_CH3_S) +#define RMT_CARRIER_LOW_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_S 0 +/** RMT_CARRIER_HIGH_THRES_CH3 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH3 + 1) for channel 3. + */ +#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_M (RMT_CARRIER_HIGH_THRES_CH3_V << RMT_CARRIER_HIGH_THRES_CH3_S) +#define RMT_CARRIER_HIGH_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_S 16 + +/** RMT_CH0_TX_LIM_REG register + * Channel 0 Tx event configuration register + */ +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x58) +/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL0 can send out. + */ +#define RMT_TX_LIM_CH0 0x000001FFU +#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) +#define RMT_TX_LIM_CH0_V 0x000001FFU +#define RMT_TX_LIM_CH0_S 0 +/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) +#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_S 9 +/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/** RMT_LOOP_STOP_EN_CH0 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL0. + */ +#define RMT_LOOP_STOP_EN_CH0 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH0_M (RMT_LOOP_STOP_EN_CH0_V << RMT_LOOP_STOP_EN_CH0_S) +#define RMT_LOOP_STOP_EN_CH0_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH0_S 21 + +/** RMT_CH1_TX_LIM_REG register + * Channel 1 Tx event configuration register + */ +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x5c) +/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL1 can send out. + */ +#define RMT_TX_LIM_CH1 0x000001FFU +#define RMT_TX_LIM_CH1_M (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S) +#define RMT_TX_LIM_CH1_V 0x000001FFU +#define RMT_TX_LIM_CH1_S 0 +/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_M (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S) +#define RMT_TX_LOOP_NUM_CH1_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_S 9 +/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/** RMT_LOOP_STOP_EN_CH1 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL1. + */ +#define RMT_LOOP_STOP_EN_CH1 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH1_M (RMT_LOOP_STOP_EN_CH1_V << RMT_LOOP_STOP_EN_CH1_S) +#define RMT_LOOP_STOP_EN_CH1_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH1_S 21 + +/** RMT_CH2_RX_LIM_REG register + * Channel 2 Rx event configuration register + */ +#define RMT_CH2_RX_LIM_REG (DR_REG_RMT_BASE + 0x60) +/** RMT_RX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL2 can receive. + */ +#define RMT_RX_LIM_CH2 0x000001FFU +#define RMT_RX_LIM_CH2_M (RMT_RX_LIM_CH2_V << RMT_RX_LIM_CH2_S) +#define RMT_RX_LIM_CH2_V 0x000001FFU +#define RMT_RX_LIM_CH2_S 0 + +/** RMT_CH3_RX_LIM_REG register + * Channel 3 Rx event configuration register + */ +#define RMT_CH3_RX_LIM_REG (DR_REG_RMT_BASE + 0x64) +/** RMT_RX_LIM_CH3 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL3 can receive. + */ +#define RMT_RX_LIM_CH3 0x000001FFU +#define RMT_RX_LIM_CH3_M (RMT_RX_LIM_CH3_V << RMT_RX_LIM_CH3_S) +#define RMT_RX_LIM_CH3_V 0x000001FFU +#define RMT_RX_LIM_CH3_S 0 + +/** RMT_SYS_CONF_REG register + * RMT apb configuration register + */ +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x68) +/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S) +#define RMT_APB_FIFO_MASK_V 0x00000001U +#define RMT_APB_FIFO_MASK_S 0 +/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S) +#define RMT_MEM_CLK_FORCE_ON_V 0x00000001U +#define RMT_MEM_CLK_FORCE_ON_S 1 +/** RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ +#define RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_MEM_FORCE_PD_M (RMT_MEM_FORCE_PD_V << RMT_MEM_FORCE_PD_S) +#define RMT_MEM_FORCE_PD_V 0x00000001U +#define RMT_MEM_FORCE_PD_S 2 +/** RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ +#define RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_MEM_FORCE_PU_M (RMT_MEM_FORCE_PU_V << RMT_MEM_FORCE_PU_S) +#define RMT_MEM_FORCE_PU_V 0x00000001U +#define RMT_MEM_FORCE_PU_S 3 +/** RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ +#define RMT_SCLK_DIV_NUM 0x000000FFU +#define RMT_SCLK_DIV_NUM_M (RMT_SCLK_DIV_NUM_V << RMT_SCLK_DIV_NUM_S) +#define RMT_SCLK_DIV_NUM_V 0x000000FFU +#define RMT_SCLK_DIV_NUM_S 4 +/** RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_A 0x0000003FU +#define RMT_SCLK_DIV_A_M (RMT_SCLK_DIV_A_V << RMT_SCLK_DIV_A_S) +#define RMT_SCLK_DIV_A_V 0x0000003FU +#define RMT_SCLK_DIV_A_S 12 +/** RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_B 0x0000003FU +#define RMT_SCLK_DIV_B_M (RMT_SCLK_DIV_B_V << RMT_SCLK_DIV_B_S) +#define RMT_SCLK_DIV_B_V 0x0000003FU +#define RMT_SCLK_DIV_B_S 18 +/** RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + */ +#define RMT_SCLK_SEL 0x00000003U +#define RMT_SCLK_SEL_M (RMT_SCLK_SEL_V << RMT_SCLK_SEL_S) +#define RMT_SCLK_SEL_V 0x00000003U +#define RMT_SCLK_SEL_S 24 +/** RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ +#define RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_SCLK_ACTIVE_M (RMT_SCLK_ACTIVE_V << RMT_SCLK_ACTIVE_S) +#define RMT_SCLK_ACTIVE_V 0x00000001U +#define RMT_SCLK_ACTIVE_S 26 +/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (RMT_CLK_EN_V << RMT_CLK_EN_S) +#define RMT_CLK_EN_V 0x00000001U +#define RMT_CLK_EN_S 31 + +/** RMT_TX_SIM_REG register + * RMT TX synchronous register + */ +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x6c) +/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S) +#define RMT_TX_SIM_CH0_V 0x00000001U +#define RMT_TX_SIM_CH0_S 0 +/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S) +#define RMT_TX_SIM_CH1_V 0x00000001U +#define RMT_TX_SIM_CH1_S 1 +/** RMT_TX_SIM_EN : R/W; bitpos: [2]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ +#define RMT_TX_SIM_EN (BIT(2)) +#define RMT_TX_SIM_EN_M (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S) +#define RMT_TX_SIM_EN_V 0x00000001U +#define RMT_TX_SIM_EN_S 2 + +/** RMT_REF_CNT_RST_REG register + * RMT clock divider reset register + */ +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x70) +/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S) +#define RMT_REF_CNT_RST_CH0_V 0x00000001U +#define RMT_REF_CNT_RST_CH0_S 0 +/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S) +#define RMT_REF_CNT_RST_CH1_V 0x00000001U +#define RMT_REF_CNT_RST_CH1_S 1 +/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S) +#define RMT_REF_CNT_RST_CH2_V 0x00000001U +#define RMT_REF_CNT_RST_CH2_S 2 +/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S) +#define RMT_REF_CNT_RST_CH3_V 0x00000001U +#define RMT_REF_CNT_RST_CH3_S 3 + +/** RMT_DATE_REG register + * RMT version register + */ +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc) +/** RMT_DATE : R/W; bitpos: [27:0]; default: 34636307; + * This is the version register. + */ +#define RMT_DATE 0x0FFFFFFFU +#define RMT_DATE_M (RMT_DATE_V << RMT_DATE_S) +#define RMT_DATE_V 0x0FFFFFFFU +#define RMT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/rmt_struct.h b/components/soc/esp32c5/include/soc/rmt_struct.h new file mode 100644 index 0000000000..4d5e16e3bc --- /dev/null +++ b/components/soc/esp32c5/include/soc/rmt_struct.h @@ -0,0 +1,788 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: FIFO R/W registers */ +/** Type of chndata register + * The read and write data register for CHANNELn by apb fifo access. + */ +typedef union { + struct { + /** chndata : HRO; bitpos: [31:0]; default: 0; + * Read and write data for channel n via APB FIFO. + */ + uint32_t chndata:32; + }; + uint32_t val; +} rmt_chndata_reg_t; + + +/** Group: Configuration registers */ +/** Type of chnconf0 register + * Channel n configure register 0 + */ +typedef union { + struct { + /** tx_start_chn : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNELn. + */ + uint32_t tx_start_chn:1; + /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNELn by accessing transmitter. + */ + uint32_t mem_rd_rst_chn:1; + /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. + */ + uint32_t apb_mem_rst_chn:1; + /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNELn. + */ + uint32_t tx_conti_mode_chn:1; + /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0; + * This is the channel n enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ + uint32_t mem_tx_wrap_en_chn:1; + /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNELn when the latter is in + * IDLE state. + */ + uint32_t idle_out_lv_chn:1; + /** idle_out_en_chn : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNELn in IDLE state. + */ + uint32_t idle_out_en_chn:1; + /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNELn sending data out. + */ + uint32_t tx_stop_chn:1; + /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNELn. + */ + uint32_t div_cnt_chn:8; + /** mem_size_chn : R/W; bitpos: [18:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELn. + */ + uint32_t mem_size_chn:3; + uint32_t reserved_19:1; + /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. + * Only valid when RMT_CARRIER_EN_CHn is 1. + */ + uint32_t carrier_eff_en_chn:1; + /** carrier_en_chn : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chn:1; + /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELn. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chn:1; + uint32_t reserved_23:1; + /** conf_update_chn : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNELn + */ + uint32_t conf_update_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} rmt_chnconf0_reg_t; + +/** Type of chmconf0 register + * Channel m configure register 0 + */ +typedef union { + struct { + /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNELm. + */ + uint32_t div_cnt_chm:8; + /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ + uint32_t idle_thres_chm:15; + /** mem_size_chm : R/W; bitpos: [25:23]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELm. + */ + uint32_t mem_size_chm:3; + uint32_t reserved_26:2; + /** carrier_en_chm : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_chm:1; + /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELm. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_chm:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} rmt_chmconf0_reg_t; + +/** Type of chmconf1 register + * Channel m configure register 1 + */ +typedef union { + struct { + /** rx_en_chm : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNELm. + */ + uint32_t rx_en_chm:1; + /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNELm by accessing receiver. + */ + uint32_t mem_wr_rst_chm:1; + /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. + */ + uint32_t apb_mem_rst_chm:1; + /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNELm's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ + uint32_t mem_owner_chm:1; + /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNELm. + */ + uint32_t rx_filter_en_chm:1; + /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ + uint32_t rx_filter_thres_chm:8; + /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0; + * This is the channel m enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ + uint32_t mem_rx_wrap_en_chm:1; + uint32_t reserved_14:1; + /** conf_update_chm : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNELm + */ + uint32_t conf_update_chm:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} rmt_chmconf1_reg_t; + +/** Type of sys_conf register + * RMT apb configuration register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ + uint32_t apb_fifo_mask:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ + uint32_t mem_clk_force_on:1; + /** mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ + uint32_t mem_force_pd:1; + /** mem_force_pu : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ + uint32_t mem_force_pu:1; + /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL + */ + uint32_t sclk_sel:2; + /** sclk_active : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ + uint32_t sclk_active:1; + uint32_t reserved_27:4; + /** clk_en : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ + uint32_t clk_en:1; + }; + uint32_t val; +} rmt_sys_conf_reg_t; + +/** Type of ref_cnt_rst register + * RMT clock divider reset register + */ +typedef union { + struct { + /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ + uint32_t ref_cnt_rst_ch0:1; + /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ + uint32_t ref_cnt_rst_ch1:1; + /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ + uint32_t ref_cnt_rst_ch2:1; + /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ + uint32_t ref_cnt_rst_ch3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} rmt_ref_cnt_rst_reg_t; + + +/** Group: Status registers */ +/** Type of chnstatus register + * Channel n status register + */ +typedef union { + struct { + /** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNELn is + * using the RAM. + */ + uint32_t mem_raddr_ex_chn:9; + /** state_chn : RO; bitpos: [11:9]; default: 0; + * This register records the FSM status of CHANNELn. + */ + uint32_t state_chn:3; + /** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ + uint32_t apb_mem_waddr_chn:9; + /** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0; + * This status bit will be set if the offset address out of memory size when reading + * via APB bus. + */ + uint32_t apb_mem_rd_err_chn:1; + /** mem_empty_chn : RO; bitpos: [22]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ + uint32_t mem_empty_chn:1; + /** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ + uint32_t apb_mem_wr_err_chn:1; + /** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0; + * This register records the memory address offset when reading RAM over APB bus. + */ + uint32_t apb_mem_raddr_chn:8; + }; + uint32_t val; +} rmt_chnstatus_reg_t; + +/** Type of chmstatus register + * Channel m status register + */ +typedef union { + struct { + /** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0; + * This register records the memory address offset when receiver of CHANNELm is using + * the RAM. + */ + uint32_t mem_waddr_ex_chm:9; + uint32_t reserved_9:3; + /** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0; + * This register records the memory address offset when reads RAM over APB bus. + */ + uint32_t apb_mem_raddr_chm:9; + uint32_t reserved_21:1; + /** state_chm : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELm. + */ + uint32_t state_chm:3; + /** mem_owner_err_chm : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ + uint32_t mem_owner_err_chm:1; + /** mem_full_chm : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ + uint32_t mem_full_chm:1; + /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ + uint32_t apb_mem_rd_err_chm:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_chmstatus_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ + uint32_t ch0_tx_end_int_raw:1; + /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ + uint32_t ch1_tx_end_int_raw:1; + /** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when reception done. + */ + uint32_t ch2_rx_end_int_raw:1; + /** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when reception done. + */ + uint32_t ch3_rx_end_int_raw:1; + /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch0_err_int_raw:1; + /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch1_err_int_raw:1; + /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch2_err_int_raw:1; + /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL$m. Triggered when error occurs. + */ + uint32_t ch3_err_int_raw:1; + /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch0_tx_thr_event_int_raw:1; + /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch1_tx_thr_event_int_raw:1; + /** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch2_rx_thr_event_int_raw:1; + /** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch3_rx_thr_event_int_raw:1; + /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch0_tx_loop_int_raw:1; + /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch1_tx_loop_int_raw:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_st:1; + /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_st:1; + /** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_RX_END_INT. + */ + uint32_t ch2_rx_end_int_st:1; + /** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_RX_END_INT. + */ + uint32_t ch3_rx_end_int_st:1; + /** ch0_err_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch0_err_int_st:1; + /** ch1_err_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch1_err_int_st:1; + /** ch2_err_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch2_err_int_st:1; + /** ch3_err_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH$n_ERR_INT. + */ + uint32_t ch3_err_int_st:1; + /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_st:1; + /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_st:1; + /** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + */ + uint32_t ch2_rx_thr_event_int_st:1; + /** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_RX_THR_EVENT_INT. + */ + uint32_t ch3_rx_thr_event_int_st:1; + /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_st:1; + /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_st:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_ena:1; + /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_ena:1; + /** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_RX_END_INT. + */ + uint32_t ch2_rx_end_int_ena:1; + /** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_RX_END_INT. + */ + uint32_t ch3_rx_end_int_ena:1; + /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch0_err_int_ena:1; + /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch1_err_int_ena:1; + /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch2_err_int_ena:1; + /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH$n_ERR_INT. + */ + uint32_t ch3_err_int_ena:1; + /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_ena:1; + /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_ena:1; + /** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_RX_THR_EVENT_INT. + */ + uint32_t ch2_rx_thr_event_int_ena:1; + /** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_RX_THR_EVENT_INT. + */ + uint32_t ch3_rx_thr_event_int_ena:1; + /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_ena:1; + /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_ena:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ + uint32_t ch0_tx_end_int_clr:1; + /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ + uint32_t ch1_tx_end_int_clr:1; + /** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_RX_END_INT interrupt. + */ + uint32_t ch2_rx_end_int_clr:1; + /** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_RX_END_INT interrupt. + */ + uint32_t ch3_rx_end_int_clr:1; + /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch0_err_int_clr:1; + /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch1_err_int_clr:1; + /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch2_err_int_clr:1; + /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH$n_ERR_INT interrupt. + */ + uint32_t ch3_err_int_clr:1; + /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch0_tx_thr_event_int_clr:1; + /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch1_tx_thr_event_int_clr:1; + /** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch2_rx_thr_event_int_clr:1; + /** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch3_rx_thr_event_int_clr:1; + /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ + uint32_t ch0_tx_loop_int_clr:1; + /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ + uint32_t ch1_tx_loop_int_clr:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} rmt_int_clr_reg_t; + + +/** Group: Carrier wave duty cycle registers */ +/** Type of chncarrier_duty register + * Channel n duty cycle configuration register + */ +typedef union { + struct { + /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNELn. + */ + uint32_t carrier_low_chn:16; + /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNELn. + */ + uint32_t carrier_high_chn:16; + }; + uint32_t val; +} rmt_chncarrier_duty_reg_t; + +/** Type of chm_rx_carrier_rm register + * Channel m carrier remove register + */ +typedef union { + struct { + /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_low_thres_chm:16; + /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_high_thres_chm:16; + }; + uint32_t val; +} rmt_chm_rx_carrier_rm_reg_t; + + +/** Group: Tx event configuration registers */ +/** Type of chn_tx_lim register + * Channel n Tx event configuration register + */ +typedef union { + struct { + /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELn can send out. + */ + uint32_t tx_lim_chn:9; + /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ + uint32_t tx_loop_num_chn:10; + /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ + uint32_t tx_loop_cnt_en_chn:1; + /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ + uint32_t loop_count_reset_chn:1; + /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNELn. + */ + uint32_t loop_stop_en_chn:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} rmt_chn_tx_lim_reg_t; + +/** Type of tx_sim register + * RMT TX synchronous register + */ +typedef union { + struct { + /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch0:1; + /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch1:1; + /** tx_sim_en : R/W; bitpos: [2]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ + uint32_t tx_sim_en:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} rmt_tx_sim_reg_t; + + +/** Group: Rx event configuration registers */ +/** Type of chm_rx_lim register + * Channel m Rx event configuration register + */ +typedef union { + struct { + /** rx_lim_chm : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELm can receive. + */ + uint32_t rx_lim_chm:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} rmt_chm_rx_lim_reg_t; + + +/** Group: Version register */ +/** Type of date register + * RMT version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34636307; + * This is the version register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} rmt_date_reg_t; + + +typedef struct { + volatile rmt_chndata_reg_t chndata[4]; + volatile rmt_chnconf0_reg_t chnconf0[2]; + volatile rmt_chmconf0_reg_t ch2conf0; + volatile rmt_chmconf1_reg_t ch2conf1; + volatile rmt_chmconf0_reg_t ch3conf0; + volatile rmt_chmconf1_reg_t ch3conf1; + volatile rmt_chnstatus_reg_t chnstatus[2]; + volatile rmt_chmstatus_reg_t chmstatus[2]; + volatile rmt_int_raw_reg_t int_raw; + volatile rmt_int_st_reg_t int_st; + volatile rmt_int_ena_reg_t int_ena; + volatile rmt_int_clr_reg_t int_clr; + volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2]; + volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2]; + volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2]; + volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2]; + volatile rmt_sys_conf_reg_t sys_conf; + volatile rmt_tx_sim_reg_t tx_sim; + volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; + uint32_t reserved_074[22]; + volatile rmt_date_reg_t date; +} rmt_dev_t; + +extern rmt_dev_t RMT; + +#ifndef __cplusplus +_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/sdio_hinf_reg.h b/components/soc/esp32c5/include/soc/sdio_hinf_reg.h new file mode 100644 index 0000000000..d8f8f45d64 --- /dev/null +++ b/components/soc/esp32c5/include/soc/sdio_hinf_reg.h @@ -0,0 +1,576 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HINF_CFG_DATA0_REG register + * Configure sdio cis content + */ +#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) +/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ +#define HINF_DEVICE_ID_FN1 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S) +#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_S 0 +/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ +#define HINF_USER_ID_FN1 0x0000FFFFU +#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S) +#define HINF_USER_ID_FN1_V 0x0000FFFFU +#define HINF_USER_ID_FN1_S 16 + +/** HINF_CFG_DATA1_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) +/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ +#define HINF_SDIO_ENABLE (BIT(0)) +#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S) +#define HINF_SDIO_ENABLE_V 0x00000001U +#define HINF_SDIO_ENABLE_S 0 +/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY1 (BIT(1)) +#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S) +#define HINF_SDIO_IOREADY1_V 0x00000001U +#define HINF_SDIO_IOREADY1_S 1 +/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ +#define HINF_HIGHSPEED_ENABLE (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S) +#define HINF_HIGHSPEED_ENABLE_V 0x00000001U +#define HINF_HIGHSPEED_ENABLE_S 2 +/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ +#define HINF_HIGHSPEED_MODE (BIT(3)) +#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S) +#define HINF_HIGHSPEED_MODE_V 0x00000001U +#define HINF_HIGHSPEED_MODE_S 3 +/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ +#define HINF_SDIO_CD_ENABLE (BIT(4)) +#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S) +#define HINF_SDIO_CD_ENABLE_V 0x00000001U +#define HINF_SDIO_CD_ENABLE_S 4 +/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY2 (BIT(5)) +#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S) +#define HINF_SDIO_IOREADY2_V 0x00000001U +#define HINF_SDIO_IOREADY2_S 5 +/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ +#define HINF_SDIO_INT_MASK (BIT(6)) +#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S) +#define HINF_SDIO_INT_MASK_V 0x00000001U +#define HINF_SDIO_INT_MASK_S 6 +/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ +#define HINF_IOENABLE2 (BIT(7)) +#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S) +#define HINF_IOENABLE2_V 0x00000001U +#define HINF_IOENABLE2_S 7 +/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ +#define HINF_CD_DISABLE (BIT(8)) +#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S) +#define HINF_CD_DISABLE_V 0x00000001U +#define HINF_CD_DISABLE_S 8 +/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ +#define HINF_FUNC1_EPS (BIT(9)) +#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S) +#define HINF_FUNC1_EPS_V 0x00000001U +#define HINF_FUNC1_EPS_S 9 +/** HINF_EMP : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ +#define HINF_EMP (BIT(10)) +#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S) +#define HINF_EMP_V 0x00000001U +#define HINF_EMP_S 10 +/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ +#define HINF_IOENABLE1 (BIT(11)) +#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S) +#define HINF_IOENABLE1_V 0x00000001U +#define HINF_IOENABLE1_S 11 +/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ +#define HINF_SDIO_VER 0x00000FFFU +#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S) +#define HINF_SDIO_VER_V 0x00000FFFU +#define HINF_SDIO_VER_S 12 +/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ +#define HINF_FUNC2_EPS (BIT(24)) +#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S) +#define HINF_FUNC2_EPS_V 0x00000001U +#define HINF_FUNC2_EPS_S 24 +/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ +#define HINF_SDIO20_CONF 0x0000007FU +#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S) +#define HINF_SDIO20_CONF_V 0x0000007FU +#define HINF_SDIO20_CONF_S 25 + +/** HINF_CFG_TIMING_REG register + * Timing configuration registers + */ +#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8) +/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ +#define HINF_NCRC 0x00000007U +#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S) +#define HINF_NCRC_V 0x00000007U +#define HINF_NCRC_S 0 +/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ +#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S) +#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_S 3 +/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ +#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S) +#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_S 10 +/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ +#define HINF_SDCLK_STOP_THRES 0x000007FFU +#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S) +#define HINF_SDCLK_STOP_THRES_V 0x000007FFU +#define HINF_SDCLK_STOP_THRES_S 16 +/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ +#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S) +#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_S 28 + +/** HINF_CFG_UPDATE_REG register + * update sdio configurations + */ +#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc) +/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ +#define HINF_CONF_UPDATE (BIT(0)) +#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S) +#define HINF_CONF_UPDATE_V 0x00000001U +#define HINF_CONF_UPDATE_S 0 + +/** HINF_CFG_DATA7_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c) +/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ +#define HINF_PIN_STATE 0x000000FFU +#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S) +#define HINF_PIN_STATE_V 0x000000FFU +#define HINF_PIN_STATE_S 0 +/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ +#define HINF_CHIP_STATE 0x000000FFU +#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S) +#define HINF_CHIP_STATE_V 0x000000FFU +#define HINF_CHIP_STATE_S 8 +/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ +#define HINF_SDIO_RST (BIT(16)) +#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S) +#define HINF_SDIO_RST_V 0x00000001U +#define HINF_SDIO_RST_S 16 +/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ +#define HINF_SDIO_IOREADY0 (BIT(17)) +#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S) +#define HINF_SDIO_IOREADY0_V 0x00000001U +#define HINF_SDIO_IOREADY0_S 17 +/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ +#define HINF_SDIO_MEM_PD (BIT(18)) +#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S) +#define HINF_SDIO_MEM_PD_V 0x00000001U +#define HINF_SDIO_MEM_PD_S 18 +/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ +#define HINF_ESDIO_DATA1_INT_EN (BIT(19)) +#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S) +#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U +#define HINF_ESDIO_DATA1_INT_EN_S 19 +/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ +#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20)) +#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S) +#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_SW_S 20 +/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ +#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21)) +#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S) +#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U +#define HINF_DDR50_BLK_LEN_FIX_EN_S 21 +/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ +#define HINF_CLK_EN (BIT(22)) +#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S) +#define HINF_CLK_EN_V 0x00000001U +#define HINF_CLK_EN_S 22 +/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ +#define HINF_SDDR50 (BIT(23)) +#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S) +#define HINF_SDDR50_V 0x00000001U +#define HINF_SDDR50_S 23 +/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ +#define HINF_SSDR104 (BIT(24)) +#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S) +#define HINF_SSDR104_V 0x00000001U +#define HINF_SSDR104_S 24 +/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ +#define HINF_SSDR50 (BIT(25)) +#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S) +#define HINF_SSDR50_V 0x00000001U +#define HINF_SSDR50_S 25 +/** HINF_SDTD : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ +#define HINF_SDTD (BIT(26)) +#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S) +#define HINF_SDTD_V 0x00000001U +#define HINF_SDTD_S 26 +/** HINF_SDTA : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ +#define HINF_SDTA (BIT(27)) +#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S) +#define HINF_SDTA_V 0x00000001U +#define HINF_SDTA_S 27 +/** HINF_SDTC : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ +#define HINF_SDTC (BIT(28)) +#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S) +#define HINF_SDTC_V 0x00000001U +#define HINF_SDTC_S 28 +/** HINF_SAI : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ +#define HINF_SAI (BIT(29)) +#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S) +#define HINF_SAI_V 0x00000001U +#define HINF_SAI_S 29 +/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ +#define HINF_SDIO_WAKEUP_CLR (BIT(30)) +#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S) +#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U +#define HINF_SDIO_WAKEUP_CLR_S 30 + +/** HINF_CIS_CONF_W0_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20) +/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ +#define HINF_CIS_CONF_W0 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S) +#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_S 0 + +/** HINF_CIS_CONF_W1_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24) +/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ +#define HINF_CIS_CONF_W1 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S) +#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_S 0 + +/** HINF_CIS_CONF_W2_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28) +/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ +#define HINF_CIS_CONF_W2 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S) +#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_S 0 + +/** HINF_CIS_CONF_W3_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c) +/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ +#define HINF_CIS_CONF_W3 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S) +#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_S 0 + +/** HINF_CIS_CONF_W4_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30) +/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ +#define HINF_CIS_CONF_W4 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S) +#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_S 0 + +/** HINF_CIS_CONF_W5_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34) +/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ +#define HINF_CIS_CONF_W5 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S) +#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_S 0 + +/** HINF_CIS_CONF_W6_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38) +/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ +#define HINF_CIS_CONF_W6 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S) +#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_S 0 + +/** HINF_CIS_CONF_W7_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c) +/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ +#define HINF_CIS_CONF_W7 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S) +#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_S 0 + +/** HINF_CFG_DATA16_REG register + * SDIO cis configuration register + */ +#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) +/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ +#define HINF_DEVICE_ID_FN2 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S) +#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_S 0 +/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ +#define HINF_USER_ID_FN2 0x0000FFFFU +#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S) +#define HINF_USER_ID_FN2_V 0x0000FFFFU +#define HINF_USER_ID_FN2_S 16 + +/** HINF_CFG_UHS1_INT_MODE_REG register + * configure int to start and end ahead of time in uhs1 mode + */ +#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44) +/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_END_AHEAD_MODE 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S) +#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_S 0 +/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_END_AHEAD_MODE 0x00000003U +#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S) +#define HINF_INT_END_AHEAD_MODE_V 0x00000003U +#define HINF_INT_END_AHEAD_MODE_S 2 +/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S) +#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_S 4 +/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_ST_AHEAD_MODE 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S) +#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_S 6 + +/** HINF_CONF_STATUS_REG register + * func0 config0 status + */ +#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54) +/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ +#define HINF_FUNC0_CONFIG0 0x000000FFU +#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S) +#define HINF_FUNC0_CONFIG0_V 0x000000FFU +#define HINF_FUNC0_CONFIG0_S 0 +/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0; + * sdr25 status + */ +#define HINF_SDR25_ST (BIT(8)) +#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S) +#define HINF_SDR25_ST_V 0x00000001U +#define HINF_SDR25_ST_S 8 +/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0; + * sdr50 status + */ +#define HINF_SDR50_ST (BIT(9)) +#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S) +#define HINF_SDR50_ST_V 0x00000001U +#define HINF_SDR50_ST_S 9 +/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0; + * sdr104 status + */ +#define HINF_SDR104_ST (BIT(10)) +#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S) +#define HINF_SDR104_ST_V 0x00000001U +#define HINF_SDR104_ST_S 10 +/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0; + * ddr50 status + */ +#define HINF_DDR50_ST (BIT(11)) +#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S) +#define HINF_DDR50_ST_V 0x00000001U +#define HINF_DDR50_ST_S 11 +/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ +#define HINF_TUNE_ST 0x00000007U +#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S) +#define HINF_TUNE_ST_V 0x00000007U +#define HINF_TUNE_ST_S 12 +/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ +#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15)) +#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S) +#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_ST_S 15 +/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ +#define HINF_SDIO_SWITCH_END (BIT(16)) +#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S) +#define HINF_SDIO_SWITCH_END_V 0x00000001U +#define HINF_SDIO_SWITCH_END_S 16 + +/** HINF_SDIO_SLAVE_LDO_CONF_REG register + * sdio slave ldo control register + */ +#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0) +/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ +#define HINF_LDO_READY_CTL_IN_EN (BIT(0)) +#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S) +#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U +#define HINF_LDO_READY_CTL_IN_EN_S 0 +/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ +#define HINF_LDO_READY_THRES 0x0000001FU +#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S) +#define HINF_LDO_READY_THRES_V 0x0000001FU +#define HINF_LDO_READY_THRES_S 1 +/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ +#define HINF_LDO_READY_IGNORE_EN (BIT(6)) +#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S) +#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U +#define HINF_LDO_READY_IGNORE_EN_S 6 + +/** HINF_SDIO_DATE_REG register + * ******* Description *********** + */ +#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc) +/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208; + * sdio version date. + */ +#define HINF_SDIO_DATE 0xFFFFFFFFU +#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S) +#define HINF_SDIO_DATE_V 0xFFFFFFFFU +#define HINF_SDIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/sdio_hinf_struct.h b/components/soc/esp32c5/include/soc/sdio_hinf_struct.h new file mode 100644 index 0000000000..e75ab3e27d --- /dev/null +++ b/components/soc/esp32c5/include/soc/sdio_hinf_struct.h @@ -0,0 +1,492 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of cfg_data0 register + * Configure sdio cis content + */ +typedef union { + struct { + /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ + uint32_t device_id_fn1:16; + /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ + uint32_t user_id_fn1:16; + }; + uint32_t val; +} hinf_cfg_data0_reg_t; + +/** Type of cfg_data1 register + * SDIO configuration register + */ +typedef union { + struct { + /** sdio_enable : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ + uint32_t sdio_enable:1; + /** sdio_ioready1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready1:1; + /** highspeed_enable : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ + uint32_t highspeed_enable:1; + /** highspeed_mode : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ + uint32_t highspeed_mode:1; + /** sdio_cd_enable : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ + uint32_t sdio_cd_enable:1; + /** sdio_ioready2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready2:1; + /** sdio_int_mask : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ + uint32_t sdio_int_mask:1; + /** ioenable2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ + uint32_t ioenable2:1; + /** cd_disable : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ + uint32_t cd_disable:1; + /** func1_eps : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ + uint32_t func1_eps:1; + /** emp : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ + uint32_t emp:1; + /** ioenable1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ + uint32_t ioenable1:1; + /** sdio_ver : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ + uint32_t sdio_ver:12; + /** func2_eps : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ + uint32_t func2_eps:1; + /** sdio20_conf : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ + uint32_t sdio20_conf:7; + }; + uint32_t val; +} hinf_cfg_data1_reg_t; + +/** Type of cfg_timing register + * Timing configuration registers + */ +typedef union { + struct { + /** ncrc : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ + uint32_t ncrc:3; + /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ + uint32_t pst_end_cmd_low_value:7; + /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ + uint32_t pst_end_data_low_value:6; + /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ + uint32_t sdclk_stop_thres:11; + uint32_t reserved_27:1; + /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ + uint32_t sample_clk_divider:4; + }; + uint32_t val; +} hinf_cfg_timing_reg_t; + +/** Type of cfg_update register + * update sdio configurations + */ +typedef union { + struct { + /** conf_update : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ + uint32_t conf_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hinf_cfg_update_reg_t; + +/** Type of cfg_data7 register + * SDIO configuration register + */ +typedef union { + struct { + /** pin_state : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ + uint32_t pin_state:8; + /** chip_state : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ + uint32_t chip_state:8; + /** sdio_rst : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ + uint32_t sdio_rst:1; + /** sdio_ioready0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ + uint32_t sdio_ioready0:1; + /** sdio_mem_pd : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ + uint32_t sdio_mem_pd:1; + /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ + uint32_t esdio_data1_int_en:1; + /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ + uint32_t sdio_switch_volt_sw:1; + /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ + uint32_t ddr50_blk_len_fix_en:1; + /** clk_en : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ + uint32_t clk_en:1; + /** sddr50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ + uint32_t sddr50:1; + /** ssdr104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ + uint32_t ssdr104:1; + /** ssdr50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ + uint32_t ssdr50:1; + /** sdtd : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ + uint32_t sdtd:1; + /** sdta : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ + uint32_t sdta:1; + /** sdtc : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ + uint32_t sdtc:1; + /** sai : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ + uint32_t sai:1; + /** sdio_wakeup_clr : WT; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ + uint32_t sdio_wakeup_clr:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} hinf_cfg_data7_reg_t; + +/** Type of cis_conf_w0 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ + uint32_t cis_conf_w0:32; + }; + uint32_t val; +} hinf_cis_conf_w0_reg_t; + +/** Type of cis_conf_w1 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ + uint32_t cis_conf_w1:32; + }; + uint32_t val; +} hinf_cis_conf_w1_reg_t; + +/** Type of cis_conf_w2 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ + uint32_t cis_conf_w2:32; + }; + uint32_t val; +} hinf_cis_conf_w2_reg_t; + +/** Type of cis_conf_w3 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ + uint32_t cis_conf_w3:32; + }; + uint32_t val; +} hinf_cis_conf_w3_reg_t; + +/** Type of cis_conf_w4 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ + uint32_t cis_conf_w4:32; + }; + uint32_t val; +} hinf_cis_conf_w4_reg_t; + +/** Type of cis_conf_w5 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ + uint32_t cis_conf_w5:32; + }; + uint32_t val; +} hinf_cis_conf_w5_reg_t; + +/** Type of cis_conf_w6 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ + uint32_t cis_conf_w6:32; + }; + uint32_t val; +} hinf_cis_conf_w6_reg_t; + +/** Type of cis_conf_w7 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ + uint32_t cis_conf_w7:32; + }; + uint32_t val; +} hinf_cis_conf_w7_reg_t; + +/** Type of cfg_data16 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ + uint32_t device_id_fn2:16; + /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ + uint32_t user_id_fn2:16; + }; + uint32_t val; +} hinf_cfg_data16_reg_t; + +/** Type of cfg_uhs1_int_mode register + * configure int to start and end ahead of time in uhs1 mode + */ +typedef union { + struct { + /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_end_ahead_mode:2; + /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_end_ahead_mode:2; + /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_st_ahead_mode:2; + /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_st_ahead_mode:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} hinf_cfg_uhs1_int_mode_reg_t; + +/** Type of sdio_slave_ldo_conf register + * sdio slave ldo control register + */ +typedef union { + struct { + /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ + uint32_t ldo_ready_ctl_in_en:1; + /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ + uint32_t ldo_ready_thres:5; + /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ + uint32_t ldo_ready_ignore_en:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} hinf_sdio_slave_ldo_conf_reg_t; + + +/** Group: Status registers */ +/** Type of conf_status register + * func0 config0 status + */ +typedef union { + struct { + /** func0_config0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ + uint32_t func0_config0:8; + /** sdr25_st : RO; bitpos: [8]; default: 0; + * sdr25 status + */ + uint32_t sdr25_st:1; + /** sdr50_st : RO; bitpos: [9]; default: 0; + * sdr50 status + */ + uint32_t sdr50_st:1; + /** sdr104_st : RO; bitpos: [10]; default: 0; + * sdr104 status + */ + uint32_t sdr104_st:1; + /** ddr50_st : RO; bitpos: [11]; default: 0; + * ddr50 status + */ + uint32_t ddr50_st:1; + /** tune_st : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ + uint32_t tune_st:3; + /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ + uint32_t sdio_switch_volt_st:1; + /** sdio_switch_end : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ + uint32_t sdio_switch_end:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hinf_conf_status_reg_t; + + +/** Group: Version register */ +/** Type of sdio_date register + * ******* Description *********** + */ +typedef union { + struct { + /** sdio_date : R/W; bitpos: [31:0]; default: 35664208; + * sdio version date. + */ + uint32_t sdio_date:32; + }; + uint32_t val; +} hinf_sdio_date_reg_t; + + +typedef struct { + volatile hinf_cfg_data0_reg_t cfg_data0; + volatile hinf_cfg_data1_reg_t cfg_data1; + volatile hinf_cfg_timing_reg_t cfg_timing; + volatile hinf_cfg_update_reg_t cfg_update; + uint32_t reserved_010[3]; + volatile hinf_cfg_data7_reg_t cfg_data7; + volatile hinf_cis_conf_w0_reg_t cis_conf_w0; + volatile hinf_cis_conf_w1_reg_t cis_conf_w1; + volatile hinf_cis_conf_w2_reg_t cis_conf_w2; + volatile hinf_cis_conf_w3_reg_t cis_conf_w3; + volatile hinf_cis_conf_w4_reg_t cis_conf_w4; + volatile hinf_cis_conf_w5_reg_t cis_conf_w5; + volatile hinf_cis_conf_w6_reg_t cis_conf_w6; + volatile hinf_cis_conf_w7_reg_t cis_conf_w7; + volatile hinf_cfg_data16_reg_t cfg_data16; + volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode; + uint32_t reserved_048[3]; + volatile hinf_conf_status_reg_t conf_status; + uint32_t reserved_058[22]; + volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf; + uint32_t reserved_0b4[18]; + volatile hinf_sdio_date_reg_t sdio_date; +} hinf_dev_t; + +extern hinf_dev_t HINF; + +#ifndef __cplusplus +_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/sdio_slc_reg.h b/components/soc/esp32c5/include/soc/sdio_slc_reg.h new file mode 100644 index 0000000000..502b77201e --- /dev/null +++ b/components/soc/esp32c5/include/soc/sdio_slc_reg.h @@ -0,0 +1,4301 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDIO_SLCCONF0_REG register + * ******* Description *********** + */ +#define SDIO_SLCCONF0_REG (DR_REG_SDIO_BASE + 0x0) +/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0; + * Set 1 to reset tx fsm in dma slc0. + */ +#define SDIO_SLC0_TX_RST (BIT(0)) +#define SDIO_SLC0_TX_RST_M (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S) +#define SDIO_SLC0_TX_RST_V 0x00000001U +#define SDIO_SLC0_TX_RST_S 0 +/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0; + * Set 1 to reset rx fsm in dma slc0. + */ +#define SDIO_SLC0_RX_RST (BIT(1)) +#define SDIO_SLC0_RX_RST_M (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S) +#define SDIO_SLC0_RX_RST_V 0x00000001U +#define SDIO_SLC0_RX_RST_S 1 +/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_FIFO_RST (BIT(2)) +#define SDIO_SLC_AHBM_FIFO_RST_M (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S) +#define SDIO_SLC_AHBM_FIFO_RST_V 0x00000001U +#define SDIO_SLC_AHBM_FIFO_RST_S 2 +/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_RST (BIT(3)) +#define SDIO_SLC_AHBM_RST_M (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S) +#define SDIO_SLC_AHBM_RST_V 0x00000001U +#define SDIO_SLC_AHBM_RST_S 3 +/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC0_TX_LOOP_TEST (BIT(4)) +#define SDIO_SLC0_TX_LOOP_TEST_M (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S) +#define SDIO_SLC0_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_TX_LOOP_TEST_S 4 +/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC0_RX_LOOP_TEST (BIT(5)) +#define SDIO_SLC0_RX_LOOP_TEST_M (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S) +#define SDIO_SLC0_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_RX_LOOP_TEST_S 5 +/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ +#define SDIO_SLC0_RX_AUTO_WRBACK (BIT(6)) +#define SDIO_SLC0_RX_AUTO_WRBACK_M (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S) +#define SDIO_SLC0_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC0_RX_AUTO_WRBACK_S 6 +/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_NO_RESTART_CLR (BIT(7)) +#define SDIO_SLC0_RX_NO_RESTART_CLR_M (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S) +#define SDIO_SLC0_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC0_RX_NO_RESTART_CLR_S 7 +/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_RXDSCR_BURST_EN (BIT(8)) +#define SDIO_SLC0_RXDSCR_BURST_EN_M (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S) +#define SDIO_SLC0_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDSCR_BURST_EN_S 8 +/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ +#define SDIO_SLC0_RXDATA_BURST_EN (BIT(9)) +#define SDIO_SLC0_RXDATA_BURST_EN_M (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S) +#define SDIO_SLC0_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_EN_S 9 +/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_RXLINK_AUTO_RET (BIT(10)) +#define SDIO_SLC0_RXLINK_AUTO_RET_M (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S) +#define SDIO_SLC0_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_RXLINK_AUTO_RET_S 10 +/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_TXLINK_AUTO_RET (BIT(11)) +#define SDIO_SLC0_TXLINK_AUTO_RET_M (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S) +#define SDIO_SLC0_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_TXLINK_AUTO_RET_S 11 +/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_TXDSCR_BURST_EN (BIT(12)) +#define SDIO_SLC0_TXDSCR_BURST_EN_M (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S) +#define SDIO_SLC0_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDSCR_BURST_EN_S 12 +/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ +#define SDIO_SLC0_TXDATA_BURST_EN (BIT(13)) +#define SDIO_SLC0_TXDATA_BURST_EN_M (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S) +#define SDIO_SLC0_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_EN_S 13 +/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ +#define SDIO_SLC0_TOKEN_AUTO_CLR (BIT(14)) +#define SDIO_SLC0_TOKEN_AUTO_CLR_M (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S) +#define SDIO_SLC0_TOKEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN_AUTO_CLR_S 14 +/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1; + * reserved + */ +#define SDIO_SLC0_TOKEN_SEL (BIT(15)) +#define SDIO_SLC0_TOKEN_SEL_M (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S) +#define SDIO_SLC0_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC0_TOKEN_SEL_S 15 +/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0; + * Set 1 to reset tx fsm in dma slc0. + */ +#define SDIO_SLC1_TX_RST (BIT(16)) +#define SDIO_SLC1_TX_RST_M (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S) +#define SDIO_SLC1_TX_RST_V 0x00000001U +#define SDIO_SLC1_TX_RST_S 16 +/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0; + * Set 1 to reset rx fsm in dma slc0. + */ +#define SDIO_SLC1_RX_RST (BIT(17)) +#define SDIO_SLC1_RX_RST_M (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S) +#define SDIO_SLC1_RX_RST_V 0x00000001U +#define SDIO_SLC1_RX_RST_S 17 +/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_MASK_EN (BIT(18)) +#define SDIO_SLC0_WR_RETRY_MASK_EN_M (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S) +#define SDIO_SLC0_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_MASK_EN_S 18 +/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_MASK_EN (BIT(19)) +#define SDIO_SLC1_WR_RETRY_MASK_EN_M (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S) +#define SDIO_SLC1_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_MASK_EN_S 19 +/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_TX_LOOP_TEST (BIT(20)) +#define SDIO_SLC1_TX_LOOP_TEST_M (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S) +#define SDIO_SLC1_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_TX_LOOP_TEST_S 20 +/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_RX_LOOP_TEST (BIT(21)) +#define SDIO_SLC1_RX_LOOP_TEST_M (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S) +#define SDIO_SLC1_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_RX_LOOP_TEST_S 21 +/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ +#define SDIO_SLC1_RX_AUTO_WRBACK (BIT(22)) +#define SDIO_SLC1_RX_AUTO_WRBACK_M (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S) +#define SDIO_SLC1_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC1_RX_AUTO_WRBACK_S 22 +/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0; + * ******* Description *********** + */ +#define SDIO_SLC1_RX_NO_RESTART_CLR (BIT(23)) +#define SDIO_SLC1_RX_NO_RESTART_CLR_M (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S) +#define SDIO_SLC1_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC1_RX_NO_RESTART_CLR_S 23 +/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc1,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc1 + */ +#define SDIO_SLC1_RXDSCR_BURST_EN (BIT(24)) +#define SDIO_SLC1_RXDSCR_BURST_EN_M (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S) +#define SDIO_SLC1_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDSCR_BURST_EN_S 24 +/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ +#define SDIO_SLC1_RXDATA_BURST_EN (BIT(25)) +#define SDIO_SLC1_RXDATA_BURST_EN_M (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S) +#define SDIO_SLC1_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_EN_S 25 +/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_RXLINK_AUTO_RET (BIT(26)) +#define SDIO_SLC1_RXLINK_AUTO_RET_M (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S) +#define SDIO_SLC1_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_RXLINK_AUTO_RET_S 26 +/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_TXLINK_AUTO_RET (BIT(27)) +#define SDIO_SLC1_TXLINK_AUTO_RET_M (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S) +#define SDIO_SLC1_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_TXLINK_AUTO_RET_S 27 +/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc1,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc1 + */ +#define SDIO_SLC1_TXDSCR_BURST_EN (BIT(28)) +#define SDIO_SLC1_TXDSCR_BURST_EN_M (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S) +#define SDIO_SLC1_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDSCR_BURST_EN_S 28 +/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ +#define SDIO_SLC1_TXDATA_BURST_EN (BIT(29)) +#define SDIO_SLC1_TXDATA_BURST_EN_M (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S) +#define SDIO_SLC1_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_EN_S 29 +/** SDIO_SLC1_TOKEN_AUTO_CLR : R/W; bitpos: [30]; default: 1; + * auto clear slc1_token1 enable + */ +#define SDIO_SLC1_TOKEN_AUTO_CLR (BIT(30)) +#define SDIO_SLC1_TOKEN_AUTO_CLR_M (SDIO_SLC1_TOKEN_AUTO_CLR_V << SDIO_SLC1_TOKEN_AUTO_CLR_S) +#define SDIO_SLC1_TOKEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN_AUTO_CLR_S 30 +/** SDIO_SLC1_TOKEN_SEL : R/W; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_SEL (BIT(31)) +#define SDIO_SLC1_TOKEN_SEL_M (SDIO_SLC1_TOKEN_SEL_V << SDIO_SLC1_TOKEN_SEL_S) +#define SDIO_SLC1_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC1_TOKEN_SEL_S 31 + +/** SDIO_SLC0INT_RAW_REG register + * ******* Description *********** + */ +#define SDIO_SLC0INT_RAW_REG (DR_REG_SDIO_BASE + 0x4) +/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC0_RX_START_INT_RAW_M (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S) +#define SDIO_SLC0_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_RAW_S 8 +/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC0_TX_START_INT_RAW_M (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S) +#define SDIO_SLC0_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_RAW_S 9 +/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_RAW_M (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S) +#define SDIO_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_RAW_M (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S) +#define SDIO_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of slc0 finishing receiving data to one buffer + */ +#define SDIO_SLC0_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_RAW_M (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S) +#define SDIO_SLC0_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of slc0 finishing receiving data + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of slc0 finishing sending data from one buffer + */ +#define SDIO_SLC0_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_RAW_M (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S) +#define SDIO_SLC0_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of slc0 finishing sending data + */ +#define SDIO_SLC0_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_RAW_M (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_RAW_M (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S) +#define SDIO_SLC0_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_RAW_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of slc0 tx link descriptor error + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of slc0 rx link descriptor error + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S 24 +/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_RAW (BIT(25)) +#define SDIO_CMD_DTC_INT_RAW_M (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S) +#define SDIO_CMD_DTC_INT_RAW_V 0x00000001U +#define SDIO_CMD_DTC_INT_RAW_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27 +/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_RAW (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_RAW_M (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S) +#define SDIO_HDA_RECV_DONE_INT_RAW_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_RAW_S 28 + +/** SDIO_SLC0INT_ST_REG register + * ******* Description *********** + */ +#define SDIO_SLC0INT_ST_REG (DR_REG_SDIO_BASE + 0x8) +/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_M (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_M (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_M (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_M (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_M (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_M (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_M (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_M (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST_S 7 +/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST_M (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S) +#define SDIO_SLC0_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST_S 8 +/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST_M (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S) +#define SDIO_SLC0_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST_M (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S) +#define SDIO_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST_M (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S) +#define SDIO_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST_M (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S) +#define SDIO_SLC0_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST_M (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S) +#define SDIO_SLC0_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST_M (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S) +#define SDIO_SLC0_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST_S 17 +/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST_M (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S) +#define SDIO_SLC0_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S 24 +/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_ST (BIT(25)) +#define SDIO_CMD_DTC_INT_ST_M (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S) +#define SDIO_CMD_DTC_INT_ST_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_ST (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST_M (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S) +#define SDIO_HDA_RECV_DONE_INT_ST_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST_S 28 + +/** SDIO_SLC0INT_ENA_REG register + * ******* Description *********** + */ +#define SDIO_SLC0INT_ENA_REG (DR_REG_SDIO_BASE + 0xc) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA_M (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S) +#define SDIO_SLC0_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA_S 8 +/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA_M (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S) +#define SDIO_SLC0_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA_M (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S) +#define SDIO_SLC0_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA_M (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S) +#define SDIO_SLC0_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA_M (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA_M (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S) +#define SDIO_SLC0_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S 24 +/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_ENA (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA_M (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S) +#define SDIO_CMD_DTC_INT_ENA_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_ENA (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA_M (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S) +#define SDIO_HDA_RECV_DONE_INT_ENA_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA_S 28 + +/** SDIO_SLC0INT_CLR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0INT_CLR_REG (DR_REG_SDIO_BASE + 0x10) +/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC0_RX_START_INT_CLR_M (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S) +#define SDIO_SLC0_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_CLR_S 8 +/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC0_TX_START_INT_CLR_M (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S) +#define SDIO_SLC0_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_CLR_S 9 +/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_CLR_M (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S) +#define SDIO_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_CLR_M (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S) +#define SDIO_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_CLR_M (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S) +#define SDIO_SLC0_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_CLR_M (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S) +#define SDIO_SLC0_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_CLR_M (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_CLR_M (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S) +#define SDIO_SLC0_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_CLR_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S 24 +/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_CLR (BIT(25)) +#define SDIO_CMD_DTC_INT_CLR_M (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S) +#define SDIO_CMD_DTC_INT_CLR_V 0x00000001U +#define SDIO_CMD_DTC_INT_CLR_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27 +/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_CLR (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_CLR_M (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S) +#define SDIO_HDA_RECV_DONE_INT_CLR_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_CLR_S 28 + +/** SDIO_SLC1INT_RAW_REG register + * reserved + */ +#define SDIO_SLC1INT_RAW_REG (DR_REG_SDIO_BASE + 0x14) +/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S 7 +/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC1_RX_START_INT_RAW_M (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S) +#define SDIO_SLC1_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_RAW_S 8 +/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC1_TX_START_INT_RAW_M (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S) +#define SDIO_SLC1_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_RAW_S 9 +/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_RAW_M (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S) +#define SDIO_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_RAW_M (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S) +#define SDIO_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_RAW_M (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S) +#define SDIO_SLC1_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_RAW_M (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S) +#define SDIO_SLC1_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_RAW_M (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S) +#define SDIO_SLC1_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_RAW_M (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S) +#define SDIO_SLC1_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_RAW_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S 24 + +/** SDIO_SLC1INT_ST_REG register + * reserved + */ +#define SDIO_SLC1INT_ST_REG (DR_REG_SDIO_BASE + 0x18) +/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_M (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_M (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_M (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_M (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_M (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_M (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_M (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_M (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST_S 7 +/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST_M (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S) +#define SDIO_SLC1_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST_S 8 +/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST_M (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S) +#define SDIO_SLC1_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST_M (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S) +#define SDIO_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST_M (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S) +#define SDIO_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST_M (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S) +#define SDIO_SLC1_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST_M (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S) +#define SDIO_SLC1_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST_M (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S) +#define SDIO_SLC1_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST_S 17 +/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST_M (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S) +#define SDIO_SLC1_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S 24 + +/** SDIO_SLC1INT_ENA_REG register + * reserved + */ +#define SDIO_SLC1INT_ENA_REG (DR_REG_SDIO_BASE + 0x1c) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S 7 +/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA_M (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S) +#define SDIO_SLC1_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA_S 8 +/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA_M (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S) +#define SDIO_SLC1_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA_M (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S) +#define SDIO_SLC1_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA_M (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S) +#define SDIO_SLC1_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA_M (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S) +#define SDIO_SLC1_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA_M (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S) +#define SDIO_SLC1_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S 24 + +/** SDIO_SLC1INT_CLR_REG register + * reserved + */ +#define SDIO_SLC1INT_CLR_REG (DR_REG_SDIO_BASE + 0x20) +/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S 7 +/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC1_RX_START_INT_CLR_M (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S) +#define SDIO_SLC1_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_CLR_S 8 +/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC1_TX_START_INT_CLR_M (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S) +#define SDIO_SLC1_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_CLR_S 9 +/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_CLR_M (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S) +#define SDIO_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_CLR_M (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S) +#define SDIO_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_CLR_M (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S) +#define SDIO_SLC1_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_CLR_M (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S) +#define SDIO_SLC1_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_CLR_M (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S) +#define SDIO_SLC1_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_CLR_M (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S) +#define SDIO_SLC1_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_CLR_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S 24 + +/** SDIO_SLCRX_STATUS_REG register + * ******* Description *********** + */ +#define SDIO_SLCRX_STATUS_REG (DR_REG_SDIO_BASE + 0x24) +/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_FULL (BIT(0)) +#define SDIO_SLC0_RX_FULL_M (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S) +#define SDIO_SLC0_RX_FULL_V 0x00000001U +#define SDIO_SLC0_RX_FULL_S 0 +/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_EMPTY (BIT(1)) +#define SDIO_SLC0_RX_EMPTY_M (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S) +#define SDIO_SLC0_RX_EMPTY_V 0x00000001U +#define SDIO_SLC0_RX_EMPTY_S 1 +/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0; + * the current buffer length when slc0 reads data from rx link + */ +#define SDIO_SLC0_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_M (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S) +#define SDIO_SLC0_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_S 2 +/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_FULL (BIT(16)) +#define SDIO_SLC1_RX_FULL_M (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S) +#define SDIO_SLC1_RX_FULL_V 0x00000001U +#define SDIO_SLC1_RX_FULL_S 16 +/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_EMPTY (BIT(17)) +#define SDIO_SLC1_RX_EMPTY_M (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S) +#define SDIO_SLC1_RX_EMPTY_V 0x00000001U +#define SDIO_SLC1_RX_EMPTY_S 17 +/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0; + * the current buffer length when slc1 reads data from rx link + */ +#define SDIO_SLC1_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_M (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S) +#define SDIO_SLC1_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_S 18 + +/** SDIO_SLC0RXFIFO_PUSH_REG register + * ******* Description *********** + */ +#define SDIO_SLC0RXFIFO_PUSH_REG (DR_REG_SDIO_BASE + 0x28) +/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_M (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S) +#define SDIO_SLC0_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_S 0 +/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC0_RXFIFO_PUSH_M (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S) +#define SDIO_SLC0_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC0_RXFIFO_PUSH_S 16 + +/** SDIO_SLC1RXFIFO_PUSH_REG register + * reserved + */ +#define SDIO_SLC1RXFIFO_PUSH_REG (DR_REG_SDIO_BASE + 0x2c) +/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_M (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S) +#define SDIO_SLC1_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_S 0 +/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC1_RXFIFO_PUSH_M (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S) +#define SDIO_SLC1_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC1_RXFIFO_PUSH_S 16 + +/** SDIO_SLCTX_STATUS_REG register + * ******* Description *********** + */ +#define SDIO_SLCTX_STATUS_REG (DR_REG_SDIO_BASE + 0x30) +/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_FULL (BIT(0)) +#define SDIO_SLC0_TX_FULL_M (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S) +#define SDIO_SLC0_TX_FULL_V 0x00000001U +#define SDIO_SLC0_TX_FULL_S 0 +/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_TX_EMPTY (BIT(1)) +#define SDIO_SLC0_TX_EMPTY_M (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S) +#define SDIO_SLC0_TX_EMPTY_V 0x00000001U +#define SDIO_SLC0_TX_EMPTY_S 1 +/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_FULL (BIT(16)) +#define SDIO_SLC1_TX_FULL_M (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S) +#define SDIO_SLC1_TX_FULL_V 0x00000001U +#define SDIO_SLC1_TX_FULL_S 16 +/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_TX_EMPTY (BIT(17)) +#define SDIO_SLC1_TX_EMPTY_M (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S) +#define SDIO_SLC1_TX_EMPTY_V 0x00000001U +#define SDIO_SLC1_TX_EMPTY_S 17 + +/** SDIO_SLC0TXFIFO_POP_REG register + * reserved + */ +#define SDIO_SLC0TXFIFO_POP_REG (DR_REG_SDIO_BASE + 0x34) +/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * reserved + */ +#define SDIO_SLC0_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_M (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S) +#define SDIO_SLC0_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_S 0 +/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXFIFO_POP (BIT(16)) +#define SDIO_SLC0_TXFIFO_POP_M (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S) +#define SDIO_SLC0_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC0_TXFIFO_POP_S 16 + +/** SDIO_SLC1TXFIFO_POP_REG register + * reserved + */ +#define SDIO_SLC1TXFIFO_POP_REG (DR_REG_SDIO_BASE + 0x38) +/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * reserved + */ +#define SDIO_SLC1_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_M (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S) +#define SDIO_SLC1_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_S 0 +/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXFIFO_POP (BIT(16)) +#define SDIO_SLC1_TXFIFO_POP_M (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S) +#define SDIO_SLC1_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC1_TXFIFO_POP_S 16 + +/** SDIO_SLC0RX_LINK_REG register + * reserved + */ +#define SDIO_SLC0RX_LINK_REG (DR_REG_SDIO_BASE + 0x3c) +/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_STOP (BIT(28)) +#define SDIO_SLC0_RXLINK_STOP_M (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S) +#define SDIO_SLC0_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_RXLINK_STOP_S 28 +/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_START (BIT(29)) +#define SDIO_SLC0_RXLINK_START_M (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S) +#define SDIO_SLC0_RXLINK_START_V 0x00000001U +#define SDIO_SLC0_RXLINK_START_S 29 +/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_RXLINK_RESTART_M (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S) +#define SDIO_SLC0_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_RXLINK_RESTART_S 30 +/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC0_RXLINK_PARK (BIT(31)) +#define SDIO_SLC0_RXLINK_PARK_M (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S) +#define SDIO_SLC0_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_RXLINK_PARK_S 31 + +/** SDIO_SLC0RX_LINK_ADDR_REG register + * reserved + */ +#define SDIO_SLC0RX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x40) +/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_M (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S) +#define SDIO_SLC0_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_S 0 + +/** SDIO_SLC0TX_LINK_REG register + * reserved + */ +#define SDIO_SLC0TX_LINK_REG (DR_REG_SDIO_BASE + 0x44) +/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_STOP (BIT(28)) +#define SDIO_SLC0_TXLINK_STOP_M (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S) +#define SDIO_SLC0_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_TXLINK_STOP_S 28 +/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_START (BIT(29)) +#define SDIO_SLC0_TXLINK_START_M (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S) +#define SDIO_SLC0_TXLINK_START_V 0x00000001U +#define SDIO_SLC0_TXLINK_START_S 29 +/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_TXLINK_RESTART_M (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S) +#define SDIO_SLC0_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_TXLINK_RESTART_S 30 +/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC0_TXLINK_PARK (BIT(31)) +#define SDIO_SLC0_TXLINK_PARK_M (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S) +#define SDIO_SLC0_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_TXLINK_PARK_S 31 + +/** SDIO_SLC0TX_LINK_ADDR_REG register + * reserved + */ +#define SDIO_SLC0TX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x48) +/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_M (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S) +#define SDIO_SLC0_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_S 0 + +/** SDIO_SLC1RX_LINK_REG register + * reserved + */ +#define SDIO_SLC1RX_LINK_REG (DR_REG_SDIO_BASE + 0x4c) +/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_BT_PACKET (BIT(20)) +#define SDIO_SLC1_BT_PACKET_M (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S) +#define SDIO_SLC1_BT_PACKET_V 0x00000001U +#define SDIO_SLC1_BT_PACKET_S 20 +/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_STOP (BIT(28)) +#define SDIO_SLC1_RXLINK_STOP_M (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S) +#define SDIO_SLC1_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_RXLINK_STOP_S 28 +/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_START (BIT(29)) +#define SDIO_SLC1_RXLINK_START_M (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S) +#define SDIO_SLC1_RXLINK_START_V 0x00000001U +#define SDIO_SLC1_RXLINK_START_S 29 +/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_RXLINK_RESTART_M (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S) +#define SDIO_SLC1_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_RXLINK_RESTART_S 30 +/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC1_RXLINK_PARK (BIT(31)) +#define SDIO_SLC1_RXLINK_PARK_M (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S) +#define SDIO_SLC1_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_RXLINK_PARK_S 31 + +/** SDIO_SLC1RX_LINK_ADDR_REG register + * reserved + */ +#define SDIO_SLC1RX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x50) +/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_M (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S) +#define SDIO_SLC1_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_S 0 + +/** SDIO_SLC1TX_LINK_REG register + * reserved + */ +#define SDIO_SLC1TX_LINK_REG (DR_REG_SDIO_BASE + 0x54) +/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_STOP (BIT(28)) +#define SDIO_SLC1_TXLINK_STOP_M (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S) +#define SDIO_SLC1_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_TXLINK_STOP_S 28 +/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_START (BIT(29)) +#define SDIO_SLC1_TXLINK_START_M (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S) +#define SDIO_SLC1_TXLINK_START_V 0x00000001U +#define SDIO_SLC1_TXLINK_START_S 29 +/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_TXLINK_RESTART_M (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S) +#define SDIO_SLC1_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_TXLINK_RESTART_S 30 +/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC1_TXLINK_PARK (BIT(31)) +#define SDIO_SLC1_TXLINK_PARK_M (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S) +#define SDIO_SLC1_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_TXLINK_PARK_S 31 + +/** SDIO_SLC1TX_LINK_ADDR_REG register + * reserved + */ +#define SDIO_SLC1TX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x58) +/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_M (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S) +#define SDIO_SLC1_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_S 0 + +/** SDIO_SLCINTVEC_TOHOST_REG register + * reserved + */ +#define SDIO_SLCINTVEC_TOHOST_REG (DR_REG_SDIO_BASE + 0x5c) +/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_M (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S) +#define SDIO_SLC0_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_S 0 +/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_M (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S) +#define SDIO_SLC1_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_S 16 + +/** SDIO_SLC0TOKEN0_REG register + * reserved + */ +#define SDIO_SLC0TOKEN0_REG (DR_REG_SDIO_BASE + 0x60) +/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_M (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S) +#define SDIO_SLC0_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_S 0 +/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_WR (BIT(12)) +#define SDIO_SLC0_TOKEN0_WR_M (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S) +#define SDIO_SLC0_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_WR_S 12 +/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_INC (BIT(13)) +#define SDIO_SLC0_TOKEN0_INC_M (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S) +#define SDIO_SLC0_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_S 13 +/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN0_INC_MORE_M (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S) +#define SDIO_SLC0_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0 0x00000FFFU +#define SDIO_SLC0_TOKEN0_M (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S) +#define SDIO_SLC0_TOKEN0_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_S 16 + +/** SDIO_SLC0TOKEN1_REG register + * reserved + */ +#define SDIO_SLC0TOKEN1_REG (DR_REG_SDIO_BASE + 0x64) +/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * slc0 token1 wdata + */ +#define SDIO_SLC0_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_M (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S) +#define SDIO_SLC0_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_S 0 +/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ +#define SDIO_SLC0_TOKEN1_WR (BIT(12)) +#define SDIO_SLC0_TOKEN1_WR_M (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S) +#define SDIO_SLC0_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_WR_S 12 +/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ +#define SDIO_SLC0_TOKEN1_INC (BIT(13)) +#define SDIO_SLC0_TOKEN1_INC_M (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S) +#define SDIO_SLC0_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_S 13 +/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add + * slc0_token1_wdata to slc0_token1 + */ +#define SDIO_SLC0_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN1_INC_MORE_M (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S) +#define SDIO_SLC0_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1 0x00000FFFU +#define SDIO_SLC0_TOKEN1_M (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S) +#define SDIO_SLC0_TOKEN1_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_S 16 + +/** SDIO_SLC1TOKEN0_REG register + * ******* Description *********** + */ +#define SDIO_SLC1TOKEN0_REG (DR_REG_SDIO_BASE + 0x68) +/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_M (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S) +#define SDIO_SLC1_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_S 0 +/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_WR (BIT(12)) +#define SDIO_SLC1_TOKEN0_WR_M (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S) +#define SDIO_SLC1_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_WR_S 12 +/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * Add 1 to slc1_token0 + */ +#define SDIO_SLC1_TOKEN0_INC (BIT(13)) +#define SDIO_SLC1_TOKEN0_INC_M (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S) +#define SDIO_SLC1_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_S 13 +/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * Add slc1_token0_wdata to slc1_token0 + */ +#define SDIO_SLC1_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN0_INC_MORE_M (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S) +#define SDIO_SLC1_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0 0x00000FFFU +#define SDIO_SLC1_TOKEN0_M (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S) +#define SDIO_SLC1_TOKEN0_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_S 16 + +/** SDIO_SLC1TOKEN1_REG register + * reserved + */ +#define SDIO_SLC1TOKEN1_REG (DR_REG_SDIO_BASE + 0x6c) +/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_M (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S) +#define SDIO_SLC1_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_S 0 +/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update slc1_token1_wdata into slc1 token1 + */ +#define SDIO_SLC1_TOKEN1_WR (BIT(12)) +#define SDIO_SLC1_TOKEN1_WR_M (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S) +#define SDIO_SLC1_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_WR_S 12 +/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_INC (BIT(13)) +#define SDIO_SLC1_TOKEN1_INC_M (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S) +#define SDIO_SLC1_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_S 13 +/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN1_INC_MORE_M (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S) +#define SDIO_SLC1_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1 0x00000FFFU +#define SDIO_SLC1_TOKEN1_M (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S) +#define SDIO_SLC1_TOKEN1_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_S 16 + +/** SDIO_SLCCONF1_REG register + * reserved + */ +#define SDIO_SLCCONF1_REG (DR_REG_SDIO_BASE + 0x70) +/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_CHECK_OWNER (BIT(0)) +#define SDIO_SLC0_CHECK_OWNER_M (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S) +#define SDIO_SLC0_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC0_CHECK_OWNER_S 0 +/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_CHECK_SUM_EN (BIT(1)) +#define SDIO_SLC0_TX_CHECK_SUM_EN_M (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S) +#define SDIO_SLC0_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_TX_CHECK_SUM_EN_S 1 +/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_CHECK_SUM_EN (BIT(2)) +#define SDIO_SLC0_RX_CHECK_SUM_EN_M (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S) +#define SDIO_SLC0_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_RX_CHECK_SUM_EN_S 2 +/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1; + * reserved + */ +#define SDIO_SDIO_CMD_HOLD_EN (BIT(3)) +#define SDIO_SDIO_CMD_HOLD_EN_M (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S) +#define SDIO_SDIO_CMD_HOLD_EN_V 0x00000001U +#define SDIO_SDIO_CMD_HOLD_EN_S 3 +/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1; + * reserved + */ +#define SDIO_SLC0_LEN_AUTO_CLR (BIT(4)) +#define SDIO_SLC0_LEN_AUTO_CLR_M (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S) +#define SDIO_SLC0_LEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_LEN_AUTO_CLR_S 4 +/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1; + * reserved + */ +#define SDIO_SLC0_TX_STITCH_EN (BIT(5)) +#define SDIO_SLC0_TX_STITCH_EN_M (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S) +#define SDIO_SLC0_TX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_TX_STITCH_EN_S 5 +/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_STITCH_EN (BIT(6)) +#define SDIO_SLC0_RX_STITCH_EN_M (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S) +#define SDIO_SLC0_RX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_RX_STITCH_EN_S 6 +/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_CHECK_OWNER (BIT(16)) +#define SDIO_SLC1_CHECK_OWNER_M (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S) +#define SDIO_SLC1_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC1_CHECK_OWNER_S 16 +/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_CHECK_SUM_EN (BIT(17)) +#define SDIO_SLC1_TX_CHECK_SUM_EN_M (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S) +#define SDIO_SLC1_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_TX_CHECK_SUM_EN_S 17 +/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_CHECK_SUM_EN (BIT(18)) +#define SDIO_SLC1_RX_CHECK_SUM_EN_M (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S) +#define SDIO_SLC1_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_RX_CHECK_SUM_EN_S 18 +/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_HOST_INT_LEVEL_SEL (BIT(19)) +#define SDIO_HOST_INT_LEVEL_SEL_M (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S) +#define SDIO_HOST_INT_LEVEL_SEL_V 0x00000001U +#define SDIO_HOST_INT_LEVEL_SEL_S 19 +/** SDIO_SLC1_TX_STITCH_EN : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_TX_STITCH_EN (BIT(20)) +#define SDIO_SLC1_TX_STITCH_EN_M (SDIO_SLC1_TX_STITCH_EN_V << SDIO_SLC1_TX_STITCH_EN_S) +#define SDIO_SLC1_TX_STITCH_EN_V 0x00000001U +#define SDIO_SLC1_TX_STITCH_EN_S 20 +/** SDIO_SLC1_RX_STITCH_EN : R/W; bitpos: [21]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_STITCH_EN (BIT(21)) +#define SDIO_SLC1_RX_STITCH_EN_M (SDIO_SLC1_RX_STITCH_EN_V << SDIO_SLC1_RX_STITCH_EN_S) +#define SDIO_SLC1_RX_STITCH_EN_V 0x00000001U +#define SDIO_SLC1_RX_STITCH_EN_S 21 +/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SDIO_CLK_EN (BIT(22)) +#define SDIO_SDIO_CLK_EN_M (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S) +#define SDIO_SDIO_CLK_EN_V 0x00000001U +#define SDIO_SDIO_CLK_EN_S 22 + +/** SDIO_SLC0_STATE0_REG register + * reserved + */ +#define SDIO_SLC0_STATE0_REG (DR_REG_SDIO_BASE + 0x74) +/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_STATE0 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_M (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S) +#define SDIO_SLC0_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_S 0 + +/** SDIO_SLC0_STATE1_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_STATE1_REG (DR_REG_SDIO_BASE + 0x78) +/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] + * rx_link fsm state, [30:24] rx_fifo_cnt + */ +#define SDIO_SLC0_STATE1 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_M (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S) +#define SDIO_SLC0_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_S 0 + +/** SDIO_SLC1_STATE0_REG register + * ******* Description *********** + */ +#define SDIO_SLC1_STATE0_REG (DR_REG_SDIO_BASE + 0x7c) +/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_STATE0 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_M (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S) +#define SDIO_SLC1_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_S 0 + +/** SDIO_SLC1_STATE1_REG register + * ******* Description *********** + */ +#define SDIO_SLC1_STATE1_REG (DR_REG_SDIO_BASE + 0x80) +/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] + * rx_link fsm state, [30:24] rx_fifo_cnt + */ +#define SDIO_SLC1_STATE1 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_M (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S) +#define SDIO_SLC1_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_S 0 + +/** SDIO_SLCBRIDGE_CONF_REG register + * ******* Description *********** + */ +#define SDIO_SLCBRIDGE_CONF_REG (DR_REG_SDIO_BASE + 0x84) +/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32; + * reserved + */ +#define SDIO_SLC_TXEOF_ENA 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_M (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S) +#define SDIO_SLC_TXEOF_ENA_V 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_S 0 +/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7; + * reserved + */ +#define SDIO_SLC_FIFO_MAP_ENA 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_M (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S) +#define SDIO_SLC_FIFO_MAP_ENA_V 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_S 8 +/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1; + * reserved + */ +#define SDIO_SLC0_TX_DUMMY_MODE (BIT(12)) +#define SDIO_SLC0_TX_DUMMY_MODE_M (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S) +#define SDIO_SLC0_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC0_TX_DUMMY_MODE_S 12 +/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1; + * reserved + */ +#define SDIO_SLC_HDA_MAP_128K (BIT(13)) +#define SDIO_SLC_HDA_MAP_128K_M (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S) +#define SDIO_SLC_HDA_MAP_128K_V 0x00000001U +#define SDIO_SLC_HDA_MAP_128K_S 13 +/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1; + * reserved + */ +#define SDIO_SLC1_TX_DUMMY_MODE (BIT(14)) +#define SDIO_SLC1_TX_DUMMY_MODE_M (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S) +#define SDIO_SLC1_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC1_TX_DUMMY_MODE_S 14 +/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10; + * reserved + */ +#define SDIO_SLC_TX_PUSH_IDLE_NUM 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_M (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S) +#define SDIO_SLC_TX_PUSH_IDLE_NUM_V 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_S 16 + +/** SDIO_SLC0_TO_EOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x88) +/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_M (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC0_TX_EOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x8c) +/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x90) +/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC1_TO_EOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x94) +/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_M (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC1_TX_EOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x98) +/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x9c) +/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC_AHB_TEST_REG register + * reserved + */ +#define SDIO_SLC_AHB_TEST_REG (DR_REG_SDIO_BASE + 0xa0) +/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define SDIO_SLC_AHB_TESTMODE 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_M (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S) +#define SDIO_SLC_AHB_TESTMODE_V 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_S 0 +/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define SDIO_SLC_AHB_TESTADDR 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_M (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S) +#define SDIO_SLC_AHB_TESTADDR_V 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_S 4 + +/** SDIO_SLC_SDIO_ST_REG register + * reserved + */ +#define SDIO_SLC_SDIO_ST_REG (DR_REG_SDIO_BASE + 0xa4) +/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0; + * reserved + */ +#define SDIO_CMD_ST 0x00000007U +#define SDIO_CMD_ST_M (SDIO_CMD_ST_V << SDIO_CMD_ST_S) +#define SDIO_CMD_ST_V 0x00000007U +#define SDIO_CMD_ST_S 0 +/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0; + * reserved + */ +#define SDIO_FUNC_ST 0x0000000FU +#define SDIO_FUNC_ST_M (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S) +#define SDIO_FUNC_ST_V 0x0000000FU +#define SDIO_FUNC_ST_S 4 +/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SDIO_WAKEUP (BIT(8)) +#define SDIO_SDIO_WAKEUP_M (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S) +#define SDIO_SDIO_WAKEUP_V 0x00000001U +#define SDIO_SDIO_WAKEUP_S 8 +/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0; + * reserved + */ +#define SDIO_BUS_ST 0x00000007U +#define SDIO_BUS_ST_M (SDIO_BUS_ST_V << SDIO_BUS_ST_S) +#define SDIO_BUS_ST_V 0x00000007U +#define SDIO_BUS_ST_S 12 +/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0; + * reserved + */ +#define SDIO_FUNC1_ACC_STATE 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_M (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S) +#define SDIO_FUNC1_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_S 16 +/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0; + * reserved + */ +#define SDIO_FUNC2_ACC_STATE 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_M (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S) +#define SDIO_FUNC2_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_S 24 + +/** SDIO_SLC_RX_DSCR_CONF_REG register + * reserved + */ +#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SDIO_BASE + 0xa8) +/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN_NO_REPLACE (BIT(0)) +#define SDIO_SLC0_TOKEN_NO_REPLACE_M (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S) +#define SDIO_SLC0_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_TOKEN_NO_REPLACE_S 0 +/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_INFOR_NO_REPLACE (BIT(1)) +#define SDIO_SLC0_INFOR_NO_REPLACE_M (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S) +#define SDIO_SLC0_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_INFOR_NO_REPLACE_S 1 +/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC0_RX_FILL_MODE (BIT(2)) +#define SDIO_SLC0_RX_FILL_MODE_M (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S) +#define SDIO_SLC0_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC0_RX_FILL_MODE_S 2 +/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ +#define SDIO_SLC0_RX_EOF_MODE (BIT(3)) +#define SDIO_SLC0_RX_EOF_MODE_M (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S) +#define SDIO_SLC0_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC0_RX_EOF_MODE_S 3 +/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_FILL_EN (BIT(4)) +#define SDIO_SLC0_RX_FILL_EN_M (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S) +#define SDIO_SLC0_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC0_RX_FILL_EN_S 4 +/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128; + * reserved + */ +#define SDIO_SLC0_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_M (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC0_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_S 5 +/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_NO_REPLACE (BIT(16)) +#define SDIO_SLC1_TOKEN_NO_REPLACE_M (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S) +#define SDIO_SLC1_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_TOKEN_NO_REPLACE_S 16 +/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_INFOR_NO_REPLACE (BIT(17)) +#define SDIO_SLC1_INFOR_NO_REPLACE_M (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S) +#define SDIO_SLC1_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_INFOR_NO_REPLACE_S 17 +/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC1_RX_FILL_MODE (BIT(18)) +#define SDIO_SLC1_RX_FILL_MODE_M (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S) +#define SDIO_SLC1_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC1_RX_FILL_MODE_S 18 +/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ +#define SDIO_SLC1_RX_EOF_MODE (BIT(19)) +#define SDIO_SLC1_RX_EOF_MODE_M (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S) +#define SDIO_SLC1_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC1_RX_EOF_MODE_S 19 +/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_FILL_EN (BIT(20)) +#define SDIO_SLC1_RX_FILL_EN_M (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S) +#define SDIO_SLC1_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC1_RX_FILL_EN_S 20 +/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128; + * reserved + */ +#define SDIO_SLC1_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_M (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC1_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_S 21 + +/** SDIO_SLC0_TXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_TXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xac) +/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_M (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S) +#define SDIO_SLC0_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_S 0 + +/** SDIO_SLC0_TXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xb0) +/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_M (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S) +#define SDIO_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC0_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xb4) +/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_M (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S) +#define SDIO_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC0_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_RXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xb8) +/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC0_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_M (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S) +#define SDIO_SLC0_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_S 0 + +/** SDIO_SLC0_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xbc) +/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_M (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S) +#define SDIO_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC0_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xc0) +/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_M (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S) +#define SDIO_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC1_TXLINK_DSCR_REG register + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xc4) +/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_M (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S) +#define SDIO_SLC1_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_S 0 + +/** SDIO_SLC1_TXLINK_DSCR_BF0_REG register + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xc8) +/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_M (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S) +#define SDIO_SLC1_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC1_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xcc) +/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_M (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S) +#define SDIO_SLC1_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC1_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC1_RXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xd0) +/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC1_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_M (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S) +#define SDIO_SLC1_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_S 0 + +/** SDIO_SLC1_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xd4) +/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_M (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S) +#define SDIO_SLC1_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC1_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xd8) +/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_M (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S) +#define SDIO_SLC1_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC0_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0xdc) +/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC1_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0xe0) +/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_TOKEN_LAT_REG register + * reserved + */ +#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SDIO_BASE + 0xe4) +/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN 0x00000FFFU +#define SDIO_SLC0_TOKEN_M (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S) +#define SDIO_SLC0_TOKEN_V 0x00000FFFU +#define SDIO_SLC0_TOKEN_S 0 +/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN 0x00000FFFU +#define SDIO_SLC1_TOKEN_M (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S) +#define SDIO_SLC1_TOKEN_V 0x00000FFFU +#define SDIO_SLC1_TOKEN_S 16 + +/** SDIO_SLC_TX_DSCR_CONF_REG register + * reserved + */ +#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SDIO_BASE + 0xe8) +/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128; + * reserved + */ +#define SDIO_SLC_WR_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_M (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S) +#define SDIO_SLC_WR_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_S 0 + +/** SDIO_SLC_CMD_INFOR0_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SDIO_BASE + 0xec) +/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT0 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_M (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S) +#define SDIO_CMD_CONTENT0_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_S 0 + +/** SDIO_SLC_CMD_INFOR1_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SDIO_BASE + 0xf0) +/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT1 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_M (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S) +#define SDIO_CMD_CONTENT1_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_S 0 + +/** SDIO_SLC0_LEN_CONF_REG register + * reserved + */ +#define SDIO_SLC0_LEN_CONF_REG (DR_REG_SDIO_BASE + 0xf4) +/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN_WDATA 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_M (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S) +#define SDIO_SLC0_LEN_WDATA_V 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_S 0 +/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN_WR (BIT(20)) +#define SDIO_SLC0_LEN_WR_M (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S) +#define SDIO_SLC0_LEN_WR_V 0x00000001U +#define SDIO_SLC0_LEN_WR_S 20 +/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN_INC (BIT(21)) +#define SDIO_SLC0_LEN_INC_M (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S) +#define SDIO_SLC0_LEN_INC_V 0x00000001U +#define SDIO_SLC0_LEN_INC_S 21 +/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN_INC_MORE (BIT(22)) +#define SDIO_SLC0_LEN_INC_MORE_M (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S) +#define SDIO_SLC0_LEN_INC_MORE_V 0x00000001U +#define SDIO_SLC0_LEN_INC_MORE_S 22 +/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN (BIT(23)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_M (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_S 23 +/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN (BIT(24)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_M (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_S 24 +/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_GET_USED_DSCR (BIT(25)) +#define SDIO_SLC0_RX_GET_USED_DSCR_M (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S) +#define SDIO_SLC0_RX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_RX_GET_USED_DSCR_S 25 +/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_GET_USED_DSCR (BIT(26)) +#define SDIO_SLC0_TX_GET_USED_DSCR_M (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S) +#define SDIO_SLC0_TX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_TX_GET_USED_DSCR_S 26 +/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_NEW_PKT_IND (BIT(27)) +#define SDIO_SLC0_RX_NEW_PKT_IND_M (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S) +#define SDIO_SLC0_RX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_RX_NEW_PKT_IND_S 27 +/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1; + * reserved + */ +#define SDIO_SLC0_TX_NEW_PKT_IND (BIT(28)) +#define SDIO_SLC0_TX_NEW_PKT_IND_M (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S) +#define SDIO_SLC0_TX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_TX_NEW_PKT_IND_S 28 +/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST (BIT(29)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S 29 +/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST (BIT(30)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S 30 + +/** SDIO_SLC0_LENGTH_REG register + * reserved + */ +#define SDIO_SLC0_LENGTH_REG (DR_REG_SDIO_BASE + 0xf8) +/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_LEN 0x000FFFFFU +#define SDIO_SLC0_LEN_M (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S) +#define SDIO_SLC0_LEN_V 0x000FFFFFU +#define SDIO_SLC0_LEN_S 0 + +/** SDIO_SLC0_TXPKT_H_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_TXPKT_H_DSCR_REG (DR_REG_SDIO_BASE + 0xfc) +/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC0_TXPKT_E_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_TXPKT_E_DSCR_REG (DR_REG_SDIO_BASE + 0x100) +/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC0_RXPKT_H_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_RXPKT_H_DSCR_REG (DR_REG_SDIO_BASE + 0x104) +/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC0_RXPKT_E_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_RXPKT_E_DSCR_REG (DR_REG_SDIO_BASE + 0x108) +/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC0_TXPKTU_H_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SDIO_BASE + 0x10c) +/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC0_TXPKTU_E_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SDIO_BASE + 0x110) +/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC0_RXPKTU_H_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SDIO_BASE + 0x114) +/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC0_RXPKTU_E_DSCR_REG register + * reserved + */ +#define SDIO_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SDIO_BASE + 0x118) +/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC_SEQ_POSITION_REG register + * reserved + */ +#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SDIO_BASE + 0x11c) +/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9; + * reserved + */ +#define SDIO_SLC0_SEQ_POSITION 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_M (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S) +#define SDIO_SLC0_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_S 0 +/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5; + * reserved + */ +#define SDIO_SLC1_SEQ_POSITION 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_M (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S) +#define SDIO_SLC1_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_S 8 + +/** SDIO_SLC0_DSCR_REC_CONF_REG register + * reserved + */ +#define SDIO_SLC0_DSCR_REC_CONF_REG (DR_REG_SDIO_BASE + 0x120) +/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_REC_LIM 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_M (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S) +#define SDIO_SLC0_RX_DSCR_REC_LIM_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_S 0 + +/** SDIO_SLC_SDIO_CRC_ST0_REG register + * reserved + */ +#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SDIO_BASE + 0x124) +/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * reserved + */ +#define SDIO_DAT0_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_M (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S) +#define SDIO_DAT0_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_S 0 +/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0; + * reserved + */ +#define SDIO_DAT1_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_M (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S) +#define SDIO_DAT1_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_S 8 +/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0; + * reserved + */ +#define SDIO_DAT2_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_M (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S) +#define SDIO_DAT2_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_S 16 +/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0; + * reserved + */ +#define SDIO_DAT3_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_M (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S) +#define SDIO_DAT3_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_S 24 + +/** SDIO_SLC_SDIO_CRC_ST1_REG register + * reserved + */ +#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SDIO_BASE + 0x128) +/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CRC_ERR_CNT 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_M (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S) +#define SDIO_CMD_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_S 0 +/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define SDIO_ERR_CNT_CLR (BIT(31)) +#define SDIO_ERR_CNT_CLR_M (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S) +#define SDIO_ERR_CNT_CLR_V 0x00000001U +#define SDIO_ERR_CNT_CLR_S 31 + +/** SDIO_SLC0_EOF_START_DES_REG register + * reserved + */ +#define SDIO_SLC0_EOF_START_DES_REG (DR_REG_SDIO_BASE + 0x12c) +/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_EOF_START_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_M (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S) +#define SDIO_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_S 0 + +/** SDIO_SLC0_PUSH_DSCR_ADDR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SDIO_BASE + 0x130) +/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S 0 + +/** SDIO_SLC0_DONE_DSCR_ADDR_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SDIO_BASE + 0x134) +/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ +#define SDIO_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S) +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S 0 + +/** SDIO_SLC0_SUB_START_DES_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_SUB_START_DES_REG (DR_REG_SDIO_BASE + 0x138) +/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S) +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 + +/** SDIO_SLC0_DSCR_CNT_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_DSCR_CNT_REG (DR_REG_SDIO_BASE + 0x13c) +/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0; + * the number of descriptors got by slc0 when it tries to read data from memory + */ +#define SDIO_SLC0_RX_DSCR_CNT_LAT 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_M (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S) +#define SDIO_SLC0_RX_DSCR_CNT_LAT_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_S 0 +/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_GET_EOF_OCC (BIT(16)) +#define SDIO_SLC0_RX_GET_EOF_OCC_M (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S) +#define SDIO_SLC0_RX_GET_EOF_OCC_V 0x00000001U +#define SDIO_SLC0_RX_GET_EOF_OCC_S 16 + +/** SDIO_SLC0_LEN_LIM_CONF_REG register + * ******* Description *********** + */ +#define SDIO_SLC0_LEN_LIM_CONF_REG (DR_REG_SDIO_BASE + 0x140) +/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504; + * reserved + */ +#define SDIO_SLC0_LEN_LIM 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_M (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S) +#define SDIO_SLC0_LEN_LIM_V 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_S 0 + +/** SDIO_SLC0INT_ST1_REG register + * reserved + */ +#define SDIO_SLC0INT_ST1_REG (DR_REG_SDIO_BASE + 0x144) +/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S 7 +/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST1_M (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S) +#define SDIO_SLC0_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST1_S 8 +/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST1_M (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S) +#define SDIO_SLC0_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST1_M (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S) +#define SDIO_SLC0_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST1_M (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S) +#define SDIO_SLC0_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST1_M (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S) +#define SDIO_SLC0_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST1_M (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S) +#define SDIO_SLC0_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST1_M (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST1_M (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S) +#define SDIO_SLC0_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S 24 +/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_ST1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ST1_M (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S) +#define SDIO_CMD_DTC_INT_ST1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_ST1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST1_M (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S) +#define SDIO_HDA_RECV_DONE_INT_ST1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST1_S 28 + +/** SDIO_SLC0INT_ENA1_REG register + * reserved + */ +#define SDIO_SLC0INT_ENA1_REG (DR_REG_SDIO_BASE + 0x148) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA1_M (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S) +#define SDIO_SLC0_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA1_S 8 +/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA1_M (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S) +#define SDIO_SLC0_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S) +#define SDIO_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S) +#define SDIO_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA1_M (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S) +#define SDIO_SLC0_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA1_M (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S) +#define SDIO_SLC0_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA1_M (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA1_M (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S) +#define SDIO_SLC0_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S 24 +/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * reserved + */ +#define SDIO_CMD_DTC_INT_ENA1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA1_M (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S) +#define SDIO_CMD_DTC_INT_ENA1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0; + * reserved + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0; + * reserved + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0; + * reserved + */ +#define SDIO_HDA_RECV_DONE_INT_ENA1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA1_M (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S) +#define SDIO_HDA_RECV_DONE_INT_ENA1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA1_S 28 + +/** SDIO_SLC1INT_ST1_REG register + * reserved + */ +#define SDIO_SLC1INT_ST1_REG (DR_REG_SDIO_BASE + 0x14c) +/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S 7 +/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST1_M (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S) +#define SDIO_SLC1_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST1_S 8 +/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST1_M (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S) +#define SDIO_SLC1_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST1_M (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S) +#define SDIO_SLC1_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST1_M (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S) +#define SDIO_SLC1_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST1_M (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S) +#define SDIO_SLC1_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST1_M (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S) +#define SDIO_SLC1_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST1_M (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S) +#define SDIO_SLC1_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST1_M (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S) +#define SDIO_SLC1_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S 24 + +/** SDIO_SLC1INT_ENA1_REG register + * reserved + */ +#define SDIO_SLC1INT_ENA1_REG (DR_REG_SDIO_BASE + 0x150) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * reserved + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S 7 +/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA1_M (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S) +#define SDIO_SLC1_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA1_S 8 +/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA1_M (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S) +#define SDIO_SLC1_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S) +#define SDIO_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S) +#define SDIO_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA1_M (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S) +#define SDIO_SLC1_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA1_M (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S) +#define SDIO_SLC1_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA1_M (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S) +#define SDIO_SLC1_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA1_M (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S) +#define SDIO_SLC1_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * reserved + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * reserved + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * reserved + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S 24 + +/** SDIO_SLC0_TX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_SLC0_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x154) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC0_TX_SHAREMEM_END_REG register + * reserved + */ +#define SDIO_SLC0_TX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x158) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC0_RX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_SLC0_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x15c) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC0_RX_SHAREMEM_END_REG register + * reserved + */ +#define SDIO_SLC0_RX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x160) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC1_TX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_SLC1_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x164) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC1_TX_SHAREMEM_END_REG register + * reserved + */ +#define SDIO_SLC1_TX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x168) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC1_RX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_SLC1_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x16c) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC1_RX_SHAREMEM_END_REG register + * reserved + */ +#define SDIO_SLC1_RX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x170) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_HDA_TX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_HDA_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x174) +/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_HDA_RX_SHAREMEM_START_REG register + * reserved + */ +#define SDIO_HDA_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x178) +/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_BURST_LEN_REG register + * reserved + */ +#define SDIO_SLC_BURST_LEN_REG (DR_REG_SDIO_BASE + 0x17c) +/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1; + * 0-incr4,1-incr8 + */ +#define SDIO_SLC0_TXDATA_BURST_LEN (BIT(0)) +#define SDIO_SLC0_TXDATA_BURST_LEN_M (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S) +#define SDIO_SLC0_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_LEN_S 0 +/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1; + * 0-incr4,1-incr8 + */ +#define SDIO_SLC0_RXDATA_BURST_LEN (BIT(1)) +#define SDIO_SLC0_RXDATA_BURST_LEN_M (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S) +#define SDIO_SLC0_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_LEN_S 1 +/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1; + * 0-incr4,1-incr8 + */ +#define SDIO_SLC1_TXDATA_BURST_LEN (BIT(2)) +#define SDIO_SLC1_TXDATA_BURST_LEN_M (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S) +#define SDIO_SLC1_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_LEN_S 2 +/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1; + * 0-incr4,1-incr8 + */ +#define SDIO_SLC1_RXDATA_BURST_LEN (BIT(3)) +#define SDIO_SLC1_RXDATA_BURST_LEN_M (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S) +#define SDIO_SLC1_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_LEN_S 3 + +/** SDIO_SLCDATE_REG register + * ******* Description *********** + */ +#define SDIO_SLCDATE_REG (DR_REG_SDIO_BASE + 0x1f8) +/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400; + * reserved + */ +#define SDIO_SLC_DATE 0xFFFFFFFFU +#define SDIO_SLC_DATE_M (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S) +#define SDIO_SLC_DATE_V 0xFFFFFFFFU +#define SDIO_SLC_DATE_S 0 + +/** SDIO_SLCID_REG register + * ******* Description *********** + */ +#define SDIO_SLCID_REG (DR_REG_SDIO_BASE + 0x1fc) +/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256; + * reserved + */ +#define SDIO_SLC_ID 0xFFFFFFFFU +#define SDIO_SLC_ID_M (SDIO_SLC_ID_V << SDIO_SLC_ID_S) +#define SDIO_SLC_ID_V 0xFFFFFFFFU +#define SDIO_SLC_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/sdio_slc_struct.h b/components/soc/esp32c5/include/soc/sdio_slc_struct.h new file mode 100644 index 0000000000..eade8a4ad9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/sdio_slc_struct.h @@ -0,0 +1,3253 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of slcconf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_tx_rst : R/W; bitpos: [0]; default: 0; + * Set 1 to reset tx fsm in dma slc0. + */ + uint32_t slc0_tx_rst:1; + /** slc0_rx_rst : R/W; bitpos: [1]; default: 0; + * Set 1 to reset rx fsm in dma slc0. + */ + uint32_t slc0_rx_rst:1; + /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ + uint32_t slc_ahbm_fifo_rst:1; + /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ + uint32_t slc_ahbm_rst:1; + /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc0_tx_loop_test:1; + /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc0_rx_loop_test:1; + /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ + uint32_t slc0_rx_auto_wrback:1; + /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc0_rx_no_restart_clr:1; + /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ + uint32_t slc0_rxdscr_burst_en:1; + /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ + uint32_t slc0_rxdata_burst_en:1; + /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_rxlink_auto_ret:1; + /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_txlink_auto_ret:1; + /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ + uint32_t slc0_txdscr_burst_en:1; + /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ + uint32_t slc0_txdata_burst_en:1; + /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ + uint32_t slc0_token_auto_clr:1; + /** slc0_token_sel : R/W; bitpos: [15]; default: 1; + * reserved + */ + uint32_t slc0_token_sel:1; + /** slc1_tx_rst : R/W; bitpos: [16]; default: 0; + * Set 1 to reset tx fsm in dma slc0. + */ + uint32_t slc1_tx_rst:1; + /** slc1_rx_rst : R/W; bitpos: [17]; default: 0; + * Set 1 to reset rx fsm in dma slc0. + */ + uint32_t slc1_rx_rst:1; + /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1; + * reserved + */ + uint32_t slc0_wr_retry_mask_en:1; + /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1; + * reserved + */ + uint32_t slc1_wr_retry_mask_en:1; + /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_tx_loop_test:1; + /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_rx_loop_test:1; + /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ + uint32_t slc1_rx_auto_wrback:1; + /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0; + * ******* Description *********** + */ + uint32_t slc1_rx_no_restart_clr:1; + /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc1,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc1 + */ + uint32_t slc1_rxdscr_burst_en:1; + /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ + uint32_t slc1_rxdata_burst_en:1; + /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc1_rxlink_auto_ret:1; + /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc1_txlink_auto_ret:1; + /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc1,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc1 + */ + uint32_t slc1_txdscr_burst_en:1; + /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ + uint32_t slc1_txdata_burst_en:1; + /** slc1_token_auto_clr : R/W; bitpos: [30]; default: 1; + * auto clear slc1_token1 enable + */ + uint32_t slc1_token_auto_clr:1; + /** slc1_token_sel : R/W; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc1_token_sel:1; + }; + uint32_t val; +} sdio_slcconf0_reg_t; + +/** Type of slc0rxfifo_push register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * reserved + */ + uint32_t slc0_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc0rxfifo_push_reg_t; + +/** Type of slc1rxfifo_push register + * reserved + */ +typedef union { + struct { + /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * reserved + */ + uint32_t slc1_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc1rxfifo_push_reg_t; + +/** Type of slc0rx_link register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_stop:1; + /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_start:1; + /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_restart:1; + /** slc0_rxlink_park : RO; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc0_rxlink_park:1; + }; + uint32_t val; +} sdio_slc0rx_link_reg_t; + +/** Type of slc0rx_link_addr register + * reserved + */ +typedef union { + struct { + /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc0rx_link_addr_reg_t; + +/** Type of slc0tx_link register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ + uint32_t slc0_txlink_stop:1; + /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc0_txlink_start:1; + /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc0_txlink_restart:1; + /** slc0_txlink_park : RO; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc0_txlink_park:1; + }; + uint32_t val; +} sdio_slc0tx_link_reg_t; + +/** Type of slc0tx_link_addr register + * reserved + */ +typedef union { + struct { + /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_addr:32; + }; + uint32_t val; +} sdio_slc0tx_link_addr_reg_t; + +/** Type of slc1rx_link register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** slc1_bt_packet : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_bt_packet:1; + uint32_t reserved_21:7; + /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_stop:1; + /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_start:1; + /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_restart:1; + /** slc1_rxlink_park : RO; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc1_rxlink_park:1; + }; + uint32_t val; +} sdio_slc1rx_link_reg_t; + +/** Type of slc1rx_link_addr register + * reserved + */ +typedef union { + struct { + /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc1rx_link_addr_reg_t; + +/** Type of slc1tx_link register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * reserved + */ + uint32_t slc1_txlink_stop:1; + /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc1_txlink_start:1; + /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc1_txlink_restart:1; + /** slc1_txlink_park : RO; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc1_txlink_park:1; + }; + uint32_t val; +} sdio_slc1tx_link_reg_t; + +/** Type of slc1tx_link_addr register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_addr:32; + }; + uint32_t val; +} sdio_slc1tx_link_addr_reg_t; + +/** Type of slcintvec_tohost register + * reserved + */ +typedef union { + struct { + /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t slc0_tohost_intvec:8; + uint32_t reserved_8:8; + /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0; + * reserved + */ + uint32_t slc1_tohost_intvec:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} sdio_slcintvec_tohost_reg_t; + +/** Type of slc0token0 register + * reserved + */ +typedef union { + struct { + /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc0_token0_wdata:12; + /** slc0_token0_wr : WT; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_wr:1; + /** slc0_token0_inc : WT; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token0_inc:1; + /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token0 : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc0_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc0token0_reg_t; + +/** Type of slc0token1 register + * reserved + */ +typedef union { + struct { + /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0; + * slc0 token1 wdata + */ + uint32_t slc0_token1_wdata:12; + /** slc0_token1_wr : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ + uint32_t slc0_token1_wr:1; + /** slc0_token1_inc : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ + uint32_t slc0_token1_inc:1; + /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0; + * slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add + * slc0_token1_wdata to slc0_token1 + */ + uint32_t slc0_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token1 : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc0_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc0token1_reg_t; + +/** Type of slc1token0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc1_token0_wdata:12; + /** slc1_token0_wr : WT; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_wr:1; + /** slc1_token0_inc : WT; bitpos: [13]; default: 0; + * Add 1 to slc1_token0 + */ + uint32_t slc1_token0_inc:1; + /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0; + * Add slc1_token0_wdata to slc1_token0 + */ + uint32_t slc1_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token0 : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc1token0_reg_t; + +/** Type of slc1token1 register + * reserved + */ +typedef union { + struct { + /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc1_token1_wdata:12; + /** slc1_token1_wr : WT; bitpos: [12]; default: 0; + * update slc1_token1_wdata into slc1 token1 + */ + uint32_t slc1_token1_wr:1; + /** slc1_token1_inc : WT; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_inc:1; + /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token1 : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc1token1_reg_t; + +/** Type of slcconf1 register + * reserved + */ +typedef union { + struct { + /** slc0_check_owner : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_check_owner:1; + /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc0_tx_check_sum_en:1; + /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc0_rx_check_sum_en:1; + /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1; + * reserved + */ + uint32_t sdio_cmd_hold_en:1; + /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1; + * reserved + */ + uint32_t slc0_len_auto_clr:1; + /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1; + * reserved + */ + uint32_t slc0_tx_stitch_en:1; + /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1; + * reserved + */ + uint32_t slc0_rx_stitch_en:1; + uint32_t reserved_7:9; + /** slc1_check_owner : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_check_owner:1; + /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_tx_check_sum_en:1; + /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_rx_check_sum_en:1; + /** host_int_level_sel : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t host_int_level_sel:1; + /** slc1_tx_stitch_en : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_tx_stitch_en:1; + /** slc1_rx_stitch_en : R/W; bitpos: [21]; default: 1; + * reserved + */ + uint32_t slc1_rx_stitch_en:1; + /** sdio_clk_en : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t sdio_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} sdio_slcconf1_reg_t; + +/** Type of slcbridge_conf register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32; + * reserved + */ + uint32_t slc_txeof_ena:6; + uint32_t reserved_6:2; + /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7; + * reserved + */ + uint32_t slc_fifo_map_ena:4; + /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1; + * reserved + */ + uint32_t slc0_tx_dummy_mode:1; + /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1; + * reserved + */ + uint32_t slc_hda_map_128k:1; + /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1; + * reserved + */ + uint32_t slc1_tx_dummy_mode:1; + uint32_t reserved_15:1; + /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10; + * reserved + */ + uint32_t slc_tx_push_idle_num:16; + }; + uint32_t val; +} sdio_slcbridge_conf_reg_t; + +/** Type of slc0_to_eof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc0_to_eof_des_addr_reg_t; + +/** Type of slc0_tx_eof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc0_tx_eof_des_addr_reg_t; + +/** Type of slc0_to_eof_bfr_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc0_to_eof_bfr_des_addr_reg_t; + +/** Type of slc1_to_eof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc1_to_eof_des_addr_reg_t; + +/** Type of slc1_tx_eof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc1_tx_eof_des_addr_reg_t; + +/** Type of slc1_to_eof_bfr_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc1_to_eof_bfr_des_addr_reg_t; + +/** Type of slc_rx_dscr_conf register + * reserved + */ +typedef union { + struct { + /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_token_no_replace:1; + /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_infor_no_replace:1; + /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc0_rx_fill_mode:1; + /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ + uint32_t slc0_rx_eof_mode:1; + /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1; + * reserved + */ + uint32_t slc0_rx_fill_en:1; + /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128; + * reserved + */ + uint32_t slc0_rd_retry_threshold:11; + /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1; + * reserved + */ + uint32_t slc1_token_no_replace:1; + /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_infor_no_replace:1; + /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc1_rx_fill_mode:1; + /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ + uint32_t slc1_rx_eof_mode:1; + /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_rx_fill_en:1; + /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128; + * reserved + */ + uint32_t slc1_rd_retry_threshold:11; + }; + uint32_t val; +} sdio_slc_rx_dscr_conf_reg_t; + +/** Type of slc_tx_dscr_conf register + * reserved + */ +typedef union { + struct { + /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128; + * reserved + */ + uint32_t slc_wr_retry_threshold:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} sdio_slc_tx_dscr_conf_reg_t; + +/** Type of slc0_len_conf register + * reserved + */ +typedef union { + struct { + /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0; + * reserved + */ + uint32_t slc0_len_wdata:20; + /** slc0_len_wr : WT; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_len_wr:1; + /** slc0_len_inc : WT; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_len_inc:1; + /** slc0_len_inc_more : WT; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_len_inc_more:1; + /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_rx_packet_load_en:1; + /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_packet_load_en:1; + /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0; + * reserved + */ + uint32_t slc0_rx_get_used_dscr:1; + /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_tx_get_used_dscr:1; + /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_rx_new_pkt_ind:1; + /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1; + * reserved + */ + uint32_t slc0_tx_new_pkt_ind:1; + /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0; + * reserved + */ + uint32_t slc0_rx_packet_load_en_st:1; + /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0; + * reserved + */ + uint32_t slc0_tx_packet_load_en_st:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} sdio_slc0_len_conf_reg_t; + +/** Type of slc0_txpkt_h_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_txpkt_h_dscr_reg_t; + +/** Type of slc0_txpkt_e_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_txpkt_e_dscr_reg_t; + +/** Type of slc0_rxpkt_h_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_rxpkt_h_dscr_reg_t; + +/** Type of slc0_rxpkt_e_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_rxpkt_e_dscr_reg_t; + +/** Type of slc0_txpktu_h_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_txpktu_h_dscr_reg_t; + +/** Type of slc0_txpktu_e_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_txpktu_e_dscr_reg_t; + +/** Type of slc0_rxpktu_h_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_rxpktu_h_dscr_reg_t; + +/** Type of slc0_rxpktu_e_dscr register + * reserved + */ +typedef union { + struct { + /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_rxpktu_e_dscr_reg_t; + +/** Type of slc_seq_position register + * reserved + */ +typedef union { + struct { + /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9; + * reserved + */ + uint32_t slc0_seq_position:8; + /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5; + * reserved + */ + uint32_t slc1_seq_position:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdio_slc_seq_position_reg_t; + +/** Type of slc0_dscr_rec_conf register + * reserved + */ +typedef union { + struct { + /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023; + * reserved + */ + uint32_t slc0_rx_dscr_rec_lim:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} sdio_slc0_dscr_rec_conf_reg_t; + +/** Type of slc_sdio_crc_st1 register + * reserved + */ +typedef union { + struct { + /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t cmd_crc_err_cnt:8; + uint32_t reserved_8:23; + /** err_cnt_clr : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t err_cnt_clr:1; + }; + uint32_t val; +} sdio_slc_sdio_crc_st1_reg_t; + +/** Type of slc0_len_lim_conf register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504; + * reserved + */ + uint32_t slc0_len_lim:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc0_len_lim_conf_reg_t; + +/** Type of slc0_tx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_slc0_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc0_tx_sharemem_start_reg_t; + +/** Type of slc0_tx_sharemem_end register + * reserved + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t sdio_slc0_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc0_tx_sharemem_end_reg_t; + +/** Type of slc0_rx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_slc0_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc0_rx_sharemem_start_reg_t; + +/** Type of slc0_rx_sharemem_end register + * reserved + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t sdio_slc0_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc0_rx_sharemem_end_reg_t; + +/** Type of slc1_tx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_slc1_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc1_tx_sharemem_start_reg_t; + +/** Type of slc1_tx_sharemem_end register + * reserved + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t sdio_slc1_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc1_tx_sharemem_end_reg_t; + +/** Type of slc1_rx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_slc1_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc1_rx_sharemem_start_reg_t; + +/** Type of slc1_rx_sharemem_end register + * reserved + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * reserved + */ + uint32_t sdio_slc1_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc1_rx_sharemem_end_reg_t; + +/** Type of hda_tx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_hda_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_hda_tx_sharemem_start_reg_t; + +/** Type of hda_rx_sharemem_start register + * reserved + */ +typedef union { + struct { + /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t sdio_hda_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_hda_rx_sharemem_start_reg_t; + +/** Type of slc_burst_len register + * reserved + */ +typedef union { + struct { + /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1; + * 0-incr4,1-incr8 + */ + uint32_t slc0_txdata_burst_len:1; + /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1; + * 0-incr4,1-incr8 + */ + uint32_t slc0_rxdata_burst_len:1; + /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1; + * 0-incr4,1-incr8 + */ + uint32_t slc1_txdata_burst_len:1; + /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1; + * 0-incr4,1-incr8 + */ + uint32_t slc1_rxdata_burst_len:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdio_slc_burst_len_reg_t; + +/** Type of slcid register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_id : R/W; bitpos: [31:0]; default: 256; + * reserved + */ + uint32_t slc_id:32; + }; + uint32_t val; +} sdio_slcid_reg_t; + + +/** Group: Interrupt registers */ +/** Type of slc0int_raw register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_raw:1; + /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_raw:1; + /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_raw:1; + /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_raw:1; + /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_raw:1; + /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_raw:1; + /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_raw:1; + /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_raw:1; + /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_raw:1; + /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_raw:1; + /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_raw:1; + /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_raw:1; + /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_raw:1; + /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_raw:1; + /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of slc0 finishing receiving data to one buffer + */ + uint32_t slc0_tx_done_int_raw:1; + /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of slc0 finishing receiving data + */ + uint32_t slc0_tx_suc_eof_int_raw:1; + /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of slc0 finishing sending data from one buffer + */ + uint32_t slc0_rx_done_int_raw:1; + /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of slc0 finishing sending data + */ + uint32_t slc0_rx_eof_int_raw:1; + /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_raw:1; + /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of slc0 tx link descriptor error + */ + uint32_t slc0_tx_dscr_err_int_raw:1; + /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of slc0 rx link descriptor error + */ + uint32_t slc0_rx_dscr_err_int_raw:1; + /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_raw:1; + /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_raw:1; + /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_raw:1; + /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_raw:1; + /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_raw:1; + /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_raw:1; + /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_raw:1; + /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_raw:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_raw_reg_t; + +/** Type of slc0int_st register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_st:1; + /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_st:1; + /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_st:1; + /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_st:1; + /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_st:1; + /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_st:1; + /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_st:1; + /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_st:1; + /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_st:1; + /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_st:1; + /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_st:1; + /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_st:1; + /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_st:1; + /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_st:1; + /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_st:1; + /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_st:1; + /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_st:1; + /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_st:1; + /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_st:1; + /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_st:1; + /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_st:1; + /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_st:1; + /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_st:1; + /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_st:1; + /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_st:1; + /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_st:1; + /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_st:1; + /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_st:1; + /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_st:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_st_reg_t; + +/** Type of slc0int_ena register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_ena:1; + /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_ena:1; + /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_ena:1; + /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_ena:1; + /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_ena:1; + /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_ena:1; + /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_ena:1; + /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_ena:1; + /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_ena:1; + /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_ena:1; + /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_ena:1; + /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_ena:1; + /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_ena:1; + /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_ena:1; + /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_ena:1; + /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_ena:1; + /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_ena:1; + /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_ena:1; + /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_ena:1; + /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_ena:1; + /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_ena:1; + /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_ena:1; + /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_ena:1; + /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_ena:1; + /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_ena:1; + /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_ena:1; + /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_ena:1; + /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_ena:1; + /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_ena:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_ena_reg_t; + +/** Type of slc0int_clr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_clr:1; + /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_clr:1; + /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_clr:1; + /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_clr:1; + /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_clr:1; + /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_clr:1; + /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_clr:1; + /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_clr:1; + /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_clr:1; + /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_clr:1; + /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_clr:1; + /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_clr:1; + /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_clr:1; + /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_clr:1; + /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_clr:1; + /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_clr:1; + /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_clr:1; + /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_clr:1; + /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_clr:1; + /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_clr:1; + /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_clr:1; + /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_clr:1; + /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_clr:1; + /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_clr:1; + /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_clr:1; + /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_clr:1; + /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_clr:1; + /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_clr:1; + /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_clr:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_clr_reg_t; + +/** Type of slc1int_raw register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_raw:1; + /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_raw:1; + /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_raw:1; + /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_raw:1; + /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_raw:1; + /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_raw:1; + /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_raw:1; + /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_raw:1; + /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_raw:1; + /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_raw:1; + /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_raw:1; + /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_raw:1; + /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_raw:1; + /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_raw:1; + /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_raw:1; + /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_raw:1; + /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_raw:1; + /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_raw:1; + /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_raw:1; + /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_raw:1; + /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_raw:1; + /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_raw:1; + /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_raw:1; + /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_raw:1; + /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_raw:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_raw_reg_t; + +/** Type of slc1int_st register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_st:1; + /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_st:1; + /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_st:1; + /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_st:1; + /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_st:1; + /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_st:1; + /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_st:1; + /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_st:1; + /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_st:1; + /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_st:1; + /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_st:1; + /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_st:1; + /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_st:1; + /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_st:1; + /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_st:1; + /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_st:1; + /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_st:1; + /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_st:1; + /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_st:1; + /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_st:1; + /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_st:1; + /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_st:1; + /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_st:1; + /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_st:1; + /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_st:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_st_reg_t; + +/** Type of slc1int_ena register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_ena:1; + /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_ena:1; + /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_ena:1; + /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_ena:1; + /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_ena:1; + /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_ena:1; + /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_ena:1; + /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_ena:1; + /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_ena:1; + /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_ena:1; + /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_ena:1; + /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_ena:1; + /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_ena:1; + /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_ena:1; + /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_ena:1; + /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_ena:1; + /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_ena:1; + /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_ena:1; + /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_ena:1; + /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_ena:1; + /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_ena:1; + /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_ena:1; + /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_ena:1; + /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_ena:1; + /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_ena:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_ena_reg_t; + +/** Type of slc1int_clr register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_clr:1; + /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_clr:1; + /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_clr:1; + /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_clr:1; + /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_clr:1; + /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_clr:1; + /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_clr:1; + /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_clr:1; + /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_clr:1; + /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_clr:1; + /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_clr:1; + /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_clr:1; + /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_clr:1; + /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_clr:1; + /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_clr:1; + /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_clr:1; + /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_clr:1; + /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_clr:1; + /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_clr:1; + /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_clr:1; + /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_clr:1; + /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_clr:1; + /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_clr:1; + /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_clr:1; + /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_clr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_clr_reg_t; + +/** Type of slc0int_st1 register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_st1:1; + /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_st1:1; + /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_st1:1; + /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_st1:1; + /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_st1:1; + /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_st1:1; + /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_st1:1; + /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_st1:1; + /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_st1:1; + /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_st1:1; + /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_st1:1; + /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_st1:1; + /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_st1:1; + /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_st1:1; + /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_st1:1; + /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_st1:1; + /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_st1:1; + /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_st1:1; + /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_st1:1; + /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_st1:1; + /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_st1:1; + /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_st1:1; + /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_st1:1; + /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_st1:1; + /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_st1:1; + /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_st1:1; + /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_st1:1; + /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_st1:1; + /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_st1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_st1_reg_t; + +/** Type of slc0int_ena1 register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit0_int_ena1:1; + /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit1_int_ena1:1; + /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit2_int_ena1:1; + /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit3_int_ena1:1; + /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit4_int_ena1:1; + /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit5_int_ena1:1; + /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit6_int_ena1:1; + /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit7_int_ena1:1; + /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc0_rx_start_int_ena1:1; + /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc0_tx_start_int_ena1:1; + /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc0_rx_udf_int_ena1:1; + /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc0_tx_ovf_int_ena1:1; + /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc0_token0_1to0_int_ena1:1; + /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc0_token1_1to0_int_ena1:1; + /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc0_tx_done_int_ena1:1; + /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc0_tx_suc_eof_int_ena1:1; + /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_done_int_ena1:1; + /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc0_rx_eof_int_ena1:1; + /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc0_tohost_int_ena1:1; + /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_err_int_ena1:1; + /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc0_rx_dscr_err_int_ena1:1; + /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc0_tx_dscr_empty_int_ena1:1; + /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc0_host_rd_ack_int_ena1:1; + /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc0_wr_retry_done_int_ena1:1; + /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_int_ena1:1; + /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0; + * reserved + */ + uint32_t cmd_dtc_int_ena1:1; + /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0; + * reserved + */ + uint32_t slc0_rx_quick_eof_int_ena1:1; + /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0; + * reserved + */ + uint32_t slc0_host_pop_eof_err_int_ena1:1; + /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0; + * reserved + */ + uint32_t hda_recv_done_int_ena1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc0int_ena1_reg_t; + +/** Type of slc1int_st1 register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_st1:1; + /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_st1:1; + /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_st1:1; + /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_st1:1; + /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_st1:1; + /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_st1:1; + /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_st1:1; + /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_st1:1; + /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_st1:1; + /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_st1:1; + /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_st1:1; + /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_st1:1; + /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_st1:1; + /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_st1:1; + /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_st1:1; + /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_st1:1; + /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_st1:1; + /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_st1:1; + /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_st1:1; + /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_st1:1; + /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_st1:1; + /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_st1:1; + /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_st1:1; + /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_st1:1; + /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_st1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_st1_reg_t; + +/** Type of slc1int_ena1 register + * reserved + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit8_int_ena1:1; + /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit9_int_ena1:1; + /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit10_int_ena1:1; + /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit11_int_ena1:1; + /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit12_int_ena1:1; + /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit13_int_ena1:1; + /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit14_int_ena1:1; + /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0; + * reserved + */ + uint32_t slc_frhost_bit15_int_ena1:1; + /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * reserved + */ + uint32_t slc1_rx_start_int_ena1:1; + /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * reserved + */ + uint32_t slc1_tx_start_int_ena1:1; + /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * reserved + */ + uint32_t slc1_rx_udf_int_ena1:1; + /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * reserved + */ + uint32_t slc1_tx_ovf_int_ena1:1; + /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * reserved + */ + uint32_t slc1_token0_1to0_int_ena1:1; + /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * reserved + */ + uint32_t slc1_token1_1to0_int_ena1:1; + /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * reserved + */ + uint32_t slc1_tx_done_int_ena1:1; + /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * reserved + */ + uint32_t slc1_tx_suc_eof_int_ena1:1; + /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_done_int_ena1:1; + /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * reserved + */ + uint32_t slc1_rx_eof_int_ena1:1; + /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * reserved + */ + uint32_t slc1_tohost_int_ena1:1; + /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_err_int_ena1:1; + /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * reserved + */ + uint32_t slc1_rx_dscr_err_int_ena1:1; + /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * reserved + */ + uint32_t slc1_tx_dscr_empty_int_ena1:1; + /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * reserved + */ + uint32_t slc1_host_rd_ack_int_ena1:1; + /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * reserved + */ + uint32_t slc1_wr_retry_done_int_ena1:1; + /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_int_ena1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc1int_ena1_reg_t; + + +/** Group: Status registers */ +/** Type of slcrx_status register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rx_full : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_rx_full:1; + /** slc0_rx_empty : RO; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_rx_empty:1; + /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0; + * the current buffer length when slc0 reads data from rx link + */ + uint32_t slc0_rx_buf_len:14; + /** slc1_rx_full : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_rx_full:1; + /** slc1_rx_empty : RO; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_rx_empty:1; + /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0; + * the current buffer length when slc1 reads data from rx link + */ + uint32_t slc1_rx_buf_len:14; + }; + uint32_t val; +} sdio_slcrx_status_reg_t; + +/** Type of slctx_status register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_tx_full : RO; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_tx_full:1; + /** slc0_tx_empty : RO; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_tx_empty:1; + uint32_t reserved_2:14; + /** slc1_tx_full : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_tx_full:1; + /** slc1_tx_empty : RO; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_tx_empty:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slctx_status_reg_t; + +/** Type of slc0_state0 register + * reserved + */ +typedef union { + struct { + /** slc0_state0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_state0:32; + }; + uint32_t val; +} sdio_slc0_state0_reg_t; + +/** Type of slc0_state1 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] + * rx_link fsm state, [30:24] rx_fifo_cnt + */ + uint32_t slc0_state1:32; + }; + uint32_t val; +} sdio_slc0_state1_reg_t; + +/** Type of slc1_state0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_state0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_state0:32; + }; + uint32_t val; +} sdio_slc1_state0_reg_t; + +/** Type of slc1_state1 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21] + * rx_link fsm state, [30:24] rx_fifo_cnt + */ + uint32_t slc1_state1:32; + }; + uint32_t val; +} sdio_slc1_state1_reg_t; + +/** Type of slc_sdio_st register + * reserved + */ +typedef union { + struct { + /** cmd_st : RO; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t cmd_st:3; + uint32_t reserved_3:1; + /** func_st : RO; bitpos: [7:4]; default: 0; + * reserved + */ + uint32_t func_st:4; + /** sdio_wakeup : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t sdio_wakeup:1; + uint32_t reserved_9:3; + /** bus_st : RO; bitpos: [14:12]; default: 0; + * reserved + */ + uint32_t bus_st:3; + uint32_t reserved_15:1; + /** func1_acc_state : RO; bitpos: [20:16]; default: 0; + * reserved + */ + uint32_t func1_acc_state:5; + uint32_t reserved_21:3; + /** func2_acc_state : RO; bitpos: [28:24]; default: 0; + * reserved + */ + uint32_t func2_acc_state:5; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_sdio_st_reg_t; + +/** Type of slc0_txlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc0_txlink_dscr_reg_t; + +/** Type of slc0_txlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc0_txlink_dscr_bf0_reg_t; + +/** Type of slc0_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc0_txlink_dscr_bf1_reg_t; + +/** Type of slc0_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ + uint32_t slc0_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc0_rxlink_dscr_reg_t; + +/** Type of slc0_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc0_rxlink_dscr_bf0_reg_t; + +/** Type of slc0_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc0_rxlink_dscr_bf1_reg_t; + +/** Type of slc1_txlink_dscr register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc1_txlink_dscr_reg_t; + +/** Type of slc1_txlink_dscr_bf0 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc1_txlink_dscr_bf0_reg_t; + +/** Type of slc1_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc1_txlink_dscr_bf1_reg_t; + +/** Type of slc1_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ + uint32_t slc1_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc1_rxlink_dscr_reg_t; + +/** Type of slc1_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc1_rxlink_dscr_bf0_reg_t; + +/** Type of slc1_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc1_rxlink_dscr_bf1_reg_t; + +/** Type of slc0_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc0_tx_erreof_des_addr_reg_t; + +/** Type of slc1_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc1_tx_erreof_des_addr_reg_t; + +/** Type of slc_token_lat register + * reserved + */ +typedef union { + struct { + /** slc0_token : RO; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc0_token:12; + uint32_t reserved_12:4; + /** slc1_token : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_token_lat_reg_t; + +/** Type of slc_cmd_infor0 register + * reserved + */ +typedef union { + struct { + /** cmd_content0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content0:32; + }; + uint32_t val; +} sdio_slc_cmd_infor0_reg_t; + +/** Type of slc_cmd_infor1 register + * reserved + */ +typedef union { + struct { + /** cmd_content1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content1:32; + }; + uint32_t val; +} sdio_slc_cmd_infor1_reg_t; + +/** Type of slc0_length register + * reserved + */ +typedef union { + struct { + /** slc0_len : RO; bitpos: [19:0]; default: 0; + * reserved + */ + uint32_t slc0_len:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc0_length_reg_t; + +/** Type of slc_sdio_crc_st0 register + * reserved + */ +typedef union { + struct { + /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t dat0_crc_err_cnt:8; + /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0; + * reserved + */ + uint32_t dat1_crc_err_cnt:8; + /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0; + * reserved + */ + uint32_t dat2_crc_err_cnt:8; + /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t dat3_crc_err_cnt:8; + }; + uint32_t val; +} sdio_slc_sdio_crc_st0_reg_t; + +/** Type of slc0_eof_start_des register + * reserved + */ +typedef union { + struct { + /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_eof_start_des_addr:32; + }; + uint32_t val; +} sdio_slc0_eof_start_des_reg_t; + +/** Type of slc0_push_dscr_addr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ + uint32_t slc0_rx_push_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_push_dscr_addr_reg_t; + +/** Type of slc0_done_dscr_addr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ + uint32_t slc0_rx_done_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_done_dscr_addr_reg_t; + +/** Type of slc0_sub_start_des register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ + uint32_t slc0_sub_pac_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc0_sub_start_des_reg_t; + +/** Type of slc0_dscr_cnt register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0; + * the number of descriptors got by slc0 when it tries to read data from memory + */ + uint32_t slc0_rx_dscr_cnt_lat:10; + uint32_t reserved_10:6; + /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_rx_get_eof_occ:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc0_dscr_cnt_reg_t; + + +/** Group: Debud registers */ +/** Type of slc0txfifo_pop register + * reserved + */ +typedef union { + struct { + /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * reserved + */ + uint32_t slc0_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc0_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc0txfifo_pop_reg_t; + +/** Type of slc1txfifo_pop register + * reserved + */ +typedef union { + struct { + /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * reserved + */ + uint32_t slc1_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * reserved + */ + uint32_t slc1_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc1txfifo_pop_reg_t; + +/** Type of slc_ahb_test register + * reserved + */ +typedef union { + struct { + /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t slc_ahb_testmode:3; + uint32_t reserved_3:1; + /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t slc_ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} sdio_slc_ahb_test_reg_t; + + +/** Group: Version registers */ +/** Type of slcdate register + * ******* Description *********** + */ +typedef union { + struct { + /** slc_date : R/W; bitpos: [31:0]; default: 554182400; + * reserved + */ + uint32_t slc_date:32; + }; + uint32_t val; +} sdio_slcdate_reg_t; + + +typedef struct { + volatile sdio_slcconf0_reg_t slcconf0; + volatile sdio_slc0int_raw_reg_t slc0int_raw; + volatile sdio_slc0int_st_reg_t slc0int_st; + volatile sdio_slc0int_ena_reg_t slc0int_ena; + volatile sdio_slc0int_clr_reg_t slc0int_clr; + volatile sdio_slc1int_raw_reg_t slc1int_raw; + volatile sdio_slc1int_st_reg_t slc1int_st; + volatile sdio_slc1int_ena_reg_t slc1int_ena; + volatile sdio_slc1int_clr_reg_t slc1int_clr; + volatile sdio_slcrx_status_reg_t slcrx_status; + volatile sdio_slc0rxfifo_push_reg_t slc0rxfifo_push; + volatile sdio_slc1rxfifo_push_reg_t slc1rxfifo_push; + volatile sdio_slctx_status_reg_t slctx_status; + volatile sdio_slc0txfifo_pop_reg_t slc0txfifo_pop; + volatile sdio_slc1txfifo_pop_reg_t slc1txfifo_pop; + volatile sdio_slc0rx_link_reg_t slc0rx_link; + volatile sdio_slc0rx_link_addr_reg_t slc0rx_link_addr; + volatile sdio_slc0tx_link_reg_t slc0tx_link; + volatile sdio_slc0tx_link_addr_reg_t slc0tx_link_addr; + volatile sdio_slc1rx_link_reg_t slc1rx_link; + volatile sdio_slc1rx_link_addr_reg_t slc1rx_link_addr; + volatile sdio_slc1tx_link_reg_t slc1tx_link; + volatile sdio_slc1tx_link_addr_reg_t slc1tx_link_addr; + volatile sdio_slcintvec_tohost_reg_t slcintvec_tohost; + volatile sdio_slc0token0_reg_t slc0token0; + volatile sdio_slc0token1_reg_t slc0token1; + volatile sdio_slc1token0_reg_t slc1token0; + volatile sdio_slc1token1_reg_t slc1token1; + volatile sdio_slcconf1_reg_t slcconf1; + volatile sdio_slc0_state0_reg_t slc0_state0; + volatile sdio_slc0_state1_reg_t slc0_state1; + volatile sdio_slc1_state0_reg_t slc1_state0; + volatile sdio_slc1_state1_reg_t slc1_state1; + volatile sdio_slcbridge_conf_reg_t slcbridge_conf; + volatile sdio_slc0_to_eof_des_addr_reg_t slc0_to_eof_des_addr; + volatile sdio_slc0_tx_eof_des_addr_reg_t slc0_tx_eof_des_addr; + volatile sdio_slc0_to_eof_bfr_des_addr_reg_t slc0_to_eof_bfr_des_addr; + volatile sdio_slc1_to_eof_des_addr_reg_t slc1_to_eof_des_addr; + volatile sdio_slc1_tx_eof_des_addr_reg_t slc1_tx_eof_des_addr; + volatile sdio_slc1_to_eof_bfr_des_addr_reg_t slc1_to_eof_bfr_des_addr; + volatile sdio_slc_ahb_test_reg_t slc_ahb_test; + volatile sdio_slc_sdio_st_reg_t slc_sdio_st; + volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf; + volatile sdio_slc0_txlink_dscr_reg_t slc0_txlink_dscr; + volatile sdio_slc0_txlink_dscr_bf0_reg_t slc0_txlink_dscr_bf0; + volatile sdio_slc0_txlink_dscr_bf1_reg_t slc0_txlink_dscr_bf1; + volatile sdio_slc0_rxlink_dscr_reg_t slc0_rxlink_dscr; + volatile sdio_slc0_rxlink_dscr_bf0_reg_t slc0_rxlink_dscr_bf0; + volatile sdio_slc0_rxlink_dscr_bf1_reg_t slc0_rxlink_dscr_bf1; + volatile sdio_slc1_txlink_dscr_reg_t slc1_txlink_dscr; + volatile sdio_slc1_txlink_dscr_bf0_reg_t slc1_txlink_dscr_bf0; + volatile sdio_slc1_txlink_dscr_bf1_reg_t slc1_txlink_dscr_bf1; + volatile sdio_slc1_rxlink_dscr_reg_t slc1_rxlink_dscr; + volatile sdio_slc1_rxlink_dscr_bf0_reg_t slc1_rxlink_dscr_bf0; + volatile sdio_slc1_rxlink_dscr_bf1_reg_t slc1_rxlink_dscr_bf1; + volatile sdio_slc0_tx_erreof_des_addr_reg_t slc0_tx_erreof_des_addr; + volatile sdio_slc1_tx_erreof_des_addr_reg_t slc1_tx_erreof_des_addr; + volatile sdio_slc_token_lat_reg_t slc_token_lat; + volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf; + volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0; + volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1; + volatile sdio_slc0_len_conf_reg_t slc0_len_conf; + volatile sdio_slc0_length_reg_t slc0_length; + volatile sdio_slc0_txpkt_h_dscr_reg_t slc0_txpkt_h_dscr; + volatile sdio_slc0_txpkt_e_dscr_reg_t slc0_txpkt_e_dscr; + volatile sdio_slc0_rxpkt_h_dscr_reg_t slc0_rxpkt_h_dscr; + volatile sdio_slc0_rxpkt_e_dscr_reg_t slc0_rxpkt_e_dscr; + volatile sdio_slc0_txpktu_h_dscr_reg_t slc0_txpktu_h_dscr; + volatile sdio_slc0_txpktu_e_dscr_reg_t slc0_txpktu_e_dscr; + volatile sdio_slc0_rxpktu_h_dscr_reg_t slc0_rxpktu_h_dscr; + volatile sdio_slc0_rxpktu_e_dscr_reg_t slc0_rxpktu_e_dscr; + volatile sdio_slc_seq_position_reg_t slc_seq_position; + volatile sdio_slc0_dscr_rec_conf_reg_t slc0_dscr_rec_conf; + volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0; + volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1; + volatile sdio_slc0_eof_start_des_reg_t slc0_eof_start_des; + volatile sdio_slc0_push_dscr_addr_reg_t slc0_push_dscr_addr; + volatile sdio_slc0_done_dscr_addr_reg_t slc0_done_dscr_addr; + volatile sdio_slc0_sub_start_des_reg_t slc0_sub_start_des; + volatile sdio_slc0_dscr_cnt_reg_t slc0_dscr_cnt; + volatile sdio_slc0_len_lim_conf_reg_t slc0_len_lim_conf; + volatile sdio_slc0int_st1_reg_t slc0int_st1; + volatile sdio_slc0int_ena1_reg_t slc0int_ena1; + volatile sdio_slc1int_st1_reg_t slc1int_st1; + volatile sdio_slc1int_ena1_reg_t slc1int_ena1; + volatile sdio_slc0_tx_sharemem_start_reg_t slc0_tx_sharemem_start; + volatile sdio_slc0_tx_sharemem_end_reg_t slc0_tx_sharemem_end; + volatile sdio_slc0_rx_sharemem_start_reg_t slc0_rx_sharemem_start; + volatile sdio_slc0_rx_sharemem_end_reg_t slc0_rx_sharemem_end; + volatile sdio_slc1_tx_sharemem_start_reg_t slc1_tx_sharemem_start; + volatile sdio_slc1_tx_sharemem_end_reg_t slc1_tx_sharemem_end; + volatile sdio_slc1_rx_sharemem_start_reg_t slc1_rx_sharemem_start; + volatile sdio_slc1_rx_sharemem_end_reg_t slc1_rx_sharemem_end; + volatile sdio_hda_tx_sharemem_start_reg_t hda_tx_sharemem_start; + volatile sdio_hda_rx_sharemem_start_reg_t hda_rx_sharemem_start; + volatile sdio_slc_burst_len_reg_t slc_burst_len; + uint32_t reserved_180[30]; + volatile sdio_slcdate_reg_t slcdate; + volatile sdio_slcid_reg_t slcid; +} sdio_dev_t; + +extern sdio_dev_t SLC; + +#ifndef __cplusplus +_Static_assert(sizeof(sdio_dev_t) == 0x200, "Invalid size of sdio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi1_mem_reg.h b/components/soc/esp32c5/include/soc/spi1_mem_reg.h new file mode 100644 index 0000000000..ce950f24f5 --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi1_mem_reg.h @@ -0,0 +1,1232 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI1_MEM_CMD_REG register + * SPI1 memory command register + */ +#define SPI1_MEM_CMD_REG (DR_REG_SPI1_MEM_BASE + 0x0) +/** SPI1_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ +#define SPI1_MEM_MST_ST 0x0000000FU +#define SPI1_MEM_MST_ST_M (SPI1_MEM_MST_ST_V << SPI1_MEM_MST_ST_S) +#define SPI1_MEM_MST_ST_V 0x0000000FU +#define SPI1_MEM_MST_ST_S 0 +/** SPI1_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI1_MEM_SLV_ST 0x0000000FU +#define SPI1_MEM_SLV_ST_M (SPI1_MEM_SLV_ST_V << SPI1_MEM_SLV_ST_S) +#define SPI1_MEM_SLV_ST_V 0x0000000FU +#define SPI1_MEM_SLV_ST_S 4 +/** SPI1_MEM_USR : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ +#define SPI1_MEM_USR (BIT(18)) +#define SPI1_MEM_USR_M (SPI1_MEM_USR_V << SPI1_MEM_USR_S) +#define SPI1_MEM_USR_V 0x00000001U +#define SPI1_MEM_USR_S 18 + +/** SPI1_MEM_ADDR_REG register + * SPI1 address register + */ +#define SPI1_MEM_ADDR_REG (DR_REG_SPI1_MEM_BASE + 0x4) +/** SPI1_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ +#define SPI1_MEM_USR_ADDR_VALUE 0xFFFFFFFFU +#define SPI1_MEM_USR_ADDR_VALUE_M (SPI1_MEM_USR_ADDR_VALUE_V << SPI1_MEM_USR_ADDR_VALUE_S) +#define SPI1_MEM_USR_ADDR_VALUE_V 0xFFFFFFFFU +#define SPI1_MEM_USR_ADDR_VALUE_S 0 + +/** SPI1_MEM_CTRL_REG register + * SPI1 control register. + */ +#define SPI1_MEM_CTRL_REG (DR_REG_SPI1_MEM_BASE + 0x8) +/** SPI1_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI1_MEM_FDUMMY_RIN (BIT(2)) +#define SPI1_MEM_FDUMMY_RIN_M (SPI1_MEM_FDUMMY_RIN_V << SPI1_MEM_FDUMMY_RIN_S) +#define SPI1_MEM_FDUMMY_RIN_V 0x00000001U +#define SPI1_MEM_FDUMMY_RIN_S 2 +/** SPI1_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ +#define SPI1_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI1_MEM_FDUMMY_WOUT_M (SPI1_MEM_FDUMMY_WOUT_V << SPI1_MEM_FDUMMY_WOUT_S) +#define SPI1_MEM_FDUMMY_WOUT_V 0x00000001U +#define SPI1_MEM_FDUMMY_WOUT_S 3 +/** SPI1_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI1_MEM_FDOUT_OCT (BIT(4)) +#define SPI1_MEM_FDOUT_OCT_M (SPI1_MEM_FDOUT_OCT_V << SPI1_MEM_FDOUT_OCT_S) +#define SPI1_MEM_FDOUT_OCT_V 0x00000001U +#define SPI1_MEM_FDOUT_OCT_S 4 +/** SPI1_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI1_MEM_FDIN_OCT (BIT(5)) +#define SPI1_MEM_FDIN_OCT_M (SPI1_MEM_FDIN_OCT_V << SPI1_MEM_FDIN_OCT_S) +#define SPI1_MEM_FDIN_OCT_V 0x00000001U +#define SPI1_MEM_FDIN_OCT_S 5 +/** SPI1_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI1_MEM_FADDR_OCT (BIT(6)) +#define SPI1_MEM_FADDR_OCT_M (SPI1_MEM_FADDR_OCT_V << SPI1_MEM_FADDR_OCT_S) +#define SPI1_MEM_FADDR_OCT_V 0x00000001U +#define SPI1_MEM_FADDR_OCT_S 6 +/** SPI1_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI1_MEM_FCMD_QUAD (BIT(8)) +#define SPI1_MEM_FCMD_QUAD_M (SPI1_MEM_FCMD_QUAD_V << SPI1_MEM_FCMD_QUAD_S) +#define SPI1_MEM_FCMD_QUAD_V 0x00000001U +#define SPI1_MEM_FCMD_QUAD_S 8 +/** SPI1_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI1_MEM_FCMD_OCT (BIT(9)) +#define SPI1_MEM_FCMD_OCT_M (SPI1_MEM_FCMD_OCT_V << SPI1_MEM_FCMD_OCT_S) +#define SPI1_MEM_FCMD_OCT_V 0x00000001U +#define SPI1_MEM_FCMD_OCT_S 9 +/** SPI1_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. + */ +#define SPI1_MEM_FASTRD_MODE (BIT(13)) +#define SPI1_MEM_FASTRD_MODE_M (SPI1_MEM_FASTRD_MODE_V << SPI1_MEM_FASTRD_MODE_S) +#define SPI1_MEM_FASTRD_MODE_V 0x00000001U +#define SPI1_MEM_FASTRD_MODE_S 13 +/** SPI1_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI1_MEM_FREAD_DUAL (BIT(14)) +#define SPI1_MEM_FREAD_DUAL_M (SPI1_MEM_FREAD_DUAL_V << SPI1_MEM_FREAD_DUAL_S) +#define SPI1_MEM_FREAD_DUAL_V 0x00000001U +#define SPI1_MEM_FREAD_DUAL_S 14 +/** SPI1_MEM_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI1_MEM_Q_POL (BIT(18)) +#define SPI1_MEM_Q_POL_M (SPI1_MEM_Q_POL_V << SPI1_MEM_Q_POL_S) +#define SPI1_MEM_Q_POL_V 0x00000001U +#define SPI1_MEM_Q_POL_S 18 +/** SPI1_MEM_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI1_MEM_D_POL (BIT(19)) +#define SPI1_MEM_D_POL_M (SPI1_MEM_D_POL_V << SPI1_MEM_D_POL_S) +#define SPI1_MEM_D_POL_V 0x00000001U +#define SPI1_MEM_D_POL_S 19 +/** SPI1_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI1_MEM_FREAD_QUAD (BIT(20)) +#define SPI1_MEM_FREAD_QUAD_M (SPI1_MEM_FREAD_QUAD_V << SPI1_MEM_FREAD_QUAD_S) +#define SPI1_MEM_FREAD_QUAD_V 0x00000001U +#define SPI1_MEM_FREAD_QUAD_S 20 +/** SPI1_MEM_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI1_MEM_WP_REG (BIT(21)) +#define SPI1_MEM_WP_REG_M (SPI1_MEM_WP_REG_V << SPI1_MEM_WP_REG_S) +#define SPI1_MEM_WP_REG_V 0x00000001U +#define SPI1_MEM_WP_REG_S 21 +/** SPI1_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI1_MEM_FREAD_DIO (BIT(23)) +#define SPI1_MEM_FREAD_DIO_M (SPI1_MEM_FREAD_DIO_V << SPI1_MEM_FREAD_DIO_S) +#define SPI1_MEM_FREAD_DIO_V 0x00000001U +#define SPI1_MEM_FREAD_DIO_S 23 +/** SPI1_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI1_MEM_FREAD_QIO (BIT(24)) +#define SPI1_MEM_FREAD_QIO_M (SPI1_MEM_FREAD_QIO_V << SPI1_MEM_FREAD_QIO_S) +#define SPI1_MEM_FREAD_QIO_V 0x00000001U +#define SPI1_MEM_FREAD_QIO_S 24 + +/** SPI1_MEM_CTRL1_REG register + * SPI1 control1 register. + */ +#define SPI1_MEM_CTRL1_REG (DR_REG_SPI1_MEM_BASE + 0xc) +/** SPI1_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ +#define SPI1_MEM_CLK_MODE 0x00000003U +#define SPI1_MEM_CLK_MODE_M (SPI1_MEM_CLK_MODE_V << SPI1_MEM_CLK_MODE_S) +#define SPI1_MEM_CLK_MODE_V 0x00000003U +#define SPI1_MEM_CLK_MODE_S 0 + +/** SPI1_MEM_CTRL2_REG register + * SPI1 control2 register. + */ +#define SPI1_MEM_CTRL2_REG (DR_REG_SPI1_MEM_BASE + 0x10) +/** SPI1_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ +#define SPI1_MEM_SYNC_RESET (BIT(31)) +#define SPI1_MEM_SYNC_RESET_M (SPI1_MEM_SYNC_RESET_V << SPI1_MEM_SYNC_RESET_S) +#define SPI1_MEM_SYNC_RESET_V 0x00000001U +#define SPI1_MEM_SYNC_RESET_S 31 + +/** SPI1_MEM_CLOCK_REG register + * SPI1 clock division control register. + */ +#define SPI1_MEM_CLOCK_REG (DR_REG_SPI1_MEM_BASE + 0x14) +/** SPI1_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ +#define SPI1_MEM_CLKCNT_L 0x000000FFU +#define SPI1_MEM_CLKCNT_L_M (SPI1_MEM_CLKCNT_L_V << SPI1_MEM_CLKCNT_L_S) +#define SPI1_MEM_CLKCNT_L_V 0x000000FFU +#define SPI1_MEM_CLKCNT_L_S 0 +/** SPI1_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI1_MEM_CLKCNT_H 0x000000FFU +#define SPI1_MEM_CLKCNT_H_M (SPI1_MEM_CLKCNT_H_V << SPI1_MEM_CLKCNT_H_S) +#define SPI1_MEM_CLKCNT_H_V 0x000000FFU +#define SPI1_MEM_CLKCNT_H_S 8 +/** SPI1_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ +#define SPI1_MEM_CLKCNT_N 0x000000FFU +#define SPI1_MEM_CLKCNT_N_M (SPI1_MEM_CLKCNT_N_V << SPI1_MEM_CLKCNT_N_S) +#define SPI1_MEM_CLKCNT_N_V 0x000000FFU +#define SPI1_MEM_CLKCNT_N_S 16 +/** SPI1_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * reserved + */ +#define SPI1_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI1_MEM_CLK_EQU_SYSCLK_M (SPI1_MEM_CLK_EQU_SYSCLK_V << SPI1_MEM_CLK_EQU_SYSCLK_S) +#define SPI1_MEM_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI1_MEM_CLK_EQU_SYSCLK_S 31 + +/** SPI1_MEM_USER_REG register + * SPI1 user register. + */ +#define SPI1_MEM_USER_REG (DR_REG_SPI1_MEM_BASE + 0x18) +/** SPI1_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + */ +#define SPI1_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI1_MEM_CK_OUT_EDGE_M (SPI1_MEM_CK_OUT_EDGE_V << SPI1_MEM_CK_OUT_EDGE_S) +#define SPI1_MEM_CK_OUT_EDGE_V 0x00000001U +#define SPI1_MEM_CK_OUT_EDGE_S 9 +/** SPI1_MEM_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ +#define SPI1_MEM_FWRITE_DUAL (BIT(12)) +#define SPI1_MEM_FWRITE_DUAL_M (SPI1_MEM_FWRITE_DUAL_V << SPI1_MEM_FWRITE_DUAL_S) +#define SPI1_MEM_FWRITE_DUAL_V 0x00000001U +#define SPI1_MEM_FWRITE_DUAL_S 12 +/** SPI1_MEM_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ +#define SPI1_MEM_FWRITE_QUAD (BIT(13)) +#define SPI1_MEM_FWRITE_QUAD_M (SPI1_MEM_FWRITE_QUAD_V << SPI1_MEM_FWRITE_QUAD_S) +#define SPI1_MEM_FWRITE_QUAD_V 0x00000001U +#define SPI1_MEM_FWRITE_QUAD_S 13 +/** SPI1_MEM_FWRITE_DIO : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ +#define SPI1_MEM_FWRITE_DIO (BIT(14)) +#define SPI1_MEM_FWRITE_DIO_M (SPI1_MEM_FWRITE_DIO_V << SPI1_MEM_FWRITE_DIO_S) +#define SPI1_MEM_FWRITE_DIO_V 0x00000001U +#define SPI1_MEM_FWRITE_DIO_S 14 +/** SPI1_MEM_FWRITE_QIO : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ +#define SPI1_MEM_FWRITE_QIO (BIT(15)) +#define SPI1_MEM_FWRITE_QIO_M (SPI1_MEM_FWRITE_QIO_V << SPI1_MEM_FWRITE_QIO_S) +#define SPI1_MEM_FWRITE_QIO_V 0x00000001U +#define SPI1_MEM_FWRITE_QIO_S 15 +/** SPI1_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ +#define SPI1_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI1_MEM_USR_DUMMY_IDLE_M (SPI1_MEM_USR_DUMMY_IDLE_V << SPI1_MEM_USR_DUMMY_IDLE_S) +#define SPI1_MEM_USR_DUMMY_IDLE_V 0x00000001U +#define SPI1_MEM_USR_DUMMY_IDLE_S 26 +/** SPI1_MEM_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ +#define SPI1_MEM_USR_MOSI (BIT(27)) +#define SPI1_MEM_USR_MOSI_M (SPI1_MEM_USR_MOSI_V << SPI1_MEM_USR_MOSI_S) +#define SPI1_MEM_USR_MOSI_V 0x00000001U +#define SPI1_MEM_USR_MOSI_S 27 +/** SPI1_MEM_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ +#define SPI1_MEM_USR_MISO (BIT(28)) +#define SPI1_MEM_USR_MISO_M (SPI1_MEM_USR_MISO_V << SPI1_MEM_USR_MISO_S) +#define SPI1_MEM_USR_MISO_V 0x00000001U +#define SPI1_MEM_USR_MISO_S 28 +/** SPI1_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI1_MEM_USR_DUMMY (BIT(29)) +#define SPI1_MEM_USR_DUMMY_M (SPI1_MEM_USR_DUMMY_V << SPI1_MEM_USR_DUMMY_S) +#define SPI1_MEM_USR_DUMMY_V 0x00000001U +#define SPI1_MEM_USR_DUMMY_S 29 +/** SPI1_MEM_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ +#define SPI1_MEM_USR_ADDR (BIT(30)) +#define SPI1_MEM_USR_ADDR_M (SPI1_MEM_USR_ADDR_V << SPI1_MEM_USR_ADDR_S) +#define SPI1_MEM_USR_ADDR_V 0x00000001U +#define SPI1_MEM_USR_ADDR_S 30 +/** SPI1_MEM_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ +#define SPI1_MEM_USR_COMMAND (BIT(31)) +#define SPI1_MEM_USR_COMMAND_M (SPI1_MEM_USR_COMMAND_V << SPI1_MEM_USR_COMMAND_S) +#define SPI1_MEM_USR_COMMAND_V 0x00000001U +#define SPI1_MEM_USR_COMMAND_S 31 + +/** SPI1_MEM_USER1_REG register + * SPI1 user1 register. + */ +#define SPI1_MEM_USER1_REG (DR_REG_SPI1_MEM_BASE + 0x1c) +/** SPI1_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI1_MEM_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI1_MEM_USR_DUMMY_CYCLELEN_M (SPI1_MEM_USR_DUMMY_CYCLELEN_V << SPI1_MEM_USR_DUMMY_CYCLELEN_S) +#define SPI1_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI1_MEM_USR_DUMMY_CYCLELEN_S 0 +/** SPI1_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_USR_ADDR_BITLEN 0x0000003FU +#define SPI1_MEM_USR_ADDR_BITLEN_M (SPI1_MEM_USR_ADDR_BITLEN_V << SPI1_MEM_USR_ADDR_BITLEN_S) +#define SPI1_MEM_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI1_MEM_USR_ADDR_BITLEN_S 26 + +/** SPI1_MEM_USER2_REG register + * SPI1 user2 register. + */ +#define SPI1_MEM_USER2_REG (DR_REG_SPI1_MEM_BASE + 0x20) +/** SPI1_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI1_MEM_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI1_MEM_USR_COMMAND_VALUE_M (SPI1_MEM_USR_COMMAND_VALUE_V << SPI1_MEM_USR_COMMAND_VALUE_S) +#define SPI1_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI1_MEM_USR_COMMAND_VALUE_S 0 +/** SPI1_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI1_MEM_USR_COMMAND_BITLEN 0x0000000FU +#define SPI1_MEM_USR_COMMAND_BITLEN_M (SPI1_MEM_USR_COMMAND_BITLEN_V << SPI1_MEM_USR_COMMAND_BITLEN_S) +#define SPI1_MEM_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI1_MEM_USR_COMMAND_BITLEN_S 28 + +/** SPI1_MEM_MOSI_DLEN_REG register + * SPI1 send data bit length control register. + */ +#define SPI1_MEM_MOSI_DLEN_REG (DR_REG_SPI1_MEM_BASE + 0x24) +/** SPI1_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_USR_MOSI_DBITLEN 0x000003FFU +#define SPI1_MEM_USR_MOSI_DBITLEN_M (SPI1_MEM_USR_MOSI_DBITLEN_V << SPI1_MEM_USR_MOSI_DBITLEN_S) +#define SPI1_MEM_USR_MOSI_DBITLEN_V 0x000003FFU +#define SPI1_MEM_USR_MOSI_DBITLEN_S 0 + +/** SPI1_MEM_MISO_DLEN_REG register + * SPI1 receive data bit length control register. + */ +#define SPI1_MEM_MISO_DLEN_REG (DR_REG_SPI1_MEM_BASE + 0x28) +/** SPI1_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ +#define SPI1_MEM_USR_MISO_DBITLEN 0x000003FFU +#define SPI1_MEM_USR_MISO_DBITLEN_M (SPI1_MEM_USR_MISO_DBITLEN_V << SPI1_MEM_USR_MISO_DBITLEN_S) +#define SPI1_MEM_USR_MISO_DBITLEN_V 0x000003FFU +#define SPI1_MEM_USR_MISO_DBITLEN_S 0 + +/** SPI1_MEM_RD_STATUS_REG register + * SPI1 status register. + */ +#define SPI1_MEM_RD_STATUS_REG (DR_REG_SPI1_MEM_BASE + 0x2c) +/** SPI1_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + */ +#define SPI1_MEM_STATUS 0x0000FFFFU +#define SPI1_MEM_STATUS_M (SPI1_MEM_STATUS_V << SPI1_MEM_STATUS_S) +#define SPI1_MEM_STATUS_V 0x0000FFFFU +#define SPI1_MEM_STATUS_S 0 + +/** SPI1_MEM_MISC_REG register + * SPI1 misc register + */ +#define SPI1_MEM_MISC_REG (DR_REG_SPI1_MEM_BASE + 0x34) +/** SPI1_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI1_MEM_CS0_DIS (BIT(0)) +#define SPI1_MEM_CS0_DIS_M (SPI1_MEM_CS0_DIS_V << SPI1_MEM_CS0_DIS_S) +#define SPI1_MEM_CS0_DIS_V 0x00000001U +#define SPI1_MEM_CS0_DIS_S 0 +/** SPI1_MEM_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ +#define SPI1_MEM_CS1_DIS (BIT(1)) +#define SPI1_MEM_CS1_DIS_M (SPI1_MEM_CS1_DIS_V << SPI1_MEM_CS1_DIS_S) +#define SPI1_MEM_CS1_DIS_V 0x00000001U +#define SPI1_MEM_CS1_DIS_S 1 +/** SPI1_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ +#define SPI1_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI1_MEM_CK_IDLE_EDGE_M (SPI1_MEM_CK_IDLE_EDGE_V << SPI1_MEM_CK_IDLE_EDGE_S) +#define SPI1_MEM_CK_IDLE_EDGE_V 0x00000001U +#define SPI1_MEM_CK_IDLE_EDGE_S 9 +/** SPI1_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ +#define SPI1_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI1_MEM_CS_KEEP_ACTIVE_M (SPI1_MEM_CS_KEEP_ACTIVE_V << SPI1_MEM_CS_KEEP_ACTIVE_S) +#define SPI1_MEM_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI1_MEM_CS_KEEP_ACTIVE_S 10 + +/** SPI1_MEM_W0_REG register + * SPI1 memory data buffer0 + */ +#define SPI1_MEM_W0_REG (DR_REG_SPI1_MEM_BASE + 0x58) +/** SPI1_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF0 0xFFFFFFFFU +#define SPI1_MEM_BUF0_M (SPI1_MEM_BUF0_V << SPI1_MEM_BUF0_S) +#define SPI1_MEM_BUF0_V 0xFFFFFFFFU +#define SPI1_MEM_BUF0_S 0 + +/** SPI1_MEM_W1_REG register + * SPI1 memory data buffer1 + */ +#define SPI1_MEM_W1_REG (DR_REG_SPI1_MEM_BASE + 0x5c) +/** SPI1_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF1 0xFFFFFFFFU +#define SPI1_MEM_BUF1_M (SPI1_MEM_BUF1_V << SPI1_MEM_BUF1_S) +#define SPI1_MEM_BUF1_V 0xFFFFFFFFU +#define SPI1_MEM_BUF1_S 0 + +/** SPI1_MEM_W2_REG register + * SPI1 memory data buffer2 + */ +#define SPI1_MEM_W2_REG (DR_REG_SPI1_MEM_BASE + 0x60) +/** SPI1_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF2 0xFFFFFFFFU +#define SPI1_MEM_BUF2_M (SPI1_MEM_BUF2_V << SPI1_MEM_BUF2_S) +#define SPI1_MEM_BUF2_V 0xFFFFFFFFU +#define SPI1_MEM_BUF2_S 0 + +/** SPI1_MEM_W3_REG register + * SPI1 memory data buffer3 + */ +#define SPI1_MEM_W3_REG (DR_REG_SPI1_MEM_BASE + 0x64) +/** SPI1_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF3 0xFFFFFFFFU +#define SPI1_MEM_BUF3_M (SPI1_MEM_BUF3_V << SPI1_MEM_BUF3_S) +#define SPI1_MEM_BUF3_V 0xFFFFFFFFU +#define SPI1_MEM_BUF3_S 0 + +/** SPI1_MEM_W4_REG register + * SPI1 memory data buffer4 + */ +#define SPI1_MEM_W4_REG (DR_REG_SPI1_MEM_BASE + 0x68) +/** SPI1_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF4 0xFFFFFFFFU +#define SPI1_MEM_BUF4_M (SPI1_MEM_BUF4_V << SPI1_MEM_BUF4_S) +#define SPI1_MEM_BUF4_V 0xFFFFFFFFU +#define SPI1_MEM_BUF4_S 0 + +/** SPI1_MEM_W5_REG register + * SPI1 memory data buffer5 + */ +#define SPI1_MEM_W5_REG (DR_REG_SPI1_MEM_BASE + 0x6c) +/** SPI1_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF5 0xFFFFFFFFU +#define SPI1_MEM_BUF5_M (SPI1_MEM_BUF5_V << SPI1_MEM_BUF5_S) +#define SPI1_MEM_BUF5_V 0xFFFFFFFFU +#define SPI1_MEM_BUF5_S 0 + +/** SPI1_MEM_W6_REG register + * SPI1 memory data buffer6 + */ +#define SPI1_MEM_W6_REG (DR_REG_SPI1_MEM_BASE + 0x70) +/** SPI1_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF6 0xFFFFFFFFU +#define SPI1_MEM_BUF6_M (SPI1_MEM_BUF6_V << SPI1_MEM_BUF6_S) +#define SPI1_MEM_BUF6_V 0xFFFFFFFFU +#define SPI1_MEM_BUF6_S 0 + +/** SPI1_MEM_W7_REG register + * SPI1 memory data buffer7 + */ +#define SPI1_MEM_W7_REG (DR_REG_SPI1_MEM_BASE + 0x74) +/** SPI1_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF7 0xFFFFFFFFU +#define SPI1_MEM_BUF7_M (SPI1_MEM_BUF7_V << SPI1_MEM_BUF7_S) +#define SPI1_MEM_BUF7_V 0xFFFFFFFFU +#define SPI1_MEM_BUF7_S 0 + +/** SPI1_MEM_W8_REG register + * SPI1 memory data buffer8 + */ +#define SPI1_MEM_W8_REG (DR_REG_SPI1_MEM_BASE + 0x78) +/** SPI1_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF8 0xFFFFFFFFU +#define SPI1_MEM_BUF8_M (SPI1_MEM_BUF8_V << SPI1_MEM_BUF8_S) +#define SPI1_MEM_BUF8_V 0xFFFFFFFFU +#define SPI1_MEM_BUF8_S 0 + +/** SPI1_MEM_W9_REG register + * SPI1 memory data buffer9 + */ +#define SPI1_MEM_W9_REG (DR_REG_SPI1_MEM_BASE + 0x7c) +/** SPI1_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF9 0xFFFFFFFFU +#define SPI1_MEM_BUF9_M (SPI1_MEM_BUF9_V << SPI1_MEM_BUF9_S) +#define SPI1_MEM_BUF9_V 0xFFFFFFFFU +#define SPI1_MEM_BUF9_S 0 + +/** SPI1_MEM_W10_REG register + * SPI1 memory data buffer10 + */ +#define SPI1_MEM_W10_REG (DR_REG_SPI1_MEM_BASE + 0x80) +/** SPI1_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF10 0xFFFFFFFFU +#define SPI1_MEM_BUF10_M (SPI1_MEM_BUF10_V << SPI1_MEM_BUF10_S) +#define SPI1_MEM_BUF10_V 0xFFFFFFFFU +#define SPI1_MEM_BUF10_S 0 + +/** SPI1_MEM_W11_REG register + * SPI1 memory data buffer11 + */ +#define SPI1_MEM_W11_REG (DR_REG_SPI1_MEM_BASE + 0x84) +/** SPI1_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF11 0xFFFFFFFFU +#define SPI1_MEM_BUF11_M (SPI1_MEM_BUF11_V << SPI1_MEM_BUF11_S) +#define SPI1_MEM_BUF11_V 0xFFFFFFFFU +#define SPI1_MEM_BUF11_S 0 + +/** SPI1_MEM_W12_REG register + * SPI1 memory data buffer12 + */ +#define SPI1_MEM_W12_REG (DR_REG_SPI1_MEM_BASE + 0x88) +/** SPI1_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF12 0xFFFFFFFFU +#define SPI1_MEM_BUF12_M (SPI1_MEM_BUF12_V << SPI1_MEM_BUF12_S) +#define SPI1_MEM_BUF12_V 0xFFFFFFFFU +#define SPI1_MEM_BUF12_S 0 + +/** SPI1_MEM_W13_REG register + * SPI1 memory data buffer13 + */ +#define SPI1_MEM_W13_REG (DR_REG_SPI1_MEM_BASE + 0x8c) +/** SPI1_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF13 0xFFFFFFFFU +#define SPI1_MEM_BUF13_M (SPI1_MEM_BUF13_V << SPI1_MEM_BUF13_S) +#define SPI1_MEM_BUF13_V 0xFFFFFFFFU +#define SPI1_MEM_BUF13_S 0 + +/** SPI1_MEM_W14_REG register + * SPI1 memory data buffer14 + */ +#define SPI1_MEM_W14_REG (DR_REG_SPI1_MEM_BASE + 0x90) +/** SPI1_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF14 0xFFFFFFFFU +#define SPI1_MEM_BUF14_M (SPI1_MEM_BUF14_V << SPI1_MEM_BUF14_S) +#define SPI1_MEM_BUF14_V 0xFFFFFFFFU +#define SPI1_MEM_BUF14_S 0 + +/** SPI1_MEM_W15_REG register + * SPI1 memory data buffer15 + */ +#define SPI1_MEM_W15_REG (DR_REG_SPI1_MEM_BASE + 0x94) +/** SPI1_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ +#define SPI1_MEM_BUF15 0xFFFFFFFFU +#define SPI1_MEM_BUF15_M (SPI1_MEM_BUF15_V << SPI1_MEM_BUF15_S) +#define SPI1_MEM_BUF15_V 0xFFFFFFFFU +#define SPI1_MEM_BUF15_S 0 + +/** SPI1_MEM_FLASH_WAITI_CTRL_REG register + * SPI1 wait idle control register + */ +#define SPI1_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPI1_MEM_BASE + 0x98) +/** SPI1_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ +#define SPI1_MEM_WAITI_EN (BIT(0)) +#define SPI1_MEM_WAITI_EN_M (SPI1_MEM_WAITI_EN_V << SPI1_MEM_WAITI_EN_S) +#define SPI1_MEM_WAITI_EN_V 0x00000001U +#define SPI1_MEM_WAITI_EN_S 0 +/** SPI1_MEM_WAITI_DUMMY : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ +#define SPI1_MEM_WAITI_DUMMY (BIT(1)) +#define SPI1_MEM_WAITI_DUMMY_M (SPI1_MEM_WAITI_DUMMY_V << SPI1_MEM_WAITI_DUMMY_S) +#define SPI1_MEM_WAITI_DUMMY_V 0x00000001U +#define SPI1_MEM_WAITI_DUMMY_S 1 +/** SPI1_MEM_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ +#define SPI1_MEM_WAITI_ADDR_EN (BIT(2)) +#define SPI1_MEM_WAITI_ADDR_EN_M (SPI1_MEM_WAITI_ADDR_EN_V << SPI1_MEM_WAITI_ADDR_EN_S) +#define SPI1_MEM_WAITI_ADDR_EN_V 0x00000001U +#define SPI1_MEM_WAITI_ADDR_EN_S 2 +/** SPI1_MEM_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0; + * When SPI1_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI1_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_WAITI_ADDR_EN is cleared. + */ +#define SPI1_MEM_WAITI_ADDR_CYCLELEN 0x00000003U +#define SPI1_MEM_WAITI_ADDR_CYCLELEN_M (SPI1_MEM_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_WAITI_ADDR_CYCLELEN_S) +#define SPI1_MEM_WAITI_ADDR_CYCLELEN_V 0x00000003U +#define SPI1_MEM_WAITI_ADDR_CYCLELEN_S 3 +/** SPI1_MEM_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ +#define SPI1_MEM_WAITI_CMD_2B (BIT(9)) +#define SPI1_MEM_WAITI_CMD_2B_M (SPI1_MEM_WAITI_CMD_2B_V << SPI1_MEM_WAITI_CMD_2B_S) +#define SPI1_MEM_WAITI_CMD_2B_V 0x00000001U +#define SPI1_MEM_WAITI_CMD_2B_S 9 +/** SPI1_MEM_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ +#define SPI1_MEM_WAITI_DUMMY_CYCLELEN 0x0000003FU +#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_M (SPI1_MEM_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_WAITI_DUMMY_CYCLELEN_S) +#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_S 10 +/** SPI1_MEM_WAITI_CMD : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ +#define SPI1_MEM_WAITI_CMD 0x0000FFFFU +#define SPI1_MEM_WAITI_CMD_M (SPI1_MEM_WAITI_CMD_V << SPI1_MEM_WAITI_CMD_S) +#define SPI1_MEM_WAITI_CMD_V 0x0000FFFFU +#define SPI1_MEM_WAITI_CMD_S 16 + +/** SPI1_MEM_FLASH_SUS_CTRL_REG register + * SPI1 flash suspend control register + */ +#define SPI1_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPI1_MEM_BASE + 0x9c) +/** SPI1_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI1_MEM_FLASH_PER (BIT(0)) +#define SPI1_MEM_FLASH_PER_M (SPI1_MEM_FLASH_PER_V << SPI1_MEM_FLASH_PER_S) +#define SPI1_MEM_FLASH_PER_V 0x00000001U +#define SPI1_MEM_FLASH_PER_S 0 +/** SPI1_MEM_FLASH_PES : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ +#define SPI1_MEM_FLASH_PES (BIT(1)) +#define SPI1_MEM_FLASH_PES_M (SPI1_MEM_FLASH_PES_V << SPI1_MEM_FLASH_PES_S) +#define SPI1_MEM_FLASH_PES_V 0x00000001U +#define SPI1_MEM_FLASH_PES_S 1 +/** SPI1_MEM_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ +#define SPI1_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI1_MEM_FLASH_PER_WAIT_EN_M (SPI1_MEM_FLASH_PER_WAIT_EN_V << SPI1_MEM_FLASH_PER_WAIT_EN_S) +#define SPI1_MEM_FLASH_PER_WAIT_EN_V 0x00000001U +#define SPI1_MEM_FLASH_PER_WAIT_EN_S 2 +/** SPI1_MEM_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ +#define SPI1_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI1_MEM_FLASH_PES_WAIT_EN_M (SPI1_MEM_FLASH_PES_WAIT_EN_V << SPI1_MEM_FLASH_PES_WAIT_EN_S) +#define SPI1_MEM_FLASH_PES_WAIT_EN_V 0x00000001U +#define SPI1_MEM_FLASH_PES_WAIT_EN_S 3 +/** SPI1_MEM_PES_PER_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ +#define SPI1_MEM_PES_PER_EN (BIT(4)) +#define SPI1_MEM_PES_PER_EN_M (SPI1_MEM_PES_PER_EN_V << SPI1_MEM_PES_PER_EN_S) +#define SPI1_MEM_PES_PER_EN_V 0x00000001U +#define SPI1_MEM_PES_PER_EN_S 4 +/** SPI1_MEM_FLASH_PES_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ +#define SPI1_MEM_FLASH_PES_EN (BIT(5)) +#define SPI1_MEM_FLASH_PES_EN_M (SPI1_MEM_FLASH_PES_EN_V << SPI1_MEM_FLASH_PES_EN_S) +#define SPI1_MEM_FLASH_PES_EN_V 0x00000001U +#define SPI1_MEM_FLASH_PES_EN_S 5 +/** SPI1_MEM_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI1_MEM_PESR_END_MSK[15:0]. + */ +#define SPI1_MEM_PESR_END_MSK 0x0000FFFFU +#define SPI1_MEM_PESR_END_MSK_M (SPI1_MEM_PESR_END_MSK_V << SPI1_MEM_PESR_END_MSK_S) +#define SPI1_MEM_PESR_END_MSK_V 0x0000FFFFU +#define SPI1_MEM_PESR_END_MSK_S 6 +/** SPI1_MEM_F_RD_SUS_2B : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ +#define SPI1_MEM_F_RD_SUS_2B (BIT(22)) +#define SPI1_MEM_F_RD_SUS_2B_M (SPI1_MEM_F_RD_SUS_2B_V << SPI1_MEM_F_RD_SUS_2B_S) +#define SPI1_MEM_F_RD_SUS_2B_V 0x00000001U +#define SPI1_MEM_F_RD_SUS_2B_S 22 +/** SPI1_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ +#define SPI1_MEM_PER_END_EN (BIT(23)) +#define SPI1_MEM_PER_END_EN_M (SPI1_MEM_PER_END_EN_V << SPI1_MEM_PER_END_EN_S) +#define SPI1_MEM_PER_END_EN_V 0x00000001U +#define SPI1_MEM_PER_END_EN_S 23 +/** SPI1_MEM_PES_END_EN : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ +#define SPI1_MEM_PES_END_EN (BIT(24)) +#define SPI1_MEM_PES_END_EN_M (SPI1_MEM_PES_END_EN_V << SPI1_MEM_PES_END_EN_S) +#define SPI1_MEM_PES_END_EN_V 0x00000001U +#define SPI1_MEM_PES_END_EN_S 24 +/** SPI1_MEM_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. + */ +#define SPI1_MEM_SUS_TIMEOUT_CNT 0x0000007FU +#define SPI1_MEM_SUS_TIMEOUT_CNT_M (SPI1_MEM_SUS_TIMEOUT_CNT_V << SPI1_MEM_SUS_TIMEOUT_CNT_S) +#define SPI1_MEM_SUS_TIMEOUT_CNT_V 0x0000007FU +#define SPI1_MEM_SUS_TIMEOUT_CNT_S 25 + +/** SPI1_MEM_FLASH_SUS_CMD_REG register + * SPI1 flash suspend command register + */ +#define SPI1_MEM_FLASH_SUS_CMD_REG (DR_REG_SPI1_MEM_BASE + 0xa0) +/** SPI1_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ +#define SPI1_MEM_FLASH_PES_COMMAND 0x0000FFFFU +#define SPI1_MEM_FLASH_PES_COMMAND_M (SPI1_MEM_FLASH_PES_COMMAND_V << SPI1_MEM_FLASH_PES_COMMAND_S) +#define SPI1_MEM_FLASH_PES_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_FLASH_PES_COMMAND_S 0 +/** SPI1_MEM_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ +#define SPI1_MEM_WAIT_PESR_COMMAND 0x0000FFFFU +#define SPI1_MEM_WAIT_PESR_COMMAND_M (SPI1_MEM_WAIT_PESR_COMMAND_V << SPI1_MEM_WAIT_PESR_COMMAND_S) +#define SPI1_MEM_WAIT_PESR_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_WAIT_PESR_COMMAND_S 16 + +/** SPI1_MEM_SUS_STATUS_REG register + * SPI1 flash suspend status register + */ +#define SPI1_MEM_SUS_STATUS_REG (DR_REG_SPI1_MEM_BASE + 0xa4) +/** SPI1_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ +#define SPI1_MEM_FLASH_SUS (BIT(0)) +#define SPI1_MEM_FLASH_SUS_M (SPI1_MEM_FLASH_SUS_V << SPI1_MEM_FLASH_SUS_S) +#define SPI1_MEM_FLASH_SUS_V 0x00000001U +#define SPI1_MEM_FLASH_SUS_S 0 +/** SPI1_MEM_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ +#define SPI1_MEM_WAIT_PESR_CMD_2B (BIT(1)) +#define SPI1_MEM_WAIT_PESR_CMD_2B_M (SPI1_MEM_WAIT_PESR_CMD_2B_V << SPI1_MEM_WAIT_PESR_CMD_2B_S) +#define SPI1_MEM_WAIT_PESR_CMD_2B_V 0x00000001U +#define SPI1_MEM_WAIT_PESR_CMD_2B_S 1 +/** SPI1_MEM_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ +#define SPI1_MEM_FLASH_HPM_DLY_128 (BIT(2)) +#define SPI1_MEM_FLASH_HPM_DLY_128_M (SPI1_MEM_FLASH_HPM_DLY_128_V << SPI1_MEM_FLASH_HPM_DLY_128_S) +#define SPI1_MEM_FLASH_HPM_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_HPM_DLY_128_S 2 +/** SPI1_MEM_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ +#define SPI1_MEM_FLASH_RES_DLY_128 (BIT(3)) +#define SPI1_MEM_FLASH_RES_DLY_128_M (SPI1_MEM_FLASH_RES_DLY_128_V << SPI1_MEM_FLASH_RES_DLY_128_S) +#define SPI1_MEM_FLASH_RES_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_RES_DLY_128_S 3 +/** SPI1_MEM_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ +#define SPI1_MEM_FLASH_DP_DLY_128 (BIT(4)) +#define SPI1_MEM_FLASH_DP_DLY_128_M (SPI1_MEM_FLASH_DP_DLY_128_V << SPI1_MEM_FLASH_DP_DLY_128_S) +#define SPI1_MEM_FLASH_DP_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_DP_DLY_128_S 4 +/** SPI1_MEM_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI1_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. + */ +#define SPI1_MEM_FLASH_PER_DLY_128 (BIT(5)) +#define SPI1_MEM_FLASH_PER_DLY_128_M (SPI1_MEM_FLASH_PER_DLY_128_V << SPI1_MEM_FLASH_PER_DLY_128_S) +#define SPI1_MEM_FLASH_PER_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_PER_DLY_128_S 5 +/** SPI1_MEM_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI1_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. + */ +#define SPI1_MEM_FLASH_PES_DLY_128 (BIT(6)) +#define SPI1_MEM_FLASH_PES_DLY_128_M (SPI1_MEM_FLASH_PES_DLY_128_V << SPI1_MEM_FLASH_PES_DLY_128_S) +#define SPI1_MEM_FLASH_PES_DLY_128_V 0x00000001U +#define SPI1_MEM_FLASH_PES_DLY_128_S 6 +/** SPI1_MEM_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ +#define SPI1_MEM_SPI0_LOCK_EN (BIT(7)) +#define SPI1_MEM_SPI0_LOCK_EN_M (SPI1_MEM_SPI0_LOCK_EN_V << SPI1_MEM_SPI0_LOCK_EN_S) +#define SPI1_MEM_SPI0_LOCK_EN_V 0x00000001U +#define SPI1_MEM_SPI0_LOCK_EN_S 7 +/** SPI1_MEM_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ +#define SPI1_MEM_FLASH_PESR_CMD_2B (BIT(15)) +#define SPI1_MEM_FLASH_PESR_CMD_2B_M (SPI1_MEM_FLASH_PESR_CMD_2B_V << SPI1_MEM_FLASH_PESR_CMD_2B_S) +#define SPI1_MEM_FLASH_PESR_CMD_2B_V 0x00000001U +#define SPI1_MEM_FLASH_PESR_CMD_2B_S 15 +/** SPI1_MEM_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ +#define SPI1_MEM_FLASH_PER_COMMAND 0x0000FFFFU +#define SPI1_MEM_FLASH_PER_COMMAND_M (SPI1_MEM_FLASH_PER_COMMAND_V << SPI1_MEM_FLASH_PER_COMMAND_S) +#define SPI1_MEM_FLASH_PER_COMMAND_V 0x0000FFFFU +#define SPI1_MEM_FLASH_PER_COMMAND_S 16 + +/** SPI1_MEM_INT_ENA_REG register + * SPI1 interrupt enable register + */ +#define SPI1_MEM_INT_ENA_REG (DR_REG_SPI1_MEM_BASE + 0xc0) +/** SPI1_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI1_MEM_PER_END_INT interrupt. + */ +#define SPI1_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI1_MEM_PER_END_INT_ENA_M (SPI1_MEM_PER_END_INT_ENA_V << SPI1_MEM_PER_END_INT_ENA_S) +#define SPI1_MEM_PER_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_PER_END_INT_ENA_S 0 +/** SPI1_MEM_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI1_MEM_PES_END_INT interrupt. + */ +#define SPI1_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI1_MEM_PES_END_INT_ENA_M (SPI1_MEM_PES_END_INT_ENA_V << SPI1_MEM_PES_END_INT_ENA_S) +#define SPI1_MEM_PES_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_PES_END_INT_ENA_S 1 +/** SPI1_MEM_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI1_MEM_WPE_END_INT interrupt. + */ +#define SPI1_MEM_WPE_END_INT_ENA (BIT(2)) +#define SPI1_MEM_WPE_END_INT_ENA_M (SPI1_MEM_WPE_END_INT_ENA_V << SPI1_MEM_WPE_END_INT_ENA_S) +#define SPI1_MEM_WPE_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_WPE_END_INT_ENA_S 2 +/** SPI1_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI1_MEM_SLV_ST_END_INT_ENA_M (SPI1_MEM_SLV_ST_END_INT_ENA_V << SPI1_MEM_SLV_ST_END_INT_ENA_S) +#define SPI1_MEM_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_SLV_ST_END_INT_ENA_S 3 +/** SPI1_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI1_MEM_MST_ST_END_INT_ENA_M (SPI1_MEM_MST_ST_END_INT_ENA_V << SPI1_MEM_MST_ST_END_INT_ENA_S) +#define SPI1_MEM_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI1_MEM_MST_ST_END_INT_ENA_S 4 +/** SPI1_MEM_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_BROWN_OUT_INT_ENA (BIT(10)) +#define SPI1_MEM_BROWN_OUT_INT_ENA_M (SPI1_MEM_BROWN_OUT_INT_ENA_V << SPI1_MEM_BROWN_OUT_INT_ENA_S) +#define SPI1_MEM_BROWN_OUT_INT_ENA_V 0x00000001U +#define SPI1_MEM_BROWN_OUT_INT_ENA_S 10 + +/** SPI1_MEM_INT_CLR_REG register + * SPI1 interrupt clear register + */ +#define SPI1_MEM_INT_CLR_REG (DR_REG_SPI1_MEM_BASE + 0xc4) +/** SPI1_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI1_MEM_PER_END_INT interrupt. + */ +#define SPI1_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI1_MEM_PER_END_INT_CLR_M (SPI1_MEM_PER_END_INT_CLR_V << SPI1_MEM_PER_END_INT_CLR_S) +#define SPI1_MEM_PER_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_PER_END_INT_CLR_S 0 +/** SPI1_MEM_PES_END_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI1_MEM_PES_END_INT interrupt. + */ +#define SPI1_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI1_MEM_PES_END_INT_CLR_M (SPI1_MEM_PES_END_INT_CLR_V << SPI1_MEM_PES_END_INT_CLR_S) +#define SPI1_MEM_PES_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_PES_END_INT_CLR_S 1 +/** SPI1_MEM_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI1_MEM_WPE_END_INT interrupt. + */ +#define SPI1_MEM_WPE_END_INT_CLR (BIT(2)) +#define SPI1_MEM_WPE_END_INT_CLR_M (SPI1_MEM_WPE_END_INT_CLR_V << SPI1_MEM_WPE_END_INT_CLR_S) +#define SPI1_MEM_WPE_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_WPE_END_INT_CLR_S 2 +/** SPI1_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI1_MEM_SLV_ST_END_INT_CLR_M (SPI1_MEM_SLV_ST_END_INT_CLR_V << SPI1_MEM_SLV_ST_END_INT_CLR_S) +#define SPI1_MEM_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_SLV_ST_END_INT_CLR_S 3 +/** SPI1_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI1_MEM_MST_ST_END_INT_CLR_M (SPI1_MEM_MST_ST_END_INT_CLR_V << SPI1_MEM_MST_ST_END_INT_CLR_S) +#define SPI1_MEM_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI1_MEM_MST_ST_END_INT_CLR_S 4 +/** SPI1_MEM_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_BROWN_OUT_INT_CLR (BIT(10)) +#define SPI1_MEM_BROWN_OUT_INT_CLR_M (SPI1_MEM_BROWN_OUT_INT_CLR_V << SPI1_MEM_BROWN_OUT_INT_CLR_S) +#define SPI1_MEM_BROWN_OUT_INT_CLR_V 0x00000001U +#define SPI1_MEM_BROWN_OUT_INT_CLR_S 10 + +/** SPI1_MEM_INT_RAW_REG register + * SPI1 interrupt raw register + */ +#define SPI1_MEM_INT_RAW_REG (DR_REG_SPI1_MEM_BASE + 0xc8) +/** SPI1_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI1_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ +#define SPI1_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI1_MEM_PER_END_INT_RAW_M (SPI1_MEM_PER_END_INT_RAW_V << SPI1_MEM_PER_END_INT_RAW_S) +#define SPI1_MEM_PER_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_PER_END_INT_RAW_S 0 +/** SPI1_MEM_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI1_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ +#define SPI1_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI1_MEM_PES_END_INT_RAW_M (SPI1_MEM_PES_END_INT_RAW_V << SPI1_MEM_PES_END_INT_RAW_S) +#define SPI1_MEM_PES_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_PES_END_INT_RAW_S 1 +/** SPI1_MEM_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI1_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ +#define SPI1_MEM_WPE_END_INT_RAW (BIT(2)) +#define SPI1_MEM_WPE_END_INT_RAW_M (SPI1_MEM_WPE_END_INT_RAW_V << SPI1_MEM_WPE_END_INT_RAW_S) +#define SPI1_MEM_WPE_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_WPE_END_INT_RAW_S 2 +/** SPI1_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI1_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI1_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI1_MEM_SLV_ST_END_INT_RAW_M (SPI1_MEM_SLV_ST_END_INT_RAW_V << SPI1_MEM_SLV_ST_END_INT_RAW_S) +#define SPI1_MEM_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_SLV_ST_END_INT_RAW_S 3 +/** SPI1_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI1_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI1_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI1_MEM_MST_ST_END_INT_RAW_M (SPI1_MEM_MST_ST_END_INT_RAW_V << SPI1_MEM_MST_ST_END_INT_RAW_S) +#define SPI1_MEM_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI1_MEM_MST_ST_END_INT_RAW_S 4 +/** SPI1_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI1_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is loosing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ +#define SPI1_MEM_BROWN_OUT_INT_RAW (BIT(10)) +#define SPI1_MEM_BROWN_OUT_INT_RAW_M (SPI1_MEM_BROWN_OUT_INT_RAW_V << SPI1_MEM_BROWN_OUT_INT_RAW_S) +#define SPI1_MEM_BROWN_OUT_INT_RAW_V 0x00000001U +#define SPI1_MEM_BROWN_OUT_INT_RAW_S 10 + +/** SPI1_MEM_INT_ST_REG register + * SPI1 interrupt status register + */ +#define SPI1_MEM_INT_ST_REG (DR_REG_SPI1_MEM_BASE + 0xcc) +/** SPI1_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI1_MEM_PER_END_INT interrupt. + */ +#define SPI1_MEM_PER_END_INT_ST (BIT(0)) +#define SPI1_MEM_PER_END_INT_ST_M (SPI1_MEM_PER_END_INT_ST_V << SPI1_MEM_PER_END_INT_ST_S) +#define SPI1_MEM_PER_END_INT_ST_V 0x00000001U +#define SPI1_MEM_PER_END_INT_ST_S 0 +/** SPI1_MEM_PES_END_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI1_MEM_PES_END_INT interrupt. + */ +#define SPI1_MEM_PES_END_INT_ST (BIT(1)) +#define SPI1_MEM_PES_END_INT_ST_M (SPI1_MEM_PES_END_INT_ST_V << SPI1_MEM_PES_END_INT_ST_S) +#define SPI1_MEM_PES_END_INT_ST_V 0x00000001U +#define SPI1_MEM_PES_END_INT_ST_S 1 +/** SPI1_MEM_WPE_END_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI1_MEM_WPE_END_INT interrupt. + */ +#define SPI1_MEM_WPE_END_INT_ST (BIT(2)) +#define SPI1_MEM_WPE_END_INT_ST_M (SPI1_MEM_WPE_END_INT_ST_V << SPI1_MEM_WPE_END_INT_ST_S) +#define SPI1_MEM_WPE_END_INT_ST_V 0x00000001U +#define SPI1_MEM_WPE_END_INT_ST_S 2 +/** SPI1_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI1_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI1_MEM_SLV_ST_END_INT_ST_M (SPI1_MEM_SLV_ST_END_INT_ST_V << SPI1_MEM_SLV_ST_END_INT_ST_S) +#define SPI1_MEM_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI1_MEM_SLV_ST_END_INT_ST_S 3 +/** SPI1_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ +#define SPI1_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI1_MEM_MST_ST_END_INT_ST_M (SPI1_MEM_MST_ST_END_INT_ST_V << SPI1_MEM_MST_ST_END_INT_ST_S) +#define SPI1_MEM_MST_ST_END_INT_ST_V 0x00000001U +#define SPI1_MEM_MST_ST_END_INT_ST_S 4 +/** SPI1_MEM_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ +#define SPI1_MEM_BROWN_OUT_INT_ST (BIT(10)) +#define SPI1_MEM_BROWN_OUT_INT_ST_M (SPI1_MEM_BROWN_OUT_INT_ST_V << SPI1_MEM_BROWN_OUT_INT_ST_S) +#define SPI1_MEM_BROWN_OUT_INT_ST_V 0x00000001U +#define SPI1_MEM_BROWN_OUT_INT_ST_S 10 + +/** SPI1_MEM_DDR_REG register + * SPI1 DDR control register + */ +#define SPI1_MEM_DDR_REG (DR_REG_SPI1_MEM_BASE + 0xd4) +/** SPI1_MEM_F_DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ +#define SPI1_MEM_F_DDR_EN (BIT(0)) +#define SPI1_MEM_F_DDR_EN_M (SPI1_MEM_F_DDR_EN_V << SPI1_MEM_F_DDR_EN_S) +#define SPI1_MEM_F_DDR_EN_V 0x00000001U +#define SPI1_MEM_F_DDR_EN_S 0 +/** SPI1_MEM_F_VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ +#define SPI1_MEM_F_VAR_DUMMY (BIT(1)) +#define SPI1_MEM_F_VAR_DUMMY_M (SPI1_MEM_F_VAR_DUMMY_V << SPI1_MEM_F_VAR_DUMMY_S) +#define SPI1_MEM_F_VAR_DUMMY_V 0x00000001U +#define SPI1_MEM_F_VAR_DUMMY_S 1 +/** SPI1_MEM_F_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ +#define SPI1_MEM_F_DDR_RDAT_SWP (BIT(2)) +#define SPI1_MEM_F_DDR_RDAT_SWP_M (SPI1_MEM_F_DDR_RDAT_SWP_V << SPI1_MEM_F_DDR_RDAT_SWP_S) +#define SPI1_MEM_F_DDR_RDAT_SWP_V 0x00000001U +#define SPI1_MEM_F_DDR_RDAT_SWP_S 2 +/** SPI1_MEM_F_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ +#define SPI1_MEM_F_DDR_WDAT_SWP (BIT(3)) +#define SPI1_MEM_F_DDR_WDAT_SWP_M (SPI1_MEM_F_DDR_WDAT_SWP_V << SPI1_MEM_F_DDR_WDAT_SWP_S) +#define SPI1_MEM_F_DDR_WDAT_SWP_V 0x00000001U +#define SPI1_MEM_F_DDR_WDAT_SWP_S 3 +/** SPI1_MEM_F_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ +#define SPI1_MEM_F_DDR_CMD_DIS (BIT(4)) +#define SPI1_MEM_F_DDR_CMD_DIS_M (SPI1_MEM_F_DDR_CMD_DIS_V << SPI1_MEM_F_DDR_CMD_DIS_S) +#define SPI1_MEM_F_DDR_CMD_DIS_V 0x00000001U +#define SPI1_MEM_F_DDR_CMD_DIS_S 4 +/** SPI1_MEM_F_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI1_MEM_F_OUTMINBYTELEN 0x0000007FU +#define SPI1_MEM_F_OUTMINBYTELEN_M (SPI1_MEM_F_OUTMINBYTELEN_V << SPI1_MEM_F_OUTMINBYTELEN_S) +#define SPI1_MEM_F_OUTMINBYTELEN_V 0x0000007FU +#define SPI1_MEM_F_OUTMINBYTELEN_S 5 +/** SPI1_MEM_F_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI1_MEM_F_USR_DDR_DQS_THD 0x0000007FU +#define SPI1_MEM_F_USR_DDR_DQS_THD_M (SPI1_MEM_F_USR_DDR_DQS_THD_V << SPI1_MEM_F_USR_DDR_DQS_THD_S) +#define SPI1_MEM_F_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI1_MEM_F_USR_DDR_DQS_THD_S 14 +/** SPI1_MEM_F_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI1_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI1_MEM_F_DDR_DQS_LOOP (BIT(21)) +#define SPI1_MEM_F_DDR_DQS_LOOP_M (SPI1_MEM_F_DDR_DQS_LOOP_V << SPI1_MEM_F_DDR_DQS_LOOP_S) +#define SPI1_MEM_F_DDR_DQS_LOOP_V 0x00000001U +#define SPI1_MEM_F_DDR_DQS_LOOP_S 21 +/** SPI1_MEM_F_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI1_MEM_F_CLK_DIFF_EN (BIT(24)) +#define SPI1_MEM_F_CLK_DIFF_EN_M (SPI1_MEM_F_CLK_DIFF_EN_V << SPI1_MEM_F_CLK_DIFF_EN_S) +#define SPI1_MEM_F_CLK_DIFF_EN_V 0x00000001U +#define SPI1_MEM_F_CLK_DIFF_EN_S 24 +/** SPI1_MEM_F_DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI1_MEM_F_DQS_CA_IN (BIT(26)) +#define SPI1_MEM_F_DQS_CA_IN_M (SPI1_MEM_F_DQS_CA_IN_V << SPI1_MEM_F_DQS_CA_IN_S) +#define SPI1_MEM_F_DQS_CA_IN_V 0x00000001U +#define SPI1_MEM_F_DQS_CA_IN_S 26 +/** SPI1_MEM_F_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI1_MEM_F_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_M (SPI1_MEM_F_HYPERBUS_DUMMY_2X_V << SPI1_MEM_F_HYPERBUS_DUMMY_2X_S) +#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_S 27 +/** SPI1_MEM_F_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI1_MEM_F_CLK_DIFF_INV (BIT(28)) +#define SPI1_MEM_F_CLK_DIFF_INV_M (SPI1_MEM_F_CLK_DIFF_INV_V << SPI1_MEM_F_CLK_DIFF_INV_S) +#define SPI1_MEM_F_CLK_DIFF_INV_V 0x00000001U +#define SPI1_MEM_F_CLK_DIFF_INV_S 28 +/** SPI1_MEM_F_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI1_MEM_F_OCTA_RAM_ADDR (BIT(29)) +#define SPI1_MEM_F_OCTA_RAM_ADDR_M (SPI1_MEM_F_OCTA_RAM_ADDR_V << SPI1_MEM_F_OCTA_RAM_ADDR_S) +#define SPI1_MEM_F_OCTA_RAM_ADDR_V 0x00000001U +#define SPI1_MEM_F_OCTA_RAM_ADDR_S 29 +/** SPI1_MEM_F_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI1_MEM_F_HYPERBUS_CA (BIT(30)) +#define SPI1_MEM_F_HYPERBUS_CA_M (SPI1_MEM_F_HYPERBUS_CA_V << SPI1_MEM_F_HYPERBUS_CA_S) +#define SPI1_MEM_F_HYPERBUS_CA_V 0x00000001U +#define SPI1_MEM_F_HYPERBUS_CA_S 30 + +/** SPI1_MEM_TIMING_CALI_REG register + * SPI1 timing control register + */ +#define SPI1_MEM_TIMING_CALI_REG (DR_REG_SPI1_MEM_BASE + 0x180) +/** SPI1_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI1_MEM_TIMING_CALI (BIT(1)) +#define SPI1_MEM_TIMING_CALI_M (SPI1_MEM_TIMING_CALI_V << SPI1_MEM_TIMING_CALI_S) +#define SPI1_MEM_TIMING_CALI_V 0x00000001U +#define SPI1_MEM_TIMING_CALI_S 1 +/** SPI1_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI1_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_S 2 + +/** SPI1_MEM_CLOCK_GATE_REG register + * SPI1 clk_gate register + */ +#define SPI1_MEM_CLOCK_GATE_REG (DR_REG_SPI1_MEM_BASE + 0x200) +/** SPI1_MEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI1_MEM_CLK_EN (BIT(0)) +#define SPI1_MEM_CLK_EN_M (SPI1_MEM_CLK_EN_V << SPI1_MEM_CLK_EN_S) +#define SPI1_MEM_CLK_EN_V 0x00000001U +#define SPI1_MEM_CLK_EN_S 0 + +/** SPI1_MEM_DATE_REG register + * Version control register + */ +#define SPI1_MEM_DATE_REG (DR_REG_SPI1_MEM_BASE + 0x3fc) +/** SPI1_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128; + * Version control register + */ +#define SPI1_MEM_DATE 0x0FFFFFFFU +#define SPI1_MEM_DATE_M (SPI1_MEM_DATE_V << SPI1_MEM_DATE_S) +#define SPI1_MEM_DATE_V 0x0FFFFFFFU +#define SPI1_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi1_mem_struct.h b/components/soc/esp32c5/include/soc/spi1_mem_struct.h new file mode 100644 index 0000000000..ba4b231859 --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi1_mem_struct.h @@ -0,0 +1,1098 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: User-defined control registers */ +/** Type of cmd register + * SPI1 memory command register + */ +typedef union { + struct { + /** mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI1 master FSM. + */ + uint32_t mst_st:4; + /** slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t slv_st:4; + uint32_t reserved_8:10; + /** usr : R/W/SC; bitpos: [18]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. + */ + uint32_t usr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi1_mem_cmd_reg_t; + +/** Type of addr register + * SPI1 address register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * In user mode, it is the memory address. other then the bit0-bit23 is the memory + * address, the bit24-bit31 are the byte length of a transfer. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi1_mem_addr_reg_t; + +/** Type of user register + * SPI1 user register. + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ + uint32_t fwrite_quad:1; + /** fwrite_dio : R/W; bitpos: [14]; default: 0; + * In the write operations address phase and read-data phase apply 2 signals. + */ + uint32_t fwrite_dio:1; + /** fwrite_qio : R/W; bitpos: [15]; default: 0; + * In the write operations address phase and read-data phase apply 4 signals. + */ + uint32_t fwrite_qio:1; + uint32_t reserved_16:10; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * SPI clock is disable in dummy phase when the bit is enable. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi1_mem_user_reg_t; + +/** Type of user1 register + * SPI1 user1 register. + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t usr_dummy_cyclelen:6; + uint32_t reserved_6:20; + /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t usr_addr_bitlen:6; + }; + uint32_t val; +} spi1_mem_user1_reg_t; + +/** Type of user2 register + * SPI1 user2 register. + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:12; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi1_mem_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI1 control register. + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** fdummy_rin : R/W; bitpos: [2]; default: 1; + * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_rin:1; + /** fdummy_wout : R/W; bitpos: [3]; default: 1; + * In the dummy phase of a MSPI write data transfer when accesses to flash, the signal + * level of SPI bus is output by the MSPI controller. + */ + uint32_t fdummy_wout:1; + /** fdout_oct : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t fdout_oct:1; + /** fdin_oct : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t fdin_oct:1; + /** faddr_oct : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t faddr_oct:1; + uint32_t reserved_7:1; + /** fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t fcmd_oct:1; + uint32_t reserved_10:3; + /** fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout + * and spi_mem_fread_dout. 1: enable 0: disable. + */ + uint32_t fastrd_mode:1; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t fread_dual:1; + uint32_t reserved_15:3; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t d_pol:1; + /** fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t fread_quad:1; + /** wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t wp_reg:1; + uint32_t reserved_22:1; + /** fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t fread_dio:1; + /** fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t fread_qio:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi1_mem_ctrl_reg_t; + +/** Type of ctrl1 register + * SPI1 control1 register. + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ + uint32_t clk_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi1_mem_ctrl1_reg_t; + +/** Type of ctrl2 register + * SPI1 control2 register. + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sync_reset : WT; bitpos: [31]; default: 0; + * The FSM will be reset. + */ + uint32_t sync_reset:1; + }; + uint32_t val; +} spi1_mem_ctrl2_reg_t; + +/** Type of clock register + * SPI1 clock division control register. + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ + uint32_t clkcnt_l:8; + /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ + uint32_t clkcnt_h:8; + /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ + uint32_t clkcnt_n:8; + uint32_t reserved_24:7; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * reserved + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi1_mem_clock_reg_t; + +/** Type of mosi_dlen register + * SPI1 send data bit length control register. + */ +typedef union { + struct { + /** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ + uint32_t usr_mosi_dbitlen:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi1_mem_mosi_dlen_reg_t; + +/** Type of miso_dlen register + * SPI1 receive data bit length control register. + */ +typedef union { + struct { + /** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ + uint32_t usr_miso_dbitlen:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi1_mem_miso_dlen_reg_t; + +/** Type of rd_status register + * SPI1 status register. + */ +typedef union { + struct { + /** status : R/W/SS; bitpos: [15:0]; default: 0; + * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + */ + uint32_t status:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi1_mem_rd_status_reg_t; + +/** Type of misc register + * SPI1 misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI + * device, such as flash, external RAM and so on. + */ + uint32_t cs1_dis:1; + uint32_t reserved_2:7; + /** ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [10]; default: 0; + * spi cs line keep low when the bit is set. + */ + uint32_t cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_misc_reg_t; + +/** Type of flash_waiti_ctrl register + * SPI1 wait idle control register + */ +typedef union { + struct { + /** waiti_en : R/W; bitpos: [0]; default: 1; + * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto + * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto + * Suspend/Resume are not supported. + */ + uint32_t waiti_en:1; + /** waiti_dummy : R/W; bitpos: [1]; default: 0; + * The dummy phase enable when wait flash idle (RDSR) + */ + uint32_t waiti_dummy:1; + /** waiti_addr_en : R/W; bitpos: [2]; default: 0; + * 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out + * address in RDSR or read SUS command transfer. + */ + uint32_t waiti_addr_en:1; + /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0; + * When SPI1_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is + * (SPI1_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active + * when SPI1_MEM_WAITI_ADDR_EN is cleared. + */ + uint32_t waiti_addr_cyclelen:2; + uint32_t reserved_5:4; + /** waiti_cmd_2b : R/W; bitpos: [9]; default: 0; + * 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + */ + uint32_t waiti_cmd_2b:1; + /** waiti_dummy_cyclelen : R/W; bitpos: [15:10]; default: 0; + * The dummy cycle length when wait flash idle(RDSR). + */ + uint32_t waiti_dummy_cyclelen:6; + /** waiti_cmd : R/W; bitpos: [31:16]; default: 5; + * The command value to wait flash idle(RDSR). + */ + uint32_t waiti_cmd:16; + }; + uint32_t val; +} spi1_mem_flash_waiti_ctrl_reg_t; + +/** Type of flash_sus_ctrl register + * SPI1 flash suspend control register + */ +typedef union { + struct { + /** flash_per : R/W/SC; bitpos: [0]; default: 0; + * program erase resume bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_per:1; + /** flash_pes : R/W/SC; bitpos: [1]; default: 0; + * program erase suspend bit, program erase suspend operation will be triggered when + * the bit is set. The bit will be cleared once the operation done.1: enable 0: + * disable. + */ + uint32_t flash_pes:1; + /** flash_per_wait_en : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase resume command is sent. 0: SPI1 does not wait after program erase + * resume command is sent. + */ + uint32_t flash_per_wait_en:1; + /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after + * program erase suspend command is sent. 0: SPI1 does not wait after program erase + * suspend command is sent. + */ + uint32_t flash_pes_wait_en:1; + /** pes_per_en : R/W; bitpos: [4]; default: 0; + * Set this bit to enable PES end triggers PER transfer option. If this bit is 0, + * application should send PER after PES is done. + */ + uint32_t pes_per_en:1; + /** flash_pes_en : R/W; bitpos: [5]; default: 0; + * Set this bit to enable Auto-suspending function. + */ + uint32_t flash_pes_en:1; + /** pesr_end_msk : R/W; bitpos: [21:6]; default: 128; + * The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is + * status_in[15:0](only status_in[7:0] is valid when only one byte of data is read + * out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = + * status_in[15:0]^ SPI1_MEM_PESR_END_MSK[15:0]. + */ + uint32_t pesr_end_msk:16; + /** f_rd_sus_2b : R/W; bitpos: [22]; default: 0; + * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when + * check flash SUS/SUS1/SUS2 status bit + */ + uint32_t f_rd_sus_2b:1; + /** per_end_en : R/W; bitpos: [23]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of + * flash. 0: Only need to check WIP is 0. + */ + uint32_t per_end_en:1; + /** pes_end_en : R/W; bitpos: [24]; default: 0; + * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status + * of flash. 0: Only need to check WIP is 0. + */ + uint32_t pes_end_en:1; + /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4; + * When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_SUS_TIMEOUT_CNT[6:0] times, + * it will be treated as check pass. + */ + uint32_t sus_timeout_cnt:7; + }; + uint32_t val; +} spi1_mem_flash_sus_ctrl_reg_t; + +/** Type of flash_sus_cmd register + * SPI1 flash suspend command register + */ +typedef union { + struct { + /** flash_pes_command : R/W; bitpos: [15:0]; default: 30069; + * Program/Erase suspend command. + */ + uint32_t flash_pes_command:16; + /** wait_pesr_command : R/W; bitpos: [31:16]; default: 5; + * Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when + * SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + */ + uint32_t wait_pesr_command:16; + }; + uint32_t val; +} spi1_mem_flash_sus_cmd_reg_t; + +/** Type of sus_status register + * SPI1 flash suspend status register + */ +typedef union { + struct { + /** flash_sus : R/W/SS/SC; bitpos: [0]; default: 0; + * The status of flash suspend, only used in SPI1. + */ + uint32_t flash_sus:1; + /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0; + * 1: SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: + * SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + */ + uint32_t wait_pesr_cmd_2b:1; + /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after HPM command is sent. + */ + uint32_t flash_hpm_dly_128:1; + /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after RES command is sent. + */ + uint32_t flash_res_dly_128:1; + /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0; + * 1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP + * command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles + * after DP command is sent. + */ + uint32_t flash_dp_dly_128:1; + /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0; + * Valid when SPI1_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + * 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER + * command is sent. + */ + uint32_t flash_per_dly_128:1; + /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0; + * Valid when SPI1_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits + * (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES + * command is sent. + */ + uint32_t flash_pes_dly_128:1; + /** spi0_lock_en : R/W; bitpos: [7]; default: 0; + * 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + */ + uint32_t spi0_lock_en:1; + uint32_t reserved_8:7; + /** flash_pesr_cmd_2b : R/W; bitpos: [15]; default: 0; + * 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length + * of Program/Erase Suspend/Resume command is 8. + */ + uint32_t flash_pesr_cmd_2b:1; + /** flash_per_command : R/W; bitpos: [31:16]; default: 31354; + * Program/Erase resume command. + */ + uint32_t flash_per_command:16; + }; + uint32_t val; +} spi1_mem_sus_status_reg_t; + +/** Type of ddr register + * SPI1 DDR control register + */ +typedef union { + struct { + /** f_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in ddr mode, 0 in sdr mode + */ + uint32_t f_ddr_en:1; + /** f_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi ddr mode. + */ + uint32_t f_var_dummy:1; + /** f_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi ddr mode. + */ + uint32_t f_ddr_rdat_swp:1; + /** f_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi ddr mode. + */ + uint32_t f_ddr_wdat_swp:1; + /** f_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when ddr mode. + */ + uint32_t f_ddr_cmd_dis:1; + /** f_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t f_outminbytelen:7; + uint32_t reserved_12:2; + /** f_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t f_usr_ddr_dqs_thd:7; + /** f_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI1_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t f_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** f_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t f_clk_diff_en:1; + uint32_t reserved_25:1; + /** f_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t f_dqs_ca_in:1; + /** f_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t f_hyperbus_dummy_2x:1; + /** f_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t f_clk_diff_inv:1; + /** f_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t f_octa_ram_addr:1; + /** f_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t f_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi1_mem_ddr_reg_t; + +/** Type of clock_gate register + * SPI1 clk_gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi1_mem_clock_gate_reg_t; + + +/** Group: Memory data buffer register */ +/** Type of w0 register + * SPI1 memory data buffer0 + */ +typedef union { + struct { + /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf0:32; + }; + uint32_t val; +} spi1_mem_w0_reg_t; + +/** Type of w1 register + * SPI1 memory data buffer1 + */ +typedef union { + struct { + /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf1:32; + }; + uint32_t val; +} spi1_mem_w1_reg_t; + +/** Type of w2 register + * SPI1 memory data buffer2 + */ +typedef union { + struct { + /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf2:32; + }; + uint32_t val; +} spi1_mem_w2_reg_t; + +/** Type of w3 register + * SPI1 memory data buffer3 + */ +typedef union { + struct { + /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf3:32; + }; + uint32_t val; +} spi1_mem_w3_reg_t; + +/** Type of w4 register + * SPI1 memory data buffer4 + */ +typedef union { + struct { + /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf4:32; + }; + uint32_t val; +} spi1_mem_w4_reg_t; + +/** Type of w5 register + * SPI1 memory data buffer5 + */ +typedef union { + struct { + /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf5:32; + }; + uint32_t val; +} spi1_mem_w5_reg_t; + +/** Type of w6 register + * SPI1 memory data buffer6 + */ +typedef union { + struct { + /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf6:32; + }; + uint32_t val; +} spi1_mem_w6_reg_t; + +/** Type of w7 register + * SPI1 memory data buffer7 + */ +typedef union { + struct { + /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf7:32; + }; + uint32_t val; +} spi1_mem_w7_reg_t; + +/** Type of w8 register + * SPI1 memory data buffer8 + */ +typedef union { + struct { + /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf8:32; + }; + uint32_t val; +} spi1_mem_w8_reg_t; + +/** Type of w9 register + * SPI1 memory data buffer9 + */ +typedef union { + struct { + /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf9:32; + }; + uint32_t val; +} spi1_mem_w9_reg_t; + +/** Type of w10 register + * SPI1 memory data buffer10 + */ +typedef union { + struct { + /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf10:32; + }; + uint32_t val; +} spi1_mem_w10_reg_t; + +/** Type of w11 register + * SPI1 memory data buffer11 + */ +typedef union { + struct { + /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf11:32; + }; + uint32_t val; +} spi1_mem_w11_reg_t; + +/** Type of w12 register + * SPI1 memory data buffer12 + */ +typedef union { + struct { + /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf12:32; + }; + uint32_t val; +} spi1_mem_w12_reg_t; + +/** Type of w13 register + * SPI1 memory data buffer13 + */ +typedef union { + struct { + /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf13:32; + }; + uint32_t val; +} spi1_mem_w13_reg_t; + +/** Type of w14 register + * SPI1 memory data buffer14 + */ +typedef union { + struct { + /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf14:32; + }; + uint32_t val; +} spi1_mem_w14_reg_t; + +/** Type of w15 register + * SPI1 memory data buffer15 + */ +typedef union { + struct { + /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf15:32; + }; + uint32_t val; +} spi1_mem_w15_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_ena register + * SPI1 interrupt enable register + */ +typedef union { + struct { + /** per_end_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI1_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_ena:1; + /** pes_end_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI1_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_ena:1; + /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI1_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_ena:1; + /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_ena:1; + /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_ena:1; + uint32_t reserved_5:5; + /** brown_out_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_ena:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_int_ena_reg_t; + +/** Type of int_clr register + * SPI1 interrupt clear register + */ +typedef union { + struct { + /** per_end_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI1_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_clr:1; + /** pes_end_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI1_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_clr:1; + /** wpe_end_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI1_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_clr:1; + /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_clr:1; + /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_clr:1; + uint32_t reserved_5:5; + /** brown_out_int_clr : WT; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_clr:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_int_clr_reg_t; + +/** Type of int_raw register + * SPI1 interrupt raw register + */ +typedef union { + struct { + /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw bit for SPI1_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume + * command (0x7A) is sent and flash is resumed successfully. 0: Others. + */ + uint32_t per_end_int_raw:1; + /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw bit for SPI1_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend + * command (0x75) is sent and flash is suspended successfully. 0: Others. + */ + uint32_t pes_end_int_raw:1; + /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI1_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE + * is sent and flash is already idle. 0: Others. + */ + uint32_t wpe_end_int_raw:1; + /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI1_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t slv_st_end_int_raw:1; + /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI1_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mst_st_end_int_raw:1; + uint32_t reserved_5:5; + /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI1_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that + * chip is loosing power and RTC module sends out brown out close flash request to + * SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered + * and MSPI returns to idle state. 0: Others. + */ + uint32_t brown_out_int_raw:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_int_raw_reg_t; + +/** Type of int_st register + * SPI1 interrupt status register + */ +typedef union { + struct { + /** per_end_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI1_MEM_PER_END_INT interrupt. + */ + uint32_t per_end_int_st:1; + /** pes_end_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI1_MEM_PES_END_INT interrupt. + */ + uint32_t pes_end_int_st:1; + /** wpe_end_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI1_MEM_WPE_END_INT interrupt. + */ + uint32_t wpe_end_int_st:1; + /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI1_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t slv_st_end_int_st:1; + /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI1_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mst_st_end_int_st:1; + uint32_t reserved_5:5; + /** brown_out_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI1_MEM_BROWN_OUT_INT interrupt. + */ + uint32_t brown_out_int_st:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi1_mem_int_st_reg_t; + + +/** Group: Timing registers */ +/** Type of timing_cali register + * SPI1 timing control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t timing_cali:1; + /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t extra_dummy_cyclelen:3; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi1_mem_timing_cali_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35660128; + * Version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi1_mem_date_reg_t; + + +typedef struct { + volatile spi1_mem_cmd_reg_t cmd; + volatile spi1_mem_addr_reg_t addr; + volatile spi1_mem_ctrl_reg_t ctrl; + volatile spi1_mem_ctrl1_reg_t ctrl1; + volatile spi1_mem_ctrl2_reg_t ctrl2; + volatile spi1_mem_clock_reg_t clock; + volatile spi1_mem_user_reg_t user; + volatile spi1_mem_user1_reg_t user1; + volatile spi1_mem_user2_reg_t user2; + volatile spi1_mem_mosi_dlen_reg_t mosi_dlen; + volatile spi1_mem_miso_dlen_reg_t miso_dlen; + volatile spi1_mem_rd_status_reg_t rd_status; + uint32_t reserved_030; + volatile spi1_mem_misc_reg_t misc; + uint32_t reserved_038[8]; + volatile spi1_mem_w0_reg_t w0; + volatile spi1_mem_w1_reg_t w1; + volatile spi1_mem_w2_reg_t w2; + volatile spi1_mem_w3_reg_t w3; + volatile spi1_mem_w4_reg_t w4; + volatile spi1_mem_w5_reg_t w5; + volatile spi1_mem_w6_reg_t w6; + volatile spi1_mem_w7_reg_t w7; + volatile spi1_mem_w8_reg_t w8; + volatile spi1_mem_w9_reg_t w9; + volatile spi1_mem_w10_reg_t w10; + volatile spi1_mem_w11_reg_t w11; + volatile spi1_mem_w12_reg_t w12; + volatile spi1_mem_w13_reg_t w13; + volatile spi1_mem_w14_reg_t w14; + volatile spi1_mem_w15_reg_t w15; + volatile spi1_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl; + volatile spi1_mem_flash_sus_ctrl_reg_t flash_sus_ctrl; + volatile spi1_mem_flash_sus_cmd_reg_t flash_sus_cmd; + volatile spi1_mem_sus_status_reg_t sus_status; + uint32_t reserved_0a8[6]; + volatile spi1_mem_int_ena_reg_t int_ena; + volatile spi1_mem_int_clr_reg_t int_clr; + volatile spi1_mem_int_raw_reg_t int_raw; + volatile spi1_mem_int_st_reg_t int_st; + uint32_t reserved_0d0; + volatile spi1_mem_ddr_reg_t ddr; + uint32_t reserved_0d8[42]; + volatile spi1_mem_timing_cali_reg_t timing_cali; + uint32_t reserved_184[31]; + volatile spi1_mem_clock_gate_reg_t clock_gate; + uint32_t reserved_204[126]; + volatile spi1_mem_date_reg_t date; +} spi1_mem_dev_t; + +extern spi1_mem_dev_t SPIMEM1; + +#ifndef __cplusplus +_Static_assert(sizeof(spi1_mem_dev_t) == 0x400, "Invalid size of spi1_mem_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi_mem_reg.h b/components/soc/esp32c5/include/soc/spi_mem_reg.h new file mode 100644 index 0000000000..14d7d5d6db --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_mem_reg.h @@ -0,0 +1,2737 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI_MEM_CMD_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_CMD_REG (DR_REG_SPI_BASE + 0x0) +/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ +#define SPI_MEM_MST_ST 0x0000000FU +#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) +#define SPI_MEM_MST_ST_V 0x0000000FU +#define SPI_MEM_MST_ST_S 0 +/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ +#define SPI_MEM_SLV_ST 0x0000000FU +#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) +#define SPI_MEM_SLV_ST_V 0x0000000FU +#define SPI_MEM_SLV_ST_S 4 +/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) +#define SPI_MEM_USR_V 0x00000001U +#define SPI_MEM_USR_S 18 + +/** SPI_MEM_CTRL_REG register + * SPI0 control register. + */ +#define SPI_MEM_CTRL_REG (DR_REG_SPI_BASE + 0x8) +/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 +/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 +/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ +#define SPI_MEM_FDUMMY_RIN (BIT(2)) +#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) +#define SPI_MEM_FDUMMY_RIN_V 0x00000001U +#define SPI_MEM_FDUMMY_RIN_S 2 +/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ +#define SPI_MEM_FDUMMY_WOUT (BIT(3)) +#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) +#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U +#define SPI_MEM_FDUMMY_WOUT_S 3 +/** SPI_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) +#define SPI_MEM_FDOUT_OCT_V 0x00000001U +#define SPI_MEM_FDOUT_OCT_S 4 +/** SPI_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) +#define SPI_MEM_FDIN_OCT_V 0x00000001U +#define SPI_MEM_FDIN_OCT_S 5 +/** SPI_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) +#define SPI_MEM_FADDR_OCT_V 0x00000001U +#define SPI_MEM_FADDR_OCT_S 6 +/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) +#define SPI_MEM_FCMD_QUAD_V 0x00000001U +#define SPI_MEM_FCMD_QUAD_S 8 +/** SPI_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) +#define SPI_MEM_FCMD_OCT_V 0x00000001U +#define SPI_MEM_FCMD_OCT_S 9 +/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + */ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) +#define SPI_MEM_FASTRD_MODE_V 0x00000001U +#define SPI_MEM_FASTRD_MODE_S 13 +/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) +#define SPI_MEM_FREAD_DUAL_V 0x00000001U +#define SPI_MEM_FREAD_DUAL_S 14 +/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) +#define SPI_MEM_Q_POL_V 0x00000001U +#define SPI_MEM_Q_POL_S 18 +/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) +#define SPI_MEM_D_POL_V 0x00000001U +#define SPI_MEM_D_POL_S 19 +/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) +#define SPI_MEM_FREAD_QUAD_V 0x00000001U +#define SPI_MEM_FREAD_QUAD_S 20 +/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) +#define SPI_MEM_WP_REG_V 0x00000001U +#define SPI_MEM_WP_REG_S 21 +/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) +#define SPI_MEM_FREAD_DIO_V 0x00000001U +#define SPI_MEM_FREAD_DIO_S 23 +/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) +#define SPI_MEM_FREAD_QIO_V 0x00000001U +#define SPI_MEM_FREAD_QIO_S 24 +/** SPI_MEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ +#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_MEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S) +#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ +#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_MEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S) +#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_CTRL1_REG register + * SPI0 control1 register. + */ +#define SPI_MEM_CTRL1_REG (DR_REG_SPI_BASE + 0xc) +/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ +#define SPI_MEM_CLK_MODE 0x00000003U +#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) +#define SPI_MEM_CLK_MODE_V 0x00000003U +#define SPI_MEM_CLK_MODE_S 0 +/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) +#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 +/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ +#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) +#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U +#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ +#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) +#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) +#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U +#define SPI_AXI_RDATA_BACK_FAST_S 23 +/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_ECC_ERR_ADDR_REG. + */ +#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) +#define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) +#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U +#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 +/** SPI_MEM_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ +#define SPI_MEM_AR_SPLICE_EN (BIT(25)) +#define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) +#define SPI_MEM_AR_SPLICE_EN_V 0x00000001U +#define SPI_MEM_AR_SPLICE_EN_S 25 +/** SPI_MEM_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ +#define SPI_MEM_AW_SPLICE_EN (BIT(26)) +#define SPI_MEM_AW_SPLICE_EN_M (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S) +#define SPI_MEM_AW_SPLICE_EN_V 0x00000001U +#define SPI_MEM_AW_SPLICE_EN_S 26 +/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ +#define SPI_MEM_RAM0_EN (BIT(27)) +#define SPI_MEM_RAM0_EN_M (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S) +#define SPI_MEM_RAM0_EN_V 0x00000001U +#define SPI_MEM_RAM0_EN_S 27 +/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ +#define SPI_MEM_DUAL_RAM_EN (BIT(28)) +#define SPI_MEM_DUAL_RAM_EN_M (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S) +#define SPI_MEM_DUAL_RAM_EN_V 0x00000001U +#define SPI_MEM_DUAL_RAM_EN_S 28 +/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ +#define SPI_MEM_FAST_WRITE_EN (BIT(29)) +#define SPI_MEM_FAST_WRITE_EN_M (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S) +#define SPI_MEM_FAST_WRITE_EN_V 0x00000001U +#define SPI_MEM_FAST_WRITE_EN_S 29 +/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S) +#define SPI_MEM_RXFIFO_RST_V 0x00000001U +#define SPI_MEM_RXFIFO_RST_S 30 +/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ +#define SPI_MEM_TXFIFO_RST (BIT(31)) +#define SPI_MEM_TXFIFO_RST_M (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S) +#define SPI_MEM_TXFIFO_RST_V 0x00000001U +#define SPI_MEM_TXFIFO_RST_S 31 + +/** SPI_MEM_CTRL2_REG register + * SPI0 control2 register. + */ +#define SPI_MEM_CTRL2_REG (DR_REG_SPI_BASE + 0x10) +/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_CS_SETUP bit. + */ +#define SPI_MEM_CS_SETUP_TIME 0x0000001FU +#define SPI_MEM_CS_SETUP_TIME_M (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S) +#define SPI_MEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_MEM_CS_SETUP_TIME_S 0 +/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_CS_HOLD bit. + */ +#define SPI_MEM_CS_HOLD_TIME 0x0000001FU +#define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) +#define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_MEM_CS_HOLD_TIME_S 5 +/** SPI_MEM_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/** SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/** SPI_MEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ +#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) +#define SPI_MEM_SPLIT_TRANS_EN_M (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S) +#define SPI_MEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_MEM_SPLIT_TRANS_EN_S 24 +/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_MEM_CS_HOLD_DELAY_M (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S) +#define SPI_MEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) +#define SPI_MEM_SYNC_RESET_V 0x00000001U +#define SPI_MEM_SYNC_RESET_S 31 + +/** SPI_MEM_CLOCK_REG register + * SPI clock division control register. + */ +#define SPI_MEM_CLOCK_REG (DR_REG_SPI_BASE + 0x14) +/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ +#define SPI_MEM_CLKCNT_L 0x000000FFU +#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) +#define SPI_MEM_CLKCNT_L_V 0x000000FFU +#define SPI_MEM_CLKCNT_L_S 0 +/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ +#define SPI_MEM_CLKCNT_H 0x000000FFU +#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) +#define SPI_MEM_CLKCNT_H_V 0x000000FFU +#define SPI_MEM_CLKCNT_H_S 8 +/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ +#define SPI_MEM_CLKCNT_N 0x000000FFU +#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) +#define SPI_MEM_CLKCNT_N_V 0x000000FFU +#define SPI_MEM_CLKCNT_N_S 16 +/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 + +/** SPI_MEM_USER_REG register + * SPI0 user register. + */ +#define SPI_MEM_USER_REG (DR_REG_SPI_BASE + 0x18) +/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S) +#define SPI_MEM_CS_HOLD_V 0x00000001U +#define SPI_MEM_CS_HOLD_S 6 +/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S) +#define SPI_MEM_CS_SETUP_V 0x00000001U +#define SPI_MEM_CS_SETUP_S 7 +/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) +#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U +#define SPI_MEM_CK_OUT_EDGE_S 9 +/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) +#define SPI_MEM_USR_DUMMY_V 0x00000001U +#define SPI_MEM_USR_DUMMY_S 29 + +/** SPI_MEM_USER1_REG register + * SPI0 user1 register. + */ +#define SPI_MEM_USER1_REG (DR_REG_SPI_BASE + 0x1c) +/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 +/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ +#define SPI_MEM_USR_DBYTELEN 0x00000007U +#define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) +#define SPI_MEM_USR_DBYTELEN_V 0x00000007U +#define SPI_MEM_USR_DBYTELEN_S 6 +/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU +#define SPI_MEM_USR_ADDR_BITLEN_S 26 + +/** SPI_MEM_USER2_REG register + * SPI0 user2 register. + */ +#define SPI_MEM_USER2_REG (DR_REG_SPI_BASE + 0x20) +/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) +#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU +#define SPI_MEM_USR_COMMAND_VALUE_S 0 +/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 + +/** SPI_MEM_MISC_REG register + * SPI0 misc register + */ +#define SPI_MEM_MISC_REG (DR_REG_SPI_BASE + 0x34) +/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S) +#define SPI_MEM_FSUB_PIN_V 0x00000001U +#define SPI_MEM_FSUB_PIN_S 7 +/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S) +#define SPI_MEM_SSUB_PIN_V 0x00000001U +#define SPI_MEM_SSUB_PIN_S 8 +/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) +#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 + +/** SPI_MEM_CACHE_FCTRL_REG register + * SPI0 bit mode control register. + */ +#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_BASE + 0x3c) +/** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ +#define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) +#define SPI_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) +#define SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U +#define SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 +/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ +#define SPI_CLOSE_AXI_INF_EN (BIT(31)) +#define SPI_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) +#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U +#define SPI_CLOSE_AXI_INF_EN_S 31 + +/** SPI_MEM_SRAM_CMD_REG register + * SPI0 external RAM mode control register + */ +#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPI_BASE + 0x44) +/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U +#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 +/** SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ +#define SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U +#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 +/** SPI_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ +#define SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) +#define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) +#define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U +#define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 +/** SPI_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ +#define SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) +#define SPI_SMEM_DATA_IE_ALWAYS_ON_M (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S) +#define SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U +#define SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 + +/** SPI_MEM_FSM_REG register + * SPI0 FSM status register + */ +#define SPI_MEM_FSM_REG (DR_REG_SPI_BASE + 0x54) +/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ +#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) +#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_S 7 + +/** SPI_MEM_INT_ENA_REG register + * SPI0 interrupt enable register + */ +#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_BASE + 0xc0) +/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) +#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 +/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) +#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ENA_S 4 +/** SPI_MEM_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_ENA_S 5 +/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ENA_M (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S) +#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 + +/** SPI_MEM_INT_CLR_REG register + * SPI0 interrupt clear register + */ +#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_BASE + 0xc4) +/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) +#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 +/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) +#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_CLR_S 4 +/** SPI_MEM_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_CLR_S 5 +/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_CLR_M (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S) +#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 + +/** SPI_MEM_INT_RAW_REG register + * SPI0 interrupt raw register + */ +#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_BASE + 0xc8) +/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ +#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) +#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 +/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ +#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) +#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_RAW_S 4 +/** SPI_MEM_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_RAW_S 5 +/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ +#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_RAW_M (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S) +#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 + +/** SPI_MEM_INT_ST_REG register + * SPI0 interrupt status register + */ +#define SPI_MEM_INT_ST_REG (DR_REG_SPI_BASE + 0xcc) +/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ +#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) +#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) +#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_SLV_ST_END_INT_ST_S 3 +/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ +#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) +#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) +#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U +#define SPI_MEM_MST_ST_END_INT_ST_S 4 +/** SPI_MEM_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) +#define SPI_MEM_ECC_ERR_INT_ST_M (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_ECC_ERR_INT_ST_S 5 +/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ +#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) +#define SPI_MEM_PMS_REJECT_INT_ST_M (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S) +#define SPI_MEM_PMS_REJECT_INT_ST_V 0x00000001U +#define SPI_MEM_PMS_REJECT_INT_ST_S 6 +/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 +/** SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ +#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U +#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 + +/** SPI_MEM_DDR_REG register + * SPI0 flash DDR mode control register + */ +#define SPI_MEM_DDR_REG (DR_REG_SPI_BASE + 0xd4) +/** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) +#define SPI_FMEM_DDR_EN_V 0x00000001U +#define SPI_FMEM_DDR_EN_S 0 +/** SPI_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) +#define SPI_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_FMEM_VAR_DUMMY_S 1 +/** SPI_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) +#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) +#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) +#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_FMEM_DDR_CMD_DIS_S 4 +/** SPI_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ +#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) +#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_S 5 +/** SPI_FMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ +#define SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) +#define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_FMEM_TX_DDR_MSK_EN_S 12 +/** SPI_FMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ +#define SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) +#define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_FMEM_RX_DDR_MSK_EN_S 13 +/** SPI_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) +#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) +#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) +#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_EN_S 24 +/** SPI_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) +#define SPI_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_FMEM_DQS_CA_IN_S 26 +/** SPI_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ +#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) +#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_INV_S 28 +/** SPI_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ +#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) +#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) +#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_FMEM_HYPERBUS_CA_S 30 + +/** SPI_SMEM_DDR_REG register + * SPI0 external RAM DDR mode control register + */ +#define SPI_SMEM_DDR_REG (DR_REG_SPI_BASE + 0xd8) +/** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ +#define SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) +#define SPI_SMEM_DDR_EN_V 0x00000001U +#define SPI_SMEM_DDR_EN_S 0 +/** SPI_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ +#define SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) +#define SPI_SMEM_VAR_DUMMY_V 0x00000001U +#define SPI_SMEM_VAR_DUMMY_S 1 +/** SPI_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ +#define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) +#define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_SMEM_DDR_RDAT_SWP_S 2 +/** SPI_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ +#define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) +#define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_SMEM_DDR_WDAT_SWP_S 3 +/** SPI_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ +#define SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) +#define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_SMEM_DDR_CMD_DIS_S 4 +/** SPI_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ +#define SPI_SMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) +#define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_SMEM_OUTMINBYTELEN_S 5 +/** SPI_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ +#define SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) +#define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U +#define SPI_SMEM_TX_DDR_MSK_EN_S 12 +/** SPI_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ +#define SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) +#define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U +#define SPI_SMEM_RX_DDR_MSK_EN_S 13 +/** SPI_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ +#define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) +#define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_SMEM_USR_DDR_DQS_THD_S 14 +/** SPI_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ +#define SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) +#define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_SMEM_DDR_DQS_LOOP_S 21 +/** SPI_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ +#define SPI_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) +#define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_SMEM_CLK_DIFF_EN_S 24 +/** SPI_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ +#define SPI_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) +#define SPI_SMEM_DQS_CA_IN_V 0x00000001U +#define SPI_SMEM_DQS_CA_IN_S 26 +/** SPI_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ +#define SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ +#define SPI_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) +#define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_SMEM_CLK_DIFF_INV_S 28 +/** SPI_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ +#define SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) +#define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_SMEM_OCTA_RAM_ADDR_S 29 +/** SPI_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ +#define SPI_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_SMEM_HYPERBUS_CA_M (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S) +#define SPI_SMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_SMEM_HYPERBUS_CA_S 30 + +/** SPI_FMEM_PMS0_ATTR_REG register + * MSPI flash PMS section 0 attribute register + */ +#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x100) +/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS0_RD_ATTR_M (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S) +#define SPI_FMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_RD_ATTR_S 0 +/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS0_WR_ATTR_M (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S) +#define SPI_FMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS0_WR_ATTR_S 1 +/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and + * SPI_FMEM_PMS0_SIZE_REG. + */ +#define SPI_FMEM_PMS0_ECC (BIT(2)) +#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) +#define SPI_FMEM_PMS0_ECC_V 0x00000001U +#define SPI_FMEM_PMS0_ECC_S 2 + +/** SPI_FMEM_PMS1_ATTR_REG register + * MSPI flash PMS section 1 attribute register + */ +#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x104) +/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS1_RD_ATTR_M (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S) +#define SPI_FMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_RD_ATTR_S 0 +/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS1_WR_ATTR_M (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S) +#define SPI_FMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS1_WR_ATTR_S 1 +/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and + * SPI_FMEM_PMS1_SIZE_REG. + */ +#define SPI_FMEM_PMS1_ECC (BIT(2)) +#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) +#define SPI_FMEM_PMS1_ECC_V 0x00000001U +#define SPI_FMEM_PMS1_ECC_S 2 + +/** SPI_FMEM_PMS2_ATTR_REG register + * MSPI flash PMS section 2 attribute register + */ +#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x108) +/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS2_RD_ATTR_M (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S) +#define SPI_FMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_RD_ATTR_S 0 +/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS2_WR_ATTR_M (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S) +#define SPI_FMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS2_WR_ATTR_S 1 +/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and + * SPI_FMEM_PMS2_SIZE_REG. + */ +#define SPI_FMEM_PMS2_ECC (BIT(2)) +#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) +#define SPI_FMEM_PMS2_ECC_V 0x00000001U +#define SPI_FMEM_PMS2_ECC_S 2 + +/** SPI_FMEM_PMS3_ATTR_REG register + * MSPI flash PMS section 3 attribute register + */ +#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x10c) +/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_FMEM_PMS3_RD_ATTR_M (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S) +#define SPI_FMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_RD_ATTR_S 0 +/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_FMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_FMEM_PMS3_WR_ATTR_M (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S) +#define SPI_FMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_FMEM_PMS3_WR_ATTR_S 1 +/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and + * SPI_FMEM_PMS3_SIZE_REG. + */ +#define SPI_FMEM_PMS3_ECC (BIT(2)) +#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) +#define SPI_FMEM_PMS3_ECC_V 0x00000001U +#define SPI_FMEM_PMS3_ECC_S 2 + +/** SPI_FMEM_PMS0_ADDR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x110) +/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 0 start address value + */ +#define SPI_FMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) +#define SPI_FMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_S 0 + +/** SPI_FMEM_PMS1_ADDR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x114) +/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 1 start address value + */ +#define SPI_FMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) +#define SPI_FMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_S 0 + +/** SPI_FMEM_PMS2_ADDR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x118) +/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 2 start address value + */ +#define SPI_FMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) +#define SPI_FMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_S 0 + +/** SPI_FMEM_PMS3_ADDR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x11c) +/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section 3 start address value + */ +#define SPI_FMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) +#define SPI_FMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_S 0 + +/** SPI_FMEM_PMS0_SIZE_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x120) +/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, + * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) + */ +#define SPI_FMEM_PMS0_SIZE 0x00007FFFU +#define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) +#define SPI_FMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS0_SIZE_S 0 + +/** SPI_FMEM_PMS1_SIZE_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x124) +/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, + * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) + */ +#define SPI_FMEM_PMS1_SIZE 0x00007FFFU +#define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) +#define SPI_FMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS1_SIZE_S 0 + +/** SPI_FMEM_PMS2_SIZE_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x128) +/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, + * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) + */ +#define SPI_FMEM_PMS2_SIZE 0x00007FFFU +#define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) +#define SPI_FMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS2_SIZE_S 0 + +/** SPI_FMEM_PMS3_SIZE_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x12c) +/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, + * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) + */ +#define SPI_FMEM_PMS3_SIZE 0x00007FFFU +#define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) +#define SPI_FMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS3_SIZE_S 0 + +/** SPI_SMEM_PMS0_ATTR_REG register + * SPI1 flash PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x130) +/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS0_RD_ATTR_M (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S) +#define SPI_SMEM_PMS0_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_RD_ATTR_S 0 +/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS0_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS0_WR_ATTR_M (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S) +#define SPI_SMEM_PMS0_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS0_WR_ATTR_S 1 +/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and + * SPI_SMEM_PMS0_SIZE_REG. + */ +#define SPI_SMEM_PMS0_ECC (BIT(2)) +#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) +#define SPI_SMEM_PMS0_ECC_V 0x00000001U +#define SPI_SMEM_PMS0_ECC_S 2 + +/** SPI_SMEM_PMS1_ATTR_REG register + * SPI1 flash PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x134) +/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS1_RD_ATTR_M (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S) +#define SPI_SMEM_PMS1_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_RD_ATTR_S 0 +/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS1_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS1_WR_ATTR_M (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S) +#define SPI_SMEM_PMS1_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS1_WR_ATTR_S 1 +/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and + * SPI_SMEM_PMS1_SIZE_REG. + */ +#define SPI_SMEM_PMS1_ECC (BIT(2)) +#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) +#define SPI_SMEM_PMS1_ECC_V 0x00000001U +#define SPI_SMEM_PMS1_ECC_S 2 + +/** SPI_SMEM_PMS2_ATTR_REG register + * SPI1 flash PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x138) +/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS2_RD_ATTR_M (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S) +#define SPI_SMEM_PMS2_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_RD_ATTR_S 0 +/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS2_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS2_WR_ATTR_M (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S) +#define SPI_SMEM_PMS2_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS2_WR_ATTR_S 1 +/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and + * SPI_SMEM_PMS2_SIZE_REG. + */ +#define SPI_SMEM_PMS2_ECC (BIT(2)) +#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) +#define SPI_SMEM_PMS2_ECC_V 0x00000001U +#define SPI_SMEM_PMS2_ECC_S 2 + +/** SPI_SMEM_PMS3_ATTR_REG register + * SPI1 flash PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x13c) +/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_RD_ATTR (BIT(0)) +#define SPI_SMEM_PMS3_RD_ATTR_M (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S) +#define SPI_SMEM_PMS3_RD_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_RD_ATTR_S 0 +/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. + */ +#define SPI_SMEM_PMS3_WR_ATTR (BIT(1)) +#define SPI_SMEM_PMS3_WR_ATTR_M (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S) +#define SPI_SMEM_PMS3_WR_ATTR_V 0x00000001U +#define SPI_SMEM_PMS3_WR_ATTR_S 1 +/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and + * SPI_SMEM_PMS3_SIZE_REG. + */ +#define SPI_SMEM_PMS3_ECC (BIT(2)) +#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) +#define SPI_SMEM_PMS3_ECC_V 0x00000001U +#define SPI_SMEM_PMS3_ECC_S 2 + +/** SPI_SMEM_PMS0_ADDR_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x140) +/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 0 start address value + */ +#define SPI_SMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) +#define SPI_SMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_S 0 + +/** SPI_SMEM_PMS1_ADDR_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x144) +/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 1 start address value + */ +#define SPI_SMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) +#define SPI_SMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_S 0 + +/** SPI_SMEM_PMS2_ADDR_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x148) +/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 2 start address value + */ +#define SPI_SMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) +#define SPI_SMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_S 0 + +/** SPI_SMEM_PMS3_ADDR_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x14c) +/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section 3 start address value + */ +#define SPI_SMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) +#define SPI_SMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_S 0 + +/** SPI_SMEM_PMS0_SIZE_REG register + * SPI1 external RAM PMS section 0 start address register + */ +#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x150) +/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, + * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) + */ +#define SPI_SMEM_PMS0_SIZE 0x00007FFFU +#define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) +#define SPI_SMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS0_SIZE_S 0 + +/** SPI_SMEM_PMS1_SIZE_REG register + * SPI1 external RAM PMS section 1 start address register + */ +#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x154) +/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, + * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) + */ +#define SPI_SMEM_PMS1_SIZE 0x00007FFFU +#define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) +#define SPI_SMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS1_SIZE_S 0 + +/** SPI_SMEM_PMS2_SIZE_REG register + * SPI1 external RAM PMS section 2 start address register + */ +#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x158) +/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, + * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) + */ +#define SPI_SMEM_PMS2_SIZE 0x00007FFFU +#define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) +#define SPI_SMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS2_SIZE_S 0 + +/** SPI_SMEM_PMS3_SIZE_REG register + * SPI1 external RAM PMS section 3 start address register + */ +#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x15c) +/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, + * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) + */ +#define SPI_SMEM_PMS3_SIZE 0x00007FFFU +#define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) +#define SPI_SMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS3_SIZE_S 0 + +/** SPI_MEM_PMS_REJECT_REG register + * SPI1 access reject register + */ +#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPI_BASE + 0x164) +/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_REJECT_ADDR 0x07FFFFFFU +#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) +#define SPI_MEM_REJECT_ADDR_V 0x07FFFFFFU +#define SPI_MEM_REJECT_ADDR_S 0 +/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ +#define SPI_MEM_PM_EN (BIT(27)) +#define SPI_MEM_PM_EN_M (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S) +#define SPI_MEM_PM_EN_V 0x00000001U +#define SPI_MEM_PM_EN_S 27 +/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_LD (BIT(28)) +#define SPI_MEM_PMS_LD_M (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S) +#define SPI_MEM_PMS_LD_V 0x00000001U +#define SPI_MEM_PMS_LD_S 28 +/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_ST (BIT(29)) +#define SPI_MEM_PMS_ST_M (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S) +#define SPI_MEM_PMS_ST_V 0x00000001U +#define SPI_MEM_PMS_ST_S 29 +/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) +#define SPI_MEM_PMS_MULTI_HIT_M (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S) +#define SPI_MEM_PMS_MULTI_HIT_V 0x00000001U +#define SPI_MEM_PMS_MULTI_HIT_S 30 +/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_PMS_IVD (BIT(31)) +#define SPI_MEM_PMS_IVD_M (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S) +#define SPI_MEM_PMS_IVD_V 0x00000001U +#define SPI_MEM_PMS_IVD_S 31 + +/** SPI_MEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x168) +/** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_ECC_ERR_CNT 0x0000003FU +#define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) +#define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU +#define SPI_MEM_ECC_ERR_CNT_S 5 +/** SPI_FMEM_ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + */ +#define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU +#define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) +#define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU +#define SPI_FMEM_ECC_ERR_INT_NUM_S 11 +/** SPI_FMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ +#define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_FMEM_ECC_ERR_INT_EN_M (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S) +#define SPI_FMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_FMEM_ECC_ERR_INT_EN_S 17 +/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ +#define SPI_FMEM_PAGE_SIZE 0x00000003U +#define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) +#define SPI_FMEM_PAGE_SIZE_V 0x00000003U +#define SPI_FMEM_PAGE_SIZE_S 18 +/** SPI_FMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ +#define SPI_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) +#define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_FMEM_ECC_ADDR_EN_S 20 +/** SPI_MEM_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) +#define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U +#define SPI_MEM_USR_ECC_ADDR_EN_S 21 +/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + */ +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U +#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 +/** SPI_MEM_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ +#define SPI_MEM_ECC_ERR_BITS 0x0000007FU +#define SPI_MEM_ECC_ERR_BITS_M (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S) +#define SPI_MEM_ECC_ERR_BITS_V 0x0000007FU +#define SPI_MEM_ECC_ERR_BITS_S 25 + +/** SPI_MEM_ECC_ERR_ADDR_REG register + * MSPI ECC error address register + */ +#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x16c) +/** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ +#define SPI_MEM_ECC_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) +#define SPI_MEM_ECC_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +/** SPI_MEM_AXI_ERR_ADDR_REG register + * SPI0 AXI request error address. + */ +#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x170) +/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + */ +#define SPI_MEM_AXI_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) +#define SPI_MEM_AXI_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_S 0 + +/** SPI_SMEM_ECC_CTRL_REG register + * MSPI ECC control register + */ +#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x174) +/** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ +#define SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) +#define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) +#define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U +#define SPI_SMEM_ECC_ERR_INT_EN_S 17 +/** SPI_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ +#define SPI_SMEM_PAGE_SIZE 0x00000003U +#define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) +#define SPI_SMEM_PAGE_SIZE_V 0x00000003U +#define SPI_SMEM_PAGE_SIZE_S 18 +/** SPI_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ +#define SPI_SMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_SMEM_ECC_ADDR_EN_M (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S) +#define SPI_SMEM_ECC_ADDR_EN_V 0x00000001U +#define SPI_SMEM_ECC_ADDR_EN_S 20 + +/** SPI_SMEM_AXI_ADDR_CTRL_REG register + * SPI0 AXI address control register + */ +#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPI_BASE + 0x178) +/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ +#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) +#define SPI_MEM_ALL_FIFO_EMPTY_M (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S) +#define SPI_MEM_ALL_FIFO_EMPTY_V 0x00000001U +#define SPI_MEM_ALL_FIFO_EMPTY_S 26 +/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_RDATA_AFIFO_REMPTY (BIT(27)) +#define SPI_RDATA_AFIFO_REMPTY_M (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S) +#define SPI_RDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_RDATA_AFIFO_REMPTY_S 27 +/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ +#define SPI_RADDR_AFIFO_REMPTY (BIT(28)) +#define SPI_RADDR_AFIFO_REMPTY_M (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S) +#define SPI_RADDR_AFIFO_REMPTY_V 0x00000001U +#define SPI_RADDR_AFIFO_REMPTY_S 28 +/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_WDATA_AFIFO_REMPTY (BIT(29)) +#define SPI_WDATA_AFIFO_REMPTY_M (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S) +#define SPI_WDATA_AFIFO_REMPTY_V 0x00000001U +#define SPI_WDATA_AFIFO_REMPTY_S 29 +/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ +#define SPI_WBLEN_AFIFO_REMPTY (BIT(30)) +#define SPI_WBLEN_AFIFO_REMPTY_M (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S) +#define SPI_WBLEN_AFIFO_REMPTY_V 0x00000001U +#define SPI_WBLEN_AFIFO_REMPTY_S 30 +/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S) +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U +#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 + +/** SPI_MEM_AXI_ERR_RESP_EN_REG register + * SPI0 AXI error response enable register + */ +#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPI_BASE + 0x17c) +/** SPI_MEM_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) +#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 +/** SPI_MEM_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) +#define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) +#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 +/** SPI_MEM_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 +/** SPI_MEM_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 +/** SPI_MEM_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) +#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 +/** SPI_MEM_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) +#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 +/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S) +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x00000001U +#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 +/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S) +#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 +/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) +#define SPI_MEM_AR_RESP_EN_MMU_GID_M (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S) +#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 +/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S) +#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 +/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ +#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S) +#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 +/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ +#define SPI_MEM_AR_RESP_EN_AXI_SIZE (BIT(11)) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S) +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x00000001U +#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S 11 + +/** SPI_MEM_TIMING_CALI_REG register + * SPI0 flash timing calibration register + */ +#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x180) +/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S) +#define SPI_MEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_MEM_TIMING_CLK_ENA_S 0 +/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) +#define SPI_MEM_TIMING_CALI_V 0x00000001U +#define SPI_MEM_TIMING_CALI_S 1 +/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_MEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ +#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_MEM_DLL_TIMING_CALI_M (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S) +#define SPI_MEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_MEM_DLL_TIMING_CALI_S 5 +/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ +#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) +#define SPI_MEM_TIMING_CALI_UPDATE_M (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S) +#define SPI_MEM_TIMING_CALI_UPDATE_V 0x00000001U +#define SPI_MEM_TIMING_CALI_UPDATE_S 6 + +/** SPI_MEM_DIN_MODE_REG register + * MSPI flash input timing delay mode control register + */ +#define SPI_MEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x184) +/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN0_MODE 0x00000007U +#define SPI_MEM_DIN0_MODE_M (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S) +#define SPI_MEM_DIN0_MODE_V 0x00000007U +#define SPI_MEM_DIN0_MODE_S 0 +/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN1_MODE 0x00000007U +#define SPI_MEM_DIN1_MODE_M (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S) +#define SPI_MEM_DIN1_MODE_V 0x00000007U +#define SPI_MEM_DIN1_MODE_S 3 +/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN2_MODE 0x00000007U +#define SPI_MEM_DIN2_MODE_M (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S) +#define SPI_MEM_DIN2_MODE_V 0x00000007U +#define SPI_MEM_DIN2_MODE_S 6 +/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_MEM_DIN3_MODE 0x00000007U +#define SPI_MEM_DIN3_MODE_M (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S) +#define SPI_MEM_DIN3_MODE_V 0x00000007U +#define SPI_MEM_DIN3_MODE_S 9 +/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN4_MODE 0x00000007U +#define SPI_MEM_DIN4_MODE_M (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S) +#define SPI_MEM_DIN4_MODE_V 0x00000007U +#define SPI_MEM_DIN4_MODE_S 12 +/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN5_MODE 0x00000007U +#define SPI_MEM_DIN5_MODE_M (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S) +#define SPI_MEM_DIN5_MODE_V 0x00000007U +#define SPI_MEM_DIN5_MODE_S 15 +/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN6_MODE 0x00000007U +#define SPI_MEM_DIN6_MODE_M (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S) +#define SPI_MEM_DIN6_MODE_V 0x00000007U +#define SPI_MEM_DIN6_MODE_S 18 +/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DIN7_MODE 0x00000007U +#define SPI_MEM_DIN7_MODE_M (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S) +#define SPI_MEM_DIN7_MODE_V 0x00000007U +#define SPI_MEM_DIN7_MODE_S 21 +/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ +#define SPI_MEM_DINS_MODE 0x00000007U +#define SPI_MEM_DINS_MODE_M (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S) +#define SPI_MEM_DINS_MODE_V 0x00000007U +#define SPI_MEM_DINS_MODE_S 24 + +/** SPI_MEM_DIN_NUM_REG register + * MSPI flash input timing delay number control register + */ +#define SPI_MEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x188) +/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN0_NUM 0x00000003U +#define SPI_MEM_DIN0_NUM_M (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S) +#define SPI_MEM_DIN0_NUM_V 0x00000003U +#define SPI_MEM_DIN0_NUM_S 0 +/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN1_NUM 0x00000003U +#define SPI_MEM_DIN1_NUM_M (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S) +#define SPI_MEM_DIN1_NUM_V 0x00000003U +#define SPI_MEM_DIN1_NUM_S 2 +/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN2_NUM 0x00000003U +#define SPI_MEM_DIN2_NUM_M (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S) +#define SPI_MEM_DIN2_NUM_V 0x00000003U +#define SPI_MEM_DIN2_NUM_S 4 +/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN3_NUM 0x00000003U +#define SPI_MEM_DIN3_NUM_M (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S) +#define SPI_MEM_DIN3_NUM_V 0x00000003U +#define SPI_MEM_DIN3_NUM_S 6 +/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN4_NUM 0x00000003U +#define SPI_MEM_DIN4_NUM_M (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S) +#define SPI_MEM_DIN4_NUM_V 0x00000003U +#define SPI_MEM_DIN4_NUM_S 8 +/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN5_NUM 0x00000003U +#define SPI_MEM_DIN5_NUM_M (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S) +#define SPI_MEM_DIN5_NUM_V 0x00000003U +#define SPI_MEM_DIN5_NUM_S 10 +/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN6_NUM 0x00000003U +#define SPI_MEM_DIN6_NUM_M (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S) +#define SPI_MEM_DIN6_NUM_V 0x00000003U +#define SPI_MEM_DIN6_NUM_S 12 +/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DIN7_NUM 0x00000003U +#define SPI_MEM_DIN7_NUM_M (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S) +#define SPI_MEM_DIN7_NUM_V 0x00000003U +#define SPI_MEM_DIN7_NUM_S 14 +/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_MEM_DINS_NUM 0x00000003U +#define SPI_MEM_DINS_NUM_M (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S) +#define SPI_MEM_DINS_NUM_V 0x00000003U +#define SPI_MEM_DINS_NUM_S 16 + +/** SPI_MEM_DOUT_MODE_REG register + * MSPI flash output timing adjustment control register + */ +#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x18c) +/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S) +#define SPI_MEM_DOUT0_MODE_V 0x00000001U +#define SPI_MEM_DOUT0_MODE_S 0 +/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S) +#define SPI_MEM_DOUT1_MODE_V 0x00000001U +#define SPI_MEM_DOUT1_MODE_S 1 +/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S) +#define SPI_MEM_DOUT2_MODE_V 0x00000001U +#define SPI_MEM_DOUT2_MODE_S 2 +/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S) +#define SPI_MEM_DOUT3_MODE_V 0x00000001U +#define SPI_MEM_DOUT3_MODE_S 3 +/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S) +#define SPI_MEM_DOUT4_MODE_V 0x00000001U +#define SPI_MEM_DOUT4_MODE_S 4 +/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S) +#define SPI_MEM_DOUT5_MODE_V 0x00000001U +#define SPI_MEM_DOUT5_MODE_S 5 +/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S) +#define SPI_MEM_DOUT6_MODE_V 0x00000001U +#define SPI_MEM_DOUT6_MODE_S 6 +/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S) +#define SPI_MEM_DOUT7_MODE_V 0x00000001U +#define SPI_MEM_DOUT7_MODE_S 7 +/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S) +#define SPI_MEM_DOUTS_MODE_V 0x00000001U +#define SPI_MEM_DOUTS_MODE_S 8 + +/** SPI_SMEM_TIMING_CALI_REG register + * MSPI external RAM timing calibration register + */ +#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x190) +/** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ +#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) +#define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U +#define SPI_SMEM_TIMING_CLK_ENA_S 0 +/** SPI_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ +#define SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) +#define SPI_SMEM_TIMING_CALI_V 0x00000001U +#define SPI_SMEM_TIMING_CALI_S 1 +/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U +#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/** SPI_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ +#define SPI_SMEM_DLL_TIMING_CALI (BIT(5)) +#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) +#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U +#define SPI_SMEM_DLL_TIMING_CALI_S 5 + +/** SPI_SMEM_DIN_MODE_REG register + * MSPI external RAM input timing delay mode control register + */ +#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x194) +/** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN0_MODE 0x00000007U +#define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) +#define SPI_SMEM_DIN0_MODE_V 0x00000007U +#define SPI_SMEM_DIN0_MODE_S 0 +/** SPI_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN1_MODE 0x00000007U +#define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) +#define SPI_SMEM_DIN1_MODE_V 0x00000007U +#define SPI_SMEM_DIN1_MODE_S 3 +/** SPI_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN2_MODE 0x00000007U +#define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) +#define SPI_SMEM_DIN2_MODE_V 0x00000007U +#define SPI_SMEM_DIN2_MODE_S 6 +/** SPI_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN3_MODE 0x00000007U +#define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) +#define SPI_SMEM_DIN3_MODE_V 0x00000007U +#define SPI_SMEM_DIN3_MODE_S 9 +/** SPI_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN4_MODE 0x00000007U +#define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) +#define SPI_SMEM_DIN4_MODE_V 0x00000007U +#define SPI_SMEM_DIN4_MODE_S 12 +/** SPI_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN5_MODE 0x00000007U +#define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) +#define SPI_SMEM_DIN5_MODE_V 0x00000007U +#define SPI_SMEM_DIN5_MODE_S 15 +/** SPI_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN6_MODE 0x00000007U +#define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) +#define SPI_SMEM_DIN6_MODE_V 0x00000007U +#define SPI_SMEM_DIN6_MODE_S 18 +/** SPI_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DIN7_MODE 0x00000007U +#define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) +#define SPI_SMEM_DIN7_MODE_V 0x00000007U +#define SPI_SMEM_DIN7_MODE_S 21 +/** SPI_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ +#define SPI_SMEM_DINS_MODE 0x00000007U +#define SPI_SMEM_DINS_MODE_M (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S) +#define SPI_SMEM_DINS_MODE_V 0x00000007U +#define SPI_SMEM_DINS_MODE_S 24 + +/** SPI_SMEM_DIN_NUM_REG register + * MSPI external RAM input timing delay number control register + */ +#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x198) +/** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN0_NUM 0x00000003U +#define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) +#define SPI_SMEM_DIN0_NUM_V 0x00000003U +#define SPI_SMEM_DIN0_NUM_S 0 +/** SPI_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN1_NUM 0x00000003U +#define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) +#define SPI_SMEM_DIN1_NUM_V 0x00000003U +#define SPI_SMEM_DIN1_NUM_S 2 +/** SPI_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN2_NUM 0x00000003U +#define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) +#define SPI_SMEM_DIN2_NUM_V 0x00000003U +#define SPI_SMEM_DIN2_NUM_S 4 +/** SPI_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN3_NUM 0x00000003U +#define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) +#define SPI_SMEM_DIN3_NUM_V 0x00000003U +#define SPI_SMEM_DIN3_NUM_S 6 +/** SPI_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN4_NUM 0x00000003U +#define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) +#define SPI_SMEM_DIN4_NUM_V 0x00000003U +#define SPI_SMEM_DIN4_NUM_S 8 +/** SPI_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN5_NUM 0x00000003U +#define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) +#define SPI_SMEM_DIN5_NUM_V 0x00000003U +#define SPI_SMEM_DIN5_NUM_S 10 +/** SPI_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN6_NUM 0x00000003U +#define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) +#define SPI_SMEM_DIN6_NUM_V 0x00000003U +#define SPI_SMEM_DIN6_NUM_S 12 +/** SPI_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DIN7_NUM 0x00000003U +#define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) +#define SPI_SMEM_DIN7_NUM_V 0x00000003U +#define SPI_SMEM_DIN7_NUM_S 14 +/** SPI_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ +#define SPI_SMEM_DINS_NUM 0x00000003U +#define SPI_SMEM_DINS_NUM_M (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S) +#define SPI_SMEM_DINS_NUM_V 0x00000003U +#define SPI_SMEM_DINS_NUM_S 16 + +/** SPI_SMEM_DOUT_MODE_REG register + * MSPI external RAM output timing adjustment control register + */ +#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x19c) +/** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) +#define SPI_SMEM_DOUT0_MODE_V 0x00000001U +#define SPI_SMEM_DOUT0_MODE_S 0 +/** SPI_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) +#define SPI_SMEM_DOUT1_MODE_V 0x00000001U +#define SPI_SMEM_DOUT1_MODE_S 1 +/** SPI_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) +#define SPI_SMEM_DOUT2_MODE_V 0x00000001U +#define SPI_SMEM_DOUT2_MODE_S 2 +/** SPI_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) +#define SPI_SMEM_DOUT3_MODE_V 0x00000001U +#define SPI_SMEM_DOUT3_MODE_S 3 +/** SPI_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) +#define SPI_SMEM_DOUT4_MODE_V 0x00000001U +#define SPI_SMEM_DOUT4_MODE_S 4 +/** SPI_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) +#define SPI_SMEM_DOUT5_MODE_V 0x00000001U +#define SPI_SMEM_DOUT5_MODE_S 5 +/** SPI_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) +#define SPI_SMEM_DOUT6_MODE_V 0x00000001U +#define SPI_SMEM_DOUT6_MODE_S 6 +/** SPI_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) +#define SPI_SMEM_DOUT7_MODE_V 0x00000001U +#define SPI_SMEM_DOUT7_MODE_S 7 +/** SPI_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ +#define SPI_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_SMEM_DOUTS_MODE_M (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S) +#define SPI_SMEM_DOUTS_MODE_V 0x00000001U +#define SPI_SMEM_DOUTS_MODE_S 8 + +/** SPI_SMEM_AC_REG register + * MSPI external RAM ECC and SPI CS timing control register + */ +#define SPI_SMEM_AC_REG (DR_REG_SPI_BASE + 0x1a0) +/** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ +#define SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) +#define SPI_SMEM_CS_SETUP_V 0x00000001U +#define SPI_SMEM_CS_SETUP_S 0 +/** SPI_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ +#define SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) +#define SPI_SMEM_CS_HOLD_V 0x00000001U +#define SPI_SMEM_CS_HOLD_S 1 +/** SPI_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ +#define SPI_SMEM_CS_SETUP_TIME 0x0000001FU +#define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) +#define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU +#define SPI_SMEM_CS_SETUP_TIME_S 2 +/** SPI_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ +#define SPI_SMEM_CS_HOLD_TIME 0x0000001FU +#define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) +#define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU +#define SPI_SMEM_CS_HOLD_TIME_S 7 +/** SPI_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ +#define SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007U +#define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) +#define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U +#define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 +/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U +#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/** SPI_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ +#define SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) +#define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U +#define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 +/** SPI_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ +#define SPI_SMEM_CS_HOLD_DELAY 0x0000003FU +#define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) +#define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU +#define SPI_SMEM_CS_HOLD_DELAY_S 25 +/** SPI_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 1; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ +#define SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) +#define SPI_SMEM_SPLIT_TRANS_EN_M (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S) +#define SPI_SMEM_SPLIT_TRANS_EN_V 0x00000001U +#define SPI_SMEM_SPLIT_TRANS_EN_S 31 + +/** SPI_MEM_CLOCK_GATE_REG register + * SPI0 clock gate register + */ +#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_BASE + 0x200) +/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001U +#define SPI_CLK_EN_S 0 + +/** SPI_MEM_XTS_PLAIN_BASE_REG register + * The base address of the memory that stores plaintext in Manual Encryption + */ +#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPI_BASE + 0x300) +/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ +#define SPI_XTS_PLAIN 0xFFFFFFFFU +#define SPI_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) +#define SPI_XTS_PLAIN_V 0xFFFFFFFFU +#define SPI_XTS_PLAIN_S 0 + +/** SPI_MEM_XTS_LINESIZE_REG register + * Manual Encryption Line-Size register + */ +#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPI_BASE + 0x340) +/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ +#define SPI_XTS_LINESIZE 0x00000003U +#define SPI_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) +#define SPI_XTS_LINESIZE_V 0x00000003U +#define SPI_XTS_LINESIZE_S 0 + +/** SPI_MEM_XTS_DESTINATION_REG register + * Manual Encryption destination register + */ +#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPI_BASE + 0x344) +/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ +#define SPI_XTS_DESTINATION (BIT(0)) +#define SPI_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) +#define SPI_XTS_DESTINATION_V 0x00000001U +#define SPI_XTS_DESTINATION_S 0 + +/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPI_BASE + 0x348) +/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ +#define SPI_XTS_PHYSICAL_ADDRESS 0x03FFFFFFU +#define SPI_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) +#define SPI_XTS_PHYSICAL_ADDRESS_V 0x03FFFFFFU +#define SPI_XTS_PHYSICAL_ADDRESS_S 0 + +/** SPI_MEM_XTS_TRIGGER_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPI_BASE + 0x34c) +/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ +#define SPI_XTS_TRIGGER (BIT(0)) +#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) +#define SPI_XTS_TRIGGER_V 0x00000001U +#define SPI_XTS_TRIGGER_S 0 + +/** SPI_MEM_XTS_RELEASE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPI_BASE + 0x350) +/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ +#define SPI_XTS_RELEASE (BIT(0)) +#define SPI_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) +#define SPI_XTS_RELEASE_V 0x00000001U +#define SPI_XTS_RELEASE_S 0 + +/** SPI_MEM_XTS_DESTROY_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPI_BASE + 0x354) +/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ +#define SPI_XTS_DESTROY (BIT(0)) +#define SPI_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) +#define SPI_XTS_DESTROY_V 0x00000001U +#define SPI_XTS_DESTROY_S 0 + +/** SPI_MEM_XTS_STATE_REG register + * Manual Encryption physical address register + */ +#define SPI_MEM_XTS_STATE_REG (DR_REG_SPI_BASE + 0x358) +/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ +#define SPI_XTS_STATE 0x00000003U +#define SPI_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) +#define SPI_XTS_STATE_V 0x00000003U +#define SPI_XTS_STATE_S 0 + +/** SPI_MEM_XTS_DATE_REG register + * Manual Encryption version register + */ +#define SPI_MEM_XTS_DATE_REG (DR_REG_SPI_BASE + 0x35c) +/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176; + * This bits stores the last modified-time of manual encryption feature. + */ +#define SPI_XTS_DATE 0x3FFFFFFFU +#define SPI_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) +#define SPI_XTS_DATE_V 0x3FFFFFFFU +#define SPI_XTS_DATE_S 0 + +/** SPI_MEM_MMU_ITEM_CONTENT_REG register + * MSPI-MMU item content register + */ +#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPI_BASE + 0x37c) +/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ +#define SPI_MMU_ITEM_CONTENT 0xFFFFFFFFU +#define SPI_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) +#define SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFFU +#define SPI_MMU_ITEM_CONTENT_S 0 + +/** SPI_MEM_MMU_ITEM_INDEX_REG register + * MSPI-MMU item index register + */ +#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPI_BASE + 0x380) +/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ +#define SPI_MMU_ITEM_INDEX 0xFFFFFFFFU +#define SPI_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) +#define SPI_MMU_ITEM_INDEX_V 0xFFFFFFFFU +#define SPI_MMU_ITEM_INDEX_S 0 + +/** SPI_MEM_MMU_POWER_CTRL_REG register + * MSPI MMU power control register + */ +#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPI_BASE + 0x384) +/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ +#define SPI_MMU_MEM_FORCE_ON (BIT(0)) +#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) +#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U +#define SPI_MMU_MEM_FORCE_ON_S 0 +/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ +#define SPI_MMU_MEM_FORCE_PD (BIT(1)) +#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) +#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U +#define SPI_MMU_MEM_FORCE_PD_S 1 +/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ +#define SPI_MMU_MEM_FORCE_PU (BIT(2)) +#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) +#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U +#define SPI_MMU_MEM_FORCE_PU_S 2 +/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ +#define SPI_MMU_PAGE_SIZE 0x00000003U +#define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) +#define SPI_MMU_PAGE_SIZE_V 0x00000003U +#define SPI_MMU_PAGE_SIZE_S 3 +/** SPI_MEM_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ +#define SPI_MEM_AUX_CTRL 0x00003FFFU +#define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) +#define SPI_MEM_AUX_CTRL_V 0x00003FFFU +#define SPI_MEM_AUX_CTRL_S 16 + +/** SPI_MEM_DPA_CTRL_REG register + * SPI memory cryption DPA register + */ +#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPI_BASE + 0x388) +/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ +#define SPI_CRYPT_SECURITY_LEVEL 0x00000007U +#define SPI_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) +#define SPI_CRYPT_SECURITY_LEVEL_V 0x00000007U +#define SPI_CRYPT_SECURITY_LEVEL_S 0 +/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ +#define SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define SPI_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) +#define SPI_CRYPT_CALC_D_DPA_EN_V 0x00000001U +#define SPI_CRYPT_CALC_D_DPA_EN_S 3 +/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ +#define SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define SPI_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) +#define SPI_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U +#define SPI_CRYPT_DPA_SELECT_REGISTER_S 4 + +/** SPI_MEM_DATE_REG register + * SPI0 version control register + */ +#define SPI_MEM_DATE_REG (DR_REG_SPI_BASE + 0x3fc) +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36712560; + * SPI0 register version. + */ +#define SPI_MEM_DATE 0x0FFFFFFFU +#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) +#define SPI_MEM_DATE_V 0x0FFFFFFFU +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/spi_mem_struct.h b/components/soc/esp32c5/include/soc/spi_mem_struct.h new file mode 100644 index 0000000000..63de4bc6ee --- /dev/null +++ b/components/soc/esp32c5/include/soc/spi_mem_struct.h @@ -0,0 +1,2029 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Status and state control register */ +/** Type of mem_cmd register + * SPI0 FSM status register + */ +typedef union { + struct { + /** mem_mst_st : RO; bitpos: [3:0]; default: 0; + * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , + * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent + * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + */ + uint32_t mem_mst_st:4; + /** mem_slv_st : RO; bitpos: [7:4]; default: 0; + * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, + * 2: send command state, 3: send address state, 4: wait state, 5: read data state, + * 6:write data state, 7: done state, 8: read data end state. + */ + uint32_t mem_slv_st:4; + uint32_t reserved_8:10; + /** mem_usr : HRO; bitpos: [18]; default: 0; + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation + * will be triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + uint32_t mem_usr:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} spi_mem_cmd_reg_t; + +/** Type of mem_axi_err_addr register + * SPI0 AXI request error address. + */ +typedef union { + struct { + /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first AXI write/read invalid error or AXI write flash error + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + */ + uint32_t mem_axi_err_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_axi_err_addr_reg_t; + + +/** Group: Flash Control and configuration registers */ +/** Type of mem_ctrl register + * SPI0 control register. + */ +typedef union { + struct { + /** mem_wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_DQS is output by the MSPI controller. + */ + uint32_t mem_wdummy_dqs_always_out:1; + /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to flash, the level + * of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t mem_wdummy_always_out:1; + /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; + * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the first half part of dummy phase. It is used to + * mask invalid SPI_DQS in the half part of dummy phase. + */ + uint32_t mem_fdummy_rin:1; + /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; + * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is + * output by the MSPI controller in the second half part of dummy phase. It is used to + * pre-drive flash. + */ + uint32_t mem_fdummy_wout:1; + /** mem_fdout_oct : HRO; bitpos: [4]; default: 0; + * Apply 8 signals during write-data phase 1:enable 0: disable + */ + uint32_t mem_fdout_oct:1; + /** mem_fdin_oct : HRO; bitpos: [5]; default: 0; + * Apply 8 signals during read-data phase 1:enable 0: disable + */ + uint32_t mem_fdin_oct:1; + /** mem_faddr_oct : HRO; bitpos: [6]; default: 0; + * Apply 8 signals during address phase 1:enable 0: disable + */ + uint32_t mem_faddr_oct:1; + uint32_t reserved_7:1; + /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_quad:1; + /** mem_fcmd_oct : HRO; bitpos: [9]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + uint32_t mem_fcmd_oct:1; + uint32_t reserved_10:3; + /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + */ + uint32_t mem_fastrd_mode:1; + /** mem_fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_dual:1; + uint32_t reserved_15:3; + /** mem_q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + uint32_t mem_q_pol:1; + /** mem_d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + uint32_t mem_d_pol:1; + /** mem_fread_quad : R/W; bitpos: [20]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + */ + uint32_t mem_fread_quad:1; + /** mem_wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. + */ + uint32_t mem_wp_reg:1; + uint32_t reserved_22:1; + /** mem_fread_dio : R/W; bitpos: [23]; default: 0; + * In the read operations address phase and read-data phase apply 2 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_dio:1; + /** mem_fread_qio : R/W; bitpos: [24]; default: 0; + * In the read operations address phase and read-data phase apply 4 signals. 1: enable + * 0: disable. + */ + uint32_t mem_fread_qio:1; + uint32_t reserved_25:5; + /** mem_dqs_ie_always_on : HRO; bitpos: [30]; default: 0; + * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always + * 1. 0: Others. + */ + uint32_t mem_dqs_ie_always_on:1; + /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are + * always 1. 0: Others. + */ + uint32_t mem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_ctrl_reg_t; + +/** Type of mem_ctrl1 register + * SPI0 control1 register. + */ +typedef union { + struct { + /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is alwasy on. + */ + uint32_t mem_clk_mode:2; + uint32_t reserved_2:19; + /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply + * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t ar_size0_1_support_en:1; + /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + */ + uint32_t aw_size0_1_support_en:1; + /** axi_rdata_back_fast : HRO; bitpos: [23]; default: 1; + * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: + * Reply AXI read data to AXI bus when all the read data is available. + */ + uint32_t axi_rdata_back_fast:1; + /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; + * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY + * when there is a ECC error in AXI read data. The ECC error information is recorded + * in SPI_MEM_ECC_ERR_ADDR_REG. + */ + uint32_t mem_rresp_ecc_err_en:1; + /** mem_ar_splice_en : HRO; bitpos: [25]; default: 0; + * Set this bit to enable AXI Read Splice-transfer. + */ + uint32_t mem_ar_splice_en:1; + /** mem_aw_splice_en : HRO; bitpos: [26]; default: 0; + * Set this bit to enable AXI Write Splice-transfer. + */ + uint32_t mem_aw_splice_en:1; + /** mem_ram0_en : HRO; bitpos: [27]; default: 1; + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * accessed at the same time. + */ + uint32_t mem_ram0_en:1; + /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; + * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the + * same time. + */ + uint32_t mem_dual_ram_en:1; + /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; + * Set this bit to write data faster, do not wait write data has been stored in + * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored + * in tx_bus_fifo_l2. + */ + uint32_t mem_fast_write_en:1; + /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; + * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to + * receive signals from AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_rxfifo_rst:1; + /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; + * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to + * send signals to AXI. Set this bit to reset these FIFO. + */ + uint32_t mem_txfifo_rst:1; + }; + uint32_t val; +} spi_mem_ctrl1_reg_t; + +/** Type of mem_ctrl2 register + * SPI0 control2 register. + */ +typedef union { + struct { + /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; + * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with + * SPI_MEM_CS_SETUP bit. + */ + uint32_t mem_cs_setup_time:5; + /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; + * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with + * SPI_MEM_CS_HOLD bit. + */ + uint32_t mem_cs_hold_time:5; + /** mem_ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * mode when accessed flash. + */ + uint32_t mem_ecc_cs_hold_time:3; + /** mem_ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; + * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when + * accesses flash. + */ + uint32_t mem_ecc_skip_page_corner:1; + /** mem_ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses flash. + */ + uint32_t mem_ecc_16to18_byte_en:1; + uint32_t reserved_15:9; + /** mem_split_trans_en : R/W; bitpos: [24]; default: 1; + * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI + * transfers when one transfer will cross flash or EXT_RAM page corner, valid no + * matter whether there is an ECC region or not. + */ + uint32_t mem_split_trans_en:1; + /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI + * core clock cycles. + */ + uint32_t mem_cs_hold_delay:6; + /** mem_sync_reset : WT; bitpos: [31]; default: 0; + * The spi0_mst_st and spi0_slv_st will be reset. + */ + uint32_t mem_sync_reset:1; + }; + uint32_t val; +} spi_mem_ctrl2_reg_t; + +/** Type of mem_misc register + * SPI0 misc register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; + * For SPI0, flash is connected to SUBPINs. + */ + uint32_t mem_fsub_pin:1; + /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; + * For SPI0, sram is connected to SUBPINs. + */ + uint32_t mem_ssub_pin:1; + /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; + * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + */ + uint32_t mem_ck_idle_edge:1; + /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; + * SPI_CS line keep low when the bit is set. + */ + uint32_t mem_cs_keep_active:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} spi_mem_misc_reg_t; + +/** Type of mem_cache_fctrl register + * SPI0 bit mode control register. + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** same_aw_ar_addr_chk_en : HRO; bitpos: [30]; default: 1; + * Set this bit to check AXI read/write the same address region. + */ + uint32_t same_aw_ar_addr_chk_en:1; + /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; + * Set this bit to close AXI read/write transfer to MSPI, which means that only + * SLV_ERR will be replied to BRESP/RRESP. + */ + uint32_t close_axi_inf_en:1; + }; + uint32_t val; +} spi_mem_cache_fctrl_reg_t; + +/** Type of mem_ddr register + * SPI0 flash DDR mode control register + */ +typedef union { + struct { + /** fmem_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t fmem_ddr_en:1; + /** fmem_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t fmem_var_dummy:1; + /** fmem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_rdat_swp:1; + /** fmem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t fmem_ddr_wdat_swp:1; + /** fmem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t fmem_ddr_cmd_dis:1; + /** fmem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the panda device. + */ + uint32_t fmem_outminbytelen:7; + /** fmem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to flash. + */ + uint32_t fmem_tx_ddr_msk_en:1; + /** fmem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to flash. + */ + uint32_t fmem_rx_ddr_msk_en:1; + /** fmem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t fmem_usr_ddr_dqs_thd:7; + /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t fmem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** fmem_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t fmem_clk_diff_en:1; + uint32_t reserved_25:1; + /** fmem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t fmem_dqs_ca_in:1; + /** fmem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t fmem_hyperbus_dummy_2x:1; + /** fmem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to flash. . + */ + uint32_t fmem_clk_diff_inv:1; + /** fmem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + uint32_t fmem_octa_ram_addr:1; + /** fmem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to flash, which means + * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t fmem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_mem_ddr_reg_t; + + +/** Group: Clock control and configuration registers */ +/** Type of mem_clock register + * SPI clock division control register. + */ +typedef union { + struct { + /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; + * In the master mode it must be equal to spi_mem_clkcnt_N. + */ + uint32_t mem_clkcnt_l:8; + /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; + * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + */ + uint32_t mem_clkcnt_h:8; + /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(spi_mem_clkcnt_N+1) + */ + uint32_t mem_clkcnt_n:8; + uint32_t reserved_24:7; + /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module + * clock. + */ + uint32_t mem_clk_equ_sysclk:1; + }; + uint32_t val; +} spi_mem_clock_reg_t; + +/** Type of mem_clock_gate register + * SPI0 clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Register clock gate enable signal. 1: Enable. 0: Disable. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_clock_gate_reg_t; + + +/** Group: Flash User-defined control registers */ +/** Type of mem_user register + * SPI0 user register. + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** mem_cs_hold : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t mem_cs_hold:1; + /** mem_cs_setup : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ + uint32_t mem_cs_setup:1; + uint32_t reserved_8:1; + /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + */ + uint32_t mem_ck_out_edge:1; + uint32_t reserved_10:16; + /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ + uint32_t mem_usr_dummy_idle:1; + uint32_t reserved_27:2; + /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + uint32_t mem_usr_dummy:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_user_reg_t; + +/** Type of mem_user1 register + * SPI0 user1 register. + */ +typedef union { + struct { + /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + * The length in spi_mem_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + uint32_t mem_usr_dummy_cyclelen:6; + /** mem_usr_dbytelen : HRO; bitpos: [8:6]; default: 1; + * SPI0 USR_CMD read or write data byte length -1 + */ + uint32_t mem_usr_dbytelen:3; + uint32_t reserved_9:17; + /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). + */ + uint32_t mem_usr_addr_bitlen:6; + }; + uint32_t val; +} spi_mem_user1_reg_t; + +/** Type of mem_user2 register + * SPI0 user2 register. + */ +typedef union { + struct { + /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + uint32_t mem_usr_command_value:16; + uint32_t reserved_16:12; + /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1) + */ + uint32_t mem_usr_command_bitlen:4; + }; + uint32_t val; +} spi_mem_user2_reg_t; + + +/** Group: External RAM Control and configuration registers */ +/** Type of mem_sram_cmd register + * SPI0 external RAM mode control register + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** smem_wdummy_dqs_always_out : HRO; bitpos: [24]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_DQS is output by the MSPI controller. + */ + uint32_t smem_wdummy_dqs_always_out:1; + /** smem_wdummy_always_out : HRO; bitpos: [25]; default: 0; + * In the dummy phase of an MSPI write data transfer when accesses to external RAM, + * the level of SPI_IO[7:0] is output by the MSPI controller. + */ + uint32_t smem_wdummy_always_out:1; + uint32_t reserved_26:4; + /** smem_dqs_ie_always_on : HRO; bitpos: [30]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are + * always 1. 0: Others. + */ + uint32_t smem_dqs_ie_always_on:1; + /** smem_data_ie_always_on : HRO; bitpos: [31]; default: 1; + * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] + * are always 1. 0: Others. + */ + uint32_t smem_data_ie_always_on:1; + }; + uint32_t val; +} spi_mem_sram_cmd_reg_t; + +/** Type of smem_ddr register + * SPI0 external RAM DDR mode control register + */ +typedef union { + struct { + /** smem_ddr_en : HRO; bitpos: [0]; default: 0; + * 1: in DDR mode, 0 in SDR mode + */ + uint32_t smem_ddr_en:1; + /** smem_var_dummy : HRO; bitpos: [1]; default: 0; + * Set the bit to enable variable dummy cycle in spi DDR mode. + */ + uint32_t smem_var_dummy:1; + /** smem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + * Set the bit to reorder rx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_rdat_swp:1; + /** smem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + * Set the bit to reorder tx data of the word in spi DDR mode. + */ + uint32_t smem_ddr_wdat_swp:1; + /** smem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + * the bit is used to disable dual edge in command phase when DDR mode. + */ + uint32_t smem_ddr_cmd_dis:1; + /** smem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + * It is the minimum output data length in the DDR psram. + */ + uint32_t smem_outminbytelen:7; + /** smem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when + * accesses to external RAM. + */ + uint32_t smem_tx_ddr_msk_en:1; + /** smem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when + * accesses to external RAM. + */ + uint32_t smem_rx_ddr_msk_en:1; + /** smem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + * The delay number of data strobe which from memory based on SPI clock. + */ + uint32_t smem_usr_ddr_dqs_thd:7; + /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or + * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and + * negative edge of SPI_DQS. + */ + uint32_t smem_ddr_dqs_loop:1; + uint32_t reserved_22:2; + /** smem_clk_diff_en : HRO; bitpos: [24]; default: 0; + * Set this bit to enable the differential SPI_CLK#. + */ + uint32_t smem_clk_diff_en:1; + uint32_t reserved_25:1; + /** smem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + */ + uint32_t smem_dqs_ca_in:1; + /** smem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 + * accesses flash or SPI1 accesses flash or sram. + */ + uint32_t smem_hyperbus_dummy_2x:1; + /** smem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + * Set this bit to invert SPI_DIFF when accesses to external RAM. . + */ + uint32_t smem_clk_diff_inv:1; + /** smem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + * Set this bit to enable octa_ram address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], + * 1'b0}. + */ + uint32_t smem_octa_ram_addr:1; + /** smem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + * Set this bit to enable HyperRAM address out when accesses to external RAM, which + * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + */ + uint32_t smem_hyperbus_ca:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_smem_ddr_reg_t; + +/** Type of smem_ac register + * MSPI external RAM ECC and SPI CS timing control register + */ +typedef union { + struct { + /** smem_cs_setup : HRO; bitpos: [0]; default: 0; + * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: + * disable. + */ + uint32_t smem_cs_setup:1; + /** smem_cs_hold : HRO; bitpos: [1]; default: 0; + * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + uint32_t smem_cs_hold:1; + /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1; + * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_mem_cs_setup bit. + */ + uint32_t smem_cs_setup_time:5; + /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1; + * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are + * combined with spi_mem_cs_hold bit. + */ + uint32_t smem_cs_hold_time:5; + /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * cycles in ECC mode when accessed external RAM. + */ + uint32_t smem_ecc_cs_hold_time:3; + /** smem_ecc_skip_page_corner : HRO; bitpos: [15]; default: 1; + * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when + * accesses external RAM. + */ + uint32_t smem_ecc_skip_page_corner:1; + /** smem_ecc_16to18_byte_en : HRO; bitpos: [16]; default: 0; + * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when + * accesses external RAM. + */ + uint32_t smem_ecc_16to18_byte_en:1; + uint32_t reserved_17:8; + /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0; + * These bits are used to set the minimum CS high time tSHSL between SPI burst + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) + * MSPI core clock cycles. + */ + uint32_t smem_cs_hold_delay:6; + /** smem_split_trans_en : HRO; bitpos: [31]; default: 1; + * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI + * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter + * whether there is an ECC region or not. + */ + uint32_t smem_split_trans_en:1; + }; + uint32_t val; +} spi_smem_ac_reg_t; + + +/** Group: State control register */ +/** Type of mem_fsm register + * SPI0 FSM status register + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + */ + uint32_t mem_lock_delay_time:5; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_fsm_reg_t; + + +/** Group: Interrupt registers */ +/** Type of mem_int_ena register + * SPI0 interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_ena:1; + /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_ena:1; + /** mem_ecc_err_int_ena : HRO; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_ena:1; + /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_ena:1; + /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_ena:1; + /** mem_axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_ena:1; + /** mem_axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int__ena:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_int_ena_reg_t; + +/** Type of mem_int_clr register + * SPI0 interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_clr:1; + /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_clr:1; + /** mem_ecc_err_int_clr : HRO; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_clr:1; + /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_clr:1; + /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_clr:1; + /** mem_axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_clr:1; + /** mem_axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_clr:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_int_clr_reg_t; + +/** Type of mem_int_raw register + * SPI0 interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * changed from non idle state to idle state. It means that SPI_CS raises high. 0: + * Others + */ + uint32_t mem_slv_st_end_int_raw:1; + /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * changed from non idle state to idle state. 0: Others. + */ + uint32_t mem_mst_st_end_int_raw:1; + /** mem_ecc_err_int_raw : HRO; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is + * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * of SPI0/1 ECC read external RAM and flash are equal or bigger than + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + * are cleared, this bit will not be triggered. + */ + uint32_t mem_ecc_err_int_raw:1; + /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * rejected. 0: Others. + */ + uint32_t mem_pms_reject_int_raw:1; + /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_raddr_err_int_raw:1; + /** mem_axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * flash request is received. 0: Others. + */ + uint32_t mem_axi_wr_flash_err_int_raw:1; + /** mem_axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * address is invalid by compared to MMU configuration. 0: Others. + */ + uint32_t mem_axi_waddr_err_int_raw:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_int_raw_reg_t; + +/** Type of mem_int_st register + * SPI0 interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + */ + uint32_t mem_slv_st_end_int_st:1; + /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. + */ + uint32_t mem_mst_st_end_int_st:1; + /** mem_ecc_err_int_st : HRO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t mem_ecc_err_int_st:1; + /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + */ + uint32_t mem_pms_reject_int_st:1; + /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_raddr_err_int_st:1; + /** mem_axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + */ + uint32_t mem_axi_wr_flash_err_int_st:1; + /** mem_axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + */ + uint32_t mem_axi_waddr_err_int_st:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_mem_int_st_reg_t; + + +/** Group: PMS control and configuration registers */ +/** Type of fmem_pmsn_attr register + * MSPI flash PMS section n attribute register + */ +typedef union { + struct { + /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_rd_attr:1; + /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. + */ + uint32_t fmem_pmsn_wr_attr:1; + /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS + * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and + * SPI_FMEM_PMSn_SIZE_REG. + */ + uint32_t fmem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_fmem_pmsn_attr_reg_t; + +/** Type of fmem_pmsn_addr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 flash PMS section n start address value + */ + uint32_t fmem_pmsn_addr_s:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_fmem_pmsn_addr_reg_t; + +/** Type of fmem_pmsn_size register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, + * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) + */ + uint32_t fmem_pmsn_size:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_fmem_pmsn_size_reg_t; + +/** Type of smem_pmsn_attr register + * SPI1 flash PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; + * 1: SPI1 external RAM PMS section n read accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_rd_attr:1; + /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; + * 1: SPI1 external RAM PMS section n write accessible. 0: Not allowed. + */ + uint32_t smem_pmsn_wr_attr:1; + /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; + * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The + * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and + * SPI_SMEM_PMSn_SIZE_REG. + */ + uint32_t smem_pmsn_ecc:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_smem_pmsn_attr_reg_t; + +/** Type of smem_pmsn_addr register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + * SPI1 external RAM PMS section n start address value + */ + uint32_t smem_pmsn_addr_s:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_smem_pmsn_addr_reg_t; + +/** Type of smem_pmsn_size register + * SPI1 external RAM PMS section n start address register + */ +typedef union { + struct { + /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, + * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) + */ + uint32_t smem_pmsn_size:15; + uint32_t reserved_15:17; + }; + uint32_t val; +} spi_smem_pmsn_size_reg_t; + +/** Type of mem_pms_reject register + * SPI1 access reject register + */ +typedef union { + struct { + /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_reject_addr:27; + /** mem_pm_en : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI0/1 transfer permission control function. + */ + uint32_t mem_pm_en:1; + /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; + * 1: SPI1 write access error. 0: No write access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ld:1; + /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; + * 1: SPI1 read access error. 0: No read access error. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_st:1; + /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; + * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_multi_hit:1; + /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; + * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_pms_ivd:1; + }; + uint32_t val; +} spi_mem_pms_reject_reg_t; + + +/** Group: MSPI ECC registers */ +/** Type of mem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** mem_ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; + * This bits show the error times of MSPI ECC read. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_cnt:6; + /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + */ + uint32_t fmem_ecc_err_int_num:6; + /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + */ + uint32_t fmem_ecc_err_int_en:1; + /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ + uint32_t fmem_page_size:2; + /** fmem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit + * should be 0. Otherwise, this bit should be 1. + */ + uint32_t fmem_ecc_addr_en:1; + /** mem_usr_ecc_addr_en : HRO; bitpos: [21]; default: 0; + * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + */ + uint32_t mem_usr_ecc_addr_en:1; + uint32_t reserved_22:2; + /** mem_ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + */ + uint32_t mem_ecc_continue_record_err_en:1; + /** mem_ecc_err_bits : HRO; bitpos: [31:25]; default: 0; + * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to + * byte 0 bit 0 to byte 15 bit 7) + */ + uint32_t mem_ecc_err_bits:7; + }; + uint32_t val; +} spi_mem_ecc_ctrl_reg_t; + +/** Type of mem_ecc_err_addr register + * MSPI ECC error address register + */ +typedef union { + struct { + /** mem_ecc_err_addr : HRO; bitpos: [26:0]; default: 0; + * This bits show the first MSPI ECC error address. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + uint32_t mem_ecc_err_addr:27; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_ecc_err_addr_reg_t; + +/** Type of smem_ecc_ctrl register + * MSPI ECC control register + */ +typedef union { + struct { + uint32_t reserved_0:17; + /** smem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + * Set this bit to calculate the error times of MSPI ECC read when accesses to + * external RAM. + */ + uint32_t smem_ecc_err_int_en:1; + /** smem_page_size : HRO; bitpos: [19:18]; default: 2; + * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. + * 2: 1024 bytes. 3: 2048 bytes. + */ + uint32_t smem_page_size:2; + /** smem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the + * ECC region or non-ECC region of external RAM. If there is no ECC region in external + * RAM, this bit should be 0. Otherwise, this bit should be 1. + */ + uint32_t smem_ecc_addr_en:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_smem_ecc_ctrl_reg_t; + + +/** Group: Status and state control registers */ +/** Type of smem_axi_addr_ctrl register + * SPI0 AXI address control register + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; + * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers + * and SPI0 transfers are done. 0: Others. + */ + uint32_t mem_all_fifo_empty:1; + /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; + * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t rdata_afifo_rempty:1; + /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; + * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + */ + uint32_t raddr_afifo_rempty:1; + /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; + * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wdata_afifo_rempty:1; + /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; + * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + */ + uint32_t wblen_afifo_rempty:1; + /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; + * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and + * RDATA_AFIFO are empty and spi0_mst_st is IDLE. + */ + uint32_t all_axi_trans_afifo_empty:1; + }; + uint32_t val; +} spi_smem_axi_addr_ctrl_reg_t; + +/** Type of mem_axi_err_resp_en register + * SPI0 AXI error response enable register + */ +typedef union { + struct { + /** mem_aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_vld:1; + /** mem_aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_gid:1; + /** mem_aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_size:1; + /** mem_aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0; + * Set this bit to enable AXI response function for axi flash err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_flash:1; + /** mem_aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_ecc:1; + /** mem_aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0; + * Set this bit to enable AXI response function for mmu sens in err axi write trans. + */ + uint32_t mem_aw_resp_en_mmu_sens:1; + /** mem_aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0; + * Set this bit to enable AXI response function for axi wstrb err in axi write trans. + */ + uint32_t mem_aw_resp_en_axi_wstrb:1; + /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; + * Set this bit to enable AXI response function for mmu valid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_vld:1; + /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; + * Set this bit to enable AXI response function for mmu gid err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_gid:1; + /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; + * Set this bit to enable AXI response function for mmu ecc err in axi read trans. + */ + uint32_t mem_ar_resp_en_mmu_ecc:1; + /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; + * Set this bit to enable AXI response function for mmu sensitive err in axi read + * trans. + */ + uint32_t mem_ar_resp_en_mmu_sens:1; + /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; + * Set this bit to enable AXI response function for axi size err in axi read trans. + */ + uint32_t mem_ar_resp_en_axi_size:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} spi_mem_axi_err_resp_en_reg_t; + + +/** Group: Flash timing registers */ +/** Type of mem_timing_cali register + * SPI0 flash timing calibration register + */ +typedef union { + struct { + /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + * The bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t mem_timing_clk_ena:1; + /** mem_timing_cali : R/W; bitpos: [1]; default: 0; + * The bit is used to enable timing auto-calibration for all reading operations. + */ + uint32_t mem_timing_cali:1; + /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + * add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t mem_extra_dummy_cyclelen:3; + /** mem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * flash. + */ + uint32_t mem_dll_timing_cali:1; + /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; + * Set this bit to update delay mode, delay num and extra dummy in MSPI. + */ + uint32_t mem_timing_cali_update:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} spi_mem_timing_cali_reg_t; + +/** Type of mem_din_mode register + * MSPI flash input timing delay mode control register + */ +typedef union { + struct { + /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din0_mode:3; + /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din1_mode:3; + /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din2_mode:3; + /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t mem_din3_mode:3; + /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din4_mode:3; + /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din5_mode:3; + /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din6_mode:3; + /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_din7_mode:3; + /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk + */ + uint32_t mem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_mem_din_mode_reg_t; + +/** Type of mem_din_num register + * MSPI flash input timing delay number control register + */ +typedef union { + struct { + /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din0_num:2; + /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din1_num:2; + /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din2_num:2; + /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din3_num:2; + /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din4_num:2; + /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din5_num:2; + /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din6_num:2; + /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_din7_num:2; + /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t mem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_mem_din_num_reg_t; + +/** Type of mem_dout_mode register + * MSPI flash output timing adjustment control register + */ +typedef union { + struct { + /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout0_mode:1; + /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout1_mode:1; + /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout2_mode:1; + /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t mem_dout3_mode:1; + /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout4_mode:1; + /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout5_mode:1; + /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout6_mode:1; + /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_dout7_mode:1; + /** mem_douts_mode : R/W; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk + */ + uint32_t mem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_mem_dout_mode_reg_t; + + +/** Group: External RAM timing registers */ +/** Type of smem_timing_cali register + * MSPI external RAM timing calibration register + */ +typedef union { + struct { + /** smem_timing_clk_ena : HRO; bitpos: [0]; default: 1; + * For sram, the bit is used to enable timing adjust clock for all reading operations. + */ + uint32_t smem_timing_clk_ena:1; + /** smem_timing_cali : HRO; bitpos: [1]; default: 0; + * For sram, the bit is used to enable timing auto-calibration for all reading + * operations. + */ + uint32_t smem_timing_cali:1; + /** smem_extra_dummy_cyclelen : HRO; bitpos: [4:2]; default: 0; + * For sram, add extra dummy spi clock cycle length for spi clock calibration. + */ + uint32_t smem_extra_dummy_cyclelen:3; + /** smem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + * Set this bit to enable DLL for timing calibration in DDR mode when accessed to + * EXT_RAM. + */ + uint32_t smem_dll_timing_cali:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} spi_smem_timing_cali_reg_t; + +/** Type of smem_din_mode register + * MSPI external RAM input timing delay mode control register + */ +typedef union { + struct { + /** smem_din0_mode : HRO; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din0_mode:3; + /** smem_din1_mode : HRO; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din1_mode:3; + /** smem_din2_mode : HRO; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din2_mode:3; + /** smem_din3_mode : HRO; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din3_mode:3; + /** smem_din4_mode : HRO; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din4_mode:3; + /** smem_din5_mode : HRO; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din5_mode:3; + /** smem_din6_mode : HRO; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din6_mode:3; + /** smem_din7_mode : HRO; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_din7_mode:3; + /** smem_dins_mode : HRO; bitpos: [26:24]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the + * spi_clk high edge, 6: input with the spi_clk low edge + */ + uint32_t smem_dins_mode:3; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_smem_din_mode_reg_t; + +/** Type of smem_din_num register + * MSPI external RAM input timing delay number control register + */ +typedef union { + struct { + /** smem_din0_num : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din0_num:2; + /** smem_din1_num : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din1_num:2; + /** smem_din2_num : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din2_num:2; + /** smem_din3_num : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din3_num:2; + /** smem_din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din4_num:2; + /** smem_din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din5_num:2; + /** smem_din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din6_num:2; + /** smem_din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_din7_num:2; + /** smem_dins_num : HRO; bitpos: [17:16]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... + */ + uint32_t smem_dins_num:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_smem_din_num_reg_t; + +/** Type of smem_dout_mode register + * MSPI external RAM output timing adjustment control register + */ +typedef union { + struct { + /** smem_dout0_mode : HRO; bitpos: [0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout0_mode:1; + /** smem_dout1_mode : HRO; bitpos: [1]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout1_mode:1; + /** smem_dout2_mode : HRO; bitpos: [2]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout2_mode:1; + /** smem_dout3_mode : HRO; bitpos: [3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout3_mode:1; + /** smem_dout4_mode : HRO; bitpos: [4]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout4_mode:1; + /** smem_dout5_mode : HRO; bitpos: [5]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout5_mode:1; + /** smem_dout6_mode : HRO; bitpos: [6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout6_mode:1; + /** smem_dout7_mode : HRO; bitpos: [7]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_dout7_mode:1; + /** smem_douts_mode : HRO; bitpos: [8]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output + * with the spi_clk high edge ,6: output with the spi_clk low edge + */ + uint32_t smem_douts_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_smem_dout_mode_reg_t; + + +/** Group: Manual Encryption plaintext Memory */ +/** Type of mem_xts_plain_base register + * The base address of the memory that stores plaintext in Manual Encryption + */ +typedef union { + struct { + /** xts_plain : R/W; bitpos: [31:0]; default: 0; + * This field is only used to generate include file in c case. This field is useless. + * Please do not use this field. + */ + uint32_t xts_plain:32; + }; + uint32_t val; +} spi_mem_xts_plain_base_reg_t; + + +/** Group: Manual Encryption configuration registers */ +/** Type of mem_xts_linesize register + * Manual Encryption Line-Size register + */ +typedef union { + struct { + /** xts_linesize : R/W; bitpos: [1:0]; default: 0; + * This bits stores the line-size parameter which will be used in manual encryption + * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: + * 32-bytes, 2: 64-bytes, 3:reserved. + */ + uint32_t xts_linesize:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_xts_linesize_reg_t; + +/** Type of mem_xts_destination register + * Manual Encryption destination register + */ +typedef union { + struct { + /** xts_destination : R/W; bitpos: [0]; default: 0; + * This bit stores the destination parameter which will be used in manual encryption + * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + */ + uint32_t xts_destination:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_destination_reg_t; + +/** Type of mem_xts_physical_address register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_physical_address : R/W; bitpos: [25:0]; default: 0; + * This bits stores the physical-address parameter which will be used in manual + * encryption calculation. This value should aligned with byte number decided by + * line-size parameter. + */ + uint32_t xts_physical_address:26; + uint32_t reserved_26:6; + }; + uint32_t val; +} spi_mem_xts_physical_address_reg_t; + + +/** Group: Manual Encryption control and status registers */ +/** Type of mem_xts_trigger register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_trigger : WT; bitpos: [0]; default: 0; + * Set this bit to trigger the process of manual encryption calculation. This action + * should only be asserted when manual encryption status is 0. After this action, + * manual encryption status becomes 1. After calculation is done, manual encryption + * status becomes 2. + */ + uint32_t xts_trigger:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_trigger_reg_t; + +/** Type of mem_xts_release register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_release : WT; bitpos: [0]; default: 0; + * Set this bit to release encrypted result to mspi. This action should only be + * asserted when manual encryption status is 2. After this action, manual encryption + * status will become 3. + */ + uint32_t xts_release:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_release_reg_t; + +/** Type of mem_xts_destroy register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_destroy : WT; bitpos: [0]; default: 0; + * Set this bit to destroy encrypted result. This action should be asserted only when + * manual encryption status is 3. After this action, manual encryption status will + * become 0. + */ + uint32_t xts_destroy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} spi_mem_xts_destroy_reg_t; + +/** Type of mem_xts_state register + * Manual Encryption physical address register + */ +typedef union { + struct { + /** xts_state : RO; bitpos: [1:0]; default: 0; + * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + * calculation, 2: encryption calculation is done but the encrypted result is + * invisible to mspi, 3: the encrypted result is visible to mspi. + */ + uint32_t xts_state:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} spi_mem_xts_state_reg_t; + + +/** Group: Manual Encryption version control register */ +/** Type of mem_xts_date register + * Manual Encryption version register + */ +typedef union { + struct { + /** xts_date : R/W; bitpos: [29:0]; default: 538972176; + * This bits stores the last modified-time of manual encryption feature. + */ + uint32_t xts_date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_xts_date_reg_t; + + +/** Group: MMU access registers */ +/** Type of mem_mmu_item_content register + * MSPI-MMU item content register + */ +typedef union { + struct { + /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; + * MSPI-MMU item content + */ + uint32_t mmu_item_content:32; + }; + uint32_t val; +} spi_mem_mmu_item_content_reg_t; + +/** Type of mem_mmu_item_index register + * MSPI-MMU item index register + */ +typedef union { + struct { + /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; + * MSPI-MMU item index + */ + uint32_t mmu_item_index:32; + }; + uint32_t val; +} spi_mem_mmu_item_index_reg_t; + + +/** Group: MMU power control and configuration registers */ +/** Type of mem_mmu_power_ctrl register + * MSPI MMU power control register + */ +typedef union { + struct { + /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; + * Set this bit to enable mmu-memory clock force on + */ + uint32_t mmu_mem_force_on:1; + /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; + * Set this bit to force mmu-memory powerdown + */ + uint32_t mmu_mem_force_pd:1; + /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; + * Set this bit to force mmu-memory powerup, in this case, the power should also be + * controlled by rtc. + */ + uint32_t mmu_mem_force_pu:1; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; + * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 + */ + uint32_t mmu_page_size:2; + uint32_t reserved_5:11; + /** mem_aux_ctrl : HRO; bitpos: [29:16]; default: 4896; + * MMU PSRAM aux control register + */ + uint32_t mem_aux_ctrl:14; + uint32_t reserved_30:2; + }; + uint32_t val; +} spi_mem_mmu_power_ctrl_reg_t; + + +/** Group: External mem cryption DPA registers */ +/** Type of mem_dpa_ctrl register + * SPI memory cryption DPA register + */ +typedef union { + struct { + /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; + * Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: + * The bigger the number is, the more secure the cryption is. (Note that the + * performance of cryption will decrease together with this number increasing) + */ + uint32_t crypt_security_level:3; + /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; + * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the + * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that + * using key 1. + */ + uint32_t crypt_calc_d_dpa_en:1; + /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; + * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and + * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + */ + uint32_t crypt_dpa_select_register:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} spi_mem_dpa_ctrl_reg_t; + + +/** Group: Version control register */ +/** Type of mem_date register + * SPI0 version control register + */ +typedef union { + struct { + /** mem_date : R/W; bitpos: [27:0]; default: 36712560; + * SPI0 register version. + */ + uint32_t mem_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_mem_date_reg_t; + + +typedef struct { + volatile spi_mem_cmd_reg_t mem_cmd; + uint32_t reserved_004; + volatile spi_mem_ctrl_reg_t mem_ctrl; + volatile spi_mem_ctrl1_reg_t mem_ctrl1; + volatile spi_mem_ctrl2_reg_t mem_ctrl2; + volatile spi_mem_clock_reg_t mem_clock; + volatile spi_mem_user_reg_t mem_user; + volatile spi_mem_user1_reg_t mem_user1; + volatile spi_mem_user2_reg_t mem_user2; + uint32_t reserved_024[4]; + volatile spi_mem_misc_reg_t mem_misc; + uint32_t reserved_038; + volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl; + uint32_t reserved_040; + volatile spi_mem_sram_cmd_reg_t mem_sram_cmd; + uint32_t reserved_048[3]; + volatile spi_mem_fsm_reg_t mem_fsm; + uint32_t reserved_058[26]; + volatile spi_mem_int_ena_reg_t mem_int_ena; + volatile spi_mem_int_clr_reg_t mem_int_clr; + volatile spi_mem_int_raw_reg_t mem_int_raw; + volatile spi_mem_int_st_reg_t mem_int_st; + uint32_t reserved_0d0; + volatile spi_mem_ddr_reg_t mem_ddr; + volatile spi_smem_ddr_reg_t smem_ddr; + uint32_t reserved_0dc[9]; + volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; + volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; + volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; + volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; + uint32_t reserved_160; + volatile spi_mem_pms_reject_reg_t mem_pms_reject; + volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl; + volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr; + volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr; + volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en; + volatile spi_mem_timing_cali_reg_t mem_timing_cali; + volatile spi_mem_din_mode_reg_t mem_din_mode; + volatile spi_mem_din_num_reg_t mem_din_num; + volatile spi_mem_dout_mode_reg_t mem_dout_mode; + volatile spi_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_smem_din_mode_reg_t smem_din_mode; + volatile spi_smem_din_num_reg_t smem_din_num; + volatile spi_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_smem_ac_reg_t smem_ac; + uint32_t reserved_1a4[23]; + volatile spi_mem_clock_gate_reg_t mem_clock_gate; + uint32_t reserved_204[63]; + volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base; + uint32_t reserved_304[15]; + volatile spi_mem_xts_linesize_reg_t mem_xts_linesize; + volatile spi_mem_xts_destination_reg_t mem_xts_destination; + volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address; + volatile spi_mem_xts_trigger_reg_t mem_xts_trigger; + volatile spi_mem_xts_release_reg_t mem_xts_release; + volatile spi_mem_xts_destroy_reg_t mem_xts_destroy; + volatile spi_mem_xts_state_reg_t mem_xts_state; + volatile spi_mem_xts_date_reg_t mem_xts_date; + uint32_t reserved_360[7]; + volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content; + volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index; + volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; + volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl; + uint32_t reserved_38c[28]; + volatile spi_mem_date_reg_t mem_date; +} spi_mem_dev_t; + +extern spi_mem_dev_t SPIMEM0; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/tee_reg.h b/components/soc/esp32c5/include/soc/tee_reg.h new file mode 100644 index 0000000000..3e083c2e23 --- /dev/null +++ b/components/soc/esp32c5/include/soc/tee_reg.h @@ -0,0 +1,680 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_M0_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M0_MODE 0x00000003U +#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) +#define TEE_M0_MODE_V 0x00000003U +#define TEE_M0_MODE_S 0 +/** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M0_LOCK (BIT(2)) +#define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S) +#define TEE_M0_LOCK_V 0x00000001U +#define TEE_M0_LOCK_S 2 + +/** TEE_M1_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3; + * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M1_MODE 0x00000003U +#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) +#define TEE_M1_MODE_V 0x00000003U +#define TEE_M1_MODE_S 0 +/** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m1 tee configuration + */ +#define TEE_M1_LOCK (BIT(2)) +#define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S) +#define TEE_M1_LOCK_V 0x00000001U +#define TEE_M1_LOCK_S 2 + +/** TEE_M2_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; + * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M2_MODE 0x00000003U +#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) +#define TEE_M2_MODE_V 0x00000003U +#define TEE_M2_MODE_S 0 +/** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m2 tee configuration + */ +#define TEE_M2_LOCK (BIT(2)) +#define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S) +#define TEE_M2_LOCK_V 0x00000001U +#define TEE_M2_LOCK_S 2 + +/** TEE_M3_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) +/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3; + * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M3_MODE 0x00000003U +#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) +#define TEE_M3_MODE_V 0x00000003U +#define TEE_M3_MODE_S 0 +/** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m3 tee configuration + */ +#define TEE_M3_LOCK (BIT(2)) +#define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S) +#define TEE_M3_LOCK_V 0x00000001U +#define TEE_M3_LOCK_S 2 + +/** TEE_M4_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) +/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3; + * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M4_MODE 0x00000003U +#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) +#define TEE_M4_MODE_V 0x00000003U +#define TEE_M4_MODE_S 0 +/** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m4 tee configuration + */ +#define TEE_M4_LOCK (BIT(2)) +#define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S) +#define TEE_M4_LOCK_V 0x00000001U +#define TEE_M4_LOCK_S 2 + +/** TEE_M5_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) +/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3; + * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M5_MODE 0x00000003U +#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) +#define TEE_M5_MODE_V 0x00000003U +#define TEE_M5_MODE_S 0 +/** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m5 tee configuration + */ +#define TEE_M5_LOCK (BIT(2)) +#define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S) +#define TEE_M5_LOCK_V 0x00000001U +#define TEE_M5_LOCK_S 2 + +/** TEE_M6_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) +/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3; + * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M6_MODE 0x00000003U +#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) +#define TEE_M6_MODE_V 0x00000003U +#define TEE_M6_MODE_S 0 +/** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m6 tee configuration + */ +#define TEE_M6_LOCK (BIT(2)) +#define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S) +#define TEE_M6_LOCK_V 0x00000001U +#define TEE_M6_LOCK_S 2 + +/** TEE_M7_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) +/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3; + * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M7_MODE 0x00000003U +#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) +#define TEE_M7_MODE_V 0x00000003U +#define TEE_M7_MODE_S 0 +/** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m7 tee configuration + */ +#define TEE_M7_LOCK (BIT(2)) +#define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S) +#define TEE_M7_LOCK_V 0x00000001U +#define TEE_M7_LOCK_S 2 + +/** TEE_M8_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) +/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3; + * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M8_MODE 0x00000003U +#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) +#define TEE_M8_MODE_V 0x00000003U +#define TEE_M8_MODE_S 0 +/** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m8 tee configuration + */ +#define TEE_M8_LOCK (BIT(2)) +#define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S) +#define TEE_M8_LOCK_V 0x00000001U +#define TEE_M8_LOCK_S 2 + +/** TEE_M9_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) +/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3; + * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M9_MODE 0x00000003U +#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) +#define TEE_M9_MODE_V 0x00000003U +#define TEE_M9_MODE_S 0 +/** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m9 tee configuration + */ +#define TEE_M9_LOCK (BIT(2)) +#define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S) +#define TEE_M9_LOCK_V 0x00000001U +#define TEE_M9_LOCK_S 2 + +/** TEE_M10_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) +/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3; + * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M10_MODE 0x00000003U +#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) +#define TEE_M10_MODE_V 0x00000003U +#define TEE_M10_MODE_S 0 +/** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m10 tee configuration + */ +#define TEE_M10_LOCK (BIT(2)) +#define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S) +#define TEE_M10_LOCK_V 0x00000001U +#define TEE_M10_LOCK_S 2 + +/** TEE_M11_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) +/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3; + * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M11_MODE 0x00000003U +#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) +#define TEE_M11_MODE_V 0x00000003U +#define TEE_M11_MODE_S 0 +/** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m11 tee configuration + */ +#define TEE_M11_LOCK (BIT(2)) +#define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S) +#define TEE_M11_LOCK_V 0x00000001U +#define TEE_M11_LOCK_S 2 + +/** TEE_M12_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3; + * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M12_MODE 0x00000003U +#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) +#define TEE_M12_MODE_V 0x00000003U +#define TEE_M12_MODE_S 0 +/** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m12 tee configuration + */ +#define TEE_M12_LOCK (BIT(2)) +#define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S) +#define TEE_M12_LOCK_V 0x00000001U +#define TEE_M12_LOCK_S 2 + +/** TEE_M13_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) +/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3; + * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M13_MODE 0x00000003U +#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) +#define TEE_M13_MODE_V 0x00000003U +#define TEE_M13_MODE_S 0 +/** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m13 tee configuration + */ +#define TEE_M13_LOCK (BIT(2)) +#define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S) +#define TEE_M13_LOCK_V 0x00000001U +#define TEE_M13_LOCK_S 2 + +/** TEE_M14_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) +/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3; + * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M14_MODE 0x00000003U +#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) +#define TEE_M14_MODE_V 0x00000003U +#define TEE_M14_MODE_S 0 +/** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m14 tee configuration + */ +#define TEE_M14_LOCK (BIT(2)) +#define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S) +#define TEE_M14_LOCK_V 0x00000001U +#define TEE_M14_LOCK_S 2 + +/** TEE_M15_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) +/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3; + * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M15_MODE 0x00000003U +#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) +#define TEE_M15_MODE_V 0x00000003U +#define TEE_M15_MODE_S 0 +/** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m15 tee configuration + */ +#define TEE_M15_LOCK (BIT(2)) +#define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S) +#define TEE_M15_LOCK_V 0x00000001U +#define TEE_M15_LOCK_S 2 + +/** TEE_M16_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) +/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3; + * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M16_MODE 0x00000003U +#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) +#define TEE_M16_MODE_V 0x00000003U +#define TEE_M16_MODE_S 0 +/** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m16 tee configuration + */ +#define TEE_M16_LOCK (BIT(2)) +#define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S) +#define TEE_M16_LOCK_V 0x00000001U +#define TEE_M16_LOCK_S 2 + +/** TEE_M17_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) +/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3; + * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M17_MODE 0x00000003U +#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) +#define TEE_M17_MODE_V 0x00000003U +#define TEE_M17_MODE_S 0 +/** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m17 tee configuration + */ +#define TEE_M17_LOCK (BIT(2)) +#define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S) +#define TEE_M17_LOCK_V 0x00000001U +#define TEE_M17_LOCK_S 2 + +/** TEE_M18_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) +/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3; + * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M18_MODE 0x00000003U +#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) +#define TEE_M18_MODE_V 0x00000003U +#define TEE_M18_MODE_S 0 +/** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m18 tee configuration + */ +#define TEE_M18_LOCK (BIT(2)) +#define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S) +#define TEE_M18_LOCK_V 0x00000001U +#define TEE_M18_LOCK_S 2 + +/** TEE_M19_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) +/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3; + * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M19_MODE 0x00000003U +#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) +#define TEE_M19_MODE_V 0x00000003U +#define TEE_M19_MODE_S 0 +/** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m19 tee configuration + */ +#define TEE_M19_LOCK (BIT(2)) +#define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S) +#define TEE_M19_LOCK_V 0x00000001U +#define TEE_M19_LOCK_S 2 + +/** TEE_M20_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) +/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3; + * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M20_MODE 0x00000003U +#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) +#define TEE_M20_MODE_V 0x00000003U +#define TEE_M20_MODE_S 0 +/** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m20 tee configuration + */ +#define TEE_M20_LOCK (BIT(2)) +#define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S) +#define TEE_M20_LOCK_V 0x00000001U +#define TEE_M20_LOCK_S 2 + +/** TEE_M21_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) +/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3; + * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M21_MODE 0x00000003U +#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) +#define TEE_M21_MODE_V 0x00000003U +#define TEE_M21_MODE_S 0 +/** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m21 tee configuration + */ +#define TEE_M21_LOCK (BIT(2)) +#define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S) +#define TEE_M21_LOCK_V 0x00000001U +#define TEE_M21_LOCK_S 2 + +/** TEE_M22_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) +/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3; + * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M22_MODE 0x00000003U +#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) +#define TEE_M22_MODE_V 0x00000003U +#define TEE_M22_MODE_S 0 +/** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m22 tee configuration + */ +#define TEE_M22_LOCK (BIT(2)) +#define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S) +#define TEE_M22_LOCK_V 0x00000001U +#define TEE_M22_LOCK_S 2 + +/** TEE_M23_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) +/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3; + * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M23_MODE 0x00000003U +#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) +#define TEE_M23_MODE_V 0x00000003U +#define TEE_M23_MODE_S 0 +/** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m23 tee configuration + */ +#define TEE_M23_LOCK (BIT(2)) +#define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S) +#define TEE_M23_LOCK_V 0x00000001U +#define TEE_M23_LOCK_S 2 + +/** TEE_M24_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) +/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3; + * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M24_MODE 0x00000003U +#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) +#define TEE_M24_MODE_V 0x00000003U +#define TEE_M24_MODE_S 0 +/** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m24 tee configuration + */ +#define TEE_M24_LOCK (BIT(2)) +#define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S) +#define TEE_M24_LOCK_V 0x00000001U +#define TEE_M24_LOCK_S 2 + +/** TEE_M25_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) +/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3; + * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M25_MODE 0x00000003U +#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) +#define TEE_M25_MODE_V 0x00000003U +#define TEE_M25_MODE_S 0 +/** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m25 tee configuration + */ +#define TEE_M25_LOCK (BIT(2)) +#define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S) +#define TEE_M25_LOCK_V 0x00000001U +#define TEE_M25_LOCK_S 2 + +/** TEE_M26_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) +/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3; + * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M26_MODE 0x00000003U +#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) +#define TEE_M26_MODE_V 0x00000003U +#define TEE_M26_MODE_S 0 +/** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m26 tee configuration + */ +#define TEE_M26_LOCK (BIT(2)) +#define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S) +#define TEE_M26_LOCK_V 0x00000001U +#define TEE_M26_LOCK_S 2 + +/** TEE_M27_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) +/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3; + * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M27_MODE 0x00000003U +#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) +#define TEE_M27_MODE_V 0x00000003U +#define TEE_M27_MODE_S 0 +/** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m27 tee configuration + */ +#define TEE_M27_LOCK (BIT(2)) +#define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S) +#define TEE_M27_LOCK_V 0x00000001U +#define TEE_M27_LOCK_S 2 + +/** TEE_M28_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) +/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3; + * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M28_MODE 0x00000003U +#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) +#define TEE_M28_MODE_V 0x00000003U +#define TEE_M28_MODE_S 0 +/** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m28 tee configuration + */ +#define TEE_M28_LOCK (BIT(2)) +#define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S) +#define TEE_M28_LOCK_V 0x00000001U +#define TEE_M28_LOCK_S 2 + +/** TEE_M29_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) +/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3; + * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M29_MODE 0x00000003U +#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) +#define TEE_M29_MODE_V 0x00000003U +#define TEE_M29_MODE_S 0 +/** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m29 tee configuration + */ +#define TEE_M29_LOCK (BIT(2)) +#define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S) +#define TEE_M29_LOCK_V 0x00000001U +#define TEE_M29_LOCK_S 2 + +/** TEE_M30_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) +/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3; + * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M30_MODE 0x00000003U +#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) +#define TEE_M30_MODE_V 0x00000003U +#define TEE_M30_MODE_S 0 +/** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m30 tee configuration + */ +#define TEE_M30_LOCK (BIT(2)) +#define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S) +#define TEE_M30_LOCK_V 0x00000001U +#define TEE_M30_LOCK_S 2 + +/** TEE_M31_MODE_CTRL_REG register + * Tee mode control register + */ +#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) +/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3; + * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ +#define TEE_M31_MODE 0x00000003U +#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) +#define TEE_M31_MODE_V 0x00000003U +#define TEE_M31_MODE_S 0 +/** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m31 tee configuration + */ +#define TEE_M31_LOCK (BIT(2)) +#define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S) +#define TEE_M31_LOCK_V 0x00000001U +#define TEE_M31_LOCK_S 2 + +/** TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80) +/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define TEE_CLK_EN (BIT(0)) +#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) +#define TEE_CLK_EN_V 0x00000001U +#define TEE_CLK_EN_S 0 + +/** TEE_DATE_REG register + * Version register + */ +#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) +/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664; + * reg_tee_date + */ +#define TEE_DATE_REG 0x0FFFFFFFU +#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S) +#define TEE_DATE_REG_V 0x0FFFFFFFU +#define TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/tee_struct.h b/components/soc/esp32c5/include/soc/tee_struct.h new file mode 100644 index 0000000000..f4fe27cca3 --- /dev/null +++ b/components/soc/esp32c5/include/soc/tee_struct.h @@ -0,0 +1,701 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of m0_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m0_mode : R/W; bitpos: [1:0]; default: 0; + * M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m0_mode:2; + /** m0_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ + uint32_t m0_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m0_mode_ctrl_reg_t; + +/** Type of m1_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m1_mode : R/W; bitpos: [1:0]; default: 3; + * M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m1_mode:2; + /** m1_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m1 tee configuration + */ + uint32_t m1_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m1_mode_ctrl_reg_t; + +/** Type of m2_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m2_mode : R/W; bitpos: [1:0]; default: 0; + * M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m2_mode:2; + /** m2_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m2 tee configuration + */ + uint32_t m2_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m2_mode_ctrl_reg_t; + +/** Type of m3_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m3_mode : R/W; bitpos: [1:0]; default: 3; + * M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m3_mode:2; + /** m3_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m3 tee configuration + */ + uint32_t m3_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m3_mode_ctrl_reg_t; + +/** Type of m4_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m4_mode : R/W; bitpos: [1:0]; default: 3; + * M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m4_mode:2; + /** m4_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m4 tee configuration + */ + uint32_t m4_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m4_mode_ctrl_reg_t; + +/** Type of m5_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m5_mode : R/W; bitpos: [1:0]; default: 3; + * M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m5_mode:2; + /** m5_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m5 tee configuration + */ + uint32_t m5_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m5_mode_ctrl_reg_t; + +/** Type of m6_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m6_mode : R/W; bitpos: [1:0]; default: 3; + * M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m6_mode:2; + /** m6_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m6 tee configuration + */ + uint32_t m6_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m6_mode_ctrl_reg_t; + +/** Type of m7_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m7_mode : R/W; bitpos: [1:0]; default: 3; + * M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m7_mode:2; + /** m7_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m7 tee configuration + */ + uint32_t m7_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m7_mode_ctrl_reg_t; + +/** Type of m8_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m8_mode : R/W; bitpos: [1:0]; default: 3; + * M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m8_mode:2; + /** m8_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m8 tee configuration + */ + uint32_t m8_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m8_mode_ctrl_reg_t; + +/** Type of m9_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m9_mode : R/W; bitpos: [1:0]; default: 3; + * M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m9_mode:2; + /** m9_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m9 tee configuration + */ + uint32_t m9_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m9_mode_ctrl_reg_t; + +/** Type of m10_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m10_mode : R/W; bitpos: [1:0]; default: 3; + * M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m10_mode:2; + /** m10_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m10 tee configuration + */ + uint32_t m10_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m10_mode_ctrl_reg_t; + +/** Type of m11_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m11_mode : R/W; bitpos: [1:0]; default: 3; + * M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m11_mode:2; + /** m11_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m11 tee configuration + */ + uint32_t m11_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m11_mode_ctrl_reg_t; + +/** Type of m12_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m12_mode : R/W; bitpos: [1:0]; default: 3; + * M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m12_mode:2; + /** m12_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m12 tee configuration + */ + uint32_t m12_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m12_mode_ctrl_reg_t; + +/** Type of m13_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m13_mode : R/W; bitpos: [1:0]; default: 3; + * M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m13_mode:2; + /** m13_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m13 tee configuration + */ + uint32_t m13_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m13_mode_ctrl_reg_t; + +/** Type of m14_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m14_mode : R/W; bitpos: [1:0]; default: 3; + * M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m14_mode:2; + /** m14_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m14 tee configuration + */ + uint32_t m14_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m14_mode_ctrl_reg_t; + +/** Type of m15_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m15_mode : R/W; bitpos: [1:0]; default: 3; + * M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m15_mode:2; + /** m15_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m15 tee configuration + */ + uint32_t m15_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m15_mode_ctrl_reg_t; + +/** Type of m16_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m16_mode : R/W; bitpos: [1:0]; default: 3; + * M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m16_mode:2; + /** m16_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m16 tee configuration + */ + uint32_t m16_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m16_mode_ctrl_reg_t; + +/** Type of m17_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m17_mode : R/W; bitpos: [1:0]; default: 3; + * M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m17_mode:2; + /** m17_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m17 tee configuration + */ + uint32_t m17_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m17_mode_ctrl_reg_t; + +/** Type of m18_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m18_mode : R/W; bitpos: [1:0]; default: 3; + * M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m18_mode:2; + /** m18_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m18 tee configuration + */ + uint32_t m18_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m18_mode_ctrl_reg_t; + +/** Type of m19_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m19_mode : R/W; bitpos: [1:0]; default: 3; + * M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m19_mode:2; + /** m19_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m19 tee configuration + */ + uint32_t m19_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m19_mode_ctrl_reg_t; + +/** Type of m20_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m20_mode : R/W; bitpos: [1:0]; default: 3; + * M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m20_mode:2; + /** m20_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m20 tee configuration + */ + uint32_t m20_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m20_mode_ctrl_reg_t; + +/** Type of m21_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m21_mode : R/W; bitpos: [1:0]; default: 3; + * M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m21_mode:2; + /** m21_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m21 tee configuration + */ + uint32_t m21_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m21_mode_ctrl_reg_t; + +/** Type of m22_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m22_mode : R/W; bitpos: [1:0]; default: 3; + * M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m22_mode:2; + /** m22_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m22 tee configuration + */ + uint32_t m22_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m22_mode_ctrl_reg_t; + +/** Type of m23_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m23_mode : R/W; bitpos: [1:0]; default: 3; + * M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m23_mode:2; + /** m23_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m23 tee configuration + */ + uint32_t m23_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m23_mode_ctrl_reg_t; + +/** Type of m24_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m24_mode : R/W; bitpos: [1:0]; default: 3; + * M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m24_mode:2; + /** m24_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m24 tee configuration + */ + uint32_t m24_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m24_mode_ctrl_reg_t; + +/** Type of m25_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m25_mode : R/W; bitpos: [1:0]; default: 3; + * M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m25_mode:2; + /** m25_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m25 tee configuration + */ + uint32_t m25_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m25_mode_ctrl_reg_t; + +/** Type of m26_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m26_mode : R/W; bitpos: [1:0]; default: 3; + * M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m26_mode:2; + /** m26_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m26 tee configuration + */ + uint32_t m26_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m26_mode_ctrl_reg_t; + +/** Type of m27_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m27_mode : R/W; bitpos: [1:0]; default: 3; + * M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m27_mode:2; + /** m27_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m27 tee configuration + */ + uint32_t m27_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m27_mode_ctrl_reg_t; + +/** Type of m28_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m28_mode : R/W; bitpos: [1:0]; default: 3; + * M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m28_mode:2; + /** m28_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m28 tee configuration + */ + uint32_t m28_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m28_mode_ctrl_reg_t; + +/** Type of m29_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m29_mode : R/W; bitpos: [1:0]; default: 3; + * M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m29_mode:2; + /** m29_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m29 tee configuration + */ + uint32_t m29_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m29_mode_ctrl_reg_t; + +/** Type of m30_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m30_mode : R/W; bitpos: [1:0]; default: 3; + * M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m30_mode:2; + /** m30_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m30 tee configuration + */ + uint32_t m30_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m30_mode_ctrl_reg_t; + +/** Type of m31_mode_ctrl register + * Tee mode control register + */ +typedef union { + struct { + /** m31_mode : R/W; bitpos: [1:0]; default: 3; + * M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: + * tee_mode + */ + uint32_t m31_mode:2; + /** m31_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m31 tee configuration + */ + uint32_t m31_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_m31_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35725664; + * reg_tee_date + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} tee_date_reg_t; + + +typedef struct { + volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl; + volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl; + volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl; + volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl; + volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl; + volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl; + volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl; + volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl; + volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl; + volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl; + volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl; + volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl; + volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl; + volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl; + volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl; + volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl; + volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl; + volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl; + volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl; + volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl; + volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl; + volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl; + volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl; + volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl; + volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl; + volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl; + volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl; + volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl; + volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl; + volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl; + volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl; + volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl; + volatile tee_clock_gate_reg_t clock_gate; + uint32_t reserved_084[990]; + volatile tee_date_reg_t date; +} tee_dev_t; + +extern tee_dev_t TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/twai_reg.h b/components/soc/esp32c5/include/soc/twai_reg.h new file mode 100644 index 0000000000..9e8be8c78d --- /dev/null +++ b/components/soc/esp32c5/include/soc/twai_reg.h @@ -0,0 +1,791 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TWAI_MODE_REG register + * TWAI mode register. + */ +#define TWAI_MODE_REG (DR_REG_TWAI_BASE + 0x0) +/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ +#define TWAI_RESET_MODE (BIT(0)) +#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S) +#define TWAI_RESET_MODE_V 0x00000001U +#define TWAI_RESET_MODE_S 0 +/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ +#define TWAI_LISTEN_ONLY_MODE (BIT(1)) +#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S) +#define TWAI_LISTEN_ONLY_MODE_V 0x00000001U +#define TWAI_LISTEN_ONLY_MODE_S 1 +/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ +#define TWAI_SELF_TEST_MODE (BIT(2)) +#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S) +#define TWAI_SELF_TEST_MODE_V 0x00000001U +#define TWAI_SELF_TEST_MODE_S 2 +/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ +#define TWAI_ACCEPTANCE_FILTER_MODE (BIT(3)) +#define TWAI_ACCEPTANCE_FILTER_MODE_M (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S) +#define TWAI_ACCEPTANCE_FILTER_MODE_V 0x00000001U +#define TWAI_ACCEPTANCE_FILTER_MODE_S 3 + +/** TWAI_CMD_REG register + * TWAI command register. + */ +#define TWAI_CMD_REG (DR_REG_TWAI_BASE + 0x4) +/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ +#define TWAI_TX_REQUEST (BIT(0)) +#define TWAI_TX_REQUEST_M (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S) +#define TWAI_TX_REQUEST_V 0x00000001U +#define TWAI_TX_REQUEST_S 0 +/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ +#define TWAI_ABORT_TX (BIT(1)) +#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S) +#define TWAI_ABORT_TX_V 0x00000001U +#define TWAI_ABORT_TX_S 1 +/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ +#define TWAI_RELEASE_BUFFER (BIT(2)) +#define TWAI_RELEASE_BUFFER_M (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S) +#define TWAI_RELEASE_BUFFER_V 0x00000001U +#define TWAI_RELEASE_BUFFER_S 2 +/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ +#define TWAI_CLEAR_DATA_OVERRUN (BIT(3)) +#define TWAI_CLEAR_DATA_OVERRUN_M (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S) +#define TWAI_CLEAR_DATA_OVERRUN_V 0x00000001U +#define TWAI_CLEAR_DATA_OVERRUN_S 3 +/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ +#define TWAI_SELF_RX_REQUEST (BIT(4)) +#define TWAI_SELF_RX_REQUEST_M (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S) +#define TWAI_SELF_RX_REQUEST_V 0x00000001U +#define TWAI_SELF_RX_REQUEST_S 4 + +/** TWAI_STATUS_REG register + * TWAI status register. + */ +#define TWAI_STATUS_REG (DR_REG_TWAI_BASE + 0x8) +/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ +#define TWAI_STATUS_RECEIVE_BUFFER (BIT(0)) +#define TWAI_STATUS_RECEIVE_BUFFER_M (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S) +#define TWAI_STATUS_RECEIVE_BUFFER_V 0x00000001U +#define TWAI_STATUS_RECEIVE_BUFFER_S 0 +/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ +#define TWAI_STATUS_OVERRUN (BIT(1)) +#define TWAI_STATUS_OVERRUN_M (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S) +#define TWAI_STATUS_OVERRUN_V 0x00000001U +#define TWAI_STATUS_OVERRUN_S 1 +/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ +#define TWAI_STATUS_TRANSMIT_BUFFER (BIT(2)) +#define TWAI_STATUS_TRANSMIT_BUFFER_M (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S) +#define TWAI_STATUS_TRANSMIT_BUFFER_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_BUFFER_S 2 +/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ +#define TWAI_STATUS_TRANSMISSION_COMPLETE (BIT(3)) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_M (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S) +#define TWAI_STATUS_TRANSMISSION_COMPLETE_V 0x00000001U +#define TWAI_STATUS_TRANSMISSION_COMPLETE_S 3 +/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ +#define TWAI_STATUS_RECEIVE (BIT(4)) +#define TWAI_STATUS_RECEIVE_M (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S) +#define TWAI_STATUS_RECEIVE_V 0x00000001U +#define TWAI_STATUS_RECEIVE_S 4 +/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ +#define TWAI_STATUS_TRANSMIT (BIT(5)) +#define TWAI_STATUS_TRANSMIT_M (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S) +#define TWAI_STATUS_TRANSMIT_V 0x00000001U +#define TWAI_STATUS_TRANSMIT_S 5 +/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ +#define TWAI_STATUS_ERR (BIT(6)) +#define TWAI_STATUS_ERR_M (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S) +#define TWAI_STATUS_ERR_V 0x00000001U +#define TWAI_STATUS_ERR_S 6 +/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ +#define TWAI_STATUS_NODE_BUS_OFF (BIT(7)) +#define TWAI_STATUS_NODE_BUS_OFF_M (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S) +#define TWAI_STATUS_NODE_BUS_OFF_V 0x00000001U +#define TWAI_STATUS_NODE_BUS_OFF_S 7 +/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ +#define TWAI_STATUS_MISS (BIT(8)) +#define TWAI_STATUS_MISS_M (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S) +#define TWAI_STATUS_MISS_V 0x00000001U +#define TWAI_STATUS_MISS_S 8 + +/** TWAI_INTERRUPT_REG register + * Interrupt signals' register. + */ +#define TWAI_INTERRUPT_REG (DR_REG_TWAI_BASE + 0xc) +/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ +#define TWAI_RECEIVE_INT_ST (BIT(0)) +#define TWAI_RECEIVE_INT_ST_M (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S) +#define TWAI_RECEIVE_INT_ST_V 0x00000001U +#define TWAI_RECEIVE_INT_ST_S 0 +/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_TRANSMIT_INT_ST (BIT(1)) +#define TWAI_TRANSMIT_INT_ST_M (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S) +#define TWAI_TRANSMIT_INT_ST_V 0x00000001U +#define TWAI_TRANSMIT_INT_ST_S 1 +/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ +#define TWAI_ERR_WARNING_INT_ST (BIT(2)) +#define TWAI_ERR_WARNING_INT_ST_M (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S) +#define TWAI_ERR_WARNING_INT_ST_V 0x00000001U +#define TWAI_ERR_WARNING_INT_ST_S 2 +/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_DATA_OVERRUN_INT_ST (BIT(3)) +#define TWAI_DATA_OVERRUN_INT_ST_M (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S) +#define TWAI_DATA_OVERRUN_INT_ST_V 0x00000001U +#define TWAI_DATA_OVERRUN_INT_ST_S 3 +/** TWAI_TS_COUNTER_OVFL_INT_ST : RO; bitpos: [4]; default: 0; + * 1: this bit is set then the timestamp counter reaches the maximum value and + * overflow. + */ +#define TWAI_TS_COUNTER_OVFL_INT_ST (BIT(4)) +#define TWAI_TS_COUNTER_OVFL_INT_ST_M (TWAI_TS_COUNTER_OVFL_INT_ST_V << TWAI_TS_COUNTER_OVFL_INT_ST_S) +#define TWAI_TS_COUNTER_OVFL_INT_ST_V 0x00000001U +#define TWAI_TS_COUNTER_OVFL_INT_ST_S 4 +/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ERR_PASSIVE_INT_ST (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S) +#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ST_S 5 +/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_ARBITRATION_LOST_INT_ST (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ST_M (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S) +#define TWAI_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ST_S 6 +/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_BUS_ERR_INT_ST (BIT(7)) +#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S) +#define TWAI_BUS_ERR_INT_ST_V 0x00000001U +#define TWAI_BUS_ERR_INT_ST_S 7 +/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ +#define TWAI_IDLE_INT_ST (BIT(8)) +#define TWAI_IDLE_INT_ST_M (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S) +#define TWAI_IDLE_INT_ST_V 0x00000001U +#define TWAI_IDLE_INT_ST_S 8 + +/** TWAI_INTERRUPT_ENABLE_REG register + * Interrupt enable register. + */ +#define TWAI_INTERRUPT_ENABLE_REG (DR_REG_TWAI_BASE + 0x10) +/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ +#define TWAI_EXT_RECEIVE_INT_ENA (BIT(0)) +#define TWAI_EXT_RECEIVE_INT_ENA_M (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S) +#define TWAI_EXT_RECEIVE_INT_ENA_V 0x00000001U +#define TWAI_EXT_RECEIVE_INT_ENA_S 0 +/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ +#define TWAI_EXT_TRANSMIT_INT_ENA (BIT(1)) +#define TWAI_EXT_TRANSMIT_INT_ENA_M (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S) +#define TWAI_EXT_TRANSMIT_INT_ENA_V 0x00000001U +#define TWAI_EXT_TRANSMIT_INT_ENA_S 1 +/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_ERR_WARNING_INT_ENA (BIT(2)) +#define TWAI_EXT_ERR_WARNING_INT_ENA_M (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S) +#define TWAI_EXT_ERR_WARNING_INT_ENA_V 0x00000001U +#define TWAI_EXT_ERR_WARNING_INT_ENA_S 2 +/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ +#define TWAI_EXT_DATA_OVERRUN_INT_ENA (BIT(3)) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S) +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V 0x00000001U +#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S 3 +/** TWAI_TS_COUNTER_OVFL_INT_ENA : R/W; bitpos: [4]; default: 0; + * enable the timestamp counter overflow interrupt request. + */ +#define TWAI_TS_COUNTER_OVFL_INT_ENA (BIT(4)) +#define TWAI_TS_COUNTER_OVFL_INT_ENA_M (TWAI_TS_COUNTER_OVFL_INT_ENA_V << TWAI_TS_COUNTER_OVFL_INT_ENA_S) +#define TWAI_TS_COUNTER_OVFL_INT_ENA_V 0x00000001U +#define TWAI_TS_COUNTER_OVFL_INT_ENA_S 4 +/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ +#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S) +#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001U +#define TWAI_ERR_PASSIVE_INT_ENA_S 5 +/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ +#define TWAI_ARBITRATION_LOST_INT_ENA (BIT(6)) +#define TWAI_ARBITRATION_LOST_INT_ENA_M (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S) +#define TWAI_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define TWAI_ARBITRATION_LOST_INT_ENA_S 6 +/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_BUS_ERR_INT_ENA (BIT(7)) +#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S) +#define TWAI_BUS_ERR_INT_ENA_V 0x00000001U +#define TWAI_BUS_ERR_INT_ENA_S 7 +/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ +#define TWAI_IDLE_INT_ENA (BIT(8)) +#define TWAI_IDLE_INT_ENA_M (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S) +#define TWAI_IDLE_INT_ENA_V 0x00000001U +#define TWAI_IDLE_INT_ENA_S 8 + +/** TWAI_BUS_TIMING_0_REG register + * Bit timing configuration register 0. + */ +#define TWAI_BUS_TIMING_0_REG (DR_REG_TWAI_BASE + 0x18) +/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ +#define TWAI_BAUD_PRESC 0x00003FFFU +#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S) +#define TWAI_BAUD_PRESC_V 0x00003FFFU +#define TWAI_BAUD_PRESC_S 0 +/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ +#define TWAI_SYNC_JUMP_WIDTH 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S) +#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003U +#define TWAI_SYNC_JUMP_WIDTH_S 14 + +/** TWAI_BUS_TIMING_1_REG register + * Bit timing configuration register 1. + */ +#define TWAI_BUS_TIMING_1_REG (DR_REG_TWAI_BASE + 0x1c) +/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT1 0x0000000FU +#define TWAI_TIME_SEGMENT1_M (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S) +#define TWAI_TIME_SEGMENT1_V 0x0000000FU +#define TWAI_TIME_SEGMENT1_S 0 +/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ +#define TWAI_TIME_SEGMENT2 0x00000007U +#define TWAI_TIME_SEGMENT2_M (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S) +#define TWAI_TIME_SEGMENT2_V 0x00000007U +#define TWAI_TIME_SEGMENT2_S 4 +/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TIME_SAMPLING (BIT(7)) +#define TWAI_TIME_SAMPLING_M (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S) +#define TWAI_TIME_SAMPLING_V 0x00000001U +#define TWAI_TIME_SAMPLING_S 7 + +/** TWAI_ARB_LOST_CAP_REG register + * TWAI arbiter lost capture register. + */ +#define TWAI_ARB_LOST_CAP_REG (DR_REG_TWAI_BASE + 0x2c) +/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ +#define TWAI_ARBITRATION_LOST_CAPTURE 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_M (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S) +#define TWAI_ARBITRATION_LOST_CAPTURE_V 0x0000001FU +#define TWAI_ARBITRATION_LOST_CAPTURE_S 0 + +/** TWAI_ERR_CODE_CAP_REG register + * TWAI error info capture register. + */ +#define TWAI_ERR_CODE_CAP_REG (DR_REG_TWAI_BASE + 0x30) +/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ +#define TWAI_ERR_CAPTURE_CODE_SEGMENT 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S) +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V 0x0000001FU +#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S 0 +/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ +#define TWAI_ERR_CAPTURE_CODE_DIRECTION (BIT(5)) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S) +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V 0x00000001U +#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S 5 +/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ +#define TWAI_ERR_CAPTURE_CODE_TYPE 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_M (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S) +#define TWAI_ERR_CAPTURE_CODE_TYPE_V 0x00000003U +#define TWAI_ERR_CAPTURE_CODE_TYPE_S 6 + +/** TWAI_ERR_WARNING_LIMIT_REG register + * TWAI error threshold configuration register. + */ +#define TWAI_ERR_WARNING_LIMIT_REG (DR_REG_TWAI_BASE + 0x34) +/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_ERR_WARNING_LIMIT 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S) +#define TWAI_ERR_WARNING_LIMIT_V 0x000000FFU +#define TWAI_ERR_WARNING_LIMIT_S 0 + +/** TWAI_RX_ERR_CNT_REG register + * Rx error counter register. + */ +#define TWAI_RX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x38) +/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_RX_ERR_CNT 0x000000FFU +#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S) +#define TWAI_RX_ERR_CNT_V 0x000000FFU +#define TWAI_RX_ERR_CNT_S 0 + +/** TWAI_TX_ERR_CNT_REG register + * Tx error counter register. + */ +#define TWAI_TX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x3c) +/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_TX_ERR_CNT 0x000000FFU +#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S) +#define TWAI_TX_ERR_CNT_V 0x000000FFU +#define TWAI_TX_ERR_CNT_S 0 + +/** TWAI_DATA_0_REG register + * Data register 0. + */ +#define TWAI_DATA_0_REG (DR_REG_TWAI_BASE + 0x40) +/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ +#define TWAI_DATA_0 0x000000FFU +#define TWAI_DATA_0_M (TWAI_DATA_0_V << TWAI_DATA_0_S) +#define TWAI_DATA_0_V 0x000000FFU +#define TWAI_DATA_0_S 0 + +/** TWAI_DATA_1_REG register + * Data register 1. + */ +#define TWAI_DATA_1_REG (DR_REG_TWAI_BASE + 0x44) +/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 1 and when + * software initiate read operation, it is rx data register 1. + */ +#define TWAI_DATA_1 0x000000FFU +#define TWAI_DATA_1_M (TWAI_DATA_1_V << TWAI_DATA_1_S) +#define TWAI_DATA_1_V 0x000000FFU +#define TWAI_DATA_1_S 0 + +/** TWAI_DATA_2_REG register + * Data register 2. + */ +#define TWAI_DATA_2_REG (DR_REG_TWAI_BASE + 0x48) +/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 2 and when + * software initiate read operation, it is rx data register 2. + */ +#define TWAI_DATA_2 0x000000FFU +#define TWAI_DATA_2_M (TWAI_DATA_2_V << TWAI_DATA_2_S) +#define TWAI_DATA_2_V 0x000000FFU +#define TWAI_DATA_2_S 0 + +/** TWAI_DATA_3_REG register + * Data register 3. + */ +#define TWAI_DATA_3_REG (DR_REG_TWAI_BASE + 0x4c) +/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 3 and when + * software initiate read operation, it is rx data register 3. + */ +#define TWAI_DATA_3 0x000000FFU +#define TWAI_DATA_3_M (TWAI_DATA_3_V << TWAI_DATA_3_S) +#define TWAI_DATA_3_V 0x000000FFU +#define TWAI_DATA_3_S 0 + +/** TWAI_DATA_4_REG register + * Data register 4. + */ +#define TWAI_DATA_4_REG (DR_REG_TWAI_BASE + 0x50) +/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 4 and when + * software initiate read operation, it is rx data register 4. + */ +#define TWAI_DATA_4 0x000000FFU +#define TWAI_DATA_4_M (TWAI_DATA_4_V << TWAI_DATA_4_S) +#define TWAI_DATA_4_V 0x000000FFU +#define TWAI_DATA_4_S 0 + +/** TWAI_DATA_5_REG register + * Data register 5. + */ +#define TWAI_DATA_5_REG (DR_REG_TWAI_BASE + 0x54) +/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 5 and when + * software initiate read operation, it is rx data register 5. + */ +#define TWAI_DATA_5 0x000000FFU +#define TWAI_DATA_5_M (TWAI_DATA_5_V << TWAI_DATA_5_S) +#define TWAI_DATA_5_V 0x000000FFU +#define TWAI_DATA_5_S 0 + +/** TWAI_DATA_6_REG register + * Data register 6. + */ +#define TWAI_DATA_6_REG (DR_REG_TWAI_BASE + 0x58) +/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 6 and when + * software initiate read operation, it is rx data register 6. + */ +#define TWAI_DATA_6 0x000000FFU +#define TWAI_DATA_6_M (TWAI_DATA_6_V << TWAI_DATA_6_S) +#define TWAI_DATA_6_V 0x000000FFU +#define TWAI_DATA_6_S 0 + +/** TWAI_DATA_7_REG register + * Data register 7. + */ +#define TWAI_DATA_7_REG (DR_REG_TWAI_BASE + 0x5c) +/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 7 and when + * software initiate read operation, it is rx data register 7. + */ +#define TWAI_DATA_7 0x000000FFU +#define TWAI_DATA_7_M (TWAI_DATA_7_V << TWAI_DATA_7_S) +#define TWAI_DATA_7_V 0x000000FFU +#define TWAI_DATA_7_S 0 + +/** TWAI_DATA_8_REG register + * Data register 8. + */ +#define TWAI_DATA_8_REG (DR_REG_TWAI_BASE + 0x60) +/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 8 and when software initiate read operation, it + * is rx data register 8. + */ +#define TWAI_DATA_8 0x000000FFU +#define TWAI_DATA_8_M (TWAI_DATA_8_V << TWAI_DATA_8_S) +#define TWAI_DATA_8_V 0x000000FFU +#define TWAI_DATA_8_S 0 + +/** TWAI_DATA_9_REG register + * Data register 9. + */ +#define TWAI_DATA_9_REG (DR_REG_TWAI_BASE + 0x64) +/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 9 and when software initiate read operation, it + * is rx data register 9. + */ +#define TWAI_DATA_9 0x000000FFU +#define TWAI_DATA_9_M (TWAI_DATA_9_V << TWAI_DATA_9_S) +#define TWAI_DATA_9_V 0x000000FFU +#define TWAI_DATA_9_S 0 + +/** TWAI_DATA_10_REG register + * Data register 10. + */ +#define TWAI_DATA_10_REG (DR_REG_TWAI_BASE + 0x68) +/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 10 and when software initiate read operation, it + * is rx data register 10. + */ +#define TWAI_DATA_10 0x000000FFU +#define TWAI_DATA_10_M (TWAI_DATA_10_V << TWAI_DATA_10_S) +#define TWAI_DATA_10_V 0x000000FFU +#define TWAI_DATA_10_S 0 + +/** TWAI_DATA_11_REG register + * Data register 11. + */ +#define TWAI_DATA_11_REG (DR_REG_TWAI_BASE + 0x6c) +/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 11 and when software initiate read operation, it + * is rx data register 11. + */ +#define TWAI_DATA_11 0x000000FFU +#define TWAI_DATA_11_M (TWAI_DATA_11_V << TWAI_DATA_11_S) +#define TWAI_DATA_11_V 0x000000FFU +#define TWAI_DATA_11_S 0 + +/** TWAI_DATA_12_REG register + * Data register 12. + */ +#define TWAI_DATA_12_REG (DR_REG_TWAI_BASE + 0x70) +/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 12 and when software initiate read operation, it + * is rx data register 12. + */ +#define TWAI_DATA_12 0x000000FFU +#define TWAI_DATA_12_M (TWAI_DATA_12_V << TWAI_DATA_12_S) +#define TWAI_DATA_12_V 0x000000FFU +#define TWAI_DATA_12_S 0 + +/** TWAI_RX_MESSAGE_COUNTER_REG register + * Received message counter register. + */ +#define TWAI_RX_MESSAGE_COUNTER_REG (DR_REG_TWAI_BASE + 0x74) +/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ +#define TWAI_RX_MESSAGE_COUNTER 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S) +#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007FU +#define TWAI_RX_MESSAGE_COUNTER_S 0 + +/** TWAI_CLOCK_DIVIDER_REG register + * Clock divider register. + */ +#define TWAI_CLOCK_DIVIDER_REG (DR_REG_TWAI_BASE + 0x7c) +/** TWAI_CD : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ +#define TWAI_CD 0x000000FFU +#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S) +#define TWAI_CD_V 0x000000FFU +#define TWAI_CD_S 0 +/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ +#define TWAI_CLOCK_OFF (BIT(8)) +#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S) +#define TWAI_CLOCK_OFF_V 0x00000001U +#define TWAI_CLOCK_OFF_S 8 + +/** TWAI_SW_STANDBY_CFG_REG register + * Software configure standby pin directly. + */ +#define TWAI_SW_STANDBY_CFG_REG (DR_REG_TWAI_BASE + 0x80) +/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ +#define TWAI_SW_STANDBY_EN (BIT(0)) +#define TWAI_SW_STANDBY_EN_M (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S) +#define TWAI_SW_STANDBY_EN_V 0x00000001U +#define TWAI_SW_STANDBY_EN_S 0 +/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ +#define TWAI_SW_STANDBY_CLR (BIT(1)) +#define TWAI_SW_STANDBY_CLR_M (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S) +#define TWAI_SW_STANDBY_CLR_V 0x00000001U +#define TWAI_SW_STANDBY_CLR_S 1 + +/** TWAI_HW_CFG_REG register + * Hardware configure standby pin. + */ +#define TWAI_HW_CFG_REG (DR_REG_TWAI_BASE + 0x84) +/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ +#define TWAI_HW_STANDBY_EN (BIT(0)) +#define TWAI_HW_STANDBY_EN_M (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S) +#define TWAI_HW_STANDBY_EN_V 0x00000001U +#define TWAI_HW_STANDBY_EN_S 0 + +/** TWAI_HW_STANDBY_CNT_REG register + * Configure standby counter. + */ +#define TWAI_HW_STANDBY_CNT_REG (DR_REG_TWAI_BASE + 0x88) +/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ +#define TWAI_STANDBY_WAIT_CNT 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_M (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S) +#define TWAI_STANDBY_WAIT_CNT_V 0xFFFFFFFFU +#define TWAI_STANDBY_WAIT_CNT_S 0 + +/** TWAI_IDLE_INTR_CNT_REG register + * Configure idle interrupt counter. + */ +#define TWAI_IDLE_INTR_CNT_REG (DR_REG_TWAI_BASE + 0x8c) +/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ +#define TWAI_IDLE_INTR_CNT 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_M (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S) +#define TWAI_IDLE_INTR_CNT_V 0xFFFFFFFFU +#define TWAI_IDLE_INTR_CNT_S 0 + +/** TWAI_ECO_CFG_REG register + * ECO configuration register. + */ +#define TWAI_ECO_CFG_REG (DR_REG_TWAI_BASE + 0x90) +/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ +#define TWAI_RDN_ENA (BIT(0)) +#define TWAI_RDN_ENA_M (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S) +#define TWAI_RDN_ENA_V 0x00000001U +#define TWAI_RDN_ENA_S 0 +/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ +#define TWAI_RDN_RESULT (BIT(1)) +#define TWAI_RDN_RESULT_M (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S) +#define TWAI_RDN_RESULT_V 0x00000001U +#define TWAI_RDN_RESULT_S 1 + +/** TWAI_TIMESTAMP_DATA_REG register + * Timestamp data register + */ +#define TWAI_TIMESTAMP_DATA_REG (DR_REG_TWAI_BASE + 0x94) +/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0; + * Data of timestamp of a CAN frame. + */ +#define TWAI_TIMESTAMP_DATA 0xFFFFFFFFU +#define TWAI_TIMESTAMP_DATA_M (TWAI_TIMESTAMP_DATA_V << TWAI_TIMESTAMP_DATA_S) +#define TWAI_TIMESTAMP_DATA_V 0xFFFFFFFFU +#define TWAI_TIMESTAMP_DATA_S 0 + +/** TWAI_TIMESTAMP_PRESCALER_REG register + * Timestamp configuration register + */ +#define TWAI_TIMESTAMP_PRESCALER_REG (DR_REG_TWAI_BASE + 0x98) +/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31; + * Configures the clock division number of timestamp counter. + */ +#define TWAI_TS_DIV_NUM 0x0000FFFFU +#define TWAI_TS_DIV_NUM_M (TWAI_TS_DIV_NUM_V << TWAI_TS_DIV_NUM_S) +#define TWAI_TS_DIV_NUM_V 0x0000FFFFU +#define TWAI_TS_DIV_NUM_S 0 + +/** TWAI_TIMESTAMP_CFG_REG register + * Timestamp configuration register + */ +#define TWAI_TIMESTAMP_CFG_REG (DR_REG_TWAI_BASE + 0x9c) +/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0; + * enable the timestamp collection function. + */ +#define TWAI_TS_ENABLE (BIT(0)) +#define TWAI_TS_ENABLE_M (TWAI_TS_ENABLE_V << TWAI_TS_ENABLE_S) +#define TWAI_TS_ENABLE_V 0x00000001U +#define TWAI_TS_ENABLE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/twai_struct.h b/components/soc/esp32c5/include/soc/twai_struct.h new file mode 100644 index 0000000000..2da08a0fe9 --- /dev/null +++ b/components/soc/esp32c5/include/soc/twai_struct.h @@ -0,0 +1,798 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of mode register + * TWAI mode register. + */ +typedef union { + struct { + /** reset_mode : R/W; bitpos: [0]; default: 1; + * 1: reset, detection of a set reset mode bit results in aborting the current + * transmission/reception of a message and entering the reset mode. 0: normal, on the + * '1-to-0' transition of the reset mode bit, the TWAI controller returns to the + * operating mode. + */ + uint32_t reset_mode:1; + /** listen_only_mode : R/W; bitpos: [1]; default: 0; + * 1: listen only, in this mode the TWAI controller would give no acknowledge to the + * TWAI-bus, even if a message is received successfully. The error counters are + * stopped at the current value. 0: normal. + */ + uint32_t listen_only_mode:1; + /** self_test_mode : R/W; bitpos: [2]; default: 0; + * 1: self test, in this mode a full node test is possible without any other active + * node on the bus using the self reception request command. The TWAI controller will + * perform a successful transmission, even if there is no acknowledge received. 0: + * normal, an acknowledge is required for successful transmission. + */ + uint32_t self_test_mode:1; + /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0; + * 1:single, the single acceptance filter option is enabled (one filter with the + * length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled + * (two filters, each with the length of 16 bit are active). + */ + uint32_t acceptance_filter_mode:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} twai_mode_reg_t; + +/** Type of cmd register + * TWAI command register. + */ +typedef union { + struct { + /** tx_request : WO; bitpos: [0]; default: 0; + * 1: present, a message shall be transmitted. 0: absent + */ + uint32_t tx_request:1; + /** abort_tx : WO; bitpos: [1]; default: 0; + * 1: present, if not already in progress, a pending transmission request is + * cancelled. 0: absent + */ + uint32_t abort_tx:1; + /** release_buffer : WO; bitpos: [2]; default: 0; + * 1: released, the receive buffer, representing the message memory space in the + * RXFIFO is released. 0: no action + */ + uint32_t release_buffer:1; + /** clear_data_overrun : WO; bitpos: [3]; default: 0; + * 1: clear, the data overrun status bit is cleared. 0: no action. + */ + uint32_t clear_data_overrun:1; + /** self_rx_request : WO; bitpos: [4]; default: 0; + * 1: present, a message shall be transmitted and received simultaneously. 0: absent. + */ + uint32_t self_rx_request:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_cmd_reg_t; + +/** Type of bus_timing_0 register + * Bit timing configuration register 0. + */ +typedef union { + struct { + /** baud_presc : R/W; bitpos: [13:0]; default: 0; + * The period of the TWAI system clock is programmable and determines the individual + * bit timing. Software has R/W permission in reset mode and RO permission in + * operation mode. + */ + uint32_t baud_presc:14; + /** sync_jump_width : R/W; bitpos: [15:14]; default: 0; + * The synchronization jump width defines the maximum number of clock cycles a bit + * period may be shortened or lengthened. Software has R/W permission in reset mode + * and RO in operation mode. + */ + uint32_t sync_jump_width:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_bus_timing_0_reg_t; + +/** Type of bus_timing_1 register + * Bit timing configuration register 1. + */ +typedef union { + struct { + /** time_segment1 : R/W; bitpos: [3:0]; default: 0; + * The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment1:4; + /** time_segment2 : R/W; bitpos: [6:4]; default: 0; + * The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in + * reset mode and RO in operation mode. + */ + uint32_t time_segment2:3; + /** time_sampling : R/W; bitpos: [7]; default: 0; + * 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t time_sampling:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_bus_timing_1_reg_t; + +/** Type of err_warning_limit register + * TWAI error threshold configuration register. + */ +typedef union { + struct { + /** err_warning_limit : R/W; bitpos: [7:0]; default: 96; + * The threshold that trigger error warning interrupt when this interrupt is enabled. + * Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t err_warning_limit:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_warning_limit_reg_t; + +/** Type of clock_divider register + * Clock divider register. + */ +typedef union { + struct { + /** cd : R/W; bitpos: [7:0]; default: 0; + * These bits are used to define the frequency at the external CLKOUT pin. + */ + uint32_t cd:8; + /** clock_off : R/W; bitpos: [8]; default: 0; + * 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has + * R/W permission in reset mode and RO in operation mode. + */ + uint32_t clock_off:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_clock_divider_reg_t; + +/** Type of sw_standby_cfg register + * Software configure standby pin directly. + */ +typedef union { + struct { + /** sw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable standby pin. + */ + uint32_t sw_standby_en:1; + /** sw_standby_clr : R/W; bitpos: [1]; default: 1; + * Clear standby pin. + */ + uint32_t sw_standby_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_sw_standby_cfg_reg_t; + +/** Type of hw_cfg register + * Hardware configure standby pin. + */ +typedef union { + struct { + /** hw_standby_en : R/W; bitpos: [0]; default: 0; + * Enable function that hardware control standby pin. + */ + uint32_t hw_standby_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_hw_cfg_reg_t; + +/** Type of hw_standby_cnt register + * Configure standby counter. + */ +typedef union { + struct { + /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN + * is enabled. + */ + uint32_t standby_wait_cnt:32; + }; + uint32_t val; +} twai_hw_standby_cnt_reg_t; + +/** Type of idle_intr_cnt register + * Configure idle interrupt counter. + */ +typedef union { + struct { + /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1; + * Configure the number of cycles before triggering idle interrupt. + */ + uint32_t idle_intr_cnt:32; + }; + uint32_t val; +} twai_idle_intr_cnt_reg_t; + +/** Type of eco_cfg register + * ECO configuration register. + */ +typedef union { + struct { + /** rdn_ena : R/W; bitpos: [0]; default: 0; + * Enable eco module. + */ + uint32_t rdn_ena:1; + /** rdn_result : RO; bitpos: [1]; default: 1; + * Output of eco module. + */ + uint32_t rdn_result:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} twai_eco_cfg_reg_t; + + +/** Group: Status Registers */ +/** Type of status register + * TWAI status register. + */ +typedef union { + struct { + /** status_receive_buffer : RO; bitpos: [0]; default: 0; + * 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no + * message is available + */ + uint32_t status_receive_buffer:1; + /** status_overrun : RO; bitpos: [1]; default: 0; + * 1: overrun, a message was lost because there was not enough space for that message + * in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data + * overrun command was given + */ + uint32_t status_overrun:1; + /** status_transmit_buffer : RO; bitpos: [2]; default: 0; + * 1: released, the CPU may write a message into the transmit buffer. 0: locked, the + * CPU cannot access the transmit buffer, a message is either waiting for transmission + * or is in the process of being transmitted + */ + uint32_t status_transmit_buffer:1; + /** status_transmission_complete : RO; bitpos: [3]; default: 0; + * 1: complete, last requested transmission has been successfully completed. 0: + * incomplete, previously requested transmission is not yet completed + */ + uint32_t status_transmission_complete:1; + /** status_receive : RO; bitpos: [4]; default: 0; + * 1: receive, the TWAI controller is receiving a message. 0: idle + */ + uint32_t status_receive:1; + /** status_transmit : RO; bitpos: [5]; default: 0; + * 1: transmit, the TWAI controller is transmitting a message. 0: idle + */ + uint32_t status_transmit:1; + /** status_err : RO; bitpos: [6]; default: 0; + * 1: error, at least one of the error counters has reached or exceeded the CPU + * warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error + * counters are below the warning limit + */ + uint32_t status_err:1; + /** status_node_bus_off : RO; bitpos: [7]; default: 0; + * 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the + * TWAI controller is involved in bus activities + */ + uint32_t status_node_bus_off:1; + /** status_miss : RO; bitpos: [8]; default: 0; + * 1: current message is destroyed because of FIFO overflow. + */ + uint32_t status_miss:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_status_reg_t; + +/** Type of arb_lost_cap register + * TWAI arbiter lost capture register. + */ +typedef union { + struct { + /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of losing arbitration. + */ + uint32_t arbitration_lost_capture:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} twai_arb_lost_cap_reg_t; + +/** Type of err_code_cap register + * TWAI error info capture register. + */ +typedef union { + struct { + /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors on the bus. + */ + uint32_t err_capture_code_segment:5; + /** err_capture_code_direction : RO; bitpos: [5]; default: 0; + * 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + */ + uint32_t err_capture_code_direction:1; + /** err_capture_code_type : RO; bitpos: [7:6]; default: 0; + * 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + */ + uint32_t err_capture_code_type:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_err_code_cap_reg_t; + +/** Type of rx_err_cnt register + * Rx error counter register. + */ +typedef union { + struct { + /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The RX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t rx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_rx_err_cnt_reg_t; + +/** Type of tx_err_cnt register + * Tx error counter register. + */ +typedef union { + struct { + /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0; + * The TX error counter register reflects the current value of the transmit error + * counter. Software has R/W permission in reset mode and RO in operation mode. + */ + uint32_t tx_err_cnt:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_tx_err_cnt_reg_t; + +/** Type of rx_message_counter register + * Received message counter register. + */ +typedef union { + struct { + /** rx_message_counter : RO; bitpos: [6:0]; default: 0; + * Reflects the number of messages available within the RXFIFO. The value is + * incremented with each receive event and decremented by the release receive buffer + * command. + */ + uint32_t rx_message_counter:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} twai_rx_message_counter_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of interrupt register + * Interrupt signals' register. + */ +typedef union { + struct { + /** receive_int_st : RO; bitpos: [0]; default: 0; + * 1: this bit is set while the receive FIFO is not empty and the RIE bit is set + * within the interrupt enable register. 0: reset + */ + uint32_t receive_int_st:1; + /** transmit_int_st : RO; bitpos: [1]; default: 0; + * 1: this bit is set whenever the transmit buffer status changes from '0-to-1' + * (released) and the TIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t transmit_int_st:1; + /** err_warning_int_st : RO; bitpos: [2]; default: 0; + * 1: this bit is set on every change (set and clear) of either the error status or + * bus status bits and the EIE bit is set within the interrupt enable register. 0: + * reset + */ + uint32_t err_warning_int_st:1; + /** data_overrun_int_st : RO; bitpos: [3]; default: 0; + * 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the + * DOIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t data_overrun_int_st:1; + /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0; + * 1: this bit is set then the timestamp counter reaches the maximum value and + * overflow. + */ + uint32_t ts_counter_ovfl_int_st:1; + /** err_passive_int_st : RO; bitpos: [5]; default: 0; + * 1: this bit is set whenever the TWAI controller has reached the error passive + * status (at least one error counter exceeds the protocol-defined level of 127) or if + * the TWAI controller is in the error passive status and enters the error active + * status again and the EPIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t err_passive_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0; + * 1: this bit is set when the TWAI controller lost the arbitration and becomes a + * receiver and the ALIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t arbitration_lost_int_st:1; + /** bus_err_int_st : RO; bitpos: [7]; default: 0; + * 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and + * the BEIE bit is set within the interrupt enable register. 0: reset + */ + uint32_t bus_err_int_st:1; + /** idle_int_st : RO; bitpos: [8]; default: 0; + * 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and + * this interrupt enable bit is set within the interrupt enable register. 0: reset + */ + uint32_t idle_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_reg_t; + +/** Type of interrupt_enable register + * Interrupt enable register. + */ +typedef union { + struct { + /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0; + * 1: enabled, when the receive buffer status is 'full' the TWAI controller requests + * the respective interrupt. 0: disable + */ + uint32_t ext_receive_int_ena:1; + /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0; + * 1: enabled, when a message has been successfully transmitted or the transmit buffer + * is accessible again (e.g. after an abort transmission command), the TWAI controller + * requests the respective interrupt. 0: disable + */ + uint32_t ext_transmit_int_ena:1; + /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0; + * 1: enabled, if the error or bus status change (see status register. Table 14), the + * TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_err_warning_int_ena:1; + /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0; + * 1: enabled, if the data overrun status bit is set (see status register. Table 14), + * the TWAI controllerrequests the respective interrupt. 0: disable + */ + uint32_t ext_data_overrun_int_ena:1; + /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0; + * enable the timestamp counter overflow interrupt request. + */ + uint32_t ts_counter_ovfl_int_ena:1; + /** err_passive_int_ena : R/W; bitpos: [5]; default: 0; + * 1: enabled, if the error status of the TWAI controller changes from error active to + * error passive or vice versa, the respective interrupt is requested. 0: disable + */ + uint32_t err_passive_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0; + * 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt + * is requested. 0: disable + */ + uint32_t arbitration_lost_int_ena:1; + /** bus_err_int_ena : R/W; bitpos: [7]; default: 0; + * 1: enabled, if an bus error has been detected, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t bus_err_int_ena:1; + /** idle_int_ena : RO; bitpos: [8]; default: 0; + * 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the + * respective interrupt. 0: disable + */ + uint32_t idle_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} twai_interrupt_enable_reg_t; + + +/** Group: Data Registers */ +/** Type of data_0 register + * Data register 0. + */ +typedef union { + struct { + /** data_0 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 0 and when + * software initiate read operation, it is rx data register 0. + */ + uint32_t data_0:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_0_reg_t; + +/** Type of data_1 register + * Data register 1. + */ +typedef union { + struct { + /** data_1 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 1 and when + * software initiate read operation, it is rx data register 1. + */ + uint32_t data_1:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_1_reg_t; + +/** Type of data_2 register + * Data register 2. + */ +typedef union { + struct { + /** data_2 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 2 and when + * software initiate read operation, it is rx data register 2. + */ + uint32_t data_2:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_2_reg_t; + +/** Type of data_3 register + * Data register 3. + */ +typedef union { + struct { + /** data_3 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance code register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 3 and when + * software initiate read operation, it is rx data register 3. + */ + uint32_t data_3:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_3_reg_t; + +/** Type of data_4 register + * Data register 4. + */ +typedef union { + struct { + /** data_4 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 0 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 4 and when + * software initiate read operation, it is rx data register 4. + */ + uint32_t data_4:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_4_reg_t; + +/** Type of data_5 register + * Data register 5. + */ +typedef union { + struct { + /** data_5 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 1 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 5 and when + * software initiate read operation, it is rx data register 5. + */ + uint32_t data_5:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_5_reg_t; + +/** Type of data_6 register + * Data register 6. + */ +typedef union { + struct { + /** data_6 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 2 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 6 and when + * software initiate read operation, it is rx data register 6. + */ + uint32_t data_6:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_6_reg_t; + +/** Type of data_7 register + * Data register 7. + */ +typedef union { + struct { + /** data_7 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, it is acceptance mask register 3 with R/W Permission. In operation + * mode, when software initiate write operation, it is tx data register 7 and when + * software initiate read operation, it is rx data register 7. + */ + uint32_t data_7:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_7_reg_t; + +/** Type of data_8 register + * Data register 8. + */ +typedef union { + struct { + /** data_8 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 8 and when software initiate read operation, it + * is rx data register 8. + */ + uint32_t data_8:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_8_reg_t; + +/** Type of data_9 register + * Data register 9. + */ +typedef union { + struct { + /** data_9 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 9 and when software initiate read operation, it + * is rx data register 9. + */ + uint32_t data_9:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_9_reg_t; + +/** Type of data_10 register + * Data register 10. + */ +typedef union { + struct { + /** data_10 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 10 and when software initiate read operation, it + * is rx data register 10. + */ + uint32_t data_10:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_10_reg_t; + +/** Type of data_11 register + * Data register 11. + */ +typedef union { + struct { + /** data_11 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 11 and when software initiate read operation, it + * is rx data register 11. + */ + uint32_t data_11:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_11_reg_t; + +/** Type of data_12 register + * Data register 12. + */ +typedef union { + struct { + /** data_12 : R/W; bitpos: [7:0]; default: 0; + * In reset mode, reserved with RO. In operation mode, when software initiate write + * operation, it is tx data register 12 and when software initiate read operation, it + * is rx data register 12. + */ + uint32_t data_12:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} twai_data_12_reg_t; + + +/** Group: Timestamp Register */ +/** Type of timestamp_data register + * Timestamp data register + */ +typedef union { + struct { + /** timestamp_data : RO; bitpos: [31:0]; default: 0; + * Data of timestamp of a CAN frame. + */ + uint32_t timestamp_data:32; + }; + uint32_t val; +} twai_timestamp_data_reg_t; + +/** Type of timestamp_prescaler register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_div_num : R/W; bitpos: [15:0]; default: 31; + * Configures the clock division number of timestamp counter. + */ + uint32_t ts_div_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} twai_timestamp_prescaler_reg_t; + +/** Type of timestamp_cfg register + * Timestamp configuration register + */ +typedef union { + struct { + /** ts_enable : R/W; bitpos: [0]; default: 0; + * enable the timestamp collection function. + */ + uint32_t ts_enable:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} twai_timestamp_cfg_reg_t; + + +typedef struct { + volatile twai_mode_reg_t mode; + volatile twai_cmd_reg_t cmd; + volatile twai_status_reg_t status; + volatile twai_interrupt_reg_t interrupt; + volatile twai_interrupt_enable_reg_t interrupt_enable; + uint32_t reserved_014; + volatile twai_bus_timing_0_reg_t bus_timing_0; + volatile twai_bus_timing_1_reg_t bus_timing_1; + uint32_t reserved_020[3]; + volatile twai_arb_lost_cap_reg_t arb_lost_cap; + volatile twai_err_code_cap_reg_t err_code_cap; + volatile twai_err_warning_limit_reg_t err_warning_limit; + volatile twai_rx_err_cnt_reg_t rx_err_cnt; + volatile twai_tx_err_cnt_reg_t tx_err_cnt; + volatile twai_data_0_reg_t data_0; + volatile twai_data_1_reg_t data_1; + volatile twai_data_2_reg_t data_2; + volatile twai_data_3_reg_t data_3; + volatile twai_data_4_reg_t data_4; + volatile twai_data_5_reg_t data_5; + volatile twai_data_6_reg_t data_6; + volatile twai_data_7_reg_t data_7; + volatile twai_data_8_reg_t data_8; + volatile twai_data_9_reg_t data_9; + volatile twai_data_10_reg_t data_10; + volatile twai_data_11_reg_t data_11; + volatile twai_data_12_reg_t data_12; + volatile twai_rx_message_counter_reg_t rx_message_counter; + uint32_t reserved_078; + volatile twai_clock_divider_reg_t clock_divider; + volatile twai_sw_standby_cfg_reg_t sw_standby_cfg; + volatile twai_hw_cfg_reg_t hw_cfg; + volatile twai_hw_standby_cnt_reg_t hw_standby_cnt; + volatile twai_idle_intr_cnt_reg_t idle_intr_cnt; + volatile twai_eco_cfg_reg_t eco_cfg; + volatile twai_timestamp_data_reg_t timestamp_data; + volatile twai_timestamp_prescaler_reg_t timestamp_prescaler; + volatile twai_timestamp_cfg_reg_t timestamp_cfg; +} twai_dev_t; + +extern twai_dev_t TWAI0; +extern twai_dev_t TWAI1; + +#ifndef __cplusplus +_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/usb_otg_misc_reg.h b/components/soc/esp32c5/include/soc/usb_otg_misc_reg.h new file mode 100644 index 0000000000..c9720ce5a6 --- /dev/null +++ b/components/soc/esp32c5/include/soc/usb_otg_misc_reg.h @@ -0,0 +1,421 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_OTG_MISC_CLK_EN0_REG register + * Reserved + */ +#define USB_OTG_MISC_CLK_EN0_REG (DR_REG_USB_OTG_MISC_BASE + 0x0) +/** USB_OTG_MISC_REG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Reserved + */ +#define USB_OTG_MISC_REG_CLK_EN (BIT(0)) +#define USB_OTG_MISC_REG_CLK_EN_M (USB_OTG_MISC_REG_CLK_EN_V << USB_OTG_MISC_REG_CLK_EN_S) +#define USB_OTG_MISC_REG_CLK_EN_V 0x00000001U +#define USB_OTG_MISC_REG_CLK_EN_S 0 + +/** USB_OTG_MISC_DATE0_REG register + * Reserved + */ +#define USB_OTG_MISC_DATE0_REG (DR_REG_USB_OTG_MISC_BASE + 0x4) +/** USB_OTG_MISC_REG_DATE : R/W; bitpos: [31:0]; default: 23050900; + * Reserved + */ +#define USB_OTG_MISC_REG_DATE 0xFFFFFFFFU +#define USB_OTG_MISC_REG_DATE_M (USB_OTG_MISC_REG_DATE_V << USB_OTG_MISC_REG_DATE_S) +#define USB_OTG_MISC_REG_DATE_V 0xFFFFFFFFU +#define USB_OTG_MISC_REG_DATE_S 0 + +/** USB_OTG_MISC_CORE_AHB_CTRL0_REG register + * USB OTG core AHB bus control. + */ +#define USB_OTG_MISC_CORE_AHB_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x8) +/** USB_OTG_MISC_REG_CORE_S_HBIGENDIAN : R/W; bitpos: [0]; default: 0; + * USB OTG core AHB slave big endian mode. 1'b0: Little, 1'b1: Big. + */ +#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN (BIT(0)) +#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_M (USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_V << USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_S) +#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_V 0x00000001U +#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_S 0 +/** USB_OTG_MISC_REG_CORE_M_HBIGENDIAN : R/W; bitpos: [1]; default: 0; + * USB OTG core AHB master big endian mode. 1'b0: Little, 1'b1: Big. + */ +#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN (BIT(1)) +#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_M (USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_V << USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_S) +#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_V 0x00000001U +#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_S 1 + +/** USB_OTG_MISC_DFIFO_CTRL0_REG register + * dfifo control. + */ +#define USB_OTG_MISC_DFIFO_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0xc) +/** USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON : R/W; bitpos: [0]; default: 0; + * enable dfifo hclk always on. + */ +#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON (BIT(0)) +#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_M (USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_V << USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_S) +#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_V 0x00000001U +#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_S 0 + +/** USB_OTG_MISC_CORE_SS_CTRL0_REG register + * USB OTG core simulation scale control. + */ +#define USB_OTG_MISC_CORE_SS_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x10) +/** USB_OTG_MISC_REG_SS_SCALEDOWN_MODE : R/W; bitpos: [1:0]; default: 0; + * USB OTG 2.0 Core Simulation Scale Down Mode, Scale-down timing values, resulting in + * simulations. + */ +#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE 0x00000003U +#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_M (USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_V << USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_S) +#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_V 0x00000003U +#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_S 0 + +/** USB_OTG_MISC_PHY_CTRL0_REG register + * USB PHY auxiliary control. + */ +#define USB_OTG_MISC_PHY_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x14) +/** USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE : R/W; bitpos: [0]; default: 0; + * Use software to override phy_pll_en. + */ +#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE (BIT(0)) +#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_M (USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_V << USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_S) +#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_S 0 +/** USB_OTG_MISC_REG_PHY_PLL_EN : R/W; bitpos: [1]; default: 0; + * Software phy_pll_en. + */ +#define USB_OTG_MISC_REG_PHY_PLL_EN (BIT(1)) +#define USB_OTG_MISC_REG_PHY_PLL_EN_M (USB_OTG_MISC_REG_PHY_PLL_EN_V << USB_OTG_MISC_REG_PHY_PLL_EN_S) +#define USB_OTG_MISC_REG_PHY_PLL_EN_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_PLL_EN_S 1 +/** USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE : R/W; bitpos: [2]; default: 0; + * Use software to override phy_suspendm. + */ +#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE (BIT(2)) +#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_M (USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_V << USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_S) +#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_S 2 +/** USB_OTG_MISC_REG_PHY_SUSPENDM : R/W; bitpos: [3]; default: 0; + * Software phy_suspendm. + */ +#define USB_OTG_MISC_REG_PHY_SUSPENDM (BIT(3)) +#define USB_OTG_MISC_REG_PHY_SUSPENDM_M (USB_OTG_MISC_REG_PHY_SUSPENDM_V << USB_OTG_MISC_REG_PHY_SUSPENDM_S) +#define USB_OTG_MISC_REG_PHY_SUSPENDM_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_SUSPENDM_S 3 +/** USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE : R/W; bitpos: [4]; default: 0; + * Use software to override phy_reset_n. + */ +#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE (BIT(4)) +#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_M (USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_V << USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_S) +#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_S 4 +/** USB_OTG_MISC_REG_PHY_RESET_N : R/W; bitpos: [5]; default: 0; + * Software phy_reset_n. + */ +#define USB_OTG_MISC_REG_PHY_RESET_N (BIT(5)) +#define USB_OTG_MISC_REG_PHY_RESET_N_M (USB_OTG_MISC_REG_PHY_RESET_N_V << USB_OTG_MISC_REG_PHY_RESET_N_S) +#define USB_OTG_MISC_REG_PHY_RESET_N_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_RESET_N_S 5 +/** USB_OTG_MISC_REG_PHY_BIST_OK : RO; bitpos: [6]; default: 0; + * USB PHY self test done. + */ +#define USB_OTG_MISC_REG_PHY_BIST_OK (BIT(6)) +#define USB_OTG_MISC_REG_PHY_BIST_OK_M (USB_OTG_MISC_REG_PHY_BIST_OK_V << USB_OTG_MISC_REG_PHY_BIST_OK_S) +#define USB_OTG_MISC_REG_PHY_BIST_OK_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_BIST_OK_S 6 +/** USB_OTG_MISC_REG_PHY_OTG_SUSPENDM : R/W; bitpos: [7]; default: 0; + * USB PHY otg_suspendm. + */ +#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM (BIT(7)) +#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_M (USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_V << USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_S) +#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_S 7 +/** USB_OTG_MISC_REG_PHY_REFCLK_MODE : R/W; bitpos: [8]; default: 1; + * Select USB PHY refclk mode. 0: refclk is 25MHz, 1: refclk is 12MHz. + */ +#define USB_OTG_MISC_REG_PHY_REFCLK_MODE (BIT(8)) +#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_M (USB_OTG_MISC_REG_PHY_REFCLK_MODE_V << USB_OTG_MISC_REG_PHY_REFCLK_MODE_S) +#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_S 8 +/** USB_OTG_MISC_REG_PHY_SELF_TEST : R/W; bitpos: [9]; default: 0; + * USB PHY self test enable. + */ +#define USB_OTG_MISC_REG_PHY_SELF_TEST (BIT(9)) +#define USB_OTG_MISC_REG_PHY_SELF_TEST_M (USB_OTG_MISC_REG_PHY_SELF_TEST_V << USB_OTG_MISC_REG_PHY_SELF_TEST_S) +#define USB_OTG_MISC_REG_PHY_SELF_TEST_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_SELF_TEST_S 9 +/** USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE : R/W; bitpos: [10]; default: 0; + * USB PHY tx bitstuff enable. + */ +#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE (BIT(10)) +#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_M (USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_V << USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_S) +#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_S 10 + +/** USB_OTG_MISC_PHY_DBG_PROBE0_REG register + * USB PHY debug probe register. + */ +#define USB_OTG_MISC_PHY_DBG_PROBE0_REG (DR_REG_USB_OTG_MISC_BASE + 0x18) +/** USB_OTG_MISC_REG_PHY_DBG_LINE_STATE : RO; bitpos: [1:0]; default: 0; + * Reserved. + */ +#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE 0x00000003U +#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_M (USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_V << USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_S) +#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_V 0x00000003U +#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_S 0 +/** USB_OTG_MISC_REG_PHY_DBG_RX_VALID : RO; bitpos: [2]; default: 0; + * Reserved. + */ +#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID (BIT(2)) +#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_M (USB_OTG_MISC_REG_PHY_DBG_RX_VALID_V << USB_OTG_MISC_REG_PHY_DBG_RX_VALID_S) +#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_S 2 +/** USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH : RO; bitpos: [3]; default: 0; + * Reserved. + */ +#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH (BIT(3)) +#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_M (USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_V << USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_S) +#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_S 3 +/** USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE : RO; bitpos: [4]; default: 0; + * Reserved. + */ +#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE (BIT(4)) +#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_M (USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_V << USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_S) +#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_S 4 +/** USB_OTG_MISC_REG_PHY_DBG_RX_ERROR : RO; bitpos: [5]; default: 0; + * Reserved. + */ +#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR (BIT(5)) +#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_M (USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_V << USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_S) +#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_S 5 +/** USB_OTG_MISC_REG_PHY_DBG_TX_READY : RO; bitpos: [6]; default: 0; + * Reserved. + */ +#define USB_OTG_MISC_REG_PHY_DBG_TX_READY (BIT(6)) +#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_M (USB_OTG_MISC_REG_PHY_DBG_TX_READY_V << USB_OTG_MISC_REG_PHY_DBG_TX_READY_S) +#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_V 0x00000001U +#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_S 6 + +/** USB_OTG_MISC_PHY_INT_RAW_REG register + * Interrupt raw of USB PHY interrupt register. + */ +#define USB_OTG_MISC_PHY_INT_RAW_REG (DR_REG_USB_OTG_MISC_BASE + 0x1c) +/** USB_OTG_MISC_REG_IDDIG_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * Interrupt raw of reg_iddig_int_st + */ +#define USB_OTG_MISC_REG_IDDIG_INT_RAW (BIT(0)) +#define USB_OTG_MISC_REG_IDDIG_INT_RAW_M (USB_OTG_MISC_REG_IDDIG_INT_RAW_V << USB_OTG_MISC_REG_IDDIG_INT_RAW_S) +#define USB_OTG_MISC_REG_IDDIG_INT_RAW_V 0x00000001U +#define USB_OTG_MISC_REG_IDDIG_INT_RAW_S 0 +/** USB_OTG_MISC_REG_VBUS_VALID_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * Interrupt raw of reg_vbus_valid_int_st + */ +#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW (BIT(1)) +#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_M (USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_V << USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_S) +#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_V 0x00000001U +#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_S 1 +/** USB_OTG_MISC_REG_SESSVALID_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * Interrupt raw of reg_sessvalid_int_st + */ +#define USB_OTG_MISC_REG_SESSVALID_INT_RAW (BIT(2)) +#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_M (USB_OTG_MISC_REG_SESSVALID_INT_RAW_V << USB_OTG_MISC_REG_SESSVALID_INT_RAW_S) +#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_V 0x00000001U +#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_S 2 +/** USB_OTG_MISC_REG_SESSEND_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * Interrupt raw of reg_sessend_int_st + */ +#define USB_OTG_MISC_REG_SESSEND_INT_RAW (BIT(3)) +#define USB_OTG_MISC_REG_SESSEND_INT_RAW_M (USB_OTG_MISC_REG_SESSEND_INT_RAW_V << USB_OTG_MISC_REG_SESSEND_INT_RAW_S) +#define USB_OTG_MISC_REG_SESSEND_INT_RAW_V 0x00000001U +#define USB_OTG_MISC_REG_SESSEND_INT_RAW_S 3 +/** USB_OTG_MISC_REG_BVALID_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * Interrupt raw of reg_bvalid_int_st + */ +#define USB_OTG_MISC_REG_BVALID_INT_RAW (BIT(4)) +#define USB_OTG_MISC_REG_BVALID_INT_RAW_M (USB_OTG_MISC_REG_BVALID_INT_RAW_V << USB_OTG_MISC_REG_BVALID_INT_RAW_S) +#define USB_OTG_MISC_REG_BVALID_INT_RAW_V 0x00000001U +#define USB_OTG_MISC_REG_BVALID_INT_RAW_S 4 +/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * Interrupt raw of reg_host_disconnect_int_st + */ +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW (BIT(5)) +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_S) +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_V 0x00000001U +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_S 5 + +/** USB_OTG_MISC_PHY_INT_CLR_REG register + * Interrupt clear of USB PHY interrupt register. + */ +#define USB_OTG_MISC_PHY_INT_CLR_REG (DR_REG_USB_OTG_MISC_BASE + 0x20) +/** USB_OTG_MISC_REG_IDDIG_INT_CLR : WT; bitpos: [0]; default: 0; + * Interrupt clear of reg_iddig_int_st + */ +#define USB_OTG_MISC_REG_IDDIG_INT_CLR (BIT(0)) +#define USB_OTG_MISC_REG_IDDIG_INT_CLR_M (USB_OTG_MISC_REG_IDDIG_INT_CLR_V << USB_OTG_MISC_REG_IDDIG_INT_CLR_S) +#define USB_OTG_MISC_REG_IDDIG_INT_CLR_V 0x00000001U +#define USB_OTG_MISC_REG_IDDIG_INT_CLR_S 0 +/** USB_OTG_MISC_REG_VBUS_VALID_INT_CLR : WT; bitpos: [1]; default: 0; + * Interrupt clear of reg_vbus_valid_int_st + */ +#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR (BIT(1)) +#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_M (USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_V << USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_S) +#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_V 0x00000001U +#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_S 1 +/** USB_OTG_MISC_REG_SESSVALID_INT_CLR : WT; bitpos: [2]; default: 0; + * Interrupt clear of reg_sessvalid_int_st + */ +#define USB_OTG_MISC_REG_SESSVALID_INT_CLR (BIT(2)) +#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_M (USB_OTG_MISC_REG_SESSVALID_INT_CLR_V << USB_OTG_MISC_REG_SESSVALID_INT_CLR_S) +#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_V 0x00000001U +#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_S 2 +/** USB_OTG_MISC_REG_SESSEND_INT_CLR : WT; bitpos: [3]; default: 0; + * Interrupt clear of reg_sessend_int_st + */ +#define USB_OTG_MISC_REG_SESSEND_INT_CLR (BIT(3)) +#define USB_OTG_MISC_REG_SESSEND_INT_CLR_M (USB_OTG_MISC_REG_SESSEND_INT_CLR_V << USB_OTG_MISC_REG_SESSEND_INT_CLR_S) +#define USB_OTG_MISC_REG_SESSEND_INT_CLR_V 0x00000001U +#define USB_OTG_MISC_REG_SESSEND_INT_CLR_S 3 +/** USB_OTG_MISC_REG_BVALID_INT_CLR : WT; bitpos: [4]; default: 0; + * Interrupt clear of reg_bvalid_int_st + */ +#define USB_OTG_MISC_REG_BVALID_INT_CLR (BIT(4)) +#define USB_OTG_MISC_REG_BVALID_INT_CLR_M (USB_OTG_MISC_REG_BVALID_INT_CLR_V << USB_OTG_MISC_REG_BVALID_INT_CLR_S) +#define USB_OTG_MISC_REG_BVALID_INT_CLR_V 0x00000001U +#define USB_OTG_MISC_REG_BVALID_INT_CLR_S 4 +/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR : WT; bitpos: [5]; default: 0; + * Interrupt clear of reg_host_disconnect_int_st + */ +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR (BIT(5)) +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_S) +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_V 0x00000001U +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_S 5 + +/** USB_OTG_MISC_PHY_INT_ENA_REG register + * Interrupt enable of USB PHY interrupt register. + */ +#define USB_OTG_MISC_PHY_INT_ENA_REG (DR_REG_USB_OTG_MISC_BASE + 0x24) +/** USB_OTG_MISC_REG_IDDIG_INT_ENA : R/W; bitpos: [0]; default: 0; + * Interrupt enable of reg_iddig_int_st + */ +#define USB_OTG_MISC_REG_IDDIG_INT_ENA (BIT(0)) +#define USB_OTG_MISC_REG_IDDIG_INT_ENA_M (USB_OTG_MISC_REG_IDDIG_INT_ENA_V << USB_OTG_MISC_REG_IDDIG_INT_ENA_S) +#define USB_OTG_MISC_REG_IDDIG_INT_ENA_V 0x00000001U +#define USB_OTG_MISC_REG_IDDIG_INT_ENA_S 0 +/** USB_OTG_MISC_REG_VBUS_VALID_INT_ENA : R/W; bitpos: [1]; default: 0; + * Interrupt enable of reg_vbus_valid_int_st + */ +#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA (BIT(1)) +#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_M (USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_V << USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_S) +#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_V 0x00000001U +#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_S 1 +/** USB_OTG_MISC_REG_SESSVALID_INT_ENA : R/W; bitpos: [2]; default: 0; + * Interrupt enable of reg_sessvalid_int_st + */ +#define USB_OTG_MISC_REG_SESSVALID_INT_ENA (BIT(2)) +#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_M (USB_OTG_MISC_REG_SESSVALID_INT_ENA_V << USB_OTG_MISC_REG_SESSVALID_INT_ENA_S) +#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_V 0x00000001U +#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_S 2 +/** USB_OTG_MISC_REG_SESSEND_INT_ENA : R/W; bitpos: [3]; default: 0; + * Interrupt enable of reg_sessend_int_st + */ +#define USB_OTG_MISC_REG_SESSEND_INT_ENA (BIT(3)) +#define USB_OTG_MISC_REG_SESSEND_INT_ENA_M (USB_OTG_MISC_REG_SESSEND_INT_ENA_V << USB_OTG_MISC_REG_SESSEND_INT_ENA_S) +#define USB_OTG_MISC_REG_SESSEND_INT_ENA_V 0x00000001U +#define USB_OTG_MISC_REG_SESSEND_INT_ENA_S 3 +/** USB_OTG_MISC_REG_BVALID_INT_ENA : R/W; bitpos: [4]; default: 0; + * Interrupt enable of reg_bvalid_int_st + */ +#define USB_OTG_MISC_REG_BVALID_INT_ENA (BIT(4)) +#define USB_OTG_MISC_REG_BVALID_INT_ENA_M (USB_OTG_MISC_REG_BVALID_INT_ENA_V << USB_OTG_MISC_REG_BVALID_INT_ENA_S) +#define USB_OTG_MISC_REG_BVALID_INT_ENA_V 0x00000001U +#define USB_OTG_MISC_REG_BVALID_INT_ENA_S 4 +/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA : R/W; bitpos: [5]; default: 0; + * Interrupt enable of reg_host_disconnect_int_st + */ +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA (BIT(5)) +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_S) +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_V 0x00000001U +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_S 5 + +/** USB_OTG_MISC_PHY_INT_ST_REG register + * USB PHY interrupt register. + */ +#define USB_OTG_MISC_PHY_INT_ST_REG (DR_REG_USB_OTG_MISC_BASE + 0x28) +/** USB_OTG_MISC_REG_IDDIG_INT_ST : RO; bitpos: [0]; default: 0; + * indicates connected plug is a mini-A or mini-B. + */ +#define USB_OTG_MISC_REG_IDDIG_INT_ST (BIT(0)) +#define USB_OTG_MISC_REG_IDDIG_INT_ST_M (USB_OTG_MISC_REG_IDDIG_INT_ST_V << USB_OTG_MISC_REG_IDDIG_INT_ST_S) +#define USB_OTG_MISC_REG_IDDIG_INT_ST_V 0x00000001U +#define USB_OTG_MISC_REG_IDDIG_INT_ST_S 0 +/** USB_OTG_MISC_REG_VBUS_VALID_INT_ST : RO; bitpos: [1]; default: 0; + * indicates if the voltage on VBUS is at a valid level for operation, 0: VBUS < 4.4V, + * 1: VBUS > 4.75V. + */ +#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST (BIT(1)) +#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_M (USB_OTG_MISC_REG_VBUS_VALID_INT_ST_V << USB_OTG_MISC_REG_VBUS_VALID_INT_ST_S) +#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_V 0x00000001U +#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_S 1 +/** USB_OTG_MISC_REG_SESSVALID_INT_ST : RO; bitpos: [2]; default: 0; + * indicates if the session for an peripheral is valid, 0: VBUS < 0.8V, 1: VBUS > 2.0V. + */ +#define USB_OTG_MISC_REG_SESSVALID_INT_ST (BIT(2)) +#define USB_OTG_MISC_REG_SESSVALID_INT_ST_M (USB_OTG_MISC_REG_SESSVALID_INT_ST_V << USB_OTG_MISC_REG_SESSVALID_INT_ST_S) +#define USB_OTG_MISC_REG_SESSVALID_INT_ST_V 0x00000001U +#define USB_OTG_MISC_REG_SESSVALID_INT_ST_S 2 +/** USB_OTG_MISC_REG_SESSEND_INT_ST : RO; bitpos: [3]; default: 0; + * indicates the voltage on VBUS, 1: VBUS < 0.2V, 0: VBUS > 0.8V. + */ +#define USB_OTG_MISC_REG_SESSEND_INT_ST (BIT(3)) +#define USB_OTG_MISC_REG_SESSEND_INT_ST_M (USB_OTG_MISC_REG_SESSEND_INT_ST_V << USB_OTG_MISC_REG_SESSEND_INT_ST_S) +#define USB_OTG_MISC_REG_SESSEND_INT_ST_V 0x00000001U +#define USB_OTG_MISC_REG_SESSEND_INT_ST_S 3 +/** USB_OTG_MISC_REG_BVALID_INT_ST : RO; bitpos: [4]; default: 0; + * indicates the voltage on VBUS, 0: VBUS < 0.8V, 1: VBUS > 4.0V. + */ +#define USB_OTG_MISC_REG_BVALID_INT_ST (BIT(4)) +#define USB_OTG_MISC_REG_BVALID_INT_ST_M (USB_OTG_MISC_REG_BVALID_INT_ST_V << USB_OTG_MISC_REG_BVALID_INT_ST_S) +#define USB_OTG_MISC_REG_BVALID_INT_ST_V 0x00000001U +#define USB_OTG_MISC_REG_BVALID_INT_ST_S 4 +/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST : RO; bitpos: [5]; default: 0; + * host disconnect. + */ +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST (BIT(5)) +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_S) +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_V 0x00000001U +#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_S 5 + +/** USB_OTG_MISC_WAKEUP_CTRL0_REG register + * USB wakeup control. + */ +#define USB_OTG_MISC_WAKEUP_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x2c) +/** USB_OTG_MISC_REG_USB_IN_SUSPEND : R/W; bitpos: [0]; default: 0; + * indicate usb is in suspend state + */ +#define USB_OTG_MISC_REG_USB_IN_SUSPEND (BIT(0)) +#define USB_OTG_MISC_REG_USB_IN_SUSPEND_M (USB_OTG_MISC_REG_USB_IN_SUSPEND_V << USB_OTG_MISC_REG_USB_IN_SUSPEND_S) +#define USB_OTG_MISC_REG_USB_IN_SUSPEND_V 0x00000001U +#define USB_OTG_MISC_REG_USB_IN_SUSPEND_S 0 +/** USB_OTG_MISC_REG_USB_WKUP_CLR : WT; bitpos: [1]; default: 0; + * clear usb wakeup signals. + */ +#define USB_OTG_MISC_REG_USB_WKUP_CLR (BIT(1)) +#define USB_OTG_MISC_REG_USB_WKUP_CLR_M (USB_OTG_MISC_REG_USB_WKUP_CLR_V << USB_OTG_MISC_REG_USB_WKUP_CLR_S) +#define USB_OTG_MISC_REG_USB_WKUP_CLR_V 0x00000001U +#define USB_OTG_MISC_REG_USB_WKUP_CLR_S 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/usb_otg_misc_struct.h b/components/soc/esp32c5/include/soc/usb_otg_misc_struct.h new file mode 100644 index 0000000000..eaba6c57da --- /dev/null +++ b/components/soc/esp32c5/include/soc/usb_otg_misc_struct.h @@ -0,0 +1,370 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: clk_en */ +/** Type of clk_en0 register + * Reserved + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 0; + * Reserved + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_otg_misc_clk_en0_reg_t; + + +/** Group: date */ +/** Type of date0 register + * Reserved + */ +typedef union { + struct { + /** reg_date : R/W; bitpos: [31:0]; default: 23050900; + * Reserved + */ + uint32_t reg_date:32; + }; + uint32_t val; +} usb_otg_misc_date0_reg_t; + + +/** Group: core_ahb_ctrl */ +/** Type of core_ahb_ctrl0 register + * USB OTG core AHB bus control. + */ +typedef union { + struct { + /** reg_core_s_hbigendian : R/W; bitpos: [0]; default: 0; + * USB OTG core AHB slave big endian mode. 1'b0: Little, 1'b1: Big. + */ + uint32_t reg_core_s_hbigendian:1; + /** reg_core_m_hbigendian : R/W; bitpos: [1]; default: 0; + * USB OTG core AHB master big endian mode. 1'b0: Little, 1'b1: Big. + */ + uint32_t reg_core_m_hbigendian:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_otg_misc_core_ahb_ctrl0_reg_t; + + +/** Group: dfifo_ctrl */ +/** Type of dfifo_ctrl0 register + * dfifo control. + */ +typedef union { + struct { + /** reg_dfifo_hclk_force_on : R/W; bitpos: [0]; default: 0; + * enable dfifo hclk always on. + */ + uint32_t reg_dfifo_hclk_force_on:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_otg_misc_dfifo_ctrl0_reg_t; + + +/** Group: core_ss_ctrl */ +/** Type of core_ss_ctrl0 register + * USB OTG core simulation scale control. + */ +typedef union { + struct { + /** reg_ss_scaledown_mode : R/W; bitpos: [1:0]; default: 0; + * USB OTG 2.0 Core Simulation Scale Down Mode, Scale-down timing values, resulting in + * simulations. + */ + uint32_t reg_ss_scaledown_mode:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_otg_misc_core_ss_ctrl0_reg_t; + + +/** Group: phy_ctrl */ +/** Type of phy_ctrl0 register + * USB PHY auxiliary control. + */ +typedef union { + struct { + /** reg_phy_pll_en_override : R/W; bitpos: [0]; default: 0; + * Use software to override phy_pll_en. + */ + uint32_t reg_phy_pll_en_override:1; + /** reg_phy_pll_en : R/W; bitpos: [1]; default: 0; + * Software phy_pll_en. + */ + uint32_t reg_phy_pll_en:1; + /** reg_phy_suspendm_override : R/W; bitpos: [2]; default: 0; + * Use software to override phy_suspendm. + */ + uint32_t reg_phy_suspendm_override:1; + /** reg_phy_suspendm : R/W; bitpos: [3]; default: 0; + * Software phy_suspendm. + */ + uint32_t reg_phy_suspendm:1; + /** reg_phy_reset_n_override : R/W; bitpos: [4]; default: 0; + * Use software to override phy_reset_n. + */ + uint32_t reg_phy_reset_n_override:1; + /** reg_phy_reset_n : R/W; bitpos: [5]; default: 0; + * Software phy_reset_n. + */ + uint32_t reg_phy_reset_n:1; + /** reg_phy_bist_ok : RO; bitpos: [6]; default: 0; + * USB PHY self test done. + */ + uint32_t reg_phy_bist_ok:1; + /** reg_phy_otg_suspendm : R/W; bitpos: [7]; default: 0; + * USB PHY otg_suspendm. + */ + uint32_t reg_phy_otg_suspendm:1; + /** reg_phy_refclk_mode : R/W; bitpos: [8]; default: 1; + * Select USB PHY refclk mode. 0: refclk is 25MHz, 1: refclk is 12MHz. + */ + uint32_t reg_phy_refclk_mode:1; + /** reg_phy_self_test : R/W; bitpos: [9]; default: 0; + * USB PHY self test enable. + */ + uint32_t reg_phy_self_test:1; + /** reg_phy_txbitstuff_enable : R/W; bitpos: [10]; default: 0; + * USB PHY tx bitstuff enable. + */ + uint32_t reg_phy_txbitstuff_enable:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_otg_misc_phy_ctrl0_reg_t; + + +/** Group: phy_dbg_probe */ +/** Type of phy_dbg_probe0 register + * USB PHY debug probe register. + */ +typedef union { + struct { + /** reg_phy_dbg_line_state : RO; bitpos: [1:0]; default: 0; + * Reserved. + */ + uint32_t reg_phy_dbg_line_state:2; + /** reg_phy_dbg_rx_valid : RO; bitpos: [2]; default: 0; + * Reserved. + */ + uint32_t reg_phy_dbg_rx_valid:1; + /** reg_phy_dbg_rx_validh : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t reg_phy_dbg_rx_validh:1; + /** reg_phy_dbg_rx_active : RO; bitpos: [4]; default: 0; + * Reserved. + */ + uint32_t reg_phy_dbg_rx_active:1; + /** reg_phy_dbg_rx_error : RO; bitpos: [5]; default: 0; + * Reserved. + */ + uint32_t reg_phy_dbg_rx_error:1; + /** reg_phy_dbg_tx_ready : RO; bitpos: [6]; default: 0; + * Reserved. + */ + uint32_t reg_phy_dbg_tx_ready:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_otg_misc_phy_dbg_probe0_reg_t; + + +/** Group: Interrupt */ +/** Type of phy_int_raw register + * Interrupt raw of USB PHY interrupt register. + */ +typedef union { + struct { + /** reg_iddig_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * Interrupt raw of reg_iddig_int_st + */ + uint32_t reg_iddig_int_raw:1; + /** reg_vbus_valid_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * Interrupt raw of reg_vbus_valid_int_st + */ + uint32_t reg_vbus_valid_int_raw:1; + /** reg_sessvalid_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * Interrupt raw of reg_sessvalid_int_st + */ + uint32_t reg_sessvalid_int_raw:1; + /** reg_sessend_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * Interrupt raw of reg_sessend_int_st + */ + uint32_t reg_sessend_int_raw:1; + /** reg_bvalid_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * Interrupt raw of reg_bvalid_int_st + */ + uint32_t reg_bvalid_int_raw:1; + /** reg_host_disconnect_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * Interrupt raw of reg_host_disconnect_int_st + */ + uint32_t reg_host_disconnect_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_otg_misc_phy_int_raw_reg_t; + +/** Type of phy_int_clr register + * Interrupt clear of USB PHY interrupt register. + */ +typedef union { + struct { + /** reg_iddig_int_clr : WT; bitpos: [0]; default: 0; + * Interrupt clear of reg_iddig_int_st + */ + uint32_t reg_iddig_int_clr:1; + /** reg_vbus_valid_int_clr : WT; bitpos: [1]; default: 0; + * Interrupt clear of reg_vbus_valid_int_st + */ + uint32_t reg_vbus_valid_int_clr:1; + /** reg_sessvalid_int_clr : WT; bitpos: [2]; default: 0; + * Interrupt clear of reg_sessvalid_int_st + */ + uint32_t reg_sessvalid_int_clr:1; + /** reg_sessend_int_clr : WT; bitpos: [3]; default: 0; + * Interrupt clear of reg_sessend_int_st + */ + uint32_t reg_sessend_int_clr:1; + /** reg_bvalid_int_clr : WT; bitpos: [4]; default: 0; + * Interrupt clear of reg_bvalid_int_st + */ + uint32_t reg_bvalid_int_clr:1; + /** reg_host_disconnect_int_clr : WT; bitpos: [5]; default: 0; + * Interrupt clear of reg_host_disconnect_int_st + */ + uint32_t reg_host_disconnect_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_otg_misc_phy_int_clr_reg_t; + +/** Type of phy_int_ena register + * Interrupt enable of USB PHY interrupt register. + */ +typedef union { + struct { + /** reg_iddig_int_ena : R/W; bitpos: [0]; default: 0; + * Interrupt enable of reg_iddig_int_st + */ + uint32_t reg_iddig_int_ena:1; + /** reg_vbus_valid_int_ena : R/W; bitpos: [1]; default: 0; + * Interrupt enable of reg_vbus_valid_int_st + */ + uint32_t reg_vbus_valid_int_ena:1; + /** reg_sessvalid_int_ena : R/W; bitpos: [2]; default: 0; + * Interrupt enable of reg_sessvalid_int_st + */ + uint32_t reg_sessvalid_int_ena:1; + /** reg_sessend_int_ena : R/W; bitpos: [3]; default: 0; + * Interrupt enable of reg_sessend_int_st + */ + uint32_t reg_sessend_int_ena:1; + /** reg_bvalid_int_ena : R/W; bitpos: [4]; default: 0; + * Interrupt enable of reg_bvalid_int_st + */ + uint32_t reg_bvalid_int_ena:1; + /** reg_host_disconnect_int_ena : R/W; bitpos: [5]; default: 0; + * Interrupt enable of reg_host_disconnect_int_st + */ + uint32_t reg_host_disconnect_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_otg_misc_phy_int_ena_reg_t; + +/** Type of phy_int_st register + * USB PHY interrupt register. + */ +typedef union { + struct { + /** reg_iddig_int_st : RO; bitpos: [0]; default: 0; + * indicates connected plug is a mini-A or mini-B. + */ + uint32_t reg_iddig_int_st:1; + /** reg_vbus_valid_int_st : RO; bitpos: [1]; default: 0; + * indicates if the voltage on VBUS is at a valid level for operation, 0: VBUS < 4.4V, + * 1: VBUS > 4.75V. + */ + uint32_t reg_vbus_valid_int_st:1; + /** reg_sessvalid_int_st : RO; bitpos: [2]; default: 0; + * indicates if the session for an peripheral is valid, 0: VBUS < 0.8V, 1: VBUS > 2.0V. + */ + uint32_t reg_sessvalid_int_st:1; + /** reg_sessend_int_st : RO; bitpos: [3]; default: 0; + * indicates the voltage on VBUS, 1: VBUS < 0.2V, 0: VBUS > 0.8V. + */ + uint32_t reg_sessend_int_st:1; + /** reg_bvalid_int_st : RO; bitpos: [4]; default: 0; + * indicates the voltage on VBUS, 0: VBUS < 0.8V, 1: VBUS > 4.0V. + */ + uint32_t reg_bvalid_int_st:1; + /** reg_host_disconnect_int_st : RO; bitpos: [5]; default: 0; + * host disconnect. + */ + uint32_t reg_host_disconnect_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_otg_misc_phy_int_st_reg_t; + + +/** Group: wakeup_ctrl */ +/** Type of wakeup_ctrl0 register + * USB wakeup control. + */ +typedef union { + struct { + /** reg_usb_in_suspend : R/W; bitpos: [0]; default: 0; + * indicate usb is in suspend state + */ + uint32_t reg_usb_in_suspend:1; + /** reg_usb_wkup_clr : WT; bitpos: [1]; default: 0; + * clear usb wakeup signals. + */ + uint32_t reg_usb_wkup_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_otg_misc_wakeup_ctrl0_reg_t; + + +typedef struct { + volatile usb_otg_misc_clk_en0_reg_t clk_en0; + volatile usb_otg_misc_date0_reg_t date0; + volatile usb_otg_misc_core_ahb_ctrl0_reg_t core_ahb_ctrl0; + volatile usb_otg_misc_dfifo_ctrl0_reg_t dfifo_ctrl0; + volatile usb_otg_misc_core_ss_ctrl0_reg_t core_ss_ctrl0; + volatile usb_otg_misc_phy_ctrl0_reg_t phy_ctrl0; + volatile usb_otg_misc_phy_dbg_probe0_reg_t phy_dbg_probe0; + volatile usb_otg_misc_phy_int_raw_reg_t phy_int_raw; + volatile usb_otg_misc_phy_int_clr_reg_t phy_int_clr; + volatile usb_otg_misc_phy_int_ena_reg_t phy_int_ena; + volatile usb_otg_misc_phy_int_st_reg_t phy_int_st; + volatile usb_otg_misc_wakeup_ctrl0_reg_t wakeup_ctrl0; +} usb_otg_misc_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(usb_otg_misc_dev_t) == 0x30, "Invalid size of usb_otg_misc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h new file mode 100644 index 0000000000..5bc71a9d1b --- /dev/null +++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h @@ -0,0 +1,1188 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_SERIAL_JTAG_EP1_REG register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 + +/** USB_SERIAL_JTAG_EP1_CONF_REG register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 + +/** USB_SERIAL_JTAG_INT_RAW_REG register + * Interrupt raw status register. + */ +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 + +/** USB_SERIAL_JTAG_INT_ST_REG register + * Interrupt status register. + */ +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 + +/** USB_SERIAL_JTAG_INT_ENA_REG register + * Interrupt enable status register. + */ +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 + +/** USB_SERIAL_JTAG_INT_CLR_REG register + * Interrupt clear status register. + */ +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 + +/** USB_SERIAL_JTAG_CONF0_REG register + * PHY hardware configuration. + */ +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 + +/** USB_SERIAL_JTAG_TEST_REG register + * Registers used for debugging the PHY. + */ +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 + +/** USB_SERIAL_JTAG_JFIFO_ST_REG register + * JTAG FIFO status and control registers. + */ +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 + +/** USB_SERIAL_JTAG_FRAM_NUM_REG register + * Last received SOF frame index register. + */ +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 + +/** USB_SERIAL_JTAG_IN_EP0_ST_REG register + * Control IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP1_ST_REG register + * CDC-ACM IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP2_ST_REG register + * CDC-ACM interrupt IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_IN_EP3_ST_REG register + * JTAG IN endpoint status information. + */ +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register + * Control OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register + * CDC-ACM OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 + +/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register + * JTAG OUT endpoint status information. + */ +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 + +/** USB_SERIAL_JTAG_MISC_CONF_REG register + * Clock enable control + */ +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 + +/** USB_SERIAL_JTAG_MEM_CONF_REG register + * Memory power control + */ +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 + +/** USB_SERIAL_JTAG_CHIP_RST_REG register + * CDC-ACM chip reset control. + */ +#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register + * W0 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register + * W1 of SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register + * W0 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 + +/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register + * W1 of GET_LINE_CODING command. + */ +#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 + +/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register + * Configuration registers' value update + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 + +/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register + * Serial AFIFO configure register + */ +#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 + +/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register + * USB Bus reset status register + */ +#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 + +/** USB_SERIAL_JTAG_DATE_REG register + * Date register + */ +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416; + * register version. + */ +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h new file mode 100644 index 0000000000..3c3442301b --- /dev/null +++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h @@ -0,0 +1,941 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of ep1 register + * FIFO access for the CDC-ACM data IN and OUT endpoints. + */ +typedef union { + struct { + /** rdwr_byte : R/W; bitpos: [7:0]; default: 0; + * Write and read byte data to/from UART Tx/Rx FIFO through this field. When + * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 + * bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user + * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know + * how many data is received, then read data from UART Rx FIFO. + */ + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} usb_serial_jtag_ep1_reg_t; + +/** Type of ep1_conf register + * Configuration and control registers for the CDC-ACM FIFOs. + */ +typedef union { + struct { + /** wr_done : WT; bitpos: [0]; default: 0; + * Set this bit to indicate writing byte data to UART Tx FIFO is done. + */ + uint32_t wr_done:1; + /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1; + * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing + * USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by + * USB Host. + */ + uint32_t serial_in_ep_data_free:1; + /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0; + * 1'b1: Indicate there is data in UART Rx FIFO. + */ + uint32_t serial_out_ep_data_avail:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_ep1_conf_reg_t; + +/** Type of conf0 register + * PHY hardware configuration. + */ +typedef union { + struct { + /** phy_sel : R/W; bitpos: [0]; default: 0; + * Select internal/external PHY + */ + uint32_t phy_sel:1; + /** exchg_pins_override : R/W; bitpos: [1]; default: 0; + * Enable software control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [2]; default: 0; + * USB D+ D- exchange + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [4:3]; default: 0; + * Control single-end input high threshold,1.76V to 2V, step 80mV + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [6:5]; default: 0; + * Control single-end input low threshold,0.8V to 1.04V, step 80mV + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [7]; default: 0; + * Enable software control input threshold + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [8]; default: 0; + * Enable software control USB D+ D- pullup pulldown + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [9]; default: 1; + * Control USB D+ pull up. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [10]; default: 0; + * Control USB D+ pull down. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [11]; default: 0; + * Control USB D- pull up. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [12]; default: 0; + * Control USB D- pull down. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [13]; default: 0; + * Control pull up value. + */ + uint32_t pullup_value:1; + /** usb_pad_enable : R/W; bitpos: [14]; default: 1; + * Enable USB pad function. + */ + uint32_t usb_pad_enable:1; + /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0; + * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is + * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input + * through GPIO Matrix. + */ + uint32_t usb_jtag_bridge_en:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_conf0_reg_t; + +/** Type of test register + * Registers used for debugging the PHY. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable test of the USB pad + */ + uint32_t test_enable:1; + /** test_usb_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test + */ + uint32_t test_usb_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 1; + * USB RCV value in test + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 1; + * USB D+ rx value in test + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test + */ + uint32_t test_rx_dm:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} usb_serial_jtag_test_reg_t; + +/** Type of misc_conf register + * Clock enable control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_misc_conf_reg_t; + +/** Type of mem_conf register + * Memory power control + */ +typedef union { + struct { + /** usb_mem_pd : R/W; bitpos: [0]; default: 0; + * 1: power down usb memory. + */ + uint32_t usb_mem_pd:1; + /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1; + * 1: Force clock on for usb memory. + */ + uint32_t usb_mem_clk_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} usb_serial_jtag_mem_conf_reg_t; + +/** Type of chip_rst register + * CDC-ACM chip reset control. + */ +typedef union { + struct { + /** rts : RO; bitpos: [0]; default: 0; + * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + */ + uint32_t rts:1; + /** dtr : RO; bitpos: [1]; default: 0; + * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + */ + uint32_t dtr:1; + /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable chip reset from usb serial channel to reset chip. + */ + uint32_t usb_uart_chip_rst_dis:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} usb_serial_jtag_chip_rst_reg_t; + +/** Type of get_line_code_w0 register + * W0 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w0_reg_t; + +/** Type of get_line_code_w1 register + * W1 of GET_LINE_CODING command. + */ +typedef union { + struct { + /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bdata_bits:8; + /** get_bparity_type : R/W; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bparity_type:8; + /** get_bchar_format : R/W; bitpos: [23:16]; default: 0; + * The value of bDataBits set by software which is requested by GET_LINE_CODING + * command. + */ + uint32_t get_bchar_format:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_get_line_code_w1_reg_t; + +/** Type of config_update register + * Configuration registers' value update + */ +typedef union { + struct { + /** config_update : WT; bitpos: [0]; default: 0; + * Write 1 to this register would update the value of configure registers from APB + * clock domain to 48MHz clock domain. + */ + uint32_t config_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_config_update_reg_t; + +/** Type of ser_afifo_config register + * Serial AFIFO configure register + */ +typedef union { + struct { + /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO write clock domain. + */ + uint32_t serial_in_afifo_reset_wr:1; + /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0; + * Write 1 to reset CDC_ACM IN async FIFO read clock domain. + */ + uint32_t serial_in_afifo_reset_rd:1; + /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + */ + uint32_t serial_out_afifo_reset_wr:1; + /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0; + * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + */ + uint32_t serial_out_afifo_reset_rd:1; + /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1; + * CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + */ + uint32_t serial_out_afifo_rempty:1; + /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0; + * CDC_ACM OUT IN async FIFO empty signal in write clock domain. + */ + uint32_t serial_in_afifo_wfull:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} usb_serial_jtag_ser_afifo_config_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of int_raw register + * Interrupt raw status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when flush cmd is received for IN + * endpoint 2 of JTAG. + */ + uint32_t jtag_in_flush_int_raw:1; + /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when SOF frame is received. + */ + uint32_t sof_int_raw:1; + /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received + * one packet. + */ + uint32_t serial_out_recv_pkt_int_raw:1; + /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1; + * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + */ + uint32_t serial_in_empty_int_raw:1; + /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when pid error is detected. + */ + uint32_t pid_err_int_raw:1; + /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when CRC5 error is detected. + */ + uint32_t crc5_err_int_raw:1; + /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when CRC16 error is detected. + */ + uint32_t crc16_err_int_raw:1; + /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when stuff error is detected. + */ + uint32_t stuff_err_int_raw:1; + /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is + * received. + */ + uint32_t in_token_rec_in_ep1_int_raw:1; + /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit turns to high level when usb bus reset is detected. + */ + uint32_t usb_bus_reset_int_raw:1; + /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with + * zero palyload. + */ + uint32_t out_ep1_zero_payload_int_raw:1; + /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with + * zero palyload. + */ + uint32_t out_ep2_zero_payload_int_raw:1; + /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit turns to high level when level of RTS from usb serial channel + * is changed. + */ + uint32_t rts_chg_int_raw:1; + /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit turns to high level when level of DTR from usb serial channel + * is changed. + */ + uint32_t dtr_chg_int_raw:1; + /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit turns to high level when level of GET LINE CODING request is + * received. + */ + uint32_t get_line_code_int_raw:1; + /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit turns to high level when level of SET LINE CODING request is + * received. + */ + uint32_t set_line_code_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_raw_reg_t; + +/** Type of int_st register + * Interrupt status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_st:1; + /** sof_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_st:1; + /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * interrupt. + */ + uint32_t serial_out_recv_pkt_int_st:1; + /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_st:1; + /** pid_err_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_st:1; + /** crc5_err_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_st:1; + /** crc16_err_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_st:1; + /** stuff_err_int_st : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_st:1; + /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT + * interrupt. + */ + uint32_t in_token_rec_in_ep1_int_st:1; + /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_st:1; + /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep1_zero_payload_int_st:1; + /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT + * interrupt. + */ + uint32_t out_ep2_zero_payload_int_st:1; + /** rts_chg_int_st : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_st:1; + /** dtr_chg_int_st : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_st:1; + /** get_line_code_int_st : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_st:1; + /** set_line_code_int_st : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_ena:1; + /** sof_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_ena:1; + /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_ena:1; + /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_ena:1; + /** pid_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_ena:1; + /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_ena:1; + /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_ena:1; + /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_ena:1; + /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_ena:1; + /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_ena:1; + /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_ena:1; + /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_ena:1; + /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_ena:1; + /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_ena:1; + /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_ena:1; + /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear status register. + */ +typedef union { + struct { + /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt. + */ + uint32_t jtag_in_flush_int_clr:1; + /** sof_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt. + */ + uint32_t sof_int_clr:1; + /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt. + */ + uint32_t serial_out_recv_pkt_int_clr:1; + /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt. + */ + uint32_t serial_in_empty_int_clr:1; + /** pid_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt. + */ + uint32_t pid_err_int_clr:1; + /** crc5_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt. + */ + uint32_t crc5_err_int_clr:1; + /** crc16_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt. + */ + uint32_t crc16_err_int_clr:1; + /** stuff_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt. + */ + uint32_t stuff_err_int_clr:1; + /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt. + */ + uint32_t in_token_rec_in_ep1_int_clr:1; + /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt. + */ + uint32_t usb_bus_reset_int_clr:1; + /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep1_zero_payload_int_clr:1; + /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + */ + uint32_t out_ep2_zero_payload_int_clr:1; + /** rts_chg_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt. + */ + uint32_t rts_chg_int_clr:1; + /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt. + */ + uint32_t dtr_chg_int_clr:1; + /** get_line_code_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt. + */ + uint32_t get_line_code_int_clr:1; + /** set_line_code_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt. + */ + uint32_t set_line_code_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_int_clr_reg_t; + + +/** Group: Status Registers */ +/** Type of jfifo_st register + * JTAG FIFO status and control registers. + */ +typedef union { + struct { + /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0; + * JTAT in fifo counter. + */ + uint32_t in_fifo_cnt:2; + /** in_fifo_empty : RO; bitpos: [2]; default: 1; + * 1: JTAG in fifo is empty. + */ + uint32_t in_fifo_empty:1; + /** in_fifo_full : RO; bitpos: [3]; default: 0; + * 1: JTAG in fifo is full. + */ + uint32_t in_fifo_full:1; + /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0; + * JTAT out fifo counter. + */ + uint32_t out_fifo_cnt:2; + /** out_fifo_empty : RO; bitpos: [6]; default: 1; + * 1: JTAG out fifo is empty. + */ + uint32_t out_fifo_empty:1; + /** out_fifo_full : RO; bitpos: [7]; default: 0; + * 1: JTAG out fifo is full. + */ + uint32_t out_fifo_full:1; + /** in_fifo_reset : R/W; bitpos: [8]; default: 0; + * Write 1 to reset JTAG in fifo. + */ + uint32_t in_fifo_reset:1; + /** out_fifo_reset : R/W; bitpos: [9]; default: 0; + * Write 1 to reset JTAG out fifo. + */ + uint32_t out_fifo_reset:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} usb_serial_jtag_jfifo_st_reg_t; + +/** Type of fram_num register + * Last received SOF frame index register. + */ +typedef union { + struct { + /** sof_frame_index : RO; bitpos: [10:0]; default: 0; + * Frame index of received SOF frame. + */ + uint32_t sof_frame_index:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} usb_serial_jtag_fram_num_reg_t; + +/** Type of in_ep0_st register + * Control IN endpoint status information. + */ +typedef union { + struct { + /** in_ep0_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 0. + */ + uint32_t in_ep0_state:2; + /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 0. + */ + uint32_t in_ep0_wr_addr:7; + /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 0. + */ + uint32_t in_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep0_st_reg_t; + +/** Type of in_ep1_st register + * CDC-ACM IN endpoint status information. + */ +typedef union { + struct { + /** in_ep1_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 1. + */ + uint32_t in_ep1_state:2; + /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 1. + */ + uint32_t in_ep1_wr_addr:7; + /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 1. + */ + uint32_t in_ep1_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep1_st_reg_t; + +/** Type of in_ep2_st register + * CDC-ACM interrupt IN endpoint status information. + */ +typedef union { + struct { + /** in_ep2_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 2. + */ + uint32_t in_ep2_state:2; + /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 2. + */ + uint32_t in_ep2_wr_addr:7; + /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 2. + */ + uint32_t in_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep2_st_reg_t; + +/** Type of in_ep3_st register + * JTAG IN endpoint status information. + */ +typedef union { + struct { + /** in_ep3_state : RO; bitpos: [1:0]; default: 1; + * State of IN Endpoint 3. + */ + uint32_t in_ep3_state:2; + /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of IN endpoint 3. + */ + uint32_t in_ep3_wr_addr:7; + /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of IN endpoint 3. + */ + uint32_t in_ep3_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_in_ep3_st_reg_t; + +/** Type of out_ep0_st register + * Control OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep0_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 0. + */ + uint32_t out_ep0_state:2; + /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + */ + uint32_t out_ep0_wr_addr:7; + /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 0. + */ + uint32_t out_ep0_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep0_st_reg_t; + +/** Type of out_ep1_st register + * CDC-ACM OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep1_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 1. + */ + uint32_t out_ep1_state:2; + /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + */ + uint32_t out_ep1_wr_addr:7; + /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 1. + */ + uint32_t out_ep1_rd_addr:7; + /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0; + * Data count in OUT endpoint 1 when one packet is received. + */ + uint32_t out_ep1_rec_data_cnt:7; + uint32_t reserved_23:9; + }; + uint32_t val; +} usb_serial_jtag_out_ep1_st_reg_t; + +/** Type of out_ep2_st register + * JTAG OUT endpoint status information. + */ +typedef union { + struct { + /** out_ep2_state : RO; bitpos: [1:0]; default: 0; + * State of OUT Endpoint 2. + */ + uint32_t out_ep2_state:2; + /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0; + * Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT + * is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + */ + uint32_t out_ep2_wr_addr:7; + /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0; + * Read data address of OUT endpoint 2. + */ + uint32_t out_ep2_rd_addr:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} usb_serial_jtag_out_ep2_st_reg_t; + +/** Type of set_line_code_w0 register + * W0 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** dw_dte_rate : RO; bitpos: [31:0]; default: 0; + * The value of dwDTERate set by host through SET_LINE_CODING command. + */ + uint32_t dw_dte_rate:32; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w0_reg_t; + +/** Type of set_line_code_w1 register + * W1 of SET_LINE_CODING command. + */ +typedef union { + struct { + /** bchar_format : RO; bitpos: [7:0]; default: 0; + * The value of bCharFormat set by host through SET_LINE_CODING command. + */ + uint32_t bchar_format:8; + /** bparity_type : RO; bitpos: [15:8]; default: 0; + * The value of bParityTpye set by host through SET_LINE_CODING command. + */ + uint32_t bparity_type:8; + /** bdata_bits : RO; bitpos: [23:16]; default: 0; + * The value of bDataBits set by host through SET_LINE_CODING command. + */ + uint32_t bdata_bits:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} usb_serial_jtag_set_line_code_w1_reg_t; + +/** Type of bus_reset_st register + * USB Bus reset status register + */ +typedef union { + struct { + /** usb_bus_reset_st : RO; bitpos: [0]; default: 1; + * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus + * reset is released. + */ + uint32_t usb_bus_reset_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} usb_serial_jtag_bus_reset_st_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Date register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 34640416; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} usb_serial_jtag_date_reg_t; + + +typedef struct { + volatile usb_serial_jtag_ep1_reg_t ep1; + volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; + volatile usb_serial_jtag_int_raw_reg_t int_raw; + volatile usb_serial_jtag_int_st_reg_t int_st; + volatile usb_serial_jtag_int_ena_reg_t int_ena; + volatile usb_serial_jtag_int_clr_reg_t int_clr; + volatile usb_serial_jtag_conf0_reg_t conf0; + volatile usb_serial_jtag_test_reg_t test; + volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st; + volatile usb_serial_jtag_fram_num_reg_t fram_num; + volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st; + volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st; + volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st; + volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st; + volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st; + volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st; + volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st; + volatile usb_serial_jtag_misc_conf_reg_t misc_conf; + volatile usb_serial_jtag_mem_conf_reg_t mem_conf; + volatile usb_serial_jtag_chip_rst_reg_t chip_rst; + volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0; + volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1; + volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0; + volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1; + volatile usb_serial_jtag_config_update_reg_t config_update; + volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config; + volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st; + uint32_t reserved_06c[5]; + volatile usb_serial_jtag_date_reg_t date; +} usb_serial_jtag_dev_t; + +extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; + +#ifndef __cplusplus +_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif