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Merge branch 'feature/esp32c5_mp_gpio_support' into 'master'

Browse Source 
C5 gpio support and update docs

See merge request espressif/esp-idf!30792
This commit is contained in:
Gao Xu 2024-05-13 18:36:52 +08:00
commit 1029476a82
11 changed files with 140 additions and 72 deletions
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1
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.heap.ld
View File

@ -76,5 +76,6 @@ PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
PROVIDE (multi_heap_check = multi_heap_check);
PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init);
PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);

2
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.pp.ld
View File

@ -62,7 +62,7 @@ ic_get_he_rts_threshold_bytes = 0x40000c88;
lmacAdjustTimestamp = 0x40000c8c;
lmacDiscardAgedMSDU = 0x40000c90;
lmacDiscardMSDU = 0x40000c94;
/*lmacEndFrameExchangeSequence = 0x40000c98;*/
lmacEndFrameExchangeSequence = 0x40000c98;
lmacIsIdle = 0x40000c9c;
lmacIsLongFrame = 0x40000ca0;
lmacMSDUAged = 0x40000ca4;

133
components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.rvfp.ld
View File

@ -18,23 +18,23 @@
***************************************/
/* Functions */
_rvfp__addsf3 = 0x40000a2c;
_rvfp__eqsf2 = 0x40000a30;
_rvfp__extendsfdf2 = 0x40000a34;
_rvfp__fixsfsi = 0x40000a38;
_rvfp__fixunssfsi = 0x40000a3c;
_rvfp__floatdisf = 0x40000a40;
_rvfp__floatsisf = 0x40000a44;
_rvfp__floatundisf = 0x40000a48;
_rvfp__floatunsisf = 0x40000a4c;
_rvfp__gesf2 = 0x40000a50;
_rvfp__gtsf2 = 0x40000a54;
_rvfp__lesf2 = 0x40000a58;
_rvfp__ltsf2 = 0x40000a5c;
_rvfp__mulsf3 = 0x40000a60;
_rvfp__nesf2 = 0x40000a64;
_rvfp__subsf3 = 0x40000a68;
_rvfp__truncdfsf2 = 0x40000a6c;
__addsf3 = 0x40000a2c;
__eqsf2 = 0x40000a30;
__extendsfdf2 = 0x40000a34;
__fixsfsi = 0x40000a38;
__fixunssfsi = 0x40000a3c;
__floatdisf = 0x40000a40;
__floatsisf = 0x40000a44;
__floatundisf = 0x40000a48;
__floatunsisf = 0x40000a4c;
__gesf2 = 0x40000a50;
__gtsf2 = 0x40000a54;
__lesf2 = 0x40000a58;
__ltsf2 = 0x40000a5c;
__mulsf3 = 0x40000a60;
__nesf2 = 0x40000a64;
__subsf3 = 0x40000a68;
__truncdfsf2 = 0x40000a6c;
/***************************************
@ -42,21 +42,84 @@ _rvfp__truncdfsf2 = 0x40000a6c;
***************************************/
/* Functions */
_rvfp__adddf3 = 0x40000a70;
_rvfp__eqdf2 = 0x40000a74;
_rvfp__fixdfdi = 0x40000a78;
_rvfp__fixdfsi = 0x40000a7c;
_rvfp__fixsfdi = 0x40000a80;
_rvfp__fixunsdfsi = 0x40000a84;
_rvfp__fixunssfdi = 0x40000a88;
_rvfp__floatdidf = 0x40000a8c;
_rvfp__floatsidf = 0x40000a90;
_rvfp__floatundidf = 0x40000a94;
_rvfp__floatunsidf = 0x40000a98;
_rvfp__gedf2 = 0x40000a9c;
_rvfp__gtdf2 = 0x40000aa0;
_rvfp__ledf2 = 0x40000aa4;
_rvfp__ltdf2 = 0x40000aa8;
_rvfp__muldf3 = 0x40000aac;
_rvfp__nedf2 = 0x40000ab0;
_rvfp__subdf3 = 0x40000ab4;
__adddf3 = 0x40000a70;
__eqdf2 = 0x40000a74;
__fixdfdi = 0x40000a78;
__fixdfsi = 0x40000a7c;
__fixsfdi = 0x40000a80;
__fixunsdfsi = 0x40000a84;
__fixunssfdi = 0x40000a88;
__floatdidf = 0x40000a8c;
__floatsidf = 0x40000a90;
__floatundidf = 0x40000a94;
__floatunsidf = 0x40000a98;
__gedf2 = 0x40000a9c;
__gtdf2 = 0x40000aa0;
__ledf2 = 0x40000aa4;
__ltdf2 = 0x40000aa8;
__muldf3 = 0x40000aac;
__nedf2 = 0x40000ab0;
__subdf3 = 0x40000ab4;
/***************************************
Group libgcc
***************************************/
/* Functions */
__divsf3 = 0x400008c0;
__negsf2 = 0x400008e8;
__powisf2 = 0x400008f0;
__unordsf2 = 0x400008fc;
__absvdi2 = 0x40000900;
__absvsi2 = 0x40000904;
__addvdi3 = 0x4000090c;
__addvsi3 = 0x40000910;
__ashldi3 = 0x40000914;
__ashrdi3 = 0x40000918;
__bswapdi2 = 0x4000091c;
__bswapsi2 = 0x40000920;
__clear_cache = 0x40000924;
__clrsbdi2 = 0x40000928;
__clrsbsi2 = 0x4000092c;
__clzdi2 = 0x40000930;
__clzsi2 = 0x40000934;
__cmpdi2 = 0x40000938;
__ctzdi2 = 0x4000093c;
__ctzsi2 = 0x40000940;
__divdc3 = 0x40000944;
__divdf3 = 0x40000948;
__divdi3 = 0x4000094c;
__divsc3 = 0x40000950;
__divsi3 = 0x40000954;
__ffsdi2 = 0x40000960;
__ffssi2 = 0x40000964;
__gcc_bcmp = 0x40000998;
__lshrdi3 = 0x400009a8;
__moddi3 = 0x400009b0;
__modsi3 = 0x400009b4;
__muldc3 = 0x400009b8;
__muldi3 = 0x400009c0;
__mulsc3 = 0x400009c4;
__mulsi3 = 0x400009c8;
__mulvdi3 = 0x400009cc;
__mulvsi3 = 0x400009d0;
__negdf2 = 0x400009d8;
__negdi2 = 0x400009dc;
__negvdi2 = 0x400009e0;
__negvsi2 = 0x400009e4;
__paritysi2 = 0x400009e8;
__popcountdi2 = 0x400009ec;
__popcountsi2 = 0x400009f0;
__powidf2 = 0x400009f4;
__subvdi3 = 0x400009fc;
__subvsi3 = 0x40000a00;
__ucmpdi2 = 0x40000a04;
__udivdi3 = 0x40000a08;
__udivmoddi4 = 0x40000a0c;
__udivsi3 = 0x40000a10;
__udiv_w_sdiv = 0x40000a14;
__umoddi3 = 0x40000a18;
__umodsi3 = 0x40000a1c;
__unorddf2 = 0x40000a20;
__extenddftf2 = 0x40000a24;
__trunctfdf2 = 0x40000a28;

2
components/espcoredump/src/core_dump_uart.c
View File

@ -154,7 +154,7 @@ static esp_err_t esp_core_dump_uart_hw_init(void)
//Make sure txd/rxd are enabled
// use direct reg access instead of gpio_pullup_dis which can cause exception when flash cache is disabled
REG_CLR_BIT(GPIO_PIN_REG_1, FUN_PU);
REG_CLR_BIT(GPIO_PIN_REG_1, FUN_PU); //TODO: IDF-9948
gpio_hal_func_sel(&gpio_hal, U0RXD_GPIO_NUM, U0RXD_MUX_FUNC);
gpio_hal_func_sel(&gpio_hal, U0TXD_GPIO_NUM, U0TXD_MUX_FUNC);
ESP_COREDUMP_LOGI("Press Enter to print core dump to UART...");

60
components/hal/esp32c61/include/hal/gpio_ll.h
View File

@ -57,15 +57,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
{
*pu = IOMUX.gpion[gpio_num].gpion_fun_wpu;
*pd = IOMUX.gpion[gpio_num].gpion_fun_wpd;
*ie = IOMUX.gpion[gpio_num].gpion_fun_ie;
*pu = IO_MUX.gpion[gpio_num].gpion_fun_wpu;
*pd = IO_MUX.gpion[gpio_num].gpion_fun_wpd;
*ie = IO_MUX.gpion[gpio_num].gpion_fun_ie;
*oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num;
*od = hw->pinn[gpio_num].pinn_pad_driver;
*drv = IOMUX.gpion[gpio_num].gpion_fun_drv;
*fun_sel = IOMUX.gpion[gpio_num].gpion_mcu_sel;
*drv = IO_MUX.gpion[gpio_num].gpion_fun_drv;
*fun_sel = IO_MUX.gpion[gpio_num].gpion_mcu_sel;
*sig_out = hw->funcn_out_sel_cfg[gpio_num].funcn_out_sel;
*slp_sel = IOMUX.gpion[gpio_num].gpion_slp_sel;
*slp_sel = IO_MUX.gpion[gpio_num].gpion_slp_sel;
}
/**
@ -76,7 +76,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_fun_wpu = 1;
IO_MUX.gpion[gpio_num].gpion_fun_wpu = 1;
}
/**
@ -88,7 +88,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_fun_wpu = 0;
IO_MUX.gpion[gpio_num].gpion_fun_wpu = 0;
}
/**
@ -99,7 +99,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_fun_wpd = 1;
IO_MUX.gpion[gpio_num].gpion_fun_wpd = 1;
}
/**
@ -120,7 +120,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IOMUX.gpion[gpio_num].gpion_fun_wpd = 0;
IO_MUX.gpion[gpio_num].gpion_fun_wpd = 0;
}
/**
@ -221,7 +221,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_fun_ie = 0;
IO_MUX.gpion[gpio_num].gpion_fun_ie = 0;
}
/**
@ -232,7 +232,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_fun_ie = 1;
IO_MUX.gpion[gpio_num].gpion_fun_ie = 1;
}
/**
@ -243,7 +243,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_filter_en = 1;
IO_MUX.gpion[gpio_num].gpion_filter_en = 1;
}
/**
@ -254,7 +254,7 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_filter_en = 0;
IO_MUX.gpion[gpio_num].gpion_filter_en = 0;
}
/**
@ -371,7 +371,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
IOMUX.gpion[gpio_num].gpion_fun_drv = strength;
IO_MUX.gpion[gpio_num].gpion_fun_drv = strength;
}
/**
@ -383,7 +383,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
{
*strength = (gpio_drive_cap_t)(IOMUX.gpion[gpio_num].gpion_fun_drv);
*strength = (gpio_drive_cap_t)(IO_MUX.gpion[gpio_num].gpion_fun_drv);
}
/**
@ -429,7 +429,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
}
/**
* @brief Set pad input to a peripheral signal through the IOMUX.
* @brief Set pad input to a peripheral signal through the IO_MUX.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number of the pad.
@ -439,7 +439,7 @@ __attribute__((always_inline))
static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
{
hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
IOMUX.gpion[gpio].gpion_fun_ie = 1;
IO_MUX.gpion[gpio].gpion_fun_ie = 1;
}
/**
@ -483,11 +483,11 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
IOMUX.gpion[gpio_num].gpion_mcu_sel = func;
IO_MUX.gpion[gpio_num].gpion_mcu_sel = func;
}
/**
* @brief Set peripheral output to an GPIO pad through the IOMUX.
* @brief Set peripheral output to an GPIO pad through the IO_MUX.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num gpio_num GPIO number of the pad.
@ -570,7 +570,7 @@ static inline void gpio_ll_force_unhold_all(void)
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_slp_sel = 1;
IO_MUX.gpion[gpio_num].gpion_slp_sel = 1;
}
/**
@ -582,7 +582,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_slp_sel = 0;
IO_MUX.gpion[gpio_num].gpion_slp_sel = 0;
}
/**
@ -593,7 +593,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_mcu_wpu = 0;
IO_MUX.gpion[gpio_num].gpion_mcu_wpu = 0;
}
/**
@ -604,7 +604,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_mcu_wpu = 1;
IO_MUX.gpion[gpio_num].gpion_mcu_wpu = 1;
}
/**
@ -615,7 +615,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_mcu_wpd = 1;
IO_MUX.gpion[gpio_num].gpion_mcu_wpd = 1;
}
/**
@ -626,7 +626,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_mcu_wpd = 0;
IO_MUX.gpion[gpio_num].gpion_mcu_wpd = 0;
}
/**
@ -637,7 +637,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_mcu_ie = 0;
IO_MUX.gpion[gpio_num].gpion_mcu_ie = 0;
}
/**
@ -648,7 +648,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
*/
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_mcu_ie = 1;
IO_MUX.gpion[gpio_num].gpion_mcu_ie = 1;
}
/**
@ -659,7 +659,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_mcu_oe = 0;
IO_MUX.gpion[gpio_num].gpion_mcu_oe = 0;
}
/**
@ -670,7 +670,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpion[gpio_num].gpion_mcu_oe = 1;
IO_MUX.gpion[gpio_num].gpion_mcu_oe = 1;
}
#ifdef __cplusplus

4
components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
View File

@ -143,6 +143,10 @@ config SOC_BT_SUPPORTED
bool
default y
config SOC_PM_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_40M
bool
default y

2
components/soc/esp32c5/beta3/include/soc/soc_caps.h
View File

@ -81,7 +81,7 @@
#define SOC_MODEM_CLOCK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8845 need check, it is opened because pll has been used on beta3
#define SOC_BT_SUPPORTED 1
#define SOC_PHY_SUPPORTED 1
// #define SOC_PM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8643
#define SOC_PM_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_40M 1

2
components/soc/esp32c61/include/soc/io_mux_struct.h
View File

@ -134,7 +134,7 @@ typedef struct {
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IOMUX;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");

2
components/soc/esp32c61/ld/esp32c61.peripherals.ld
View File

@ -26,7 +26,7 @@ PROVIDE ( GPSPI2 = 0x60081000 );
PROVIDE ( SHA = 0x60089000 );
PROVIDE ( ECC = 0x6008B000 );
PROVIDE ( ECDSA = 0x6008E000 );
PROVIDE ( IOMUX = 0x60090000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( TCM_MEM_MONITOR = 0x60092000 );
PROVIDE ( PAU = 0x60093000 );

2
docs/en/api-reference/peripherals/gpio/esp32c5.inc
View File

@ -9,7 +9,7 @@
.. gpio-summary
The {IDF_TARGET_NAME} chip features 27 physical GPIO pins (GPIO0 ~ GPIO26). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The {IDF_TARGET_NAME} chip features 29 physical GPIO pins (GPIO0 ~ GPIO28). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.