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https://github.com/espressif/esp-idf.git
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Merge branch 'feature/add_new_pkg_and_flash_psram_efuses_v5.0' into 'release/v5.0'
feat(efuse): Add flash&psram efuses for S3 (v5.0) See merge request espressif/esp-idf!29144
This commit is contained in:
Michael (XIAO Xufeng)
commit
0ce1c1b494
@ -4,11 +4,9 @@
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#
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#
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# Converts efuse table to header file efuse_table.h.
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# Converts efuse table to header file efuse_table.h.
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#
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#
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# SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
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# SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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#
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#
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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from __future__ import division, print_function
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import argparse
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import argparse
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import hashlib
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import hashlib
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import os
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import os
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@ -261,7 +259,11 @@ class FuseTable(list):
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last_field_name = ''
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last_field_name = ''
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for p in self:
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for p in self:
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if (p.field_name != last_field_name):
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if (p.field_name != last_field_name):
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rows += ['extern const esp_efuse_desc_t* ' + 'ESP_EFUSE_' + p.field_name.replace('.', '_') + '[];']
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name = 'ESP_EFUSE_' + p.field_name.replace('.', '_')
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rows += ['extern const esp_efuse_desc_t* ' + name + '[];']
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for alt_name in p.get_alt_names():
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alt_name = 'ESP_EFUSE_' + alt_name.replace('.', '_')
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rows += ['#define ' + alt_name + ' ' + name]
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last_field_name = p.field_name
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last_field_name = p.field_name
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rows += ['',
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rows += ['',
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@ -434,6 +436,12 @@ class FuseDefinition(object):
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str(self.bit_start),
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str(self.bit_start),
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str(self.get_bit_count()) + '}, \t // ' + self.comment])
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str(self.get_bit_count()) + '}, \t // ' + self.comment])
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def get_alt_names(self):
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result = re.search(r'^\[(.*?)\]', self.comment)
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if result:
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return result.group(1).split()
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return []
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def process_input_file(file, type_table):
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def process_input_file(file, type_table):
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status('Parsing efuse CSV input file ' + file.name + ' ...')
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status('Parsing efuse CSV input file ' + file.name + ' ...')
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File diff suppressed because it is too large
Load Diff
@ -9,185 +9,236 @@
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# this will generate new source files, next rebuild all the sources.
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# !!!!!!!!!!! #
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# EFUSE_RD_REPEAT_DATA BLOCK #
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# This file was generated by regtools.py based on the efuses.yaml file with the version: f75f74727101326a187188a23f4a6c70
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##############################
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# EFUSE_RD_WR_DIS_REG #
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WR_DIS, EFUSE_BLK0, 0, 32, Write protection
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
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WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
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WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
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WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
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WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
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WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
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WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
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WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
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WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
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WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
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WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
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WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
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WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
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WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
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WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
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WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
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WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
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WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
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WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
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WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
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WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
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WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
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WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
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WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
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WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
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WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
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WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS
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# EFUSE_RD_REPEAT_DATA0_REG #
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WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
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RD_DIS, EFUSE_BLK0, 32, 7, Read protection
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
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RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
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WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
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RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
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WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE
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RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
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WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
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RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
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WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE
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RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
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WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
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RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
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WR_DIS.DIS_USB_OTG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG
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RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
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WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
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DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
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WR_DIS.DIS_APP_CPU, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_APP_CPU
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DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace
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WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG
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DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7
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WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
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DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
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WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
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DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
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WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG
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DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function
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WR_DIS.STRAP_JTAG_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of STRAP_JTAG_SEL
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DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function
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WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of USB_PHY_SEL
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DIS_APP_CPU, EFUSE_BLK0, 47, 1, Disables APP CPU
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WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD
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SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral
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WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH
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HARD_DIS_JTAG, EFUSE_BLK0, 51, 1, Hardware disable jtag permanently disable jtag function
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WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE
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DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode
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WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
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USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
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WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
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USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, Enable external PHY
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WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
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BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enables BTLC GPIO
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WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
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WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
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# EFUSE_RD_REPEAT_DATA1_REG #
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WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
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VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up
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WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
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VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda
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WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
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VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI
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WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
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WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
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WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
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SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
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WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
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SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
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WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
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SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
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WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
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SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
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WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
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KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
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WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
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KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
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WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT
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WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
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# EFUSE_RD_REPEAT_DATA2_REG #
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WR_DIS.FLASH_ECC_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_MODE
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KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
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WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
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KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
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WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
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KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
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WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
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KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
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WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION
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SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
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WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE
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SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
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WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE
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DIS_USB_JTAG, EFUSE_BLK0, 118, 1, Set to disable usb_serial_jtag-to-jtag function
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WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN
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DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, Set to disable usb_serial_jtag module
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WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
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STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, Enable selection between usb_to_jtag or pad_to_jtag through gpio10
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WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
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USB_PHY_SEL, EFUSE_BLK0, 121, 1, Select internal/external PHY for USB OTG and usb_serial_jtag
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WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 19, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
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FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
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WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
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WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
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# EFUSE_RD_REPEAT_DATA3_REG #
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WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
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DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
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WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
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DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode
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WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK
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DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot
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WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q
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FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode
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WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D
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DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Set this bit to disable download through USB-Serial-JTAG
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WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS
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ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
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WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD
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UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
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WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP
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PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
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WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS
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FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line
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WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4
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FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Sets the size of flash page
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WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5
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FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enables ECC in Flash boot mode
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WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6
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FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
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WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7
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SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
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WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO
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DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, Set this bit to disable download through USB-OTG
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WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
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WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
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# EFUSE_RD_REPEAT_DATA4_REG #
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WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
|
||||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
|
WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP
|
||||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
|
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
|
||||||
|
WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
|
||||||
|
WR_DIS.PSRAM_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_TEMP
|
||||||
# MAC_SPI_8M_SYS BLOCK#
|
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
|
||||||
#######################
|
WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO
|
||||||
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
|
WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO
|
||||||
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
|
WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20
|
||||||
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
|
WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20
|
||||||
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
|
WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT
|
||||||
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
|
WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI
|
||||||
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
|
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
|
||||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
|
WR_DIS.ADC2_CAL_VOL_ATTEN3, EFUSE_BLK0, 20, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN3
|
||||||
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
|
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||||
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
|
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
|
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||||
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
|
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB
|
||||||
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
|
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
|
WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
|
||||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
|
WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
|
||||||
|
WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
|
||||||
# RD_MAC_SPI_SYS_3
|
WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
|
||||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
|
WR_DIS.ADC2_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN0
|
||||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
|
WR_DIS.ADC2_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN1
|
||||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
|
WR_DIS.ADC2_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN2
|
||||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
|
WR_DIS.ADC2_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN3
|
||||||
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
|
WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
|
||||||
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
|
WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
|
||||||
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version
|
WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
|
||||||
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
|
WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
|
||||||
|
WR_DIS.ADC2_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN0
|
||||||
# RD_MAC_SPI_SYS_5
|
WR_DIS.ADC2_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN1
|
||||||
# WAFER_VERSION_MINOR most significant bit
|
WR_DIS.ADC2_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN2
|
||||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
|
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||||
ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, ADC2 calibration voltage at atten3
|
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||||
|
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||||
|
WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
|
||||||
# SYS_DATA_PART1 BLOCK# - System configuration
|
WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
|
||||||
#######################
|
WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
|
||||||
# RD_SYS_PART1_DATA0
|
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
|
||||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
|
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
|
||||||
|
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
|
||||||
# RD_SYS_PART1_DATA4
|
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
|
||||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
|
WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE
|
||||||
TEMP_CALIB, EFUSE_BLK2, 132, 9, Temperature calibration data
|
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
|
||||||
OCODE, EFUSE_BLK2, 141, 8, ADC OCode
|
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
|
||||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, ADC1 init code at atten0
|
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
|
||||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, ADC1 init code at atten1
|
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
|
||||||
|
RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
|
||||||
# RD_SYS_PART1_DATA5
|
RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
|
||||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, ADC1 init code at atten2
|
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
|
||||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, ADC1 init code at atten3
|
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
|
||||||
ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, ADC2 init code at atten0
|
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
|
||||||
ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, ADC2 init code at atten1
|
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache
|
||||||
ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, ADC2 init code at atten2
|
DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache
|
||||||
ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, ADC2 init code at atten3
|
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
|
||||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, ADC1 calibration voltage at atten0
|
DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
|
||||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, ADC1 calibration voltage at atten1
|
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode
|
||||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, ADC1 calibration voltage at atten2
|
DIS_USB_OTG, EFUSE_BLK0, 45, 1, [DIS_USB] Set this bit to disable USB function
|
||||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, ADC1 calibration voltage at atten3
|
DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function
|
||||||
ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, ADC2 calibration voltage at atten0
|
DIS_APP_CPU, EFUSE_BLK0, 47, 1, [] Disable app cpu
|
||||||
ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, ADC2 calibration voltage at atten1
|
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module
|
||||||
ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, ADC2 calibration voltage at atten2
|
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
|
||||||
|
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes
|
||||||
################
|
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins
|
||||||
USER_DATA, EFUSE_BLK3, 0, 256, User data
|
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, [EXT_PHY_ENABLE] Set this bit to enable external PHY
|
||||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
|
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] SPI regulator power up signal
|
||||||
|
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}
|
||||||
################
|
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI
|
||||||
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
|
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
|
||||||
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
|
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||||
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
|
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
|
||||||
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
|
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
|
||||||
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
|
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
|
||||||
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
|
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0
|
||||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
|
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1
|
||||||
|
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2
|
||||||
# AUTO CONFIG DIG&RTC DBIAS#
|
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3
|
||||||
################
|
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4
|
||||||
K_RTC_LDO, EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO
|
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5
|
||||||
K_DIG_LDO, EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO
|
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot
|
||||||
V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20
|
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot
|
||||||
V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20
|
DIS_USB_JTAG, EFUSE_BLK0, 118, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device
|
||||||
DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt
|
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, [DIS_USB_DEVICE] Set this bit to disable usb device
|
||||||
|
STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0
|
||||||
|
USB_PHY_SEL, EFUSE_BLK0, 121, 1, [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"}
|
||||||
|
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value
|
||||||
|
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)
|
||||||
|
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode
|
||||||
|
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}
|
||||||
|
FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"}
|
||||||
|
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB
|
||||||
|
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode
|
||||||
|
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}
|
||||||
|
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}
|
||||||
|
FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}
|
||||||
|
FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, [] Set Flash page size
|
||||||
|
FLASH_ECC_EN, EFUSE_BLK0, 140, 1, [] Set 1 to enable ECC for flash boot
|
||||||
|
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot
|
||||||
|
SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature)
|
||||||
|
DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, [] Set this bit to disable download through USB-OTG
|
||||||
|
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major
|
||||||
|
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major
|
||||||
|
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
|
||||||
|
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
|
||||||
|
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
|
||||||
|
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||||
|
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||||
|
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||||
|
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK
|
||||||
|
SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1)
|
||||||
|
SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0)
|
||||||
|
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS
|
||||||
|
SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3)
|
||||||
|
SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2)
|
||||||
|
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS
|
||||||
|
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4
|
||||||
|
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5
|
||||||
|
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6
|
||||||
|
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7
|
||||||
|
WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits
|
||||||
|
PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version
|
||||||
|
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR
|
||||||
|
FLASH_CAP, EFUSE_BLK1, 123, 3, [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"}
|
||||||
|
FLASH_TEMP, EFUSE_BLK1, 126, 2, [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"}
|
||||||
|
FLASH_VENDOR, EFUSE_BLK1, 128, 3, [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"}
|
||||||
|
PSRAM_CAP, EFUSE_BLK1, 131, 2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}
|
||||||
|
PSRAM_TEMP, EFUSE_BLK1, 133, 2, [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"}
|
||||||
|
PSRAM_VENDOR, EFUSE_BLK1, 135, 2, [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"}
|
||||||
|
K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO
|
||||||
|
K_DIG_LDO, EFUSE_BLK1, 148, 7, [] BLOCK1 K_DIG_LDO
|
||||||
|
V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, [] BLOCK1 voltage of rtc dbias20
|
||||||
|
V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, [] BLOCK1 voltage of digital dbias20
|
||||||
|
DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, [] BLOCK1 digital dbias when hvt
|
||||||
|
WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit
|
||||||
|
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR
|
||||||
|
ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, [] ADC2 calibration voltage at atten3
|
||||||
|
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||||
|
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"}
|
||||||
|
TEMP_CALIB, EFUSE_BLK2, 132, 9, [] Temperature calibration data
|
||||||
|
OCODE, EFUSE_BLK2, 141, 8, [] ADC OCode
|
||||||
|
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, [] ADC1 init code at atten0
|
||||||
|
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, [] ADC1 init code at atten1
|
||||||
|
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, [] ADC1 init code at atten2
|
||||||
|
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, [] ADC1 init code at atten3
|
||||||
|
ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, [] ADC2 init code at atten0
|
||||||
|
ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, [] ADC2 init code at atten1
|
||||||
|
ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, [] ADC2 init code at atten2
|
||||||
|
ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, [] ADC2 init code at atten3
|
||||||
|
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, [] ADC1 calibration voltage at atten0
|
||||||
|
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, [] ADC1 calibration voltage at atten1
|
||||||
|
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, [] ADC1 calibration voltage at atten2
|
||||||
|
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, [] ADC1 calibration voltage at atten3
|
||||||
|
ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, [] ADC2 calibration voltage at atten0
|
||||||
|
ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, [] ADC2 calibration voltage at atten1
|
||||||
|
ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, [] ADC2 calibration voltage at atten2
|
||||||
|
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||||
|
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||||
|
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||||
|
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
|
||||||
|
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
|
||||||
|
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||||
|
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||||
|
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
|
||||||
|
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
|
||||||
|
|||||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -10,7 +10,7 @@ extern "C" {
|
|||||||
|
|
||||||
#include "esp_efuse.h"
|
#include "esp_efuse.h"
|
||||||
|
|
||||||
// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2
|
// md5_digest_table e0674ff40a1e124670c6eecf33410e76
|
||||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||||
@ -19,54 +19,172 @@ extern "C" {
|
|||||||
|
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_DIS_USB ESP_EFUSE_WR_DIS_DIS_USB_OTG
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_APP_CPU[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_HARD_DIS_JTAG ESP_EFUSE_WR_DIS_DIS_PAD_JTAG
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_STRAP_JTAG_SEL[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
|
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
|
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
|
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_MODE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN3[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN0[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN1[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN2[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN3[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN0[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN1[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN2[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||||
|
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[];
|
||||||
|
#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
|
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
|
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
|
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||||
|
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||||
|
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||||
|
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||||
|
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
|
#define ESP_EFUSE_DIS_USB ESP_EFUSE_DIS_USB_OTG
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||||
|
#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||||
|
#define ESP_EFUSE_HARD_DIS_JTAG ESP_EFUSE_DIS_PAD_JTAG
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[];
|
#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[];
|
||||||
@ -76,23 +194,33 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
|||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||||
|
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||||
|
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||||
|
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||||
|
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||||
|
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||||
|
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
|
||||||
|
#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||||
|
#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||||
|
#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||||
|
#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
|
||||||
@ -104,21 +232,34 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
|||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||||
|
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
||||||
|
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||||
@ -141,19 +282,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[];
|
|||||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||||
|
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||||
|
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||||
|
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||||
|
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||||
|
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||||
|
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||||
|
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||||
|
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||||
|
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
|
||||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -22,32 +22,32 @@ extern "C" {
|
|||||||
|
|
||||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
|
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
|
||||||
{
|
{
|
||||||
return EFUSE.rd_repeat_data1.reg_spi_boot_crypt_cnt;
|
return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
|
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
|
||||||
{
|
{
|
||||||
return EFUSE.rd_repeat_data1.reg_wdt_delay_sel;
|
return EFUSE.rd_repeat_data1.wdt_delay_sel;
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void)
|
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void)
|
||||||
{
|
{
|
||||||
return EFUSE.rd_repeat_data3.reg_flash_type;
|
return EFUSE.rd_repeat_data3.flash_type;
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
|
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
|
||||||
{
|
{
|
||||||
return EFUSE.rd_mac_spi_sys_0;
|
return EFUSE.rd_mac_spi_sys_0.mac_0;
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
|
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
|
||||||
{
|
{
|
||||||
return EFUSE.rd_mac_spi_sys_1.reg_mac_1;
|
return EFUSE.rd_mac_spi_sys_1.mac_1;
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
|
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
|
||||||
{
|
{
|
||||||
return EFUSE.rd_repeat_data2.reg_secure_boot_en;
|
return EFUSE.rd_repeat_data2.secure_boot_en;
|
||||||
}
|
}
|
||||||
|
|
||||||
// use efuse_hal_get_major_chip_version() to get major chip version
|
// use efuse_hal_get_major_chip_version() to get major chip version
|
||||||
@ -59,7 +59,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_ve
|
|||||||
// use efuse_hal_get_minor_chip_version() to get minor chip version
|
// use efuse_hal_get_minor_chip_version() to get minor chip version
|
||||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
|
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
|
||||||
{
|
{
|
||||||
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
|
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_lo;
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
|
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
|
||||||
@ -84,7 +84,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_versi
|
|||||||
|
|
||||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
|
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
|
||||||
{
|
{
|
||||||
return 0;
|
return EFUSE.rd_mac_spi_sys_3.pkg_version;
|
||||||
}
|
}
|
||||||
|
|
||||||
/******************* eFuse control functions *************************/
|
/******************* eFuse control functions *************************/
|
||||||
|
|||||||
31
components/soc/esp32s3/include/soc/efuse_defs.h
Normal file
31
components/soc/esp32s3/include/soc/efuse_defs.h
Normal file
@ -0,0 +1,31 @@
|
|||||||
|
/**
|
||||||
|
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||||
|
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||||
|
|
||||||
|
#define EFUSE_PKG_VERSION_ESP32S3 0 // QFN56
|
||||||
|
#define EFUSE_PKG_VERSION_ESP32S3PICO 1 // LGA56
|
||||||
|
|
||||||
|
/** EFUSE_RD_MAC_SPI_SYS_3_REG register
|
||||||
|
* BLOCK1 data register 3.
|
||||||
|
*/
|
||||||
|
//#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
|
||||||
|
/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
|
||||||
|
/*description: Stores the second part of SPI_PAD_CONF..*/
|
||||||
|
#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF
|
||||||
|
#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S))
|
||||||
|
#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF
|
||||||
|
#define EFUSE_SPI_PAD_CONF_2_S 0
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
@ -8,6 +8,8 @@
|
|||||||
|
|
||||||
|
|
||||||
#include "soc.h"
|
#include "soc.h"
|
||||||
|
#include "efuse_defs.h"
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
@ -560,27 +562,127 @@ apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/
|
|||||||
#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF
|
#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF
|
||||||
#define EFUSE_SPI_PAD_CONF_1_S 0
|
#define EFUSE_SPI_PAD_CONF_1_S 0
|
||||||
|
|
||||||
#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
|
/** EFUSE_RD_MAC_SPI_SYS_3_REG register
|
||||||
/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */
|
* BLOCK1 data register 3.
|
||||||
/*description: Stores the fist 14 bits of the zeroth part of system data..*/
|
*/
|
||||||
#define EFUSE_SYS_DATA_PART0_0 0x00003FFF
|
#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
|
||||||
#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
|
/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0;
|
||||||
#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF
|
* SPI_PAD_configure D5
|
||||||
#define EFUSE_SYS_DATA_PART0_0_S 18
|
*/
|
||||||
/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
|
#define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU
|
||||||
/*description: Stores the second part of SPI_PAD_CONF..*/
|
#define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S)
|
||||||
#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF
|
#define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU
|
||||||
#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S))
|
#define EFUSE_SPI_PAD_CONFIG_D5_S 0
|
||||||
#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF
|
/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0;
|
||||||
#define EFUSE_SPI_PAD_CONF_2_S 0
|
* SPI_PAD_configure D6
|
||||||
|
*/
|
||||||
|
#define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU
|
||||||
|
#define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S)
|
||||||
|
#define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU
|
||||||
|
#define EFUSE_SPI_PAD_CONFIG_D6_S 6
|
||||||
|
/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0;
|
||||||
|
* SPI_PAD_configure D7
|
||||||
|
*/
|
||||||
|
#define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU
|
||||||
|
#define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S)
|
||||||
|
#define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU
|
||||||
|
#define EFUSE_SPI_PAD_CONFIG_D7_S 12
|
||||||
|
/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0;
|
||||||
|
* WAFER_VERSION_MINOR least significant bits
|
||||||
|
*/
|
||||||
|
#define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U
|
||||||
|
#define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S)
|
||||||
|
#define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U
|
||||||
|
#define EFUSE_WAFER_VERSION_MINOR_LO_S 18
|
||||||
|
/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0;
|
||||||
|
* Package version
|
||||||
|
*/
|
||||||
|
#define EFUSE_PKG_VERSION 0x00000007U
|
||||||
|
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
|
||||||
|
#define EFUSE_PKG_VERSION_V 0x00000007U
|
||||||
|
#define EFUSE_PKG_VERSION_S 21
|
||||||
|
/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0;
|
||||||
|
* BLK_VERSION_MINOR
|
||||||
|
*/
|
||||||
|
#define EFUSE_BLK_VERSION_MINOR 0x00000007U
|
||||||
|
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
|
||||||
|
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
|
||||||
|
#define EFUSE_BLK_VERSION_MINOR_S 24
|
||||||
|
/** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0;
|
||||||
|
* Flash capacity
|
||||||
|
*/
|
||||||
|
#define EFUSE_FLASH_CAP 0x00000007U
|
||||||
|
#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
|
||||||
|
#define EFUSE_FLASH_CAP_V 0x00000007U
|
||||||
|
#define EFUSE_FLASH_CAP_S 27
|
||||||
|
/** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0;
|
||||||
|
* Flash temperature
|
||||||
|
*/
|
||||||
|
#define EFUSE_FLASH_TEMP 0x00000003U
|
||||||
|
#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
|
||||||
|
#define EFUSE_FLASH_TEMP_V 0x00000003U
|
||||||
|
#define EFUSE_FLASH_TEMP_S 30
|
||||||
|
|
||||||
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
|
/** EFUSE_RD_MAC_SPI_SYS_4_REG register
|
||||||
/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
* BLOCK1 data register 4.
|
||||||
/*description: Stores the fist 32 bits of the zeroth part of system data..*/
|
*/
|
||||||
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF
|
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
|
||||||
#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
|
/** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0;
|
||||||
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF
|
* Flash vendor
|
||||||
#define EFUSE_SYS_DATA_PART0_1_S 0
|
*/
|
||||||
|
#define EFUSE_FLASH_VENDOR 0x00000007U
|
||||||
|
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
|
||||||
|
#define EFUSE_FLASH_VENDOR_V 0x00000007U
|
||||||
|
#define EFUSE_FLASH_VENDOR_S 0
|
||||||
|
/** EFUSE_PSRAM_CAP : R; bitpos: [4:3]; default: 0;
|
||||||
|
* PSRAM capacity
|
||||||
|
*/
|
||||||
|
#define EFUSE_PSRAM_CAP 0x00000003U
|
||||||
|
#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
|
||||||
|
#define EFUSE_PSRAM_CAP_V 0x00000003U
|
||||||
|
#define EFUSE_PSRAM_CAP_S 3
|
||||||
|
/** EFUSE_PSRAM_TEMP : R; bitpos: [6:5]; default: 0;
|
||||||
|
* PSRAM temperature
|
||||||
|
*/
|
||||||
|
#define EFUSE_PSRAM_TEMP 0x00000003U
|
||||||
|
#define EFUSE_PSRAM_TEMP_M (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S)
|
||||||
|
#define EFUSE_PSRAM_TEMP_V 0x00000003U
|
||||||
|
#define EFUSE_PSRAM_TEMP_S 5
|
||||||
|
/** EFUSE_PSRAM_VENDOR : R; bitpos: [8:7]; default: 0;
|
||||||
|
* PSRAM vendor
|
||||||
|
*/
|
||||||
|
#define EFUSE_PSRAM_VENDOR 0x00000003U
|
||||||
|
#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
|
||||||
|
#define EFUSE_PSRAM_VENDOR_V 0x00000003U
|
||||||
|
#define EFUSE_PSRAM_VENDOR_S 7
|
||||||
|
/** EFUSE_RESERVED_1_137 : R; bitpos: [12:9]; default: 0;
|
||||||
|
* reserved
|
||||||
|
*/
|
||||||
|
#define EFUSE_RESERVED_1_137 0x0000000FU
|
||||||
|
#define EFUSE_RESERVED_1_137_M (EFUSE_RESERVED_1_137_V << EFUSE_RESERVED_1_137_S)
|
||||||
|
#define EFUSE_RESERVED_1_137_V 0x0000000FU
|
||||||
|
#define EFUSE_RESERVED_1_137_S 9
|
||||||
|
/** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0;
|
||||||
|
* BLOCK1 K_RTC_LDO
|
||||||
|
*/
|
||||||
|
#define EFUSE_K_RTC_LDO 0x0000007FU
|
||||||
|
#define EFUSE_K_RTC_LDO_M (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S)
|
||||||
|
#define EFUSE_K_RTC_LDO_V 0x0000007FU
|
||||||
|
#define EFUSE_K_RTC_LDO_S 13
|
||||||
|
/** EFUSE_K_DIG_LDO : R; bitpos: [26:20]; default: 0;
|
||||||
|
* BLOCK1 K_DIG_LDO
|
||||||
|
*/
|
||||||
|
#define EFUSE_K_DIG_LDO 0x0000007FU
|
||||||
|
#define EFUSE_K_DIG_LDO_M (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S)
|
||||||
|
#define EFUSE_K_DIG_LDO_V 0x0000007FU
|
||||||
|
#define EFUSE_K_DIG_LDO_S 20
|
||||||
|
/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [31:27]; default: 0;
|
||||||
|
* BLOCK1 voltage of rtc dbias20
|
||||||
|
*/
|
||||||
|
#define EFUSE_V_RTC_DBIAS20 0x0000001FU
|
||||||
|
#define EFUSE_V_RTC_DBIAS20_M (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S)
|
||||||
|
#define EFUSE_V_RTC_DBIAS20_V 0x0000001FU
|
||||||
|
#define EFUSE_V_RTC_DBIAS20_S 27
|
||||||
|
|
||||||
#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
|
#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
|
||||||
/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user