diff --git a/components/efuse/efuse_table_gen.py b/components/efuse/efuse_table_gen.py index 0d6ea61394..15ff01b50e 100755 --- a/components/efuse/efuse_table_gen.py +++ b/components/efuse/efuse_table_gen.py @@ -4,11 +4,9 @@ # # Converts efuse table to header file efuse_table.h. # -# SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: Apache-2.0 -from __future__ import division, print_function - import argparse import hashlib import os @@ -261,7 +259,11 @@ class FuseTable(list): last_field_name = '' for p in self: if (p.field_name != last_field_name): - rows += ['extern const esp_efuse_desc_t* ' + 'ESP_EFUSE_' + p.field_name.replace('.', '_') + '[];'] + name = 'ESP_EFUSE_' + p.field_name.replace('.', '_') + rows += ['extern const esp_efuse_desc_t* ' + name + '[];'] + for alt_name in p.get_alt_names(): + alt_name = 'ESP_EFUSE_' + alt_name.replace('.', '_') + rows += ['#define ' + alt_name + ' ' + name] last_field_name = p.field_name rows += ['', @@ -434,6 +436,12 @@ class FuseDefinition(object): str(self.bit_start), str(self.get_bit_count()) + '}, \t // ' + self.comment]) + def get_alt_names(self): + result = re.search(r'^\[(.*?)\]', self.comment) + if result: + return result.group(1).split() + return [] + def process_input_file(file, type_table): status('Parsing efuse CSV input file ' + file.name + ' ...') diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c index b2a99a0b83..bcf4b18a73 100644 --- a/components/efuse/esp32s3/esp_efuse_table.c +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,564 +9,919 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2 +// md5_digest_table e0674ff40a1e124670c6eecf33410e76 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // To show efuse_table run the command 'show_efuse_table'. static const esp_efuse_desc_t WR_DIS[] = { - {EFUSE_BLK0, 0, 32}, // Write protection, + {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses, }; static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { - {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, + {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; -static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { - {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, +static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { - {EFUSE_BLK0, 3, 1}, // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL, +static const esp_efuse_desc_t WR_DIS_DIS_DCACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DCACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_DCACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_DCACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_APP_CPU[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_APP_CPU, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_STRAP_JTAG_SEL[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of STRAP_JTAG_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_USB_PHY_SEL[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of USB_PHY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_XPD[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_XPD, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_TIEH[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_TIEH, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_FORCE[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_FORCE, +}; + +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, }; static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, + {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, + {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, + {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2, }; -static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { - {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0, }; -static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { - {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1, }; -static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { - {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2, }; -static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { - {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3, }; -static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { - {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4, }; -static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { - {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, + {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, + {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, }; -static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { - {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_ECC_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL, +}; + +static const esp_efuse_desc_t WR_DIS_PIN_POWER_SELECTION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of PIN_POWER_SELECTION, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TYPE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TYPE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_PAGE_SIZE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_PAGE_SIZE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_ECC_EN[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_EN, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, }; static const esp_efuse_desc_t WR_DIS_BLK1[] = { - {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_CS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_HD, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_WP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_WP, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_DQS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_DQS, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D4[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D4, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D5[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D5, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D6[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D6, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_PAD_CONFIG_D7[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D7, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR_LO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_LO, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_K_RTC_LDO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_RTC_LDO, +}; + +static const esp_efuse_desc_t WR_DIS_K_DIG_LDO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_DIG_LDO, +}; + +static const esp_efuse_desc_t WR_DIS_V_RTC_DBIAS20[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of V_RTC_DBIAS20, +}; + +static const esp_efuse_desc_t WR_DIS_V_DIG_DBIAS20[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of V_DIG_DBIAS20, +}; + +static const esp_efuse_desc_t WR_DIS_DIG_DBIAS_HVT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DIG_DBIAS_HVT, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR_HI[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_HI, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN3, }; static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { - {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; -static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { - {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; -static const esp_efuse_desc_t WR_DIS_KEY0[] = { - {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MAJOR, }; -static const esp_efuse_desc_t WR_DIS_KEY1[] = { - {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, +static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, }; -static const esp_efuse_desc_t WR_DIS_KEY2[] = { - {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, +static const esp_efuse_desc_t WR_DIS_OCODE[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, }; -static const esp_efuse_desc_t WR_DIS_KEY3[] = { - {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0, }; -static const esp_efuse_desc_t WR_DIS_KEY4[] = { - {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN1, }; -static const esp_efuse_desc_t WR_DIS_KEY5[] = { - {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN2, }; -static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, }; static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 30, 1}, // Write protection for USB_EXCHG_PINS, + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_USB_EXT_PHY_ENABLE[] = { + {EFUSE_BLK0, 30, 1}, // [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, }; static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 7}, // Read protection, + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, }; -static const esp_efuse_desc_t RD_DIS_KEY0[] = { - {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0, }; -static const esp_efuse_desc_t RD_DIS_KEY1[] = { - {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1, }; -static const esp_efuse_desc_t RD_DIS_KEY2[] = { - {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2, }; -static const esp_efuse_desc_t RD_DIS_KEY3[] = { - {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3, }; -static const esp_efuse_desc_t RD_DIS_KEY4[] = { - {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, }; -static const esp_efuse_desc_t RD_DIS_KEY5[] = { - {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5, }; -static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { - {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, +static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, }; static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // Disable Icache, + {EFUSE_BLK0, 40, 1}, // [] Set this bit to disable Icache, }; static const esp_efuse_desc_t DIS_DCACHE[] = { - {EFUSE_BLK0, 41, 1}, // Disable Dcace, + {EFUSE_BLK0, 41, 1}, // [] Set this bit to disable Dcache, }; static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode include boot_mode 0 1 2 3 6 7, + {EFUSE_BLK0, 42, 1}, // [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7), }; static const esp_efuse_desc_t DIS_DOWNLOAD_DCACHE[] = { - {EFUSE_BLK0, 43, 1}, // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7, + {EFUSE_BLK0, 43, 1}, // [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7), }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, + {EFUSE_BLK0, 44, 1}, // [] Set this bit to disable the function that forces chip into download mode, }; -static const esp_efuse_desc_t DIS_USB[] = { - {EFUSE_BLK0, 45, 1}, // Disable USB function, +static const esp_efuse_desc_t DIS_USB_OTG[] = { + {EFUSE_BLK0, 45, 1}, // [DIS_USB] Set this bit to disable USB function, }; -static const esp_efuse_desc_t DIS_CAN[] = { - {EFUSE_BLK0, 46, 1}, // Disable CAN function, +static const esp_efuse_desc_t DIS_TWAI[] = { + {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Set this bit to disable CAN function, }; static const esp_efuse_desc_t DIS_APP_CPU[] = { - {EFUSE_BLK0, 47, 1}, // Disables APP CPU, + {EFUSE_BLK0, 47, 1}, // [] Disable app cpu, }; static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral, + {EFUSE_BLK0, 48, 3}, // [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module, }; -static const esp_efuse_desc_t HARD_DIS_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // Hardware disable jtag permanently disable jtag function, +static const esp_efuse_desc_t DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 51, 1}, // [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // Disable flash encrypt function, + {EFUSE_BLK0, 52, 1}, // [] Set this bit to disable flash encryption when in download boot modes, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, + {EFUSE_BLK0, 57, 1}, // [] Set this bit to exchange USB D+ and D- pins, }; static const esp_efuse_desc_t USB_EXT_PHY_ENABLE[] = { - {EFUSE_BLK0, 58, 1}, // Enable external PHY, -}; - -static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = { - {EFUSE_BLK0, 59, 2}, // Enables BTLC GPIO, + {EFUSE_BLK0, 58, 1}, // [EXT_PHY_ENABLE] Set this bit to enable external PHY, }; static const esp_efuse_desc_t VDD_SPI_XPD[] = { - {EFUSE_BLK0, 68, 1}, // VDD_SPI regulator power up, + {EFUSE_BLK0, 68, 1}, // [] SPI regulator power up signal, }; static const esp_efuse_desc_t VDD_SPI_TIEH[] = { - {EFUSE_BLK0, 69, 1}, // VDD_SPI regulator tie high to vdda, + {EFUSE_BLK0, 69, 1}, // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}, }; static const esp_efuse_desc_t VDD_SPI_FORCE[] = { - {EFUSE_BLK0, 70, 1}, // Force using eFuse configuration of VDD_SPI, + {EFUSE_BLK0, 70, 1}, // [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, + {EFUSE_BLK0, 80, 2}, // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, + {EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { - {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, + {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { - {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, + {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { - {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, + {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key, }; static const esp_efuse_desc_t KEY_PURPOSE_0[] = { - {EFUSE_BLK0, 88, 4}, // Key0 purpose, + {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Purpose of Key0, }; static const esp_efuse_desc_t KEY_PURPOSE_1[] = { - {EFUSE_BLK0, 92, 4}, // Key1 purpose, + {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Purpose of Key1, }; static const esp_efuse_desc_t KEY_PURPOSE_2[] = { - {EFUSE_BLK0, 96, 4}, // Key2 purpose, + {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Purpose of Key2, }; static const esp_efuse_desc_t KEY_PURPOSE_3[] = { - {EFUSE_BLK0, 100, 4}, // Key3 purpose, + {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Purpose of Key3, }; static const esp_efuse_desc_t KEY_PURPOSE_4[] = { - {EFUSE_BLK0, 104, 4}, // Key4 purpose, + {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Purpose of Key4, }; static const esp_efuse_desc_t KEY_PURPOSE_5[] = { - {EFUSE_BLK0, 108, 4}, // Key5 purpose, + {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Purpose of Key5, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // Secure boot enable, + {EFUSE_BLK0, 116, 1}, // [] Set this bit to enable secure boot, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, + {EFUSE_BLK0, 117, 1}, // [] Set this bit to enable revoking aggressive secure boot, }; static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 118, 1}, // Set to disable usb_serial_jtag-to-jtag function, + {EFUSE_BLK0, 118, 1}, // [] Set this bit to disable function of usb switch to jtag in module of usb device, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = { - {EFUSE_BLK0, 119, 1}, // Set to disable usb_serial_jtag module, + {EFUSE_BLK0, 119, 1}, // [DIS_USB_DEVICE] Set this bit to disable usb device, }; static const esp_efuse_desc_t STRAP_JTAG_SEL[] = { - {EFUSE_BLK0, 120, 1}, // Enable selection between usb_to_jtag or pad_to_jtag through gpio10, + {EFUSE_BLK0, 120, 1}, // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0, }; static const esp_efuse_desc_t USB_PHY_SEL[] = { - {EFUSE_BLK0, 121, 1}, // Select internal/external PHY for USB OTG and usb_serial_jtag, + {EFUSE_BLK0, 121, 1}, // [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"}, }; static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, + {EFUSE_BLK0, 124, 4}, // [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, + {EFUSE_BLK0, 128, 1}, // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7), }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // Disable direct boot mode, + {EFUSE_BLK0, 129, 1}, // [DIS_LEGACY_SPI_BOOT] Disable direct boot mode, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // Disable usb serial jtag print during rom boot, + {EFUSE_BLK0, 130, 1}, // [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}, }; static const esp_efuse_desc_t FLASH_ECC_MODE[] = { - {EFUSE_BLK0, 131, 1}, // Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode, + {EFUSE_BLK0, 131, 1}, // [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"}, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // Set this bit to disable download through USB-Serial-JTAG, + {EFUSE_BLK0, 132, 1}, // [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // Enable security download mode, + {EFUSE_BLK0, 133, 1}, // [] Set this bit to enable secure UART download mode, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print., + {EFUSE_BLK0, 134, 2}, // [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}, }; static const esp_efuse_desc_t PIN_POWER_SELECTION[] = { - {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI., + {EFUSE_BLK0, 136, 1}, // [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}, }; static const esp_efuse_desc_t FLASH_TYPE[] = { - {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line, + {EFUSE_BLK0, 137, 1}, // [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}, }; static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = { - {EFUSE_BLK0, 138, 2}, // Sets the size of flash page, + {EFUSE_BLK0, 138, 2}, // [] Set Flash page size, }; static const esp_efuse_desc_t FLASH_ECC_EN[] = { - {EFUSE_BLK0, 140, 1}, // Enables ECC in Flash boot mode, + {EFUSE_BLK0, 140, 1}, // [] Set 1 to enable ECC for flash boot, }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot, + {EFUSE_BLK0, 141, 1}, // [] Set this bit to force ROM code to send a resume command during SPI boot, }; static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, + {EFUSE_BLK0, 142, 16}, // [] Secure version (used by ESP-IDF anti-rollback feature), }; static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 159, 1}, // Set this bit to disable download through USB-OTG, + {EFUSE_BLK0, 159, 1}, // [] Set this bit to disable download through USB-OTG, }; static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, + {EFUSE_BLK0, 160, 1}, // [] Disables check of wafer version major, }; static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 161, 1}, // Disables check of blk version major, + {EFUSE_BLK0, 161, 1}, // [] Disables check of blk version major, }; -static const esp_efuse_desc_t MAC_FACTORY[] = { - {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], - {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], - {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], - {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], - {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], - {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK1, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 32, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 24, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 16, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 8, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { - {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, + {EFUSE_BLK1, 48, 6}, // [] SPI_PAD_configure CLK, }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { - {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), +static const esp_efuse_desc_t SPI_PAD_CONFIG_Q[] = { + {EFUSE_BLK1, 54, 6}, // [] SPI_PAD_configure Q(D1), }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { - {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), +static const esp_efuse_desc_t SPI_PAD_CONFIG_D[] = { + {EFUSE_BLK1, 60, 6}, // [] SPI_PAD_configure D(D0), }; static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { - {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, + {EFUSE_BLK1, 66, 6}, // [] SPI_PAD_configure CS, }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { - {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), +static const esp_efuse_desc_t SPI_PAD_CONFIG_HD[] = { + {EFUSE_BLK1, 72, 6}, // [] SPI_PAD_configure HD(D3), }; -static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { - {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), +static const esp_efuse_desc_t SPI_PAD_CONFIG_WP[] = { + {EFUSE_BLK1, 78, 6}, // [] SPI_PAD_configure WP(D2), }; static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { - {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, + {EFUSE_BLK1, 84, 6}, // [] SPI_PAD_configure DQS, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { - {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, + {EFUSE_BLK1, 90, 6}, // [] SPI_PAD_configure D4, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { - {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, + {EFUSE_BLK1, 96, 6}, // [] SPI_PAD_configure D5, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { - {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, + {EFUSE_BLK1, 102, 6}, // [] SPI_PAD_configure D6, }; static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { - {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, + {EFUSE_BLK1, 108, 6}, // [] SPI_PAD_configure D7, }; -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits, - {EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit, +static const esp_efuse_desc_t WAFER_VERSION_MINOR_LO[] = { + {EFUSE_BLK1, 114, 3}, // [] WAFER_VERSION_MINOR least significant bits, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 117, 3}, // Package version, + {EFUSE_BLK1, 117, 3}, // [] Package version, }; static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR, + {EFUSE_BLK1, 120, 3}, // [] BLK_VERSION_MINOR, }; -static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR, +static const esp_efuse_desc_t FLASH_CAP[] = { + {EFUSE_BLK1, 123, 3}, // [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"}, }; -static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK1, 186, 6}, // ADC2 calibration voltage at atten3, +static const esp_efuse_desc_t FLASH_TEMP[] = { + {EFUSE_BLK1, 126, 2}, // [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"}, }; -static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, +static const esp_efuse_desc_t FLASH_VENDOR[] = { + {EFUSE_BLK1, 128, 3}, // [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"}, }; -static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware, +static const esp_efuse_desc_t PSRAM_CAP[] = { + {EFUSE_BLK1, 131, 2}, // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}, }; -static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 132, 9}, // Temperature calibration data, +static const esp_efuse_desc_t PSRAM_TEMP[] = { + {EFUSE_BLK1, 133, 2}, // [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"}, }; -static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 141, 8}, // ADC OCode, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 149, 8}, // ADC1 init code at atten0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 157, 6}, // ADC1 init code at atten1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 163, 6}, // ADC1 init code at atten2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 169, 6}, // ADC1 init code at atten3, -}; - -static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 175, 8}, // ADC2 init code at atten0, -}; - -static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 183, 6}, // ADC2 init code at atten1, -}; - -static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 189, 6}, // ADC2 init code at atten2, -}; - -static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 195, 6}, // ADC2 init code at atten3, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 201, 8}, // ADC1 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 209, 8}, // ADC1 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 217, 8}, // ADC1 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK2, 225, 8}, // ADC1 calibration voltage at atten3, -}; - -static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 233, 8}, // ADC2 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 241, 7}, // ADC2 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 248, 7}, // ADC2 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t USER_DATA[] = { - {EFUSE_BLK3, 0, 256}, // User data, -}; - -static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { - {EFUSE_BLK3, 200, 48}, // Custom MAC, -}; - -static const esp_efuse_desc_t KEY0[] = { - {EFUSE_BLK4, 0, 256}, // Key0 or user data, -}; - -static const esp_efuse_desc_t KEY1[] = { - {EFUSE_BLK5, 0, 256}, // Key1 or user data, -}; - -static const esp_efuse_desc_t KEY2[] = { - {EFUSE_BLK6, 0, 256}, // Key2 or user data, -}; - -static const esp_efuse_desc_t KEY3[] = { - {EFUSE_BLK7, 0, 256}, // Key3 or user data, -}; - -static const esp_efuse_desc_t KEY4[] = { - {EFUSE_BLK8, 0, 256}, // Key4 or user data, -}; - -static const esp_efuse_desc_t KEY5[] = { - {EFUSE_BLK9, 0, 256}, // Key5 or user data, -}; - -static const esp_efuse_desc_t SYS_DATA_PART2[] = { - {EFUSE_BLK10, 0, 256}, // System configuration, +static const esp_efuse_desc_t PSRAM_VENDOR[] = { + {EFUSE_BLK1, 135, 2}, // [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"}, }; static const esp_efuse_desc_t K_RTC_LDO[] = { - {EFUSE_BLK1, 141, 7}, // BLOCK1 K_RTC_LDO, + {EFUSE_BLK1, 141, 7}, // [] BLOCK1 K_RTC_LDO, }; static const esp_efuse_desc_t K_DIG_LDO[] = { - {EFUSE_BLK1, 148, 7}, // BLOCK1 K_DIG_LDO, + {EFUSE_BLK1, 148, 7}, // [] BLOCK1 K_DIG_LDO, }; static const esp_efuse_desc_t V_RTC_DBIAS20[] = { - {EFUSE_BLK1, 155, 8}, // BLOCK1 voltage of rtc dbias20, + {EFUSE_BLK1, 155, 8}, // [] BLOCK1 voltage of rtc dbias20, }; static const esp_efuse_desc_t V_DIG_DBIAS20[] = { - {EFUSE_BLK1, 163, 8}, // BLOCK1 voltage of digital dbias20, + {EFUSE_BLK1, 163, 8}, // [] BLOCK1 voltage of digital dbias20, }; static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { - {EFUSE_BLK1, 171, 5}, // BLOCK1 digital dbias when hvt, + {EFUSE_BLK1, 171, 5}, // [] BLOCK1 digital dbias when hvt, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR_HI[] = { + {EFUSE_BLK1, 183, 1}, // [] WAFER_VERSION_MINOR most significant bit, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 184, 2}, // [] WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK1, 186, 6}, // [] ADC2 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK2, 128, 2}, // [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"}, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 132, 9}, // [] Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 141, 8}, // [] ADC OCode, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 149, 8}, // [] ADC1 init code at atten0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 157, 6}, // [] ADC1 init code at atten1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 163, 6}, // [] ADC1 init code at atten2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 169, 6}, // [] ADC1 init code at atten3, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 175, 8}, // [] ADC2 init code at atten0, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 183, 6}, // [] ADC2 init code at atten1, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 189, 6}, // [] ADC2 init code at atten2, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 195, 6}, // [] ADC2 init code at atten3, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 201, 8}, // [] ADC1 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 209, 8}, // [] ADC1 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 217, 8}, // [] ADC1 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK2, 225, 8}, // [] ADC1 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 233, 8}, // [] ADC2 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 241, 7}, // [] ADC2 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 248, 7}, // [] ADC2 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, +}; + +static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { + {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // [BLOCK_KEY0] Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // [BLOCK_KEY1] Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // [BLOCK_KEY2] Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // [BLOCK_KEY3] Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // [BLOCK_KEY5] Key5 or user data, +}; + +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK10, 0, 256}, // [BLOCK_SYS_DATA2] System data part 2 (reserved), }; @@ -574,692 +929,1136 @@ static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { - &WR_DIS[0], // Write protection + &WR_DIS[0], // [] Disable programming of individual eFuses NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { - &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { - &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { + &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { - &WR_DIS_GROUP_2[0], // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[] = { + &WR_DIS_DIS_DCACHE[0], // [] wr_dis of DIS_DCACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + &WR_DIS_DIS_DOWNLOAD_ICACHE[0], // [] wr_dis of DIS_DOWNLOAD_ICACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[] = { + &WR_DIS_DIS_DOWNLOAD_DCACHE[0], // [] wr_dis of DIS_DOWNLOAD_DCACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { + &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG[] = { + &WR_DIS_DIS_USB_OTG[0], // [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { + &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_APP_CPU[] = { + &WR_DIS_DIS_APP_CPU[0], // [] wr_dis of DIS_APP_CPU + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = { + &WR_DIS_DIS_PAD_JTAG[0], // [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { + &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG[0], // [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_STRAP_JTAG_SEL[] = { + &WR_DIS_STRAP_JTAG_SEL[0], // [] wr_dis of STRAP_JTAG_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = { + &WR_DIS_USB_PHY_SEL[0], // [] wr_dis of USB_PHY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[] = { + &WR_DIS_VDD_SPI_XPD[0], // [] wr_dis of VDD_SPI_XPD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[] = { + &WR_DIS_VDD_SPI_TIEH[0], // [] wr_dis of VDD_SPI_TIEH + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[] = { + &WR_DIS_VDD_SPI_FORCE[0], // [] wr_dis of VDD_SPI_FORCE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { - &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { - &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { - &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = { + &WR_DIS_KEY_PURPOSE_0[0], // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { - &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = { + &WR_DIS_KEY_PURPOSE_1[0], // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { - &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = { + &WR_DIS_KEY_PURPOSE_2[0], // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { - &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = { + &WR_DIS_KEY_PURPOSE_3[0], // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { - &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = { + &WR_DIS_KEY_PURPOSE_4[0], // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { - &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { + &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { - &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN + &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { - &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { + &WR_DIS_DIS_DIRECT_BOOT[0], // [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_MODE[] = { + &WR_DIS_FLASH_ECC_MODE[0], // [] wr_dis of FLASH_ECC_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[] = { + &WR_DIS_PIN_POWER_SELECTION[0], // [] wr_dis of PIN_POWER_SELECTION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[] = { + &WR_DIS_FLASH_TYPE[0], // [] wr_dis of FLASH_TYPE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[] = { + &WR_DIS_FLASH_PAGE_SIZE[0], // [] wr_dis of FLASH_PAGE_SIZE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[] = { + &WR_DIS_FLASH_ECC_EN[0], // [] wr_dis of FLASH_ECC_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { - &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[] = { + &WR_DIS_SPI_PAD_CONFIG_CLK[0], // [] wr_dis of SPI_PAD_CONFIG_CLK + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[] = { + &WR_DIS_SPI_PAD_CONFIG_Q[0], // [] wr_dis of SPI_PAD_CONFIG_Q + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[] = { + &WR_DIS_SPI_PAD_CONFIG_D[0], // [] wr_dis of SPI_PAD_CONFIG_D + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[] = { + &WR_DIS_SPI_PAD_CONFIG_CS[0], // [] wr_dis of SPI_PAD_CONFIG_CS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[] = { + &WR_DIS_SPI_PAD_CONFIG_HD[0], // [] wr_dis of SPI_PAD_CONFIG_HD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[] = { + &WR_DIS_SPI_PAD_CONFIG_WP[0], // [] wr_dis of SPI_PAD_CONFIG_WP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[] = { + &WR_DIS_SPI_PAD_CONFIG_DQS[0], // [] wr_dis of SPI_PAD_CONFIG_DQS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[] = { + &WR_DIS_SPI_PAD_CONFIG_D4[0], // [] wr_dis of SPI_PAD_CONFIG_D4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[] = { + &WR_DIS_SPI_PAD_CONFIG_D5[0], // [] wr_dis of SPI_PAD_CONFIG_D5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[] = { + &WR_DIS_SPI_PAD_CONFIG_D6[0], // [] wr_dis of SPI_PAD_CONFIG_D6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[] = { + &WR_DIS_SPI_PAD_CONFIG_D7[0], // [] wr_dis of SPI_PAD_CONFIG_D7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[] = { + &WR_DIS_WAFER_VERSION_MINOR_LO[0], // [] wr_dis of WAFER_VERSION_MINOR_LO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { + &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = { + &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { + &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = { + &WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[] = { + &WR_DIS_PSRAM_TEMP[0], // [] wr_dis of PSRAM_TEMP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = { + &WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[] = { + &WR_DIS_K_RTC_LDO[0], // [] wr_dis of K_RTC_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[] = { + &WR_DIS_K_DIG_LDO[0], // [] wr_dis of K_DIG_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[] = { + &WR_DIS_V_RTC_DBIAS20[0], // [] wr_dis of V_RTC_DBIAS20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[] = { + &WR_DIS_V_DIG_DBIAS20[0], // [] wr_dis of V_DIG_DBIAS20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[] = { + &WR_DIS_DIG_DBIAS_HVT[0], // [] wr_dis of DIG_DBIAS_HVT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[] = { + &WR_DIS_WAFER_VERSION_MINOR_HI[0], // [] wr_dis of WAFER_VERSION_MINOR_HI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN3[] = { + &WR_DIS_ADC2_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC2_CAL_VOL_ATTEN3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { - &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { - &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { - &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { - &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { + &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { - &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { + &WR_DIS_OCODE[0], // [] wr_dis of OCODE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { - &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { - &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { - &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { - &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN0[] = { + &WR_DIS_ADC2_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC2_INIT_CODE_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN1[] = { + &WR_DIS_ADC2_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC2_INIT_CODE_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN2[] = { + &WR_DIS_ADC2_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC2_INIT_CODE_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN3[] = { + &WR_DIS_ADC2_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC2_INIT_CODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN0[] = { + &WR_DIS_ADC2_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC2_CAL_VOL_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN1[] = { + &WR_DIS_ADC2_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC2_CAL_VOL_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN2[] = { + &WR_DIS_ADC2_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC2_CAL_VOL_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { + &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { + &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = { + &WR_DIS_BLOCK_KEY1[0], // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = { + &WR_DIS_BLOCK_KEY2[0], // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = { + &WR_DIS_BLOCK_KEY3[0], // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = { + &WR_DIS_BLOCK_KEY4[0], // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = { + &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { + &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = { - &WR_DIS_USB_EXCHG_PINS[0], // Write protection for USB_EXCHG_PINS + &WR_DIS_USB_EXCHG_PINS[0], // [] wr_dis of USB_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[] = { + &WR_DIS_USB_EXT_PHY_ENABLE[0], // [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { + &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG NULL }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // Read protection + &RD_DIS[0], // [] Disable reading from BlOCK4-10 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { - &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = { + &RD_DIS_BLOCK_KEY0[0], // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { - &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = { + &RD_DIS_BLOCK_KEY1[0], // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { - &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = { + &RD_DIS_BLOCK_KEY2[0], // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { - &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = { + &RD_DIS_BLOCK_KEY3[0], // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { - &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { + &RD_DIS_BLOCK_KEY4[0], // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { - &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = { + &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { - &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { + &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // Disable Icache + &DIS_ICACHE[0], // [] Set this bit to disable Icache NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[] = { - &DIS_DCACHE[0], // Disable Dcace + &DIS_DCACHE[0], // [] Set this bit to disable Dcache NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { - &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode include boot_mode 0 1 2 3 6 7 + &DIS_DOWNLOAD_ICACHE[0], // [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[] = { - &DIS_DOWNLOAD_DCACHE[0], // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 + &DIS_DOWNLOAD_DCACHE[0], // [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function + &DIS_FORCE_DOWNLOAD[0], // [] Set this bit to disable the function that forces chip into download mode NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = { - &DIS_USB[0], // Disable USB function +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG[] = { + &DIS_USB_OTG[0], // [DIS_USB] Set this bit to disable USB function NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = { - &DIS_CAN[0], // Disable CAN function +const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { + &DIS_TWAI[0], // [DIS_CAN] Set this bit to disable CAN function NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[] = { - &DIS_APP_CPU[0], // Disables APP CPU + &DIS_APP_CPU[0], // [] Disable app cpu NULL }; const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral + &SOFT_DIS_JTAG[0], // [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module NULL }; -const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[] = { - &HARD_DIS_JTAG[0], // Hardware disable jtag permanently disable jtag function +const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { + &DIS_PAD_JTAG[0], // [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encrypt function + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Set this bit to disable flash encryption when in download boot modes NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // Exchange D+ D- pins + &USB_EXCHG_PINS[0], // [] Set this bit to exchange USB D+ and D- pins NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[] = { - &USB_EXT_PHY_ENABLE[0], // Enable external PHY - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = { - &BTLC_GPIO_ENABLE[0], // Enables BTLC GPIO + &USB_EXT_PHY_ENABLE[0], // [EXT_PHY_ENABLE] Set this bit to enable external PHY NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[] = { - &VDD_SPI_XPD[0], // VDD_SPI regulator power up + &VDD_SPI_XPD[0], // [] SPI regulator power up signal NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[] = { - &VDD_SPI_TIEH[0], // VDD_SPI regulator tie high to vdda + &VDD_SPI_TIEH[0], // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[] = { - &VDD_SPI_FORCE[0], // Force using eFuse configuration of VDD_SPI + &VDD_SPI_FORCE[0], // [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold + &WDT_DELAY_SEL[0], // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { - &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { - &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key + &SECURE_BOOT_KEY_REVOKE0[0], // [] Revoke 1st secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { - &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key + &SECURE_BOOT_KEY_REVOKE1[0], // [] Revoke 2nd secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { - &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key + &SECURE_BOOT_KEY_REVOKE2[0], // [] Revoke 3rd secure boot key NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { - &KEY_PURPOSE_0[0], // Key0 purpose + &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Purpose of Key0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { - &KEY_PURPOSE_1[0], // Key1 purpose + &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Purpose of Key1 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { - &KEY_PURPOSE_2[0], // Key2 purpose + &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Purpose of Key2 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { - &KEY_PURPOSE_3[0], // Key3 purpose + &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Purpose of Key3 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { - &KEY_PURPOSE_4[0], // Key4 purpose + &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Purpose of Key4 NULL }; const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { - &KEY_PURPOSE_5[0], // Key5 purpose + &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Purpose of Key5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // Secure boot enable + &SECURE_BOOT_EN[0], // [] Set this bit to enable secure boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Set this bit to enable revoking aggressive secure boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // Set to disable usb_serial_jtag-to-jtag function + &DIS_USB_JTAG[0], // [] Set this bit to disable function of usb switch to jtag in module of usb device NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = { - &DIS_USB_SERIAL_JTAG[0], // Set to disable usb_serial_jtag module + &DIS_USB_SERIAL_JTAG[0], // [DIS_USB_DEVICE] Set this bit to disable usb device NULL }; const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[] = { - &STRAP_JTAG_SEL[0], // Enable selection between usb_to_jtag or pad_to_jtag through gpio10 + &STRAP_JTAG_SEL[0], // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0 NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = { - &USB_PHY_SEL[0], // Select internal/external PHY for USB OTG and usb_serial_jtag + &USB_PHY_SEL[0], // [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + &FLASH_TPUW[0], // [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + &DIS_DOWNLOAD_MODE[0], // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // Disable direct boot mode + &DIS_DIRECT_BOOT[0], // [DIS_LEGACY_SPI_BOOT] Disable direct boot mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // Disable usb serial jtag print during rom boot + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = { - &FLASH_ECC_MODE[0], // Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode + &FLASH_ECC_MODE[0], // [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // Set this bit to disable download through USB-Serial-JTAG + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode + &ENABLE_SECURITY_DOWNLOAD[0], // [] Set this bit to enable secure UART download mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. + &UART_PRINT_CONTROL[0], // [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = { - &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. + &PIN_POWER_SELECTION[0], // [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = { - &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line + &FLASH_TYPE[0], // [] SPI flash type {0: "4 data lines"; 1: "8 data lines"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = { - &FLASH_PAGE_SIZE[0], // Sets the size of flash page + &FLASH_PAGE_SIZE[0], // [] Set Flash page size NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = { - &FLASH_ECC_EN[0], // Enables ECC in Flash boot mode + &FLASH_ECC_EN[0], // [] Set 1 to enable ECC for flash boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot + &FORCE_SEND_RESUME[0], // [] Set this bit to force ROM code to send a resume command during SPI boot NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { - &SECURE_VERSION[0], // Secure version for anti-rollback + &SECURE_VERSION[0], // [] Secure version (used by ESP-IDF anti-rollback feature) NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = { - &DIS_USB_OTG_DOWNLOAD_MODE[0], // Set this bit to disable download through USB-OTG + &DIS_USB_OTG_DOWNLOAD_MODE[0], // [] Set this bit to disable download through USB-OTG NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { - &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major NULL }; const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { - &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major NULL }; -const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { - &MAC_FACTORY[0], // Factory MAC addr [0] - &MAC_FACTORY[1], // Factory MAC addr [1] - &MAC_FACTORY[2], // Factory MAC addr [2] - &MAC_FACTORY[3], // Factory MAC addr [3] - &MAC_FACTORY[4], // Factory MAC addr [4] - &MAC_FACTORY[5], // Factory MAC addr [5] +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { - &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK + &SPI_PAD_CONFIG_CLK[0], // [] SPI_PAD_configure CLK NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { - &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[] = { + &SPI_PAD_CONFIG_Q[0], // [] SPI_PAD_configure Q(D1) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { - &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[] = { + &SPI_PAD_CONFIG_D[0], // [] SPI_PAD_configure D(D0) NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { - &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS + &SPI_PAD_CONFIG_CS[0], // [] SPI_PAD_configure CS NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { - &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[] = { + &SPI_PAD_CONFIG_HD[0], // [] SPI_PAD_configure HD(D3) NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { - &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[] = { + &SPI_PAD_CONFIG_WP[0], // [] SPI_PAD_configure WP(D2) NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { - &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS + &SPI_PAD_CONFIG_DQS[0], // [] SPI_PAD_configure DQS NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { - &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 + &SPI_PAD_CONFIG_D4[0], // [] SPI_PAD_configure D4 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { - &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 + &SPI_PAD_CONFIG_D5[0], // [] SPI_PAD_configure D5 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { - &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 + &SPI_PAD_CONFIG_D6[0], // [] SPI_PAD_configure D6 NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { - &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 + &SPI_PAD_CONFIG_D7[0], // [] SPI_PAD_configure D7 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits - &WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[] = { + &WAFER_VERSION_MINOR_LO[0], // [] WAFER_VERSION_MINOR least significant bits NULL }; const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // Package version + &PKG_VERSION[0], // [] Package version NULL }; const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR +const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { + &FLASH_CAP[0], // [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"} NULL }; -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[] = { - &ADC2_CAL_VOL_ATTEN3[0], // ADC2 calibration voltage at atten3 +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { + &FLASH_TEMP[0], // [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"} NULL }; -const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID +const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { + &FLASH_VENDOR[0], // [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"} NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = { + &PSRAM_CAP[0], // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"} NULL }; -const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // Temperature calibration data +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[] = { + &PSRAM_TEMP[0], // [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"} NULL }; -const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // ADC OCode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { - &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { - &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { - &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { - &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN0[] = { - &ADC2_INIT_CODE_ATTEN0[0], // ADC2 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN1[] = { - &ADC2_INIT_CODE_ATTEN1[0], // ADC2 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN2[] = { - &ADC2_INIT_CODE_ATTEN2[0], // ADC2 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN3[] = { - &ADC2_INIT_CODE_ATTEN3[0], // ADC2 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { - &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { - &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { - &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { - &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[] = { - &ADC2_CAL_VOL_ATTEN0[0], // ADC2 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[] = { - &ADC2_CAL_VOL_ATTEN1[0], // ADC2 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[] = { - &ADC2_CAL_VOL_ATTEN2[0], // ADC2 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { - &USER_DATA[0], // User data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { - &USER_DATA_MAC_CUSTOM[0], // Custom MAC - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { - &KEY0[0], // Key0 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { - &KEY1[0], // Key1 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { - &KEY2[0], // Key2 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { - &KEY3[0], // Key3 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { - &KEY4[0], // Key4 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { - &KEY5[0], // Key5 or user data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { - &SYS_DATA_PART2[0], // System configuration +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = { + &PSRAM_VENDOR[0], // [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"} NULL }; const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { - &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO + &K_RTC_LDO[0], // [] BLOCK1 K_RTC_LDO NULL }; const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = { - &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO + &K_DIG_LDO[0], // [] BLOCK1 K_DIG_LDO NULL }; const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = { - &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20 + &V_RTC_DBIAS20[0], // [] BLOCK1 voltage of rtc dbias20 NULL }; const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = { - &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20 + &V_DIG_DBIAS20[0], // [] BLOCK1 voltage of digital dbias20 NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { - &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt + &DIG_DBIAS_HVT[0], // [] BLOCK1 digital dbias when hvt + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[] = { + &WAFER_VERSION_MINOR_HI[0], // [] WAFER_VERSION_MINOR most significant bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // [] WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[] = { + &ADC2_CAL_VOL_ATTEN3[0], // [] ADC2 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // [] Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // [] ADC OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { + &ADC1_INIT_CODE_ATTEN0[0], // [] ADC1 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { + &ADC1_INIT_CODE_ATTEN1[0], // [] ADC1 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { + &ADC1_INIT_CODE_ATTEN2[0], // [] ADC1 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { + &ADC1_INIT_CODE_ATTEN3[0], // [] ADC1 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN0[] = { + &ADC2_INIT_CODE_ATTEN0[0], // [] ADC2 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN1[] = { + &ADC2_INIT_CODE_ATTEN1[0], // [] ADC2 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN2[] = { + &ADC2_INIT_CODE_ATTEN2[0], // [] ADC2 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN3[] = { + &ADC2_INIT_CODE_ATTEN3[0], // [] ADC2 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { + &ADC1_CAL_VOL_ATTEN0[0], // [] ADC1 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { + &ADC1_CAL_VOL_ATTEN1[0], // [] ADC1 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { + &ADC1_CAL_VOL_ATTEN2[0], // [] ADC1 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { + &ADC1_CAL_VOL_ATTEN3[0], // [] ADC1 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[] = { + &ADC2_CAL_VOL_ATTEN0[0], // [] ADC2 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[] = { + &ADC2_CAL_VOL_ATTEN1[0], // [] ADC2 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[] = { + &ADC2_CAL_VOL_ATTEN2[0], // [] ADC2 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // [BLOCK_USR_DATA] User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // [BLOCK_KEY0] Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // [BLOCK_KEY1] Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // [BLOCK_KEY2] Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // [BLOCK_KEY3] Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // [BLOCK_KEY4] Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // [BLOCK_KEY5] Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved) NULL }; diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv index 8efee7c24b..cb915db58c 100644 --- a/components/efuse/esp32s3/esp_efuse_table.csv +++ b/components/efuse/esp32s3/esp_efuse_table.csv @@ -9,185 +9,236 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# EFUSE_RD_REPEAT_DATA BLOCK # -############################## - # EFUSE_RD_WR_DIS_REG # - WR_DIS, EFUSE_BLK0, 0, 32, Write protection - WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 - WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT - WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL - WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT - WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 - WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 - WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 - WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 - WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 - WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 - WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 - WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 - WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 - WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN - WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE - WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION - WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS - WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 - WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA - WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 - WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 - WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 - WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 - WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 - WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 - WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 - WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS +# This file was generated by regtools.py based on the efuses.yaml file with the version: f75f74727101326a187188a23f4a6c70 - # EFUSE_RD_REPEAT_DATA0_REG # - RD_DIS, EFUSE_BLK0, 32, 7, Read protection - RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 - RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 - RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 - RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 - RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 - RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 - RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 - DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache - DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace - DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7 - DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 - DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function - DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function - DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function - DIS_APP_CPU, EFUSE_BLK0, 47, 1, Disables APP CPU - SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral - HARD_DIS_JTAG, EFUSE_BLK0, 51, 1, Hardware disable jtag permanently disable jtag function - DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode - USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins - USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, Enable external PHY - BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enables BTLC GPIO - - # EFUSE_RD_REPEAT_DATA1_REG # - VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up - VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda - VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI - WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold - SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable - SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key - SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key - SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key - KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose - KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose - - # EFUSE_RD_REPEAT_DATA2_REG # - KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose - KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose - KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose - KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose - SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable - SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke - DIS_USB_JTAG, EFUSE_BLK0, 118, 1, Set to disable usb_serial_jtag-to-jtag function - DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, Set to disable usb_serial_jtag module - STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, Enable selection between usb_to_jtag or pad_to_jtag through gpio10 - USB_PHY_SEL, EFUSE_BLK0, 121, 1, Select internal/external PHY for USB OTG and usb_serial_jtag - FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms - - # EFUSE_RD_REPEAT_DATA3_REG # - DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 - DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode - DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot - FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Set this bit to disable download through USB-Serial-JTAG - ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode - UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. - PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. - FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line - FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Sets the size of flash page - FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enables ECC in Flash boot mode - FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot - SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback - DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, Set this bit to disable download through USB-OTG - - # EFUSE_RD_REPEAT_DATA4_REG # - DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major - DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major - - -# MAC_SPI_8M_SYS BLOCK# -####################### - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - - # RD_MAC_SPI_SYS_3 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits - , EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit - # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5 - PKG_VERSION, EFUSE_BLK1, 117, 3, Package version - BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR - - # RD_MAC_SPI_SYS_5 - # WAFER_VERSION_MINOR most significant bit - WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR - ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, ADC2 calibration voltage at atten3 - - -# SYS_DATA_PART1 BLOCK# - System configuration -####################### - # RD_SYS_PART1_DATA0 - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - - # RD_SYS_PART1_DATA4 - BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware - TEMP_CALIB, EFUSE_BLK2, 132, 9, Temperature calibration data - OCODE, EFUSE_BLK2, 141, 8, ADC OCode - ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, ADC1 init code at atten0 - ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, ADC1 init code at atten1 - - # RD_SYS_PART1_DATA5 - ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, ADC1 init code at atten2 - ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, ADC1 init code at atten3 - ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, ADC2 init code at atten0 - ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, ADC2 init code at atten1 - ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, ADC2 init code at atten2 - ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, ADC2 init code at atten3 - ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, ADC1 calibration voltage at atten0 - ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, ADC1 calibration voltage at atten1 - ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, ADC1 calibration voltage at atten2 - ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, ADC1 calibration voltage at atten3 - ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, ADC2 calibration voltage at atten0 - ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, ADC2 calibration voltage at atten1 - ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, ADC2 calibration voltage at atten2 - -################ -USER_DATA, EFUSE_BLK3, 0, 256, User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC - -################ -KEY0, EFUSE_BLK4, 0, 256, Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration - -# AUTO CONFIG DIG&RTC DBIAS# -################ -K_RTC_LDO, EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO -K_DIG_LDO, EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO -V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20 -V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20 -DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt +WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE +WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE +WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE +WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE +WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.DIS_USB_OTG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI +WR_DIS.DIS_APP_CPU, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_APP_CPU +WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG +WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG +WR_DIS.STRAP_JTAG_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of STRAP_JTAG_SEL +WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of USB_PHY_SEL +WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD +WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH +WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT +WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 +WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 +WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 +WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 +WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 +WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 +WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 +WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 +WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.FLASH_ECC_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_MODE +WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION +WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE +WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE +WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION +WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 19, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 +WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK +WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q +WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D +WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS +WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD +WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP +WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS +WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4 +WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5 +WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6 +WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7 +WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP +WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP +WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR +WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP +WR_DIS.PSRAM_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_TEMP +WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR +WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO +WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO +WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20 +WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20 +WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT +WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.ADC2_CAL_VOL_ATTEN3, EFUSE_BLK0, 20, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN3 +WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB +WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE +WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 +WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 +WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 +WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 +WR_DIS.ADC2_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN0 +WR_DIS.ADC2_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN1 +WR_DIS.ADC2_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN2 +WR_DIS.ADC2_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN3 +WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 +WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 +WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 +WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 +WR_DIS.ADC2_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN0 +WR_DIS.ADC2_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN1 +WR_DIS.ADC2_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN2 +WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 +WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 +WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 +WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 +WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 +WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 +WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS +WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE +WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 +RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 +RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 +RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 +RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 +RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 +RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 +RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 +DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache +DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache +DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7) +DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7) +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode +DIS_USB_OTG, EFUSE_BLK0, 45, 1, [DIS_USB] Set this bit to disable USB function +DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function +DIS_APP_CPU, EFUSE_BLK0, 47, 1, [] Disable app cpu +SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module +DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes +USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins +USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, [EXT_PHY_ENABLE] Set this bit to enable external PHY +VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] SPI regulator power up signal +VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} +VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI +WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key +SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key +SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key +KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0 +KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1 +KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2 +KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3 +KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4 +KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5 +SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot +DIS_USB_JTAG, EFUSE_BLK0, 118, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device +DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, [DIS_USB_DEVICE] Set this bit to disable usb device +STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0 +USB_PHY_SEL, EFUSE_BLK0, 121, 1, [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"} +FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7) +DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"} +FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"} +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode +UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} +PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} +FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"} +FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, [] Set Flash page size +FLASH_ECC_EN, EFUSE_BLK0, 140, 1, [] Set 1 to enable ECC for flash boot +FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot +SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature) +DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, [] Set this bit to disable download through USB-OTG +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major +MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address +SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK +SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1) +SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0) +SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS +SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3) +SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2) +SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS +SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4 +SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5 +SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6 +SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7 +WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits +PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version +BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR +FLASH_CAP, EFUSE_BLK1, 123, 3, [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"} +FLASH_TEMP, EFUSE_BLK1, 126, 2, [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"} +FLASH_VENDOR, EFUSE_BLK1, 128, 3, [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"} +PSRAM_CAP, EFUSE_BLK1, 131, 2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"} +PSRAM_TEMP, EFUSE_BLK1, 133, 2, [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"} +PSRAM_VENDOR, EFUSE_BLK1, 135, 2, [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"} +K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO +K_DIG_LDO, EFUSE_BLK1, 148, 7, [] BLOCK1 K_DIG_LDO +V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, [] BLOCK1 voltage of rtc dbias20 +V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, [] BLOCK1 voltage of digital dbias20 +DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, [] BLOCK1 digital dbias when hvt +WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit +WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR +ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, [] ADC2 calibration voltage at atten3 +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"} +TEMP_CALIB, EFUSE_BLK2, 132, 9, [] Temperature calibration data +OCODE, EFUSE_BLK2, 141, 8, [] ADC OCode +ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, [] ADC1 init code at atten0 +ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, [] ADC1 init code at atten1 +ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, [] ADC1 init code at atten2 +ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, [] ADC1 init code at atten3 +ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, [] ADC2 init code at atten0 +ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, [] ADC2 init code at atten1 +ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, [] ADC2 init code at atten2 +ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, [] ADC2 init code at atten3 +ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, [] ADC1 calibration voltage at atten0 +ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, [] ADC1 calibration voltage at atten1 +ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, [] ADC1 calibration voltage at atten2 +ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, [] ADC1 calibration voltage at atten3 +ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, [] ADC2 calibration voltage at atten0 +ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, [] ADC2 calibration voltage at atten1 +ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, [] ADC2 calibration voltage at atten2 +USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC +KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h index 93be6aae49..aa723f89bc 100644 --- a/components/efuse/esp32s3/include/esp_efuse_table.h +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2 +// md5_digest_table e0674ff40a1e124670c6eecf33410e76 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,54 +19,172 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG[]; +#define ESP_EFUSE_WR_DIS_DIS_USB ESP_EFUSE_WR_DIS_DIS_USB_OTG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_APP_CPU[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +#define ESP_EFUSE_WR_DIS_HARD_DIS_JTAG ESP_EFUSE_WR_DIS_DIS_PAD_JTAG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_STRAP_JTAG_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[]; +#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG[]; +#define ESP_EFUSE_DIS_USB ESP_EFUSE_DIS_USB_OTG +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +#define ESP_EFUSE_HARD_DIS_JTAG ESP_EFUSE_DIS_PAD_JTAG extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[]; +#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[]; @@ -76,23 +194,33 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; +#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG extern const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[]; @@ -104,21 +232,34 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; @@ -141,19 +282,24 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 #ifdef __cplusplus } diff --git a/components/hal/esp32s3/include/hal/efuse_ll.h b/components/hal/esp32s3/include/hal/efuse_ll.h index 1e408e453c..14e7864679 100644 --- a/components/hal/esp32s3/include/hal/efuse_ll.h +++ b/components/hal/esp32s3/include/hal/efuse_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,32 +22,32 @@ extern "C" { __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) { - return EFUSE.rd_repeat_data1.reg_spi_boot_crypt_cnt; + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) { - return EFUSE.rd_repeat_data1.reg_wdt_delay_sel; + return EFUSE.rd_repeat_data1.wdt_delay_sel; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void) { - return EFUSE.rd_repeat_data3.reg_flash_type; + return EFUSE.rd_repeat_data3.flash_type; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - return EFUSE.rd_mac_spi_sys_0; + return EFUSE.rd_mac_spi_sys_0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - return EFUSE.rd_mac_spi_sys_1.reg_mac_1; + return EFUSE.rd_mac_spi_sys_1.mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) { - return EFUSE.rd_repeat_data2.reg_secure_boot_en; + return EFUSE.rd_repeat_data2.secure_boot_en; } // use efuse_hal_get_major_chip_version() to get major chip version @@ -59,7 +59,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_ve // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low; + return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_hi << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_lo; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) @@ -84,7 +84,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_versi __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - return 0; + return EFUSE.rd_mac_spi_sys_3.pkg_version; } /******************* eFuse control functions *************************/ diff --git a/components/soc/esp32s3/include/soc/efuse_defs.h b/components/soc/esp32s3/include/soc/efuse_defs.h new file mode 100644 index 0000000000..98cc1f24fc --- /dev/null +++ b/components/soc/esp32s3/include/soc/efuse_defs.h @@ -0,0 +1,31 @@ +/** + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#define EFUSE_PKG_VERSION_ESP32S3 0 // QFN56 +#define EFUSE_PKG_VERSION_ESP32S3PICO 1 // LGA56 + +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register 3. + */ +//#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ +/*description: Stores the second part of SPI_PAD_CONF..*/ +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) +#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h index 94e6851ae0..d7233b65db 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/include/soc/efuse_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,8 @@ #include "soc.h" +#include "efuse_defs.h" + #ifdef __cplusplus extern "C" { #endif @@ -560,27 +562,127 @@ apping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0..*/ #define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_S 0 -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */ -/*description: Stores the fist 14 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFF -#define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF -#define EFUSE_SYS_DATA_PART0_0_S 18 -/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ -/*description: Stores the second part of SPI_PAD_CONF..*/ -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) -#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 +/** EFUSE_RD_MAC_SPI_SYS_3_REG register + * BLOCK1 data register 3. + */ +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ +#define EFUSE_SPI_PAD_CONFIG_D5 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_M (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S) +#define EFUSE_SPI_PAD_CONFIG_D5_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D5_S 0 +/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ +#define EFUSE_SPI_PAD_CONFIG_D6 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_M (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S) +#define EFUSE_SPI_PAD_CONFIG_D6_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D6_S 6 +/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ +#define EFUSE_SPI_PAD_CONFIG_D7 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_M (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S) +#define EFUSE_SPI_PAD_CONFIG_D7_V 0x0000003FU +#define EFUSE_SPI_PAD_CONFIG_D7_S 12 +/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ +#define EFUSE_WAFER_VERSION_MINOR_LO 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_M (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S) +#define EFUSE_WAFER_VERSION_MINOR_LO_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_LO_S 18 +/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 21 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 24 +/** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0; + * Flash capacity + */ +#define EFUSE_FLASH_CAP 0x00000007U +#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) +#define EFUSE_FLASH_CAP_V 0x00000007U +#define EFUSE_FLASH_CAP_S 27 +/** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0; + * Flash temperature + */ +#define EFUSE_FLASH_TEMP 0x00000003U +#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) +#define EFUSE_FLASH_TEMP_V 0x00000003U +#define EFUSE_FLASH_TEMP_S 30 -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) -/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: Stores the fist 32 bits of the zeroth part of system data..*/ -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 0 +/** EFUSE_RD_MAC_SPI_SYS_4_REG register + * BLOCK1 data register 4. + */ +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0; + * Flash vendor + */ +#define EFUSE_FLASH_VENDOR 0x00000007U +#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) +#define EFUSE_FLASH_VENDOR_V 0x00000007U +#define EFUSE_FLASH_VENDOR_S 0 +/** EFUSE_PSRAM_CAP : R; bitpos: [4:3]; default: 0; + * PSRAM capacity + */ +#define EFUSE_PSRAM_CAP 0x00000003U +#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S) +#define EFUSE_PSRAM_CAP_V 0x00000003U +#define EFUSE_PSRAM_CAP_S 3 +/** EFUSE_PSRAM_TEMP : R; bitpos: [6:5]; default: 0; + * PSRAM temperature + */ +#define EFUSE_PSRAM_TEMP 0x00000003U +#define EFUSE_PSRAM_TEMP_M (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S) +#define EFUSE_PSRAM_TEMP_V 0x00000003U +#define EFUSE_PSRAM_TEMP_S 5 +/** EFUSE_PSRAM_VENDOR : R; bitpos: [8:7]; default: 0; + * PSRAM vendor + */ +#define EFUSE_PSRAM_VENDOR 0x00000003U +#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S) +#define EFUSE_PSRAM_VENDOR_V 0x00000003U +#define EFUSE_PSRAM_VENDOR_S 7 +/** EFUSE_RESERVED_1_137 : R; bitpos: [12:9]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_137 0x0000000FU +#define EFUSE_RESERVED_1_137_M (EFUSE_RESERVED_1_137_V << EFUSE_RESERVED_1_137_S) +#define EFUSE_RESERVED_1_137_V 0x0000000FU +#define EFUSE_RESERVED_1_137_S 9 +/** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0; + * BLOCK1 K_RTC_LDO + */ +#define EFUSE_K_RTC_LDO 0x0000007FU +#define EFUSE_K_RTC_LDO_M (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S) +#define EFUSE_K_RTC_LDO_V 0x0000007FU +#define EFUSE_K_RTC_LDO_S 13 +/** EFUSE_K_DIG_LDO : R; bitpos: [26:20]; default: 0; + * BLOCK1 K_DIG_LDO + */ +#define EFUSE_K_DIG_LDO 0x0000007FU +#define EFUSE_K_DIG_LDO_M (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S) +#define EFUSE_K_DIG_LDO_V 0x0000007FU +#define EFUSE_K_DIG_LDO_S 20 +/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [31:27]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ +#define EFUSE_V_RTC_DBIAS20 0x0000001FU +#define EFUSE_V_RTC_DBIAS20_M (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S) +#define EFUSE_V_RTC_DBIAS20_V 0x0000001FU +#define EFUSE_V_RTC_DBIAS20_S 27 #define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) /* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h index 4ad916e67a..afe940f4d0 100644 --- a/components/soc/esp32s3/include/soc/efuse_struct.h +++ b/components/soc/esp32s3/include/soc/efuse_struct.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,468 +12,2518 @@ extern "C" { #endif -typedef volatile struct efuse_dev_s { - uint32_t pgm_data0; - uint32_t pgm_data1; - uint32_t pgm_data2; - uint32_t pgm_data3; - uint32_t pgm_data4; - uint32_t pgm_data5; - uint32_t pgm_data6; - uint32_t pgm_data7; - uint32_t pgm_check_value0; - uint32_t pgm_check_value1; - uint32_t pgm_check_value2; - uint32_t rd_wr_dis; - union { - struct { - uint32_t reg_rd_dis : 7; /*Set this bit to disable reading from BlOCK4-10.*/ - uint32_t reg_rpt4_reserved5 : 1; /*Reserved*/ - uint32_t reg_dis_icache : 1; /*Set this bit to disable Icache.*/ - uint32_t reg_dis_dcache : 1; /*Set this bit to disable Dcache.*/ - uint32_t reg_dis_download_icache : 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_download_dcache : 1; /*Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_force_download : 1; /*Set this bit to disable the function that forces chip into download mode.*/ - uint32_t reg_dis_usb : 1; /*Set this bit to disable USB function.*/ - uint32_t reg_dis_can : 1; /*Set this bit to disable CAN function.*/ - uint32_t reg_dis_app_cpu : 1; /*Disable app cpu.*/ - uint32_t reg_soft_dis_jtag : 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ - uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ - uint32_t reg_dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ - uint32_t reg_usb_drefh : 2; /*Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.*/ - uint32_t reg_usb_drefl : 2; /*Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.*/ - uint32_t reg_usb_exchg_pins : 1; /*Set this bit to exchange USB D+ and D- pins.*/ - uint32_t reg_ext_phy_enable : 1; /*Set this bit to enable external PHY.*/ - uint32_t reg_btlc_gpio_enable : 2; /*Enable btlc gpio.*/ - uint32_t reg_vdd_spi_modecurlim : 1; /*SPI regulator switches current limit mode.*/ - uint32_t reg_vdd_spi_drefh : 2; /*SPI regulator high voltage reference.*/ - }; - uint32_t val; - } rd_repeat_data0; - union { - struct { - uint32_t reg_vdd_spi_drefm : 2; /*SPI regulator medium voltage reference.*/ - uint32_t reg_vdd_spi_drefl : 2; /*SPI regulator low voltage reference.*/ - uint32_t reg_vdd_spi_xpd : 1; /*SPI regulator power up signal.*/ - uint32_t reg_vdd_spi_tieh : 1; /*SPI regulator output is short connected to VDD3P3_RTC_IO.*/ - uint32_t reg_vdd_spi_force : 1; /*Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ - uint32_t reg_vdd_spi_en_init : 1; /*Set SPI regulator to 0 to configure init[1:0]=0.*/ - uint32_t reg_vdd_spi_encurlim : 1; /*Set SPI regulator to 1 to enable output current limit.*/ - uint32_t reg_vdd_spi_dcurlim : 3; /*Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).*/ - uint32_t reg_vdd_spi_init : 2; /*Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/ - uint32_t reg_vdd_spi_dcap : 2; /*Prevents SPI regulator from overshoot.*/ - uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ - uint32_t reg_spi_boot_crypt_cnt : 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ - uint32_t reg_secure_boot_key_revoke0 : 1; /*Set this bit to enable revoking first secure boot key.*/ - uint32_t reg_secure_boot_key_revoke1 : 1; /*Set this bit to enable revoking second secure boot key.*/ - uint32_t reg_secure_boot_key_revoke2 : 1; /*Set this bit to enable revoking third secure boot key.*/ - uint32_t reg_key_purpose_0 : 4; /*Purpose of Key0.*/ - uint32_t reg_key_purpose_1 : 4; /*Purpose of Key1.*/ - }; - uint32_t val; - } rd_repeat_data1; - union { - struct { - uint32_t reg_key_purpose_2 : 4; /*Purpose of Key2.*/ - uint32_t reg_key_purpose_3 : 4; /*Purpose of Key3.*/ - uint32_t reg_key_purpose_4 : 4; /*Purpose of Key4.*/ - uint32_t reg_key_purpose_5 : 4; /*Purpose of Key5.*/ - uint32_t reg_rpt4_reserved0 : 4; /*Reserved (used for four backups method).*/ - uint32_t reg_secure_boot_en : 1; /*Set this bit to enable secure boot.*/ - uint32_t reg_secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ - uint32_t reg_dis_usb_jtag : 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ - uint32_t reg_dis_usb_device : 1; /*Set this bit to disable usb device.*/ - uint32_t reg_strap_jtag_sel : 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ - uint32_t reg_usb_phy_sel : 1; /*This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.*/ - uint32_t reg_power_glitch_dsense : 2; /*Sample delay configuration of power glitch.*/ - uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.*/ - }; - uint32_t val; - } rd_repeat_data2; - union { - struct { - uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).*/ - uint32_t reg_dis_direct_boot : 1; /*Set this bit to disable direct boot..*/ - uint32_t dis_usb_serial_jtag_rom_print : 1; /*Set this bit to disable USB-Serial-JTAG print during rom boot*/ - uint32_t reg_flash_ecc_mode : 1; /*Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/ - uint32_t reg_dis_usb_serial_jtag_download_mode: 1; /*Set this bit to disable download through USB-Serial-JTAG.*/ - uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/ - uint32_t reg_uart_print_control : 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ - uint32_t reg_pin_power_selection : 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/ - uint32_t reg_flash_type : 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/ - uint32_t reg_flash_page_size : 2; /*Set Flash page size.*/ - uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/ - uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ - uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ - uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/ - uint32_t reg_dis_usb_otg_download_mode : 1; /*Set this bit to disable download through USB-OTG*/ - }; - uint32_t val; - } rd_repeat_data3; - union { - struct { - uint32_t disable_wafer_version_major : 1; - uint32_t disable_blk_version_major : 1; - uint32_t reg_rpt4_reserved2 : 22; /*Reserved.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_data4; - uint32_t rd_mac_spi_sys_0; - union { - struct { - uint32_t reg_mac_1 : 16; /*Stores the high 16 bits of MAC address.*/ - uint32_t reg_spi_pad_conf_0 : 16; /*Stores the zeroth part of SPI_PAD_CONF.*/ - }; - uint32_t val; - } rd_mac_spi_sys_1; - uint32_t rd_mac_spi_sys_2; - union { - struct { - uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t wafer_version_minor_low: 3; - uint32_t pkg_version: 3; - uint32_t blk_version_minor:3; - uint32_t reg_sys_data_part0_0: 5; - }; - uint32_t val; - } rd_mac_spi_sys_3; - uint32_t rd_mac_spi_sys_4; - union { - struct { - uint32_t reserved1: 23; - uint32_t wafer_version_minor_high: 1; - uint32_t wafer_version_major: 2; - uint32_t reserved2: 6; - }; - uint32_t val; - } rd_mac_spi_sys_5; - uint32_t rd_sys_part1_data0; - uint32_t rd_sys_part1_data1; - uint32_t rd_sys_part1_data2; - uint32_t rd_sys_part1_data3; - union { - struct { - uint32_t blk_version_major : 2; - uint32_t reserved1: 30; - }; - uint32_t val; - } rd_sys_part1_data4; - uint32_t rd_sys_part1_data5; - uint32_t rd_sys_part1_data6; - uint32_t rd_sys_part1_data7; - uint32_t rd_usr_data0; - uint32_t rd_usr_data1; - uint32_t rd_usr_data2; - uint32_t rd_usr_data3; - uint32_t rd_usr_data4; - uint32_t rd_usr_data5; - uint32_t rd_usr_data6; - uint32_t rd_usr_data7; - uint32_t rd_key0_data0; - uint32_t rd_key0_data1; - uint32_t rd_key0_data2; - uint32_t rd_key0_data3; - uint32_t rd_key0_data4; - uint32_t rd_key0_data5; - uint32_t rd_key0_data6; - uint32_t rd_key0_data7; - uint32_t rd_key1_data0; - uint32_t rd_key1_data1; - uint32_t rd_key1_data2; - uint32_t rd_key1_data3; - uint32_t rd_key1_data4; - uint32_t rd_key1_data5; - uint32_t rd_key1_data6; - uint32_t rd_key1_data7; - uint32_t rd_key2_data0; - uint32_t rd_key2_data1; - uint32_t rd_key2_data2; - uint32_t rd_key2_data3; - uint32_t rd_key2_data4; - uint32_t rd_key2_data5; - uint32_t rd_key2_data6; - uint32_t rd_key2_data7; - uint32_t rd_key3_data0; - uint32_t rd_key3_data1; - uint32_t rd_key3_data2; - uint32_t rd_key3_data3; - uint32_t rd_key3_data4; - uint32_t rd_key3_data5; - uint32_t rd_key3_data6; - uint32_t rd_key3_data7; - uint32_t rd_key4_data0; - uint32_t rd_key4_data1; - uint32_t rd_key4_data2; - uint32_t rd_key4_data3; - uint32_t rd_key4_data4; - uint32_t rd_key4_data5; - uint32_t rd_key4_data6; - uint32_t rd_key4_data7; - uint32_t rd_key5_data0; - uint32_t rd_key5_data1; - uint32_t rd_key5_data2; - uint32_t rd_key5_data3; - uint32_t rd_key5_data4; - uint32_t rd_key5_data5; - uint32_t rd_key5_data6; - uint32_t rd_key5_data7; - uint32_t rd_sys_part2_data0; - uint32_t rd_sys_part2_data1; - uint32_t rd_sys_part2_data2; - uint32_t rd_sys_part2_data3; - uint32_t rd_sys_part2_data4; - uint32_t rd_sys_part2_data5; - uint32_t rd_sys_part2_data6; - uint32_t rd_sys_part2_data7; - union { - struct { - uint32_t reg_rd_dis_err : 7; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved5_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_force_download_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_can_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_app_cpu_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_soft_dis_jtag_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_pad_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_exchg_pins_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_ext_phy_enable_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_btlc_gpio_enable_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_modecurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err0; - union { - struct { - uint32_t reg_vdd_spi_drefm_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_xpd_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_tieh_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_force_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_en_init_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_encurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_dcurlim_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_init_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_vdd_spi_dcap_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_wdt_delay_sel_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_spi_boot_crypt_cnt_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke0_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke1_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_key_revoke2_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_1_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err1; - union { - struct { - uint32_t reg_key_purpose_2_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_3_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_4_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_key_purpose_5_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_boot_aggressive_revoke_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_device_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_strap_jtag_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_usb_phy_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_power_glitch_dsense_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_tpuw_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ - }; - uint32_t val; - } rd_repeat_err2; - union { - struct { - uint32_t reg_dis_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_direct_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_serial_jtag_rom_print_err:1;/*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_ecc_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_dis_usb_serial_jtag_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_enable_security_download_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_uart_print_control_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_pin_power_selection_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_type_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_page_size_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/ - uint32_t reg_dis_usb_otg_download_mode_err: 1; /*Set this bit to disable download through USB-OTG*/ - }; - uint32_t val; - } rd_repeat_err3; - union { - struct { - uint32_t reg_rpt4_reserved2_err : 24; /*If any bits in this filed are 1, then it indicates a programming error.*/ - uint32_t reserved24 : 8; /*Reserved.*/ - }; - uint32_t val; - } rd_repeat_err4; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - union { - struct { - uint32_t rd_mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_key0_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key1_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key2_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key3_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - uint32_t rd_key4_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ - }; - uint32_t val; - } rd_rs_err0; - union { - struct { - uint32_t rd_key5_err_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t rd_sys_part2_num: 3; /*The value of this signal means the number of error bytes.*/ - uint32_t rd_sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ - uint32_t reserved8: 24; /*Reserved.*/ - }; - uint32_t val; - } rd_rs_err1; - union { - struct { - uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ - uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ - uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/ - uint32_t reserved3: 13; /*Reserved.*/ - uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ - uint32_t reserved17: 15; /*Reserved.*/ - }; - uint32_t val; - } clk; - union { - struct { - uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } conf; - union { - struct { - uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/ - uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/ - uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/ - uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/ - uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/ - uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/ - uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/ - uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } status; - union { - struct { - uint32_t read_cmd: 1; /*Set this bit to send read command.*/ - uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/ - uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/ - uint32_t reserved6: 26; /*Reserved.*/ - }; - uint32_t val; - } cmd; - union { - struct { - uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t read_done: 1; /*The status signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/ - uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/ - uint32_t reserved2: 30; /*Reserved.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/ - uint32_t dac_clk_pad_sel: 1; /*Don't care.*/ - uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/ - uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/ - uint32_t reserved18: 14; /*Reserved.*/ - }; - uint32_t val; - } dac_conf; - union { - struct { - uint32_t reserved0 : 24; /*Reserved. (Default read timing parameter)*/ - uint32_t reg_read_init_num : 8; /*Configures the initial read time of eFuse.*/ - }; - uint32_t val; - } rd_tim_conf; - uint32_t wr_tim_conf0; - union { - struct { - uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/ - uint32_t pwr_on_num: 16; /*Configures the power up time for VDDQ.*/ - uint32_t reserved24: 8; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf1; - union { - struct { - uint32_t pwr_off_num: 16; /*Configures the power outage time for VDDQ.*/ - uint32_t reserved16: 16; /*Reserved.*/ - }; - uint32_t val; - } wr_tim_conf2; - union { - struct { - uint32_t date: 28; /*Stores eFuse version.*/ - uint32_t reserved28: 4; /*Reserved.*/ - }; - uint32_t val; - } date; +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_0:32; + }; + uint32_t val; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Register */ +/** Type of rd_wr_dis register + * BLOCK0 data register 0. + */ +typedef union { + struct { + /** wr_dis : RO; bitpos: [31:0]; default: 0; + * Disable programming of individual eFuses. + */ + uint32_t wr_dis:32; + }; + uint32_t val; +} efuse_rd_wr_dis_reg_t; + +/** Type of rd_repeat_data0 register + * BLOCK0 data register 1. + */ +typedef union { + struct { + /** rd_dis : RO; bitpos: [6:0]; default: 0; + * Set this bit to disable reading from BlOCK4-10. + */ + uint32_t rd_dis:7; + /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + uint32_t dis_rtc_ram_boot:1; + /** dis_icache : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + uint32_t dis_icache:1; + /** dis_dcache : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + uint32_t dis_dcache:1; + /** dis_download_icache : RO; bitpos: [10]; default: 0; + * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ + uint32_t dis_download_icache:1; + /** dis_download_dcache : RO; bitpos: [11]; default: 0; + * Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, + * 7). + */ + uint32_t dis_download_dcache:1; + /** dis_force_download : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + uint32_t dis_force_download:1; + /** dis_usb_otg : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ + uint32_t dis_usb_otg:1; + /** dis_twai : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + uint32_t dis_twai:1; + /** dis_app_cpu : RO; bitpos: [15]; default: 0; + * Disable app cpu. + */ + uint32_t dis_app_cpu:1; + /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; + * Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG + * can be enabled in HMAC module. + */ + uint32_t soft_dis_jtag:3; + /** dis_pad_jtag : RO; bitpos: [19]; default: 0; + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + */ + uint32_t dis_pad_jtag:1; + /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; + * Set this bit to disable flash encryption when in download boot modes. + */ + uint32_t dis_download_manual_encrypt:1; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored + * in eFuse. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, + * stored in eFuse. + */ + uint32_t usb_drefl:2; + /** usb_exchg_pins : RO; bitpos: [25]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + uint32_t usb_exchg_pins:1; + /** usb_ext_phy_enable : RO; bitpos: [26]; default: 0; + * Set this bit to enable external PHY. + */ + uint32_t usb_ext_phy_enable:1; + /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0; + * Bluetooth GPIO signal output security level control. + */ + uint32_t btlc_gpio_enable:2; + /** vdd_spi_modecurlim : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + uint32_t vdd_spi_modecurlim:1; + /** vdd_spi_drefh : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + uint32_t vdd_spi_drefh:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** vdd_spi_drefm : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + uint32_t vdd_spi_drefm:2; + /** vdd_spi_drefl : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + uint32_t vdd_spi_drefl:2; + /** vdd_spi_xpd : RO; bitpos: [4]; default: 0; + * SPI regulator power up signal. + */ + uint32_t vdd_spi_xpd:1; + /** vdd_spi_tieh : RO; bitpos: [5]; default: 0; + * SPI regulator output is short connected to VDD3P3_RTC_IO. + */ + uint32_t vdd_spi_tieh:1; + /** vdd_spi_force : RO; bitpos: [6]; default: 0; + * Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + */ + uint32_t vdd_spi_force:1; + /** vdd_spi_en_init : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + uint32_t vdd_spi_en_init:1; + /** vdd_spi_encurlim : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + uint32_t vdd_spi_encurlim:1; + /** vdd_spi_dcurlim : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + */ + uint32_t vdd_spi_dcurlim:3; + /** vdd_spi_init : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. + */ + uint32_t vdd_spi_init:2; + /** vdd_spi_dcap : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + uint32_t vdd_spi_dcap:2; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: + * 80000. 2: 160000. 3:320000. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking first secure boot key. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Set this bit to enable revoking second secure boot key. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Set this bit to enable revoking third secure boot key. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** rpt4_reserved0 : RO; bitpos: [19:16]; default: 0; + * Reserved (used for four backups method). + */ + uint32_t rpt4_reserved0:4; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Set this bit to enable revoking aggressive secure boot. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** dis_usb_jtag : RO; bitpos: [22]; default: 0; + * Set this bit to disable function of usb switch to jtag in module of usb device. + */ + uint32_t dis_usb_jtag:1; + /** dis_usb_serial_jtag : RO; bitpos: [23]; default: 0; + * Set this bit to disable usb device. + */ + uint32_t dis_usb_serial_jtag:1; + /** strap_jtag_sel : RO; bitpos: [24]; default: 0; + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + */ + uint32_t strap_jtag_sel:1; + /** usb_phy_sel : RO; bitpos: [25]; default: 0; + * This bit is used to switch internal PHY and external PHY for USB OTG and USB + * Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to + * USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to + * USB Device. + */ + uint32_t usb_phy_sel:1; + /** power_glitch_dsense : RO; bitpos: [27:26]; default: 0; + * Sample delay configuration of power glitch. + */ + uint32_t power_glitch_dsense:2; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Configures flash waiting time after power-up, in unit of ms. If the value is less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time + * is twice the configurable value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Disable direct boot mode + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Selectes the default UART print channel. 0: UART0. 1: UART1. + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** flash_ecc_mode : RO; bitpos: [3]; default: 0; + * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would + * use 16to17 byte mode. + */ + uint32_t flash_ecc_mode:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Set this bit to disable UART download mode through USB. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 + * is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + */ + uint32_t uart_print_control:2; + /** pin_power_selection : RO; bitpos: [8]; default: 0; + * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + */ + uint32_t pin_power_selection:1; + /** flash_type : RO; bitpos: [9]; default: 0; + * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + */ + uint32_t flash_type:1; + /** flash_page_size : RO; bitpos: [11:10]; default: 0; + * Set Flash page size. + */ + uint32_t flash_page_size:2; + /** flash_ecc_en : RO; bitpos: [12]; default: 0; + * Set 1 to enable ECC for flash boot. + */ + uint32_t flash_ecc_en:1; + /** force_send_resume : RO; bitpos: [13]; default: 0; + * Set this bit to force ROM code to send a resume command during SPI boot. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [29:14]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + uint32_t secure_version:16; + /** powerglitch_en : RO; bitpos: [30]; default: 0; + * Set this bit to enable power glitch function. + */ + uint32_t powerglitch_en:1; + /** dis_usb_otg_download_mode : R; bitpos: [31]; default: 0; + * Set this bit to disable download through USB-OTG + */ + uint32_t dis_usb_otg_download_mode:1; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + /** disable_wafer_version_major : R; bitpos: [0]; default: 0; + * Disables check of wafer version major + */ + uint32_t disable_wafer_version_major:1; + /** disable_blk_version_major : R; bitpos: [1]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** reserved_0_162 : R; bitpos: [23:2]; default: 0; + * reserved + */ + uint32_t reserved_0_162:22; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_spi_sys_0 register + * BLOCK1 data register 0. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_0_reg_t; + +/** Type of rd_mac_spi_sys_1 register + * BLOCK1 data register 1. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; + * SPI_PAD_configure CLK + */ + uint32_t spi_pad_config_clk:6; + /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; + * SPI_PAD_configure Q(D1) + */ + uint32_t spi_pad_config_q:6; + /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d:4; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_1_reg_t; + +/** Type of rd_mac_spi_sys_2 register + * BLOCK1 data register 2. + */ +typedef union { + struct { + /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; + * SPI_PAD_configure D(D0) + */ + uint32_t spi_pad_config_d_1:2; + /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; + * SPI_PAD_configure CS + */ + uint32_t spi_pad_config_cs:6; + /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; + * SPI_PAD_configure HD(D3) + */ + uint32_t spi_pad_config_hd:6; + /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; + * SPI_PAD_configure WP(D2) + */ + uint32_t spi_pad_config_wp:6; + /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; + * SPI_PAD_configure DQS + */ + uint32_t spi_pad_config_dqs:6; + /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; + * SPI_PAD_configure D4 + */ + uint32_t spi_pad_config_d4:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_2_reg_t; + +/** Type of rd_mac_spi_sys_3 register + * BLOCK1 data register 3. + */ +typedef union { + struct { + /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; + * SPI_PAD_configure D5 + */ + uint32_t spi_pad_config_d5:6; + /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; + * SPI_PAD_configure D6 + */ + uint32_t spi_pad_config_d6:6; + /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; + * SPI_PAD_configure D7 + */ + uint32_t spi_pad_config_d7:6; + /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0; + * WAFER_VERSION_MINOR least significant bits + */ + uint32_t wafer_version_minor_lo:3; + /** pkg_version : R; bitpos: [23:21]; default: 0; + * Package version + */ + uint32_t pkg_version:3; + /** blk_version_minor : R; bitpos: [26:24]; default: 0; + * BLK_VERSION_MINOR + */ + uint32_t blk_version_minor:3; + /** flash_cap : R; bitpos: [29:27]; default: 0; + * Flash capacity + */ + uint32_t flash_cap:3; + /** flash_temp : R; bitpos: [31:30]; default: 0; + * Flash temperature + */ + uint32_t flash_temp:2; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_3_reg_t; + +/** Type of rd_mac_spi_sys_4 register + * BLOCK1 data register 4. + */ +typedef union { + struct { + /** flash_vendor : R; bitpos: [2:0]; default: 0; + * Flash vendor + */ + uint32_t flash_vendor:3; + /** psram_cap : R; bitpos: [4:3]; default: 0; + * PSRAM capacity + */ + uint32_t psram_cap:2; + /** psram_temp : R; bitpos: [6:5]; default: 0; + * PSRAM temperature + */ + uint32_t psram_temp:2; + /** psram_vendor : R; bitpos: [8:7]; default: 0; + * PSRAM vendor + */ + uint32_t psram_vendor:2; + /** reserved_1_137 : R; bitpos: [12:9]; default: 0; + * reserved + */ + uint32_t reserved_1_137:4; + /** k_rtc_ldo : R; bitpos: [19:13]; default: 0; + * BLOCK1 K_RTC_LDO + */ + uint32_t k_rtc_ldo:7; + /** k_dig_ldo : R; bitpos: [26:20]; default: 0; + * BLOCK1 K_DIG_LDO + */ + uint32_t k_dig_ldo:7; + /** v_rtc_dbias20 : R; bitpos: [31:27]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ + uint32_t v_rtc_dbias20:5; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_4_reg_t; + +/** Type of rd_mac_spi_sys_5 register + * BLOCK1 data register 5. + */ +typedef union { + struct { + /** v_rtc_dbias20_1 : R; bitpos: [2:0]; default: 0; + * BLOCK1 voltage of rtc dbias20 + */ + uint32_t v_rtc_dbias20_1:3; + /** v_dig_dbias20 : R; bitpos: [10:3]; default: 0; + * BLOCK1 voltage of digital dbias20 + */ + uint32_t v_dig_dbias20:8; + /** dig_dbias_hvt : R; bitpos: [15:11]; default: 0; + * BLOCK1 digital dbias when hvt + */ + uint32_t dig_dbias_hvt:5; + /** reserved_1_176 : R; bitpos: [22:16]; default: 0; + * reserved + */ + uint32_t reserved_1_176:7; + /** wafer_version_minor_hi : R; bitpos: [23]; default: 0; + * WAFER_VERSION_MINOR most significant bit + */ + uint32_t wafer_version_minor_hi:1; + /** wafer_version_major : R; bitpos: [25:24]; default: 0; + * WAFER_VERSION_MAJOR + */ + uint32_t wafer_version_major:2; + /** adc2_cal_vol_atten3 : R; bitpos: [31:26]; default: 0; + * ADC2 calibration voltage at atten3 + */ + uint32_t adc2_cal_vol_atten3:6; + }; + uint32_t val; +} efuse_rd_mac_spi_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register 0 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register 1 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register 2 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register 3 of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register 4 of BLOCK2 (system). + */ +typedef union { + struct { + /** blk_version_major : R; bitpos: [1:0]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware + */ + uint32_t blk_version_major:2; + /** reserved_2_130 : R; bitpos: [3:2]; default: 0; + * reserved + */ + uint32_t reserved_2_130:2; + /** temp_calib : R; bitpos: [12:4]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** ocode : R; bitpos: [20:13]; default: 0; + * ADC OCode + */ + uint32_t ocode:8; + /** adc1_init_code_atten0 : R; bitpos: [28:21]; default: 0; + * ADC1 init code at atten0 + */ + uint32_t adc1_init_code_atten0:8; + /** adc1_init_code_atten1 : R; bitpos: [31:29]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1:3; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register 5 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_init_code_atten1_1 : R; bitpos: [2:0]; default: 0; + * ADC1 init code at atten1 + */ + uint32_t adc1_init_code_atten1_1:3; + /** adc1_init_code_atten2 : R; bitpos: [8:3]; default: 0; + * ADC1 init code at atten2 + */ + uint32_t adc1_init_code_atten2:6; + /** adc1_init_code_atten3 : R; bitpos: [14:9]; default: 0; + * ADC1 init code at atten3 + */ + uint32_t adc1_init_code_atten3:6; + /** adc2_init_code_atten0 : R; bitpos: [22:15]; default: 0; + * ADC2 init code at atten0 + */ + uint32_t adc2_init_code_atten0:8; + /** adc2_init_code_atten1 : R; bitpos: [28:23]; default: 0; + * ADC2 init code at atten1 + */ + uint32_t adc2_init_code_atten1:6; + /** adc2_init_code_atten2 : R; bitpos: [31:29]; default: 0; + * ADC2 init code at atten2 + */ + uint32_t adc2_init_code_atten2:3; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register 6 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc2_init_code_atten2_1 : R; bitpos: [2:0]; default: 0; + * ADC2 init code at atten2 + */ + uint32_t adc2_init_code_atten2_1:3; + /** adc2_init_code_atten3 : R; bitpos: [8:3]; default: 0; + * ADC2 init code at atten3 + */ + uint32_t adc2_init_code_atten3:6; + /** adc1_cal_vol_atten0 : R; bitpos: [16:9]; default: 0; + * ADC1 calibration voltage at atten0 + */ + uint32_t adc1_cal_vol_atten0:8; + /** adc1_cal_vol_atten1 : R; bitpos: [24:17]; default: 0; + * ADC1 calibration voltage at atten1 + */ + uint32_t adc1_cal_vol_atten1:8; + /** adc1_cal_vol_atten2 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration voltage at atten2 + */ + uint32_t adc1_cal_vol_atten2:7; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register 7 of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_cal_vol_atten2_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration voltage at atten2 + */ + uint32_t adc1_cal_vol_atten2_1:1; + /** adc1_cal_vol_atten3 : R; bitpos: [8:1]; default: 0; + * ADC1 calibration voltage at atten3 + */ + uint32_t adc1_cal_vol_atten3:8; + /** adc2_cal_vol_atten0 : R; bitpos: [16:9]; default: 0; + * ADC2 calibration voltage at atten0 + */ + uint32_t adc2_cal_vol_atten0:8; + /** adc2_cal_vol_atten1 : R; bitpos: [23:17]; default: 0; + * ADC2 calibration voltage at atten1 + */ + uint32_t adc2_cal_vol_atten1:7; + /** adc2_cal_vol_atten2 : R; bitpos: [30:24]; default: 0; + * ADC2 calibration voltage at atten2 + */ + uint32_t adc2_cal_vol_atten2:7; + /** reserved_2_255 : R; bitpos: [31]; default: 0; + * reserved + */ + uint32_t reserved_2_255:1; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register 0 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register 1 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register 2 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register 3 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register 4 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register 5 of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register 6 of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register 7 of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register 0 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register 1 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register 2 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register 3 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register 4 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register 5 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register 6 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register 7 of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register 0 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register 1 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register 2 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register 3 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register 4 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register 5 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register 6 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register 7 of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register 0 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register 1 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register 2 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register 3 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register 4 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register 5 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register 6 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register 7 of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register 0 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register 1 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register 2 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register 3 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register 4 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Register 5 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Register 6 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Register 7 of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; + +/** Type of rd_key4_data0 register + * Register 0 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. + */ + uint32_t key4_data0:32; + }; + uint32_t val; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Register 1 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Register 2 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Register 3 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Register 4 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Register 5 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Register 6 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Register 7 of BLOCK8 (KEY4). + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; + +/** Type of rd_key5_data0 register + * Register 0 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Register 2 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Register 3 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Register 4 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Register 5 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Register 6 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Register 7 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; + +/** Type of rd_sys_part2_data0 register + * Register 0 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Register 1 of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1st 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Register 2 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2nd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Register 3 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3rd 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Register 4 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Register 5 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Register 6 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Register 7 of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; + + +/** Group: Report Register */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. + */ +typedef union { + struct { + /** rd_dis_err : RO; bitpos: [6:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rd_dis_err:7; + /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_rtc_ram_boot_err:1; + /** dis_icache_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_icache_err:1; + /** dis_dcache_err : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_dcache_err:1; + /** dis_download_icache_err : RO; bitpos: [10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_icache_err:1; + /** dis_download_dcache_err : RO; bitpos: [11]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_dcache_err:1; + /** dis_force_download_err : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_force_download_err:1; + /** dis_usb_err : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_err:1; + /** dis_can_err : RO; bitpos: [14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_can_err:1; + /** dis_app_cpu_err : RO; bitpos: [15]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_app_cpu_err:1; + /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t soft_dis_jtag_err:3; + /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_pad_jtag_err:1; + /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_manual_encrypt_err:1; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_drefl_err:2; + /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_exchg_pins_err:1; + /** ext_phy_enable_err : RO; bitpos: [26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t ext_phy_enable_err:1; + /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t btlc_gpio_enable_err:2; + /** vdd_spi_modecurlim_err : RO; bitpos: [29]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_modecurlim_err:1; + /** vdd_spi_drefh_err : RO; bitpos: [31:30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefh_err:2; + }; + uint32_t val; +} efuse_rd_repeat_err0_reg_t; + +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. + */ +typedef union { + struct { + /** vdd_spi_drefm_err : RO; bitpos: [1:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefm_err:2; + /** vdd_spi_drefl_err : RO; bitpos: [3:2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_drefl_err:2; + /** vdd_spi_xpd_err : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_xpd_err:1; + /** vdd_spi_tieh_err : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_tieh_err:1; + /** vdd_spi_force_err : RO; bitpos: [6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_force_err:1; + /** vdd_spi_en_init_err : RO; bitpos: [7]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_en_init_err:1; + /** vdd_spi_encurlim_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_encurlim_err:1; + /** vdd_spi_dcurlim_err : RO; bitpos: [11:9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_dcurlim_err:3; + /** vdd_spi_init_err : RO; bitpos: [13:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_init_err:2; + /** vdd_spi_dcap_err : RO; bitpos: [15:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t vdd_spi_dcap_err:2; + /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t wdt_delay_sel_err:2; + /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t spi_boot_crypt_cnt_err:3; + /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke0_err:1; + /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke1_err:1; + /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_key_revoke2_err:1; + /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_0_err:4; + /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_1_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err1_reg_t; + +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. + */ +typedef union { + struct { + /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_2_err:4; + /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_3_err:4; + /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_4_err:4; + /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t key_purpose_5_err:4; + /** rpt4_reserved0_err : RO; bitpos: [19:16]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rpt4_reserved0_err:4; + /** secure_boot_en_err : RO; bitpos: [20]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_en_err:1; + /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_boot_aggressive_revoke_err:1; + /** dis_usb_jtag_err : RO; bitpos: [22]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_jtag_err:1; + /** dis_usb_device_err : RO; bitpos: [23]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_device_err:1; + /** strap_jtag_sel_err : RO; bitpos: [24]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t strap_jtag_sel_err:1; + /** usb_phy_sel_err : RO; bitpos: [25]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t usb_phy_sel_err:1; + /** power_glitch_dsense_err : RO; bitpos: [27:26]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t power_glitch_dsense_err:2; + /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_tpuw_err:4; + }; + uint32_t val; +} efuse_rd_repeat_err2_reg_t; + +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. + */ +typedef union { + struct { + /** dis_download_mode_err : RO; bitpos: [0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_download_mode_err:1; + /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_legacy_spi_boot_err:1; + /** uart_print_channel_err : RO; bitpos: [2]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t uart_print_channel_err:1; + /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_ecc_mode_err:1; + /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t dis_usb_download_mode_err:1; + /** enable_security_download_err : RO; bitpos: [5]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t enable_security_download_err:1; + /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t uart_print_control_err:2; + /** pin_power_selection_err : RO; bitpos: [8]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t pin_power_selection_err:1; + /** flash_type_err : RO; bitpos: [9]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_type_err:1; + /** flash_page_size_err : RO; bitpos: [11:10]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_page_size_err:2; + /** flash_ecc_en_err : RO; bitpos: [12]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t flash_ecc_en_err:1; + /** force_send_resume_err : RO; bitpos: [13]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t force_send_resume_err:1; + /** secure_version_err : RO; bitpos: [29:14]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t secure_version_err:16; + /** powerglitch_en_err : RO; bitpos: [30]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t powerglitch_en_err:1; + /** rpt4_reserved1_err : RO; bitpos: [31]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_err:1; + }; + uint32_t val; +} efuse_rd_repeat_err3_reg_t; + +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. + */ +typedef union { + struct { + /** rpt4_reserved2_err : RO; bitpos: [23:0]; default: 0; + * If any bits in this filed are 1, then it indicates a programming error. + */ + uint32_t rpt4_reserved2_err:24; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_rd_repeat_err4_reg_t; + +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; + +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. + */ +typedef union { + struct { + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} efuse_rd_rs_err1_reg_t; + + +/** Group: Configuration Register */ +/** Type of clk register + * eFuse clcok configuration register. + */ +typedef union { + struct { + /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; + * Set this bit to force eFuse SRAM into power-saving mode. + */ + uint32_t efuse_mem_force_pd:1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; + * Set this bit and force to activate clock signal of eFuse SRAM. + */ + uint32_t mem_clk_force_on:1; + /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; + * Set this bit to force eFuse SRAM into working mode. + */ + uint32_t efuse_mem_force_pu:1; + uint32_t reserved_3:13; + /** clk_en : R/W; bitpos: [16]; default: 0; + * Set this bit and force to enable clock signal of eFuse memory. + */ + uint32_t clk_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} efuse_clk_reg_t; + +/** Type of conf register + * eFuse operation mode configuraiton register + */ +typedef union { + struct { + /** op_code : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command 0x5AA5: Operate read command. + */ + uint32_t op_code:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_conf_reg_t; + +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/WS/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + uint32_t reserved_24:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + + +/** Group: Status Register */ +/** Type of status register + * eFuse status register. + */ +typedef union { + struct { + /** state : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + uint32_t state:4; + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + uint32_t otp_vddq_is_sw:1; + /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + uint32_t repeat_err_cnt:8; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_status_reg_t; + + +/** Group: Interrupt Register */ +/** Type of int_raw register + * eFuse raw interrupt register. + */ +typedef union { + struct { + /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + uint32_t read_done_int_raw:1; + /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_raw_reg_t; + +/** Type of int_st register + * eFuse interrupt status register. + */ +typedef union { + struct { + /** read_done_int_st : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + uint32_t read_done_int_st:1; + /** pgm_done_int_st : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_st_reg_t; + +/** Type of int_ena register + * eFuse interrupt enable register. + */ +typedef union { + struct { + /** read_done_int_ena : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + uint32_t read_done_int_ena:1; + /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_ena_reg_t; + +/** Type of int_clr register + * eFuse interrupt clear register. + */ +typedef union { + struct { + /** read_done_int_clr : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + uint32_t read_done_int_clr:1; + /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + uint32_t pgm_done_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} efuse_int_clr_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34607760; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + +typedef struct { + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; + volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; + volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; + volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; + volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; + volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; + volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; + volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; + volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; + volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; + volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + uint32_t reserved_18c; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_194[11]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_clk_reg_t clk; + volatile efuse_conf_reg_t conf; + volatile efuse_status_reg_t status; + volatile efuse_cmd_reg_t cmd; + volatile efuse_int_raw_reg_t int_raw; + volatile efuse_int_st_reg_t int_st; + volatile efuse_int_ena_reg_t int_ena; + volatile efuse_int_clr_reg_t int_clr; + volatile efuse_dac_conf_reg_t dac_conf; + volatile efuse_rd_tim_conf_reg_t rd_tim_conf; + uint32_t reserved_1f0; + volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; + volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE;