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Merge branch 'feature/add_esp32c5_beta3_soc_header_files_part3' into 'master'

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feat(esp32c5): add struct name and reformat struct headers (stage 2/8, part3)

See merge request espressif/esp-idf!27521
This commit is contained in:
Kevin (Lao Kaiyao) 2023-12-02 21:49:31 +08:00
commit 03414a1550
73 changed files with 600 additions and 19153 deletions
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2
components/soc/esp32c5/include/soc/aes_struct.h
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@ -391,7 +391,7 @@ typedef union {
} aes_date_reg_t;
typedef struct {
typedef struct aes_dev_t {
volatile aes_key_0_reg_t key_0;
volatile aes_key_1_reg_t key_1;
volatile aes_key_2_reg_t key_2;

2
components/soc/esp32c5/include/soc/apb_saradc_struct.h
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@ -655,7 +655,7 @@ typedef union {
} apb_saradc_ctrl_date_reg_t;
typedef struct {
typedef struct apb_dev_t {
volatile apb_saradc_ctrl_reg_t saradc_ctrl;
volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;

3
components/soc/esp32c5/include/soc/assist_debug_struct.h
View File

@ -508,7 +508,7 @@ typedef union {
} assist_debug_date_reg_t;
typedef struct {
typedef struct assist_debug_dev_t {
volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
@ -538,6 +538,7 @@ typedef struct {
volatile assist_debug_date_reg_t date;
} assist_debug_dev_t;
extern assist_debug_dev_t ASSIST_DEBUG;
#ifndef __cplusplus
_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");

3
components/soc/esp32c5/include/soc/bitscrambler_struct.h
View File

@ -406,7 +406,7 @@ typedef union {
} bitscrambler_version_reg_t;
typedef struct {
typedef struct bitscrambler_dev_t {
volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
@ -426,6 +426,7 @@ typedef struct {
volatile bitscrambler_version_reg_t version;
} bitscrambler_dev_t;
extern bitscrambler_dev_t BITSCRAMBLER;
#ifndef __cplusplus
_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");

3
components/soc/esp32c5/include/soc/cache_struct.h
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@ -1319,7 +1319,7 @@ typedef union {
} cache_date_reg_t;
typedef struct {
typedef struct cache_dev_t {
uint32_t reserved_000;
volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl;
uint32_t reserved_008[6];
@ -1399,6 +1399,7 @@ typedef struct {
volatile cache_date_reg_t date;
} cache_dev_t;
extern cache_dev_t CACHE;
#ifndef __cplusplus
_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");

2
components/soc/esp32c5/include/soc/ds_struct.h
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@ -118,7 +118,7 @@ typedef union {
} ds_date_reg_t;
typedef struct {
typedef struct ds_dev_t {
volatile uint32_t y[128];
volatile uint32_t m[128];
volatile uint32_t rb[128];

2
components/soc/esp32c5/include/soc/ecc_mult_struct.h
View File

@ -139,7 +139,7 @@ typedef union {
} ecc_mult_date_reg_t;
typedef struct {
typedef struct ecc_mult_dev_t {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t int_raw;
volatile ecc_mult_int_st_reg_t int_st;

3
components/soc/esp32c5/include/soc/ecdsa_struct.h
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@ -284,7 +284,7 @@ typedef union {
} ecdsa_date_reg_t;
typedef struct {
typedef struct ecdsa_dev_t {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
@ -313,6 +313,7 @@ typedef struct {
volatile uint32_t qay[8];
} ecdsa_dev_t;
extern ecdsa_dev_t ECDSA;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");

2
components/soc/esp32c5/include/soc/efuse_struct.h
View File

@ -2112,7 +2112,7 @@ typedef union {
} efuse_date_reg_t;
typedef struct {
typedef struct efuse_dev_t {
volatile efuse_pgm_data0_reg_t pgm_data0;
volatile efuse_pgm_data1_reg_t pgm_data1;
volatile efuse_pgm_data2_reg_t pgm_data2;

2
components/soc/esp32c5/include/soc/gdma_struct.h
View File

@ -2040,7 +2040,7 @@ typedef union {
} gdma_bt_rx_sel_reg_t;
typedef struct {
typedef struct gdma_dev_t {
volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0;
volatile gdma_in_int_st_chn_reg_t in_int_st_ch0;
volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0;

2
components/soc/esp32c5/include/soc/gpio_struct.h
View File

@ -2512,7 +2512,7 @@ typedef union {
} gpio_date_reg_t;
typedef struct {
typedef struct gpio_dev_t {
volatile gpio_bt_select_reg_t bt_select;
volatile gpio_out_reg_t out;
volatile gpio_out_w1ts_reg_t out_w1ts;

3
components/soc/esp32c5/include/soc/hardware_lock_struct.h
View File

@ -80,7 +80,7 @@ typedef union {
} atomic_counter_reg_t;
typedef struct {
typedef struct atomic_dev_t {
volatile atomic_addr_lock_reg_t addr_lock;
volatile atomic_lr_addr_reg_t lr_addr;
volatile atomic_lr_value_reg_t lr_value;
@ -88,7 +88,6 @@ typedef struct {
volatile atomic_counter_reg_t counter;
} atomic_dev_t;
extern atomic_dev_t ATOMIC_LOCKER;
#ifndef __cplusplus
_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");

2
components/soc/esp32c5/include/soc/hmac_struct.h
View File

@ -255,7 +255,7 @@ typedef union {
} hmac_date_reg_t;
typedef struct {
typedef struct hmac_dev_t {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;

3883
components/soc/esp32c5/include/soc/host_reg.h
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2738
components/soc/esp32c5/include/soc/host_struct.h
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File diff suppressed because it is too large Load Diff

2
components/soc/esp32c5/include/soc/hp_apm_struct.h
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@ -1650,7 +1650,7 @@ typedef union {
} hp_apm_date_reg_t;
typedef struct {
typedef struct hp_apm_dev_t {
volatile hp_apm_region_filter_en_reg_t region_filter_en;
volatile hp_apm_region0_addr_start_reg_t region0_addr_start;
volatile hp_apm_region0_addr_end_reg_t region0_addr_end;

2
components/soc/esp32c5/include/soc/hp_system_struct.h
View File

@ -391,7 +391,7 @@ typedef union {
} hp_sys_date_reg_t;
typedef struct {
typedef struct hp_sys_dev_t {
volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf;
volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf;

3
components/soc/esp32c5/include/soc/huk_struct.h
View File

@ -213,7 +213,7 @@ typedef union {
} huk_date_reg_t;
typedef struct {
typedef struct huk_dev_t {
uint32_t reserved_000;
volatile huk_clk_reg_t clk;
volatile huk_int_raw_reg_t int_raw;
@ -231,6 +231,7 @@ typedef struct {
volatile uint32_t info[96];
} huk_dev_t;
extern huk_dev_t HUK;
#ifndef __cplusplus
_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");

70
components/soc/esp32c5/include/soc/i2c_reg.h
View File

@ -14,7 +14,7 @@ extern "C" {
/** I2C_SCL_LOW_PERIOD_REG register
* Configures the low level width of the SCL Clock.
*/
#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
* Configures the low level width of the SCL Clock.
* Measurement unit: i2c_sclk.
@ -27,7 +27,7 @@ extern "C" {
/** I2C_CTR_REG register
* Transmission setting
*/
#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4)
/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
* Configures the SDA output mode
* 1: Direct output,
@ -181,7 +181,7 @@ extern "C" {
/** I2C_SR_REG register
* Describe I2C work status.
*/
#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8)
/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
* Represents the received ACK value in master mode or slave mode.
* 0: ACK,
@ -304,7 +304,7 @@ extern "C" {
/** I2C_TO_REG register
* Setting time out control for receiving data.
*/
#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc)
/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
* Configures the timeout threshold period for SCL stucking at high or low level. The
* actual period is 2^(reg_time_out_value).
@ -328,7 +328,7 @@ extern "C" {
/** I2C_SLAVE_ADDR_REG register
* Local slave address setting
*/
#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10)
/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
* Configure the slave address of I2C Slave.
*/
@ -350,7 +350,7 @@ extern "C" {
/** I2C_FIFO_ST_REG register
* FIFO status register.
*/
#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
* Represents the offset address of the APB reading from RXFIFO
*/
@ -391,7 +391,7 @@ extern "C" {
/** I2C_FIFO_CONF_REG register
* FIFO configuration register.
*/
#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18)
/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
* Configures the water mark threshold of RXFIFO in nonfifo access mode. When
* reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
@ -464,7 +464,7 @@ extern "C" {
/** I2C_DATA_REG register
* Rx FIFO read data.
*/
#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c)
/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
* Represents the value of RXFIFO read data.
*/
@ -476,7 +476,7 @@ extern "C" {
/** I2C_INT_RAW_REG register
* Raw interrupt status
*/
#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
*/
@ -614,7 +614,7 @@ extern "C" {
/** I2C_INT_CLR_REG register
* Interrupt clear bits
*/
#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24)
/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
*/
@ -752,7 +752,7 @@ extern "C" {
/** I2C_INT_ENA_REG register
* Interrupt enable bits
*/
#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28)
/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
*/
@ -890,7 +890,7 @@ extern "C" {
/** I2C_INT_STATUS_REG register
* Status of captured I2C communication events
*/
#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c)
/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
*/
@ -1028,7 +1028,7 @@ extern "C" {
/** I2C_SDA_HOLD_REG register
* Configures the hold time after a negative SCL edge.
*/
#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
* Configures the time to hold the data after the falling edge of SCL.
* Measurement unit: i2c_sclk
@ -1041,7 +1041,7 @@ extern "C" {
/** I2C_SDA_SAMPLE_REG register
* Configures the sample time after a positive SCL edge.
*/
#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34)
/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
* Configures the sample time after a positive SCL edge.
* Measurement unit: i2c_sclk
@ -1054,7 +1054,7 @@ extern "C" {
/** I2C_SCL_HIGH_PERIOD_REG register
* Configures the high level width of SCL
*/
#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38)
/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
* Configures for how long SCL remains high in master mode.
* Measurement unit: i2c_sclk
@ -1075,7 +1075,7 @@ extern "C" {
/** I2C_SCL_START_HOLD_REG register
* Configures the delay between the SDA and SCL negative edge for a start condition
*/
#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the falling edge of SDA and the falling edge of SCL for
* a START condition.
@ -1089,7 +1089,7 @@ extern "C" {
/** I2C_SCL_RSTART_SETUP_REG register
* Configures the delay between the positive edge of SCL and the negative edge of SDA
*/
#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44)
/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the positive edge of SCL and the negative edge of SDA
* for a RESTART condition.
@ -1103,7 +1103,7 @@ extern "C" {
/** I2C_SCL_STOP_HOLD_REG register
* Configures the delay after the SCL clock edge for a stop condition
*/
#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48)
/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the delay after the STOP condition.
* Measurement unit: i2c_sclk
@ -1117,7 +1117,7 @@ extern "C" {
* Configures the delay between the SDA and SCL rising edge for a stop condition.
* Measurement unit: i2c_sclk
*/
#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c)
/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
* Configures the time between the rising edge of SCL and the rising edge of SDA.
* Measurement unit: i2c_sclk
@ -1130,7 +1130,7 @@ extern "C" {
/** I2C_FILTER_CFG_REG register
* SCL and SDA filter configuration register
*/
#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50)
/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
* Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
* input has smaller width than this register value, the I2C controller will ignore
@ -1169,7 +1169,7 @@ extern "C" {
/** I2C_COMD0_REG register
* I2C command register 0
*/
#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58)
/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. It consists of three parts:
* op_code is the command,
@ -1201,7 +1201,7 @@ extern "C" {
/** I2C_COMD1_REG register
* I2C command register 1
*/
#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c)
/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
* Configures command 1. See details in I2C_CMD0_REG[13:0].
*/
@ -1223,7 +1223,7 @@ extern "C" {
/** I2C_COMD2_REG register
* I2C command register 2
*/
#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60)
/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
* Configures command 2. See details in I2C_CMD0_REG[13:0].
*/
@ -1245,7 +1245,7 @@ extern "C" {
/** I2C_COMD3_REG register
* I2C command register 3
*/
#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
* Configures command 3. See details in I2C_CMD0_REG[13:0].
*/
@ -1267,7 +1267,7 @@ extern "C" {
/** I2C_COMD4_REG register
* I2C command register 4
*/
#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68)
/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
* Configures command 4. See details in I2C_CMD0_REG[13:0].
*/
@ -1289,7 +1289,7 @@ extern "C" {
/** I2C_COMD5_REG register
* I2C command register 5
*/
#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c)
/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
* Configures command 5. See details in I2C_CMD0_REG[13:0].
*/
@ -1311,7 +1311,7 @@ extern "C" {
/** I2C_COMD6_REG register
* I2C command register 6
*/
#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70)
/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
* Configures command 6. See details in I2C_CMD0_REG[13:0].
*/
@ -1333,7 +1333,7 @@ extern "C" {
/** I2C_COMD7_REG register
* I2C command register 7
*/
#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
* Configures command 7. See details in I2C_CMD0_REG[13:0].
*/
@ -1355,7 +1355,7 @@ extern "C" {
/** I2C_SCL_ST_TIME_OUT_REG register
* SCL status time out register
*/
#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78)
/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_FSM state unchanged period. It should be no
* more than 23.
@ -1369,7 +1369,7 @@ extern "C" {
/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
* SCL main status time out register
*/
#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c)
/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
* Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
* no more than 23.
@ -1383,7 +1383,7 @@ extern "C" {
/** I2C_SCL_SP_CONF_REG register
* Power configuration register
*/
#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
* Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
* equals to reg_scl_rst_slv_num[4:0].
@ -1427,7 +1427,7 @@ extern "C" {
/** I2C_SCL_STRETCH_CONF_REG register
* Set SCL stretch of I2C slave
*/
#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
* Configures the time period to release the SCL line from stretching to avoid timing
* violation. Usually it should be larger than the SDA setup time.
@ -1483,7 +1483,7 @@ extern "C" {
/** I2C_DATE_REG register
* Version register
*/
#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8)
/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050;
* Version control register.
*/
@ -1495,7 +1495,7 @@ extern "C" {
/** I2C_TXFIFO_START_ADDR_REG register
* I2C TXFIFO base address register
*/
#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100)
/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
* Represents the I2C txfifo first address.
*/
@ -1507,7 +1507,7 @@ extern "C" {
/** I2C_RXFIFO_START_ADDR_REG register
* I2C RXFIFO base address register
*/
#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180)
/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
* Represents the I2C rxfifo first address.
*/

172
components/soc/esp32c5/include/soc/i2c_struct.h
View File

@ -1001,8 +1001,8 @@ typedef union {
/** Group: Command registers */
/** Type of comd0 register
* I2C command register 0
/** Type of comd register
* I2C command register n
*/
typedef union {
struct {
@ -1019,166 +1019,18 @@ typedef union {
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more information.
*/
uint32_t command0:14;
uint32_t command:14;
uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0;
/** command_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command0_done:1;
uint32_t command_done:1;
};
uint32_t val;
} i2c_comd0_reg_t;
/** Type of comd1 register
* I2C command register 1
*/
typedef union {
struct {
/** command1 : R/W; bitpos: [13:0]; default: 0;
* Configures command 1. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command1:14;
uint32_t reserved_14:17;
/** command1_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 1 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command1_done:1;
};
uint32_t val;
} i2c_comd1_reg_t;
/** Type of comd2 register
* I2C command register 2
*/
typedef union {
struct {
/** command2 : R/W; bitpos: [13:0]; default: 0;
* Configures command 2. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command2:14;
uint32_t reserved_14:17;
/** command2_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 2 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command2_done:1;
};
uint32_t val;
} i2c_comd2_reg_t;
/** Type of comd3 register
* I2C command register 3
*/
typedef union {
struct {
/** command3 : R/W; bitpos: [13:0]; default: 0;
* Configures command 3. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command3:14;
uint32_t reserved_14:17;
/** command3_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 3 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command3_done:1;
};
uint32_t val;
} i2c_comd3_reg_t;
/** Type of comd4 register
* I2C command register 4
*/
typedef union {
struct {
/** command4 : R/W; bitpos: [13:0]; default: 0;
* Configures command 4. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command4:14;
uint32_t reserved_14:17;
/** command4_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 4 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command4_done:1;
};
uint32_t val;
} i2c_comd4_reg_t;
/** Type of comd5 register
* I2C command register 5
*/
typedef union {
struct {
/** command5 : R/W; bitpos: [13:0]; default: 0;
* Configures command 5. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command5:14;
uint32_t reserved_14:17;
/** command5_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 5 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command5_done:1;
};
uint32_t val;
} i2c_comd5_reg_t;
/** Type of comd6 register
* I2C command register 6
*/
typedef union {
struct {
/** command6 : R/W; bitpos: [13:0]; default: 0;
* Configures command 6. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command6:14;
uint32_t reserved_14:17;
/** command6_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 6 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command6_done:1;
};
uint32_t val;
} i2c_comd6_reg_t;
/** Type of comd7 register
* I2C command register 7
*/
typedef union {
struct {
/** command7 : R/W; bitpos: [13:0]; default: 0;
* Configures command 7. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command7:14;
uint32_t reserved_14:17;
/** command7_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 7 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command7_done:1;
};
uint32_t val;
} i2c_comd7_reg_t;
} i2c_comd_reg_t;
/** Group: Version register */
/** Type of date register
@ -1223,7 +1075,7 @@ typedef union {
} i2c_rxfifo_start_addr_reg_t;
typedef struct {
typedef struct i2c_dev_t {
volatile i2c_scl_low_period_reg_t scl_low_period;
volatile i2c_ctr_reg_t ctr;
volatile i2c_sr_reg_t sr;
@ -1246,14 +1098,7 @@ typedef struct {
volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg;
uint32_t reserved_054;
volatile i2c_comd0_reg_t comd0;
volatile i2c_comd1_reg_t comd1;
volatile i2c_comd2_reg_t comd2;
volatile i2c_comd3_reg_t comd3;
volatile i2c_comd4_reg_t comd4;
volatile i2c_comd5_reg_t comd5;
volatile i2c_comd6_reg_t comd6;
volatile i2c_comd7_reg_t comd7;
volatile i2c_comd_reg_t comd[8];
volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@ -1267,6 +1112,7 @@ typedef struct {
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifndef __cplusplus
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");

2
components/soc/esp32c5/include/soc/i2s_struct.h
View File

@ -965,7 +965,7 @@ typedef union {
} i2s_date_reg_t;
typedef struct {
typedef struct i2s_dev_t {
uint32_t reserved_000[3];
volatile i2s_int_raw_reg_t int_raw;
volatile i2s_int_st_reg_t int_st;

2
components/soc/esp32c5/include/soc/interrupt_matrix_struct.h
View File

@ -1280,7 +1280,7 @@ typedef union {
} interrupt_core0_interrupt_date_reg_t;
typedef struct {
typedef struct intmtx_core0_dev_t {
volatile interrupt_core0_wifi_mac_intr_map_reg_t wifi_mac_intr_map;
volatile interrupt_core0_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map;
volatile interrupt_core0_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map;

3
components/soc/esp32c5/include/soc/intpri_struct.h
View File

@ -100,7 +100,7 @@ typedef union {
} intpri_clock_gate_reg_t;
typedef struct {
typedef struct intpri_dev_t {
uint32_t reserved_000[36];
volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
@ -110,6 +110,7 @@ typedef struct {
volatile intpri_clock_gate_reg_t clock_gate;
} intpri_dev_t;
extern intpri_dev_t INTPRI;
#ifndef __cplusplus
_Static_assert(sizeof(intpri_dev_t) == 0xa8, "Invalid size of intpri_dev_t structure");

2
components/soc/esp32c5/include/soc/io_mux_struct.h
View File

@ -125,7 +125,7 @@ typedef union {
} io_mux_date_reg_t;
typedef struct {
typedef struct io_mux_dev_t {
volatile io_mux_pin_ctrl_reg_t pin_ctrl;
volatile io_mux_gpion_reg_t gpion[27];
uint32_t reserved_070[35];

3
components/soc/esp32c5/include/soc/keymng_struct.h
View File

@ -307,7 +307,7 @@ typedef union {
} keymng_date_reg_t;
typedef struct {
typedef struct keymng_dev_t {
uint32_t reserved_000;
volatile keymng_clk_reg_t clk;
volatile keymng_int_raw_reg_t int_raw;
@ -329,6 +329,7 @@ typedef struct {
volatile uint32_t sw_init_key[8];
} keymng_dev_t;
extern keymng_dev_t KEYMNG;
#ifndef __cplusplus
_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");

78
components/soc/esp32c5/include/soc/ledc_struct.h
View File

@ -1014,60 +1014,56 @@ typedef union {
uint32_t val;
} ledc_date_reg_t;
typedef struct {
volatile ledc_chn_conf0_reg_t conf0;
volatile ledc_chn_hpoint_reg_t hpoint;
volatile ledc_chn_duty_reg_t duty;
volatile ledc_chn_conf1_reg_t conf1;
volatile ledc_chn_duty_r_reg_t duty_rd;
} ledc_chn_reg_t;
typedef struct {
volatile ledc_chn_conf0_reg_t ch0_conf0;
volatile ledc_chn_hpoint_reg_t ch0_hpoint;
volatile ledc_chn_duty_reg_t ch0_duty;
volatile ledc_chn_conf1_reg_t ch0_conf1;
volatile ledc_chn_duty_r_reg_t ch0_duty_r;
volatile ledc_chn_conf0_reg_t ch1_conf0;
volatile ledc_chn_hpoint_reg_t ch1_hpoint;
volatile ledc_chn_duty_reg_t ch1_duty;
volatile ledc_chn_conf1_reg_t ch1_conf1;
volatile ledc_chn_duty_r_reg_t ch1_duty_r;
volatile ledc_chn_conf0_reg_t ch2_conf0;
volatile ledc_chn_hpoint_reg_t ch2_hpoint;
volatile ledc_chn_duty_reg_t ch2_duty;
volatile ledc_chn_conf1_reg_t ch2_conf1;
volatile ledc_chn_duty_r_reg_t ch2_duty_r;
volatile ledc_chn_conf0_reg_t ch3_conf0;
volatile ledc_chn_hpoint_reg_t ch3_hpoint;
volatile ledc_chn_duty_reg_t ch3_duty;
volatile ledc_chn_conf1_reg_t ch3_conf1;
volatile ledc_chn_duty_r_reg_t ch3_duty_r;
volatile ledc_chn_conf0_reg_t ch4_conf0;
volatile ledc_chn_hpoint_reg_t ch4_hpoint;
volatile ledc_chn_duty_reg_t ch4_duty;
volatile ledc_chn_conf1_reg_t ch4_conf1;
volatile ledc_chn_duty_r_reg_t ch4_duty_r;
volatile ledc_chn_conf0_reg_t ch5_conf0;
volatile ledc_chn_hpoint_reg_t ch5_hpoint;
volatile ledc_chn_duty_reg_t ch5_duty;
volatile ledc_chn_conf1_reg_t ch5_conf1;
volatile ledc_chn_duty_r_reg_t ch5_duty_r;
volatile ledc_chn_reg_t channel[6];
} ledc_ch_group_reg_t;
typedef struct {
volatile ledc_timern_conf_reg_t conf;
volatile ledc_timern_value_reg_t value;
} ledc_timerx_reg_t;
typedef struct {
volatile ledc_timerx_reg_t timer[4];
} ledc_timer_group_reg_t;
typedef struct {
volatile ledc_chn_gamma_conf_reg_t gamma_conf[6];
} ledc_ch_gamma_conf_group_reg_t;
typedef struct {
volatile ledc_timern_cmp_reg_t cmp[4];
} ledc_timer_cmp_group_reg_t;
typedef struct {
volatile ledc_timern_cnt_cap_reg_t cnt_cap[4];
} ledc_timer_cnt_cap_group_reg_t;
typedef struct ledc_dev_t {
volatile ledc_ch_group_reg_t channel_group[1];
uint32_t reserved_078[10];
volatile ledc_timern_conf_reg_t timer0_conf;
volatile ledc_timern_value_reg_t timer0_value;
volatile ledc_timern_conf_reg_t timer1_conf;
volatile ledc_timern_value_reg_t timer1_value;
volatile ledc_timern_conf_reg_t timer2_conf;
volatile ledc_timern_value_reg_t timer2_value;
volatile ledc_timern_conf_reg_t timer3_conf;
volatile ledc_timern_value_reg_t timer3_value;
volatile ledc_timer_group_reg_t timer_group[1];
volatile ledc_int_raw_reg_t int_raw;
volatile ledc_int_st_reg_t int_st;
volatile ledc_int_ena_reg_t int_ena;
volatile ledc_int_clr_reg_t int_clr;
uint32_t reserved_0d0[12];
volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[6];
volatile ledc_ch_gamma_conf_group_reg_t channel_gamma_conf_group[1];
uint32_t reserved_118[2];
volatile ledc_evt_task_en0_reg_t evt_task_en0;
volatile ledc_evt_task_en1_reg_t evt_task_en1;
volatile ledc_evt_task_en2_reg_t evt_task_en2;
uint32_t reserved_12c[5];
volatile ledc_timern_cmp_reg_t timern_cmp[4];
volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4];
volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1];
volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1];
uint32_t reserved_160[4];
volatile ledc_conf_reg_t conf;
volatile ledc_date_reg_t date;

2
components/soc/esp32c5/include/soc/lp_analog_peri_struct.h
View File

@ -224,7 +224,7 @@ typedef union {
} lp_ana_date_reg_t;
typedef struct {
typedef struct lp_ana_dev_t {
volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;

138
components/soc/esp32c5/include/soc/lp_aon_struct.h
View File

@ -11,135 +11,18 @@ extern "C" {
#endif
/** Group: configure_register */
/** Type of store0 register
/** Type of store n register
* need_des
*/
typedef union {
struct {
/** lp_aon_store0 : R/W; bitpos: [31:0]; default: 0;
/** lp_aon_store : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store0:32;
uint32_t lp_aon_store:32;
};
uint32_t val;
} lp_aon_store0_reg_t;
/** Type of store1 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store1:32;
};
uint32_t val;
} lp_aon_store1_reg_t;
/** Type of store2 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store2 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store2:32;
};
uint32_t val;
} lp_aon_store2_reg_t;
/** Type of store3 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store3 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store3:32;
};
uint32_t val;
} lp_aon_store3_reg_t;
/** Type of store4 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store4 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store4:32;
};
uint32_t val;
} lp_aon_store4_reg_t;
/** Type of store5 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store5 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store5:32;
};
uint32_t val;
} lp_aon_store5_reg_t;
/** Type of store6 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store6 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store6:32;
};
uint32_t val;
} lp_aon_store6_reg_t;
/** Type of store7 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store7 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store7:32;
};
uint32_t val;
} lp_aon_store7_reg_t;
/** Type of store8 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store8 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store8:32;
};
uint32_t val;
} lp_aon_store8_reg_t;
/** Type of store9 register
* need_des
*/
typedef union {
struct {
/** lp_aon_store9 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t lp_aon_store9:32;
};
uint32_t val;
} lp_aon_store9_reg_t;
} lp_aon_store_reg_t;
/** Type of gpio_mux register
* need_des
@ -449,17 +332,8 @@ typedef union {
} lp_aon_sprf_ctrl_reg_t;
typedef struct {
volatile lp_aon_store0_reg_t store0;
volatile lp_aon_store1_reg_t store1;
volatile lp_aon_store2_reg_t store2;
volatile lp_aon_store3_reg_t store3;
volatile lp_aon_store4_reg_t store4;
volatile lp_aon_store5_reg_t store5;
volatile lp_aon_store6_reg_t store6;
volatile lp_aon_store7_reg_t store7;
volatile lp_aon_store8_reg_t store8;
volatile lp_aon_store9_reg_t store9;
typedef struct lp_aon_dev_t {
volatile lp_aon_store_reg_t store[10];
volatile lp_aon_gpio_mux_reg_t gpio_mux;
volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
volatile lp_aon_gpio_hold1_reg_t gpio_hold1;

3
components/soc/esp32c5/include/soc/lp_apm0_struct.h
View File

@ -478,7 +478,7 @@ typedef union {
} lp_apm0_date_reg_t;
typedef struct {
typedef struct lp_apm0_dev_t {
volatile lp_apm0_region_filter_en_reg_t region_filter_en;
volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
@ -504,6 +504,7 @@ typedef struct {
volatile lp_apm0_date_reg_t date;
} lp_apm0_dev_t;
extern lp_apm0_dev_t LP_APM0;
#ifndef __cplusplus
_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");

2
components/soc/esp32c5/include/soc/lp_apm_struct.h
View File

@ -558,7 +558,7 @@ typedef union {
} lp_apm_date_reg_t;
typedef struct {
typedef struct lp_apm_dev_t {
volatile lp_apm_region_filter_en_reg_t region_filter_en;
volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
volatile lp_apm_region0_addr_end_reg_t region0_addr_end;

2
components/soc/esp32c5/include/soc/lp_clkrst_struct.h
View File

@ -326,7 +326,7 @@ typedef union {
} lp_clkrst_date_reg_t;
typedef struct {
typedef struct lp_clkrst_dev_t {
volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;

2
components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
View File

@ -128,7 +128,7 @@ typedef union {
} lp_i2c_ana_mst_date_reg_t;
typedef struct {
typedef struct lp_i2c_ana_mst_dev_t {
volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;

175
components/soc/esp32c5/include/soc/lp_i2c_struct.h
View File

@ -843,12 +843,12 @@ typedef union {
/** Group: Command registers */
/** Type of comd0 register
* I2C command register 0
/** Type of comd register
* I2C command register n
*/
typedef union {
struct {
/** command0 : R/W; bitpos: [13:0]; default: 0;
/** command : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. It consists of three parts:
* op_code is the command,
* 0: RSTART,
@ -861,166 +861,18 @@ typedef union {
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure for more information.
*/
uint32_t command0:14;
uint32_t command:14;
uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.
/** command_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command n is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command0_done:1;
uint32_t command_done:1;
};
uint32_t val;
} lp_i2c_comd0_reg_t;
/** Type of comd1 register
* I2C command register 1
*/
typedef union {
struct {
/** command1 : R/W; bitpos: [13:0]; default: 0;
* Configures command 1. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command1:14;
uint32_t reserved_14:17;
/** command1_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 1 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command1_done:1;
};
uint32_t val;
} lp_i2c_comd1_reg_t;
/** Type of comd2 register
* I2C command register 2
*/
typedef union {
struct {
/** command2 : R/W; bitpos: [13:0]; default: 0;
* Configures command 2. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command2:14;
uint32_t reserved_14:17;
/** command2_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 2 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command2_done:1;
};
uint32_t val;
} lp_i2c_comd2_reg_t;
/** Type of comd3 register
* I2C command register 3
*/
typedef union {
struct {
/** command3 : R/W; bitpos: [13:0]; default: 0;
* Configures command 3. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command3:14;
uint32_t reserved_14:17;
/** command3_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 3 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command3_done:1;
};
uint32_t val;
} lp_i2c_comd3_reg_t;
/** Type of comd4 register
* I2C command register 4
*/
typedef union {
struct {
/** command4 : R/W; bitpos: [13:0]; default: 0;
* Configures command 4. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command4:14;
uint32_t reserved_14:17;
/** command4_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 4 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command4_done:1;
};
uint32_t val;
} lp_i2c_comd4_reg_t;
/** Type of comd5 register
* I2C command register 5
*/
typedef union {
struct {
/** command5 : R/W; bitpos: [13:0]; default: 0;
* Configures command 5. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command5:14;
uint32_t reserved_14:17;
/** command5_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 5 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command5_done:1;
};
uint32_t val;
} lp_i2c_comd5_reg_t;
/** Type of comd6 register
* I2C command register 6
*/
typedef union {
struct {
/** command6 : R/W; bitpos: [13:0]; default: 0;
* Configures command 6. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command6:14;
uint32_t reserved_14:17;
/** command6_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 6 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command6_done:1;
};
uint32_t val;
} lp_i2c_comd6_reg_t;
/** Type of comd7 register
* I2C command register 7
*/
typedef union {
struct {
/** command7 : R/W; bitpos: [13:0]; default: 0;
* Configures command 7. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command7:14;
uint32_t reserved_14:17;
/** command7_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 7 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command7_done:1;
};
uint32_t val;
} lp_i2c_comd7_reg_t;
} lp_i2c_comd_reg_t;
/** Group: Version register */
/** Type of date register
@ -1065,7 +917,7 @@ typedef union {
} lp_i2c_rxfifo_start_addr_reg_t;
typedef struct {
typedef struct lp_i2c_dev_t {
volatile lp_i2c_scl_low_period_reg_t scl_low_period;
volatile lp_i2c_ctr_reg_t ctr;
volatile lp_i2c_sr_reg_t sr;
@ -1088,14 +940,7 @@ typedef struct {
volatile lp_i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile lp_i2c_filter_cfg_reg_t filter_cfg;
volatile lp_i2c_clk_conf_reg_t clk_conf;
volatile lp_i2c_comd0_reg_t comd0;
volatile lp_i2c_comd1_reg_t comd1;
volatile lp_i2c_comd2_reg_t comd2;
volatile lp_i2c_comd3_reg_t comd3;
volatile lp_i2c_comd4_reg_t comd4;
volatile lp_i2c_comd5_reg_t comd5;
volatile lp_i2c_comd6_reg_t comd6;
volatile lp_i2c_comd7_reg_t comd7;
volatile lp_i2c_comd_reg_t comd[8];
volatile lp_i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile lp_i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile lp_i2c_scl_sp_conf_reg_t scl_sp_conf;

341
components/soc/esp32c5/include/soc/lp_io_struct.h
View File

@ -151,339 +151,94 @@ typedef union {
uint32_t val;
} lp_io_in_reg_t;
/** Type of pin0 register
/** Type of pin n register
* need des
*/
typedef union {
struct {
/** lp_gpio0_sync_bypass : R/W; bitpos: [1:0]; default: 0;
/** lp_gpio_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio0_sync_bypass:2;
/** lp_gpio0_pad_driver : R/W; bitpos: [2]; default: 0;
uint32_t lp_gpio_sync_bypass:2;
/** lp_gpio_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio0_pad_driver:1;
/** lp_gpio0_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
uint32_t lp_gpio_pad_driver:1;
/** lp_gpio_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio0_edge_wakeup_clr:1;
uint32_t lp_gpio_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio0_int_type : R/W; bitpos: [9:7]; default: 0;
/** lp_gpio_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio0_int_type:3;
/** lp_gpio0_wakeup_enable : R/W; bitpos: [10]; default: 0;
uint32_t lp_gpio_int_type:3;
/** lp_gpio_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio0_wakeup_enable:1;
/** lp_gpio0_filter_en : R/W; bitpos: [11]; default: 0;
uint32_t lp_gpio_wakeup_enable:1;
/** lp_gpio_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio0_filter_en:1;
uint32_t lp_gpio_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin0_reg_t;
} lp_io_pin_reg_t;
/** Type of pin1 register
/** Type of gpio n register
* need des
*/
typedef union {
struct {
/** lp_gpio1_sync_bypass : R/W; bitpos: [1:0]; default: 0;
/** lp_gpio_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio1_sync_bypass:2;
/** lp_gpio1_pad_driver : R/W; bitpos: [2]; default: 0;
uint32_t lp_gpio_mcu_oe:1;
/** lp_gpio_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio1_pad_driver:1;
/** lp_gpio1_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
uint32_t lp_gpio_slp_sel:1;
/** lp_gpio_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio1_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio1_int_type : R/W; bitpos: [9:7]; default: 0;
uint32_t lp_gpio_mcu_wpd:1;
/** lp_gpio_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio1_int_type:3;
/** lp_gpio1_wakeup_enable : R/W; bitpos: [10]; default: 0;
uint32_t lp_gpio_mcu_wpu:1;
/** lp_gpio_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio1_wakeup_enable:1;
/** lp_gpio1_filter_en : R/W; bitpos: [11]; default: 0;
uint32_t lp_gpio_mcu_ie:1;
/** lp_gpio_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio1_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin1_reg_t;
/** Type of pin2 register
* need des
*/
typedef union {
struct {
/** lp_gpio2_sync_bypass : R/W; bitpos: [1:0]; default: 0;
uint32_t lp_gpio_mcu_drv:2;
/** lp_gpio_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio2_sync_bypass:2;
/** lp_gpio2_pad_driver : R/W; bitpos: [2]; default: 0;
uint32_t lp_gpio_fun_wpd:1;
/** lp_gpio_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio2_pad_driver:1;
/** lp_gpio2_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
uint32_t lp_gpio_fun_wpu:1;
/** lp_gpio_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio2_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio2_int_type : R/W; bitpos: [9:7]; default: 0;
uint32_t lp_gpio_fun_ie:1;
/** lp_gpio_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio2_int_type:3;
/** lp_gpio2_wakeup_enable : R/W; bitpos: [10]; default: 0;
uint32_t lp_gpio_fun_drv:2;
/** lp_gpio_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio2_wakeup_enable:1;
/** lp_gpio2_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio2_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin2_reg_t;
/** Type of pin3 register
* need des
*/
typedef union {
struct {
/** lp_gpio3_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio3_sync_bypass:2;
/** lp_gpio3_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio3_pad_driver:1;
/** lp_gpio3_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio3_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio3_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio3_int_type:3;
/** lp_gpio3_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio3_wakeup_enable:1;
/** lp_gpio3_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio3_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin3_reg_t;
/** Type of pin4 register
* need des
*/
typedef union {
struct {
/** lp_gpio4_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio4_sync_bypass:2;
/** lp_gpio4_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio4_pad_driver:1;
/** lp_gpio4_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio4_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio4_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio4_int_type:3;
/** lp_gpio4_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio4_wakeup_enable:1;
/** lp_gpio4_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio4_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin4_reg_t;
/** Type of pin5 register
* need des
*/
typedef union {
struct {
/** lp_gpio5_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio5_sync_bypass:2;
/** lp_gpio5_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio5_pad_driver:1;
/** lp_gpio5_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio5_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio5_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio5_int_type:3;
/** lp_gpio5_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio5_wakeup_enable:1;
/** lp_gpio5_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio5_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin5_reg_t;
/** Type of pin6 register
* need des
*/
typedef union {
struct {
/** lp_gpio6_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio6_sync_bypass:2;
/** lp_gpio6_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio6_pad_driver:1;
/** lp_gpio6_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio6_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio6_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio6_int_type:3;
/** lp_gpio6_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio6_wakeup_enable:1;
/** lp_gpio6_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio6_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin6_reg_t;
/** Type of pin7 register
* need des
*/
typedef union {
struct {
/** lp_gpio7_sync_bypass : R/W; bitpos: [1:0]; default: 0;
* need des
*/
uint32_t lp_gpio7_sync_bypass:2;
/** lp_gpio7_pad_driver : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio7_pad_driver:1;
/** lp_gpio7_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio7_edge_wakeup_clr:1;
uint32_t reserved_4:3;
/** lp_gpio7_int_type : R/W; bitpos: [9:7]; default: 0;
* need des
*/
uint32_t lp_gpio7_int_type:3;
/** lp_gpio7_wakeup_enable : R/W; bitpos: [10]; default: 0;
* need des
*/
uint32_t lp_gpio7_wakeup_enable:1;
/** lp_gpio7_filter_en : R/W; bitpos: [11]; default: 0;
* need des
*/
uint32_t lp_gpio7_filter_en:1;
uint32_t reserved_12:20;
};
uint32_t val;
} lp_io_pin7_reg_t;
/** Type of gpio0 register
* need des
*/
typedef union {
struct {
/** lp_gpio0_mcu_oe : R/W; bitpos: [0]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_oe:1;
/** lp_gpio0_slp_sel : R/W; bitpos: [1]; default: 0;
* need des
*/
uint32_t lp_gpio0_slp_sel:1;
/** lp_gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_wpd:1;
/** lp_gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_wpu:1;
/** lp_gpio0_mcu_ie : R/W; bitpos: [4]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_ie:1;
/** lp_gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_drv:2;
/** lp_gpio0_fun_wpd : R/W; bitpos: [7]; default: 0;
* need des
*/
uint32_t lp_gpio0_fun_wpd:1;
/** lp_gpio0_fun_wpu : R/W; bitpos: [8]; default: 0;
* need des
*/
uint32_t lp_gpio0_fun_wpu:1;
/** lp_gpio0_fun_ie : R/W; bitpos: [9]; default: 0;
* need des
*/
uint32_t lp_gpio0_fun_ie:1;
/** lp_gpio0_fun_drv : R/W; bitpos: [11:10]; default: 0;
* need des
*/
uint32_t lp_gpio0_fun_drv:2;
/** lp_gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0;
* need des
*/
uint32_t lp_gpio0_mcu_sel:3;
uint32_t lp_gpio_mcu_sel:3;
uint32_t reserved_15:17;
};
uint32_t val;
} lp_io_gpio0_reg_t;
} lp_io_gpio_reg_t;
/** Type of gpio1 register
* need des
@ -953,7 +708,7 @@ typedef union {
} lp_io_date_reg_t;
typedef struct {
typedef struct lp_io_dev_t {
volatile lp_io_out_data_reg_t out_data;
volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
@ -964,22 +719,8 @@ typedef struct {
volatile lp_io_status_w1ts_reg_t status_w1ts;
volatile lp_io_status_w1tc_reg_t status_w1tc;
volatile lp_io_in_reg_t in;
volatile lp_io_pin0_reg_t pin0;
volatile lp_io_pin1_reg_t pin1;
volatile lp_io_pin2_reg_t pin2;
volatile lp_io_pin3_reg_t pin3;
volatile lp_io_pin4_reg_t pin4;
volatile lp_io_pin5_reg_t pin5;
volatile lp_io_pin6_reg_t pin6;
volatile lp_io_pin7_reg_t pin7;
volatile lp_io_gpio0_reg_t gpio0;
volatile lp_io_gpio1_reg_t gpio1;
volatile lp_io_gpio2_reg_t gpio2;
volatile lp_io_gpio3_reg_t gpio3;
volatile lp_io_gpio4_reg_t gpio4;
volatile lp_io_gpio5_reg_t gpio5;
volatile lp_io_gpio6_reg_t gpio6;
volatile lp_io_gpio7_reg_t gpio7;
volatile lp_io_pin_reg_t pin[8];
volatile lp_io_gpio_reg_t gpio[8];
volatile lp_io_status_interrupt_reg_t status_interrupt;
volatile lp_io_debug_sel0_reg_t debug_sel0;
volatile lp_io_debug_sel1_reg_t debug_sel1;

3
components/soc/esp32c5/include/soc/lp_tee_struct.h
View File

@ -79,7 +79,7 @@ typedef union {
} lp_tee_date_reg_t;
typedef struct {
typedef struct lp_tee_dev_t {
volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile lp_tee_clock_gate_reg_t clock_gate;
uint32_t reserved_008[34];
@ -88,6 +88,7 @@ typedef struct {
volatile lp_tee_date_reg_t date;
} lp_tee_dev_t;
extern lp_tee_dev_t LP_TEE;
#ifndef __cplusplus
_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");

87
components/soc/esp32c5/include/soc/lp_timer_struct.h
View File

@ -11,67 +11,36 @@ extern "C" {
#endif
/** Group: configure_register */
/** Type of tar0_low register
/** Type of tar_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
/** main_timer_tar_low : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low0:32;
uint32_t main_timer_tar_low:32;
};
uint32_t val;
} lp_timer_tar0_low_reg_t;
} lp_timer_tar_low_reg_t;
/** Type of tar0_high register
/** Type of tar_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
/** main_timer_tar_high : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high0:16;
uint32_t main_timer_tar_high:16;
uint32_t reserved_16:15;
/** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
/** main_timer_tar_en : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en0:1;
uint32_t main_timer_tar_en:1;
};
uint32_t val;
} lp_timer_tar0_high_reg_t;
/** Type of tar1_low register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_low1:32;
};
uint32_t val;
} lp_timer_tar1_low_reg_t;
/** Type of tar1_high register
* need_des
*/
typedef union {
struct {
/** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_tar_high1:16;
uint32_t reserved_16:15;
/** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t main_timer_tar_en1:1;
};
uint32_t val;
} lp_timer_tar1_high_reg_t;
} lp_timer_tar_high_reg_t;
/** Type of update register
* need_des
@ -99,32 +68,32 @@ typedef union {
uint32_t val;
} lp_timer_update_reg_t;
/** Type of main_buf0_low register
/** Type of main_buf_low register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
/** main_timer_buf_low : RO; bitpos: [31:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_low:32;
uint32_t main_timer_buf_low:32;
};
uint32_t val;
} lp_timer_main_buf0_low_reg_t;
} lp_timer_main_buf_low_reg_t;
/** Type of main_buf0_high register
/** Type of main_buf_high register
* need_des
*/
typedef union {
struct {
/** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
/** main_timer_buf_high : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t main_timer_buf0_high:16;
uint32_t main_timer_buf_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf0_high_reg_t;
} lp_timer_main_buf_high_reg_t;
/** Type of main_buf1_low register
* need_des
@ -328,18 +297,20 @@ typedef union {
uint32_t val;
} lp_timer_date_reg_t;
typedef struct {
volatile lp_timer_tar_low_reg_t lo;
volatile lp_timer_tar_high_reg_t hi;
} lp_timer_target_reg_t;
typedef struct {
volatile lp_timer_tar0_low_reg_t tar0_low;
volatile lp_timer_tar0_high_reg_t tar0_high;
volatile lp_timer_tar1_low_reg_t tar1_low;
volatile lp_timer_tar1_high_reg_t tar1_high;
volatile lp_timer_main_buf_low_reg_t lo;
volatile lp_timer_main_buf_high_reg_t hi;
} lp_timer_counter_reg_t;
typedef struct lp_timer_dev_t {
volatile lp_timer_target_reg_t target[2];
volatile lp_timer_update_reg_t update;
volatile lp_timer_main_buf0_low_reg_t main_buf0_low;
volatile lp_timer_main_buf0_high_reg_t main_buf0_high;
volatile lp_timer_main_buf1_low_reg_t main_buf1_low;
volatile lp_timer_main_buf1_high_reg_t main_buf1_high;
volatile lp_timer_main_overflow_reg_t main_overflow;
volatile lp_timer_counter_reg_t counter[2];
volatile lp_timer_int_raw_reg_t int_raw;
volatile lp_timer_int_st_reg_t int_st;
volatile lp_timer_int_ena_reg_t int_ena;

2
components/soc/esp32c5/include/soc/lp_uart_struct.h
View File

@ -1077,7 +1077,7 @@ typedef union {
} lp_uart_id_reg_t;
typedef struct {
typedef struct lp_uart_dev_t {
volatile lp_uart_fifo_reg_t fifo;
volatile lp_uart_int_raw_reg_t int_raw;
volatile lp_uart_int_st_reg_t int_st;

3
components/soc/esp32c5/include/soc/lp_wdt_struct.h
View File

@ -281,7 +281,7 @@ typedef union {
} lp_wdt_date_reg_t;
typedef struct {
typedef struct lp_wdt_dev_t {
volatile lp_wdt_config0_reg_t config0;
volatile lp_wdt_config1_reg_t config1;
volatile lp_wdt_config2_reg_t config2;
@ -299,6 +299,7 @@ typedef struct {
volatile lp_wdt_date_reg_t date;
} lp_wdt_dev_t;
extern lp_wdt_dev_t LP_WDT;
#ifndef __cplusplus
_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");

2
components/soc/esp32c5/include/soc/lpperi_struct.h
View File

@ -263,7 +263,7 @@ typedef union {
} lpperi_date_reg_t;
typedef struct {
typedef struct lpperi_dev_t {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_reset_en_reg_t reset_en;
volatile lpperi_rng_data_reg_t rng_data;

2
components/soc/esp32c5/include/soc/mcpwm_struct.h
View File

@ -1938,7 +1938,7 @@ typedef union {
} mcpwm_version_reg_t;
typedef struct {
typedef struct mcpwm_dev_t {
volatile mcpwm_clk_cfg_reg_t clk_cfg;
volatile mcpwm_timern_cfg0_reg_t timer0_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer0_cfg1;

2
components/soc/esp32c5/include/soc/mem_monitor_struct.h
View File

@ -193,7 +193,7 @@ typedef union {
} mem_monitor_date_reg_t;
typedef struct {
typedef struct mem_monitor_dev_t {
volatile mem_monitor_log_setting_reg_t log_setting;
volatile mem_monitor_log_check_data_reg_t log_check_data;
volatile mem_monitor_log_data_mask_reg_t log_data_mask;

2
components/soc/esp32c5/include/soc/otp_debug_struct.h
View File

@ -1991,7 +1991,7 @@ typedef union {
} otp_debug_date_reg_t;
typedef struct {
typedef struct otp_debug_dev_t {
volatile otp_debug_wr_dis_reg_t wr_dis;
volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1;
volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2;

2
components/soc/esp32c5/include/soc/parl_io_struct.h
View File

@ -472,7 +472,7 @@ typedef union {
} parl_io_version_reg_t;
typedef struct {
typedef struct parl_io_dev_t {
volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;

2
components/soc/esp32c5/include/soc/pau_struct.h
View File

@ -307,7 +307,7 @@ typedef union {
} pau_date_reg_t;
typedef struct {
typedef struct pau_dev_t {
volatile pau_regdma_conf_reg_t regdma_conf;
volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;

88
components/soc/esp32c5/include/soc/pcnt_struct.h
View File

@ -213,74 +213,22 @@ typedef union {
uint32_t val;
} pcnt_ctrl_reg_t;
/** Type of u3_change_conf register
/** Type of change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0;
/** cnt_step : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 3.
*/
uint32_t cnt_step_u3:16;
/** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0;
uint32_t cnt_step:16;
/** cnt_step_lim : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 3.
*/
uint32_t cnt_step_lim_u3:16;
uint32_t cnt_step_lim:16;
};
uint32_t val;
} pcnt_u3_change_conf_reg_t;
/** Type of u2_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 2.
*/
uint32_t cnt_step_u2:16;
/** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 2.
*/
uint32_t cnt_step_lim_u2:16;
};
uint32_t val;
} pcnt_u2_change_conf_reg_t;
/** Type of u1_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 1.
*/
uint32_t cnt_step_u1:16;
/** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 1.
*/
uint32_t cnt_step_lim_u1:16;
};
uint32_t val;
} pcnt_u1_change_conf_reg_t;
/** Type of u0_change_conf register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0;
* Configures the step value for unit 0.
*/
uint32_t cnt_step_u0:16;
/** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0;
* Configures the step limit value for unit 0.
*/
uint32_t cnt_step_lim_u0:16;
};
uint32_t val;
} pcnt_u0_change_conf_reg_t;
} pcnt_un_change_conf_reg_t;
/** Group: Status Register */
/** Type of un_cnt register
@ -465,19 +413,12 @@ typedef union {
} pcnt_date_reg_t;
typedef struct {
volatile pcnt_un_conf0_reg_t u0_conf0;
volatile pcnt_un_conf1_reg_t u0_conf1;
volatile pcnt_un_conf2_reg_t u0_conf2;
volatile pcnt_un_conf0_reg_t u1_conf0;
volatile pcnt_un_conf1_reg_t u1_conf1;
volatile pcnt_un_conf2_reg_t u1_conf2;
volatile pcnt_un_conf0_reg_t u2_conf0;
volatile pcnt_un_conf1_reg_t u2_conf1;
volatile pcnt_un_conf2_reg_t u2_conf2;
volatile pcnt_un_conf0_reg_t u3_conf0;
volatile pcnt_un_conf1_reg_t u3_conf1;
volatile pcnt_un_conf2_reg_t u3_conf2;
typedef struct pcnt_dev_t {
volatile struct {
pcnt_un_conf0_reg_t conf0;
pcnt_un_conf1_reg_t conf1;
pcnt_un_conf2_reg_t conf2;
} conf_unit[4];
volatile pcnt_un_cnt_reg_t un_cnt[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
@ -485,10 +426,7 @@ typedef struct {
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t un_status[4];
volatile pcnt_ctrl_reg_t ctrl;
volatile pcnt_u3_change_conf_reg_t u3_change_conf;
volatile pcnt_u2_change_conf_reg_t u2_change_conf;
volatile pcnt_u1_change_conf_reg_t u1_change_conf;
volatile pcnt_u0_change_conf_reg_t u0_change_conf;
volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210
uint32_t reserved_074[34];
volatile pcnt_date_reg_t date;
} pcnt_dev_t;

2
components/soc/esp32c5/include/soc/pcr_struct.h
View File

@ -2125,7 +2125,7 @@ typedef union {
} pcr_date_reg_t;
typedef struct {
typedef struct pcr_dev_t {
volatile pcr_uart0_conf_reg_t uart0_conf;
volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf;
volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl;

2
components/soc/esp32c5/include/soc/pmu_struct.h
View File

@ -2666,7 +2666,7 @@ typedef union {
} pmu_vdd_spi_status_reg_t;
typedef struct {
typedef struct pmu_dev_t {
volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power;
volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func;
volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb;

101
components/soc/esp32c5/include/soc/reg_base.h Normal file
View File

@ -0,0 +1,101 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Peripheral 0 Modules
*
*/
#define DR_REG_UART0_BASE 0x60000000
#define DR_REG_UART1_BASE 0x60001000
#define DR_REG_SPIMEM0_BASE 0x60002000
#define DR_REG_SPIMEM1_BASE 0x60003000
#define DR_REG_I2C0_BASE 0x60004000
#define DR_REG_UHCI0_BASE 0x60005000
#define DR_REG_RMT_BASE 0x60006000
#define DR_REG_LEDC_BASE 0x60007000
#define DR_REG_TIMERG0_BASE 0x60008000
#define DR_REG_TIMERG1_BASE 0x60009000
#define DR_REG_SYSTIMER_BASE 0x6000A000
#define DR_REG_TWAI0_BASE 0x6000B000
#define DR_REG_I2S_BASE 0x6000C000
#define DR_REG_TWAI1_BASE 0x6000D000
#define DR_REG_APB_SARADC_BASE 0x6000E000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
#define DR_REG_INTMTX_BASE 0x60010000
#define DR_REG_I2C1_BASE 0x60011000
#define DR_REG_PCNT_BASE 0x60012000
#define DR_REG_SOC_ETM_BASE 0x60013000
#define DR_REG_MCPWM_BASE 0x60014000
#define DR_REG_PARL_IO_BASE 0x60015000
#define DR_REG_PVT_MONITOR_BASE 0x60019000
/**
* @brief Peripheral 1 Modules
*
*/
#define DR_REG_GDMA_BASE 0x60080000
#define DR_REG_GPSPI2_BASE 0x60081000
#define DR_REG_BITSCRAMBLER_BASE 0x60082000
#define DR_REG_KEYMNG_BASE 0x60087000
#define DR_REG_AES_BASE 0x60088000
#define DR_REG_SHA_BASE 0x60089000
#define DR_REG_RSA_BASE 0x6008A000
#define DR_REG_ECC_BASE 0x6008B000
#define DR_REG_DS_BASE 0x6008C000
#define DR_REG_HMAC_BASE 0x6008D000
#define DR_REG_ECDSA_BASE 0x6008E000
/**
* @brief HP Top Peripheral Modules
*
*/
#define DR_REG_IO_MUX_BASE 0x60090000
#define DR_REG_GPIO_BASE 0x60091000
#define DR_REG_MEM_MONITOR_BASE 0x60092000
#define DR_REG_PAU_BASE 0x60093000
#define DR_REG_HP_SYSTEM_BASE 0x60095000
#define DR_REG_PCR_BASE 0x60096000
#define DR_REG_TEE_BASE 0x60098000
#define DR_REG_HP_APM_BASE 0x60099000
#define DR_REG_LP_APM0_BASE 0x60099800
#define DR_REG_MISC_BASE 0x6009F000
/**
* @brief Modem Module
*
*/
#define DR_REG_MODEM_BASE 0x600A4000
#define DR_REG_MODEM_PWR_BASE 0x600AD000
/**
* @brief LP System (RTC) Modules
*
*/
#define DR_REG_PMU_BASE 0x600B0000
#define DR_REG_LP_CLKRST_BASE 0x600B0400
#define DR_REG_EFUSE_BASE 0x600B0800
#define DR_REG_LP_TIMER_BASE 0x600B0C00
#define DR_REG_LP_AON_BASE 0x600B1000
#define DR_REG_LP_UART_BASE 0x600B1400
#define DR_REG_LP_I2C_BASE 0x600B1800
#define DR_REG_LP_WDT_BASE 0x600B1C00
#define DR_REG_LP_IO_BASE 0x600B2000
#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400
#define DR_REG_LPPERI_BASE 0x600B2800
#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00
#define DR_REG_HUK_BASE 0x600B3000
#define DR_REG_LP_TEE_BASE 0x600B3400
#define DR_REG_LP_APM_BASE 0x600B3800
#define DR_REG_OTP_DEBUG_BASE 0x600B3C00
/**
* @brief CPU Peripheral Modules
*
*/
#define DR_REG_TRACE_BASE 0x600C0000
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_CACHE_BASE 0x600C8000

26
components/soc/esp32c5/include/soc/rmt_struct.h
View File

@ -24,6 +24,19 @@ typedef union {
uint32_t val;
} rmt_chndata_reg_t;
/** Type of chmdata register
* The read and write data register for CHANNELn by apb fifo access.
*/
typedef union {
struct {
/** chmdata : HRO; bitpos: [31:0]; default: 0;
* Read and write data for channel n via APB FIFO.
*/
uint32_t chmdata:32;
};
uint32_t val;
} rmt_chmdata_reg_t;
/** Group: Configuration registers */
/** Type of chnconf0 register
@ -753,13 +766,14 @@ typedef union {
} rmt_date_reg_t;
typedef struct {
volatile rmt_chndata_reg_t chndata[4];
typedef struct rmt_dev_t {
volatile rmt_chndata_reg_t chndata[2];
volatile rmt_chmdata_reg_t chmdata[2];
volatile rmt_chnconf0_reg_t chnconf0[2];
volatile rmt_chmconf0_reg_t ch2conf0;
volatile rmt_chmconf1_reg_t ch2conf1;
volatile rmt_chmconf0_reg_t ch3conf0;
volatile rmt_chmconf1_reg_t ch3conf1;
volatile struct {
rmt_chmconf0_reg_t conf0;
rmt_chmconf1_reg_t conf1;
} chmconf[2];;
volatile rmt_chnstatus_reg_t chnstatus[2];
volatile rmt_chmstatus_reg_t chmstatus[2];
volatile rmt_int_raw_reg_t int_raw;

2
components/soc/esp32c5/include/soc/rsa_struct.h
View File

@ -238,7 +238,7 @@ typedef union {
} rsa_date_reg_t;
typedef struct {
typedef struct rsa_dev_t {
volatile uint32_t m[4];
uint32_t reserved_010[124];
volatile uint32_t z[4];

576
components/soc/esp32c5/include/soc/sdio_hinf_reg.h
View File

@ -1,576 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HINF_CFG_DATA0_REG register
* Configure sdio cis content
*/
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
#define HINF_DEVICE_ID_FN1 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN1_S 0
/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
#define HINF_USER_ID_FN1 0x0000FFFFU
#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
#define HINF_USER_ID_FN1_V 0x0000FFFFU
#define HINF_USER_ID_FN1_S 16
/** HINF_CFG_DATA1_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
#define HINF_SDIO_ENABLE (BIT(0))
#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
#define HINF_SDIO_ENABLE_V 0x00000001U
#define HINF_SDIO_ENABLE_S 0
/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY1 (BIT(1))
#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
#define HINF_SDIO_IOREADY1_V 0x00000001U
#define HINF_SDIO_IOREADY1_S 1
/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
#define HINF_HIGHSPEED_ENABLE (BIT(2))
#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
#define HINF_HIGHSPEED_ENABLE_V 0x00000001U
#define HINF_HIGHSPEED_ENABLE_S 2
/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
#define HINF_HIGHSPEED_MODE (BIT(3))
#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
#define HINF_HIGHSPEED_MODE_V 0x00000001U
#define HINF_HIGHSPEED_MODE_S 3
/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
#define HINF_SDIO_CD_ENABLE (BIT(4))
#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
#define HINF_SDIO_CD_ENABLE_V 0x00000001U
#define HINF_SDIO_CD_ENABLE_S 4
/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
#define HINF_SDIO_IOREADY2 (BIT(5))
#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
#define HINF_SDIO_IOREADY2_V 0x00000001U
#define HINF_SDIO_IOREADY2_S 5
/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
#define HINF_SDIO_INT_MASK (BIT(6))
#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
#define HINF_SDIO_INT_MASK_V 0x00000001U
#define HINF_SDIO_INT_MASK_S 6
/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
#define HINF_IOENABLE2 (BIT(7))
#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
#define HINF_IOENABLE2_V 0x00000001U
#define HINF_IOENABLE2_S 7
/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
#define HINF_CD_DISABLE (BIT(8))
#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
#define HINF_CD_DISABLE_V 0x00000001U
#define HINF_CD_DISABLE_S 8
/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
#define HINF_FUNC1_EPS (BIT(9))
#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
#define HINF_FUNC1_EPS_V 0x00000001U
#define HINF_FUNC1_EPS_S 9
/** HINF_EMP : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
#define HINF_EMP (BIT(10))
#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S)
#define HINF_EMP_V 0x00000001U
#define HINF_EMP_S 10
/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
#define HINF_IOENABLE1 (BIT(11))
#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
#define HINF_IOENABLE1_V 0x00000001U
#define HINF_IOENABLE1_S 11
/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
#define HINF_SDIO_VER 0x00000FFFU
#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
#define HINF_SDIO_VER_V 0x00000FFFU
#define HINF_SDIO_VER_S 12
/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
#define HINF_FUNC2_EPS (BIT(24))
#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
#define HINF_FUNC2_EPS_V 0x00000001U
#define HINF_FUNC2_EPS_S 24
/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
#define HINF_SDIO20_CONF 0x0000007FU
#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
#define HINF_SDIO20_CONF_V 0x0000007FU
#define HINF_SDIO20_CONF_S 25
/** HINF_CFG_TIMING_REG register
* Timing configuration registers
*/
#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
#define HINF_NCRC 0x00000007U
#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S)
#define HINF_NCRC_V 0x00000007U
#define HINF_NCRC_S 0
/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU
#define HINF_PST_END_CMD_LOW_VALUE_S 3
/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU
#define HINF_PST_END_DATA_LOW_VALUE_S 10
/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
#define HINF_SDCLK_STOP_THRES 0x000007FFU
#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
#define HINF_SDCLK_STOP_THRES_V 0x000007FFU
#define HINF_SDCLK_STOP_THRES_S 16
/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU
#define HINF_SAMPLE_CLK_DIVIDER_S 28
/** HINF_CFG_UPDATE_REG register
* update sdio configurations
*/
#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
#define HINF_CONF_UPDATE (BIT(0))
#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
#define HINF_CONF_UPDATE_V 0x00000001U
#define HINF_CONF_UPDATE_S 0
/** HINF_CFG_DATA7_REG register
* SDIO configuration register
*/
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
#define HINF_PIN_STATE 0x000000FFU
#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
#define HINF_PIN_STATE_V 0x000000FFU
#define HINF_PIN_STATE_S 0
/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
#define HINF_CHIP_STATE 0x000000FFU
#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
#define HINF_CHIP_STATE_V 0x000000FFU
#define HINF_CHIP_STATE_S 8
/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
#define HINF_SDIO_RST (BIT(16))
#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
#define HINF_SDIO_RST_V 0x00000001U
#define HINF_SDIO_RST_S 16
/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
#define HINF_SDIO_IOREADY0 (BIT(17))
#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
#define HINF_SDIO_IOREADY0_V 0x00000001U
#define HINF_SDIO_IOREADY0_S 17
/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
#define HINF_SDIO_MEM_PD (BIT(18))
#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
#define HINF_SDIO_MEM_PD_V 0x00000001U
#define HINF_SDIO_MEM_PD_S 18
/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
#define HINF_ESDIO_DATA1_INT_EN (BIT(19))
#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U
#define HINF_ESDIO_DATA1_INT_EN_S 19
/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20))
#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_SW_S 20
/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21))
#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U
#define HINF_DDR50_BLK_LEN_FIX_EN_S 21
/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
#define HINF_CLK_EN (BIT(22))
#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S)
#define HINF_CLK_EN_V 0x00000001U
#define HINF_CLK_EN_S 22
/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
#define HINF_SDDR50 (BIT(23))
#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S)
#define HINF_SDDR50_V 0x00000001U
#define HINF_SDDR50_S 23
/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
#define HINF_SSDR104 (BIT(24))
#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S)
#define HINF_SSDR104_V 0x00000001U
#define HINF_SSDR104_S 24
/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
#define HINF_SSDR50 (BIT(25))
#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S)
#define HINF_SSDR50_V 0x00000001U
#define HINF_SSDR50_S 25
/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
#define HINF_SDTD (BIT(26))
#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S)
#define HINF_SDTD_V 0x00000001U
#define HINF_SDTD_S 26
/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
#define HINF_SDTA (BIT(27))
#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S)
#define HINF_SDTA_V 0x00000001U
#define HINF_SDTA_S 27
/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
#define HINF_SDTC (BIT(28))
#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S)
#define HINF_SDTC_V 0x00000001U
#define HINF_SDTC_S 28
/** HINF_SAI : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
#define HINF_SAI (BIT(29))
#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S)
#define HINF_SAI_V 0x00000001U
#define HINF_SAI_S 29
/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
#define HINF_SDIO_WAKEUP_CLR (BIT(30))
#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U
#define HINF_SDIO_WAKEUP_CLR_S 30
/** HINF_CIS_CONF_W0_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
#define HINF_CIS_CONF_W0 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W0_S 0
/** HINF_CIS_CONF_W1_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
#define HINF_CIS_CONF_W1 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W1_S 0
/** HINF_CIS_CONF_W2_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
#define HINF_CIS_CONF_W2 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W2_S 0
/** HINF_CIS_CONF_W3_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
#define HINF_CIS_CONF_W3 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W3_S 0
/** HINF_CIS_CONF_W4_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
#define HINF_CIS_CONF_W4 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W4_S 0
/** HINF_CIS_CONF_W5_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
#define HINF_CIS_CONF_W5 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W5_S 0
/** HINF_CIS_CONF_W6_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
#define HINF_CIS_CONF_W6 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W6_S 0
/** HINF_CIS_CONF_W7_REG register
* SDIO cis configuration register
*/
#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
#define HINF_CIS_CONF_W7 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU
#define HINF_CIS_CONF_W7_S 0
/** HINF_CFG_DATA16_REG register
* SDIO cis configuration register
*/
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
#define HINF_DEVICE_ID_FN2 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU
#define HINF_DEVICE_ID_FN2_S 0
/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
#define HINF_USER_ID_FN2 0x0000FFFFU
#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
#define HINF_USER_ID_FN2_V 0x0000FFFFU
#define HINF_USER_ID_FN2_S 16
/** HINF_CFG_UHS1_INT_MODE_REG register
* configure int to start and end ahead of time in uhs1 mode
*/
#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_END_AHEAD_MODE 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_END_AHEAD_MODE_S 0
/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_END_AHEAD_MODE 0x00000003U
#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
#define HINF_INT_END_AHEAD_MODE_V 0x00000003U
#define HINF_INT_END_AHEAD_MODE_S 2
/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INTOE_ST_AHEAD_MODE_S 4
/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
#define HINF_INT_ST_AHEAD_MODE 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U
#define HINF_INT_ST_AHEAD_MODE_S 6
/** HINF_CONF_STATUS_REG register
* func0 config0 status
*/
#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
#define HINF_FUNC0_CONFIG0 0x000000FFU
#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
#define HINF_FUNC0_CONFIG0_V 0x000000FFU
#define HINF_FUNC0_CONFIG0_S 0
/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
#define HINF_SDR25_ST (BIT(8))
#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
#define HINF_SDR25_ST_V 0x00000001U
#define HINF_SDR25_ST_S 8
/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
#define HINF_SDR50_ST (BIT(9))
#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
#define HINF_SDR50_ST_V 0x00000001U
#define HINF_SDR50_ST_S 9
/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
#define HINF_SDR104_ST (BIT(10))
#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
#define HINF_SDR104_ST_V 0x00000001U
#define HINF_SDR104_ST_S 10
/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
#define HINF_DDR50_ST (BIT(11))
#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
#define HINF_DDR50_ST_V 0x00000001U
#define HINF_DDR50_ST_S 11
/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
#define HINF_TUNE_ST 0x00000007U
#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
#define HINF_TUNE_ST_V 0x00000007U
#define HINF_TUNE_ST_S 12
/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15))
#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U
#define HINF_SDIO_SWITCH_VOLT_ST_S 15
/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
#define HINF_SDIO_SWITCH_END (BIT(16))
#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
#define HINF_SDIO_SWITCH_END_V 0x00000001U
#define HINF_SDIO_SWITCH_END_S 16
/** HINF_SDIO_SLAVE_LDO_CONF_REG register
* sdio slave ldo control register
*/
#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
#define HINF_LDO_READY_CTL_IN_EN (BIT(0))
#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U
#define HINF_LDO_READY_CTL_IN_EN_S 0
/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
#define HINF_LDO_READY_THRES 0x0000001FU
#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
#define HINF_LDO_READY_THRES_V 0x0000001FU
#define HINF_LDO_READY_THRES_S 1
/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
#define HINF_LDO_READY_IGNORE_EN (BIT(6))
#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U
#define HINF_LDO_READY_IGNORE_EN_S 6
/** HINF_SDIO_DATE_REG register
* ******* Description ***********
*/
#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208;
* sdio version date.
*/
#define HINF_SDIO_DATE 0xFFFFFFFFU
#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
#define HINF_SDIO_DATE_V 0xFFFFFFFFU
#define HINF_SDIO_DATE_S 0
#ifdef __cplusplus
}
#endif

492
components/soc/esp32c5/include/soc/sdio_hinf_struct.h
View File

@ -1,492 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration registers */
/** Type of cfg_data0 register
* Configure sdio cis content
*/
typedef union {
struct {
/** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
* configure device id of function1 in cis
*/
uint32_t device_id_fn1:16;
/** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function1 in cis
*/
uint32_t user_id_fn1:16;
};
uint32_t val;
} hinf_cfg_data0_reg_t;
/** Type of cfg_data1 register
* SDIO configuration register
*/
typedef union {
struct {
/** sdio_enable : R/W; bitpos: [0]; default: 1;
* Sdio clock enable
*/
uint32_t sdio_enable:1;
/** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready1:1;
/** highspeed_enable : R/W; bitpos: [2]; default: 0;
* Highspeed enable in cccr
*/
uint32_t highspeed_enable:1;
/** highspeed_mode : RO; bitpos: [3]; default: 0;
* highspeed mode status in cccr
*/
uint32_t highspeed_mode:1;
/** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
* sdio card detect enable
*/
uint32_t sdio_cd_enable:1;
/** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
* sdio function1 io ready signal in cis
*/
uint32_t sdio_ioready2:1;
/** sdio_int_mask : R/W; bitpos: [6]; default: 0;
* mask sdio interrupt in cccr, high active
*/
uint32_t sdio_int_mask:1;
/** ioenable2 : RO; bitpos: [7]; default: 0;
* ioe2 status in cccr
*/
uint32_t ioenable2:1;
/** cd_disable : RO; bitpos: [8]; default: 0;
* card disable status in cccr
*/
uint32_t cd_disable:1;
/** func1_eps : RO; bitpos: [9]; default: 0;
* function1 eps status in fbr
*/
uint32_t func1_eps:1;
/** emp : RO; bitpos: [10]; default: 0;
* empc status in cccr
*/
uint32_t emp:1;
/** ioenable1 : RO; bitpos: [11]; default: 0;
* ioe1 status in cccr
*/
uint32_t ioenable1:1;
/** sdio_ver : R/W; bitpos: [23:12]; default: 562;
* sdio version in cccr
*/
uint32_t sdio_ver:12;
/** func2_eps : RO; bitpos: [24]; default: 0;
* function2 eps status in fbr
*/
uint32_t func2_eps:1;
/** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
* [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
* in delayed cycles control,0:no delay, 1:delay 1 cycle.
* [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
* mode.
* [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
* [12]=0,posedge when highspeed mode enable.
* [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
* [28]: sdio data pad pull up enable
*/
uint32_t sdio20_conf:7;
};
uint32_t val;
} hinf_cfg_data1_reg_t;
/** Type of cfg_timing register
* Timing configuration registers
*/
typedef union {
struct {
/** ncrc : R/W; bitpos: [2:0]; default: 2;
* configure Ncrc parameter in sdr50/104 mode, no more than 6.
*/
uint32_t ncrc:3;
/** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
* configure cycles to lower cmd after voltage is changed to 1.8V.
*/
uint32_t pst_end_cmd_low_value:7;
/** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
* configure cycles to lower data after voltage is changed to 1.8V.
*/
uint32_t pst_end_data_low_value:6;
/** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
* Configure the number of cycles of module clk to judge sdclk has stopped
*/
uint32_t sdclk_stop_thres:11;
uint32_t reserved_27:1;
/** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
* module clk divider to sample sdclk
*/
uint32_t sample_clk_divider:4;
};
uint32_t val;
} hinf_cfg_timing_reg_t;
/** Type of cfg_update register
* update sdio configurations
*/
typedef union {
struct {
/** conf_update : WT; bitpos: [0]; default: 0;
* update the timing configurations
*/
uint32_t conf_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hinf_cfg_update_reg_t;
/** Type of cfg_data7 register
* SDIO configuration register
*/
typedef union {
struct {
/** pin_state : R/W; bitpos: [7:0]; default: 0;
* configure cis addr 318 and 574
*/
uint32_t pin_state:8;
/** chip_state : R/W; bitpos: [15:8]; default: 0;
* configure cis addr 312, 315, 568 and 571
*/
uint32_t chip_state:8;
/** sdio_rst : R/W; bitpos: [16]; default: 0;
* soft reset control for sdio module
*/
uint32_t sdio_rst:1;
/** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
* sdio io ready, high enable
*/
uint32_t sdio_ioready0:1;
/** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
* sdio memory power down, high active
*/
uint32_t sdio_mem_pd:1;
/** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
* enable sdio interrupt on data1 line
*/
uint32_t esdio_data1_int_en:1;
/** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
* control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
*/
uint32_t sdio_switch_volt_sw:1;
/** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
* enable block length to be fixed to 512 bytes in ddr50 mode
*/
uint32_t ddr50_blk_len_fix_en:1;
/** clk_en : R/W; bitpos: [22]; default: 0;
* sdio apb clock for configuration force on control:0-gating,1-force on.
*/
uint32_t clk_en:1;
/** sddr50 : R/W; bitpos: [23]; default: 1;
* configure if support sdr50 mode in cccr
*/
uint32_t sddr50:1;
/** ssdr104 : R/W; bitpos: [24]; default: 1;
* configure if support sdr104 mode in cccr
*/
uint32_t ssdr104:1;
/** ssdr50 : R/W; bitpos: [25]; default: 1;
* configure if support ddr50 mode in cccr
*/
uint32_t ssdr50:1;
/** sdtd : R/W; bitpos: [26]; default: 0;
* configure if support driver type D in cccr
*/
uint32_t sdtd:1;
/** sdta : R/W; bitpos: [27]; default: 0;
* configure if support driver type A in cccr
*/
uint32_t sdta:1;
/** sdtc : R/W; bitpos: [28]; default: 0;
* configure if support driver type C in cccr
*/
uint32_t sdtc:1;
/** sai : R/W; bitpos: [29]; default: 1;
* configure if support asynchronous interrupt in cccr
*/
uint32_t sai:1;
/** sdio_wakeup_clr : WT; bitpos: [30]; default: 0;
* clear sdio_wake_up signal after the chip wakes up
*/
uint32_t sdio_wakeup_clr:1;
uint32_t reserved_31:1;
};
uint32_t val;
} hinf_cfg_data7_reg_t;
/** Type of cis_conf_w0 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 39~36
*/
uint32_t cis_conf_w0:32;
};
uint32_t val;
} hinf_cis_conf_w0_reg_t;
/** Type of cis_conf_w1 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 43~40
*/
uint32_t cis_conf_w1:32;
};
uint32_t val;
} hinf_cis_conf_w1_reg_t;
/** Type of cis_conf_w2 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 47~44
*/
uint32_t cis_conf_w2:32;
};
uint32_t val;
} hinf_cis_conf_w2_reg_t;
/** Type of cis_conf_w3 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 51~48
*/
uint32_t cis_conf_w3:32;
};
uint32_t val;
} hinf_cis_conf_w3_reg_t;
/** Type of cis_conf_w4 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 55~52
*/
uint32_t cis_conf_w4:32;
};
uint32_t val;
} hinf_cis_conf_w4_reg_t;
/** Type of cis_conf_w5 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 59~56
*/
uint32_t cis_conf_w5:32;
};
uint32_t val;
} hinf_cis_conf_w5_reg_t;
/** Type of cis_conf_w6 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 63~60
*/
uint32_t cis_conf_w6:32;
};
uint32_t val;
} hinf_cis_conf_w6_reg_t;
/** Type of cis_conf_w7 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
* Configure cis addr 67~64
*/
uint32_t cis_conf_w7:32;
};
uint32_t val;
} hinf_cis_conf_w7_reg_t;
/** Type of cfg_data16 register
* SDIO cis configuration register
*/
typedef union {
struct {
/** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
* configure device id of function2 in cis
*/
uint32_t device_id_fn2:16;
/** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
* configure user id of function2 in cis
*/
uint32_t user_id_fn2:16;
};
uint32_t val;
} hinf_cfg_data16_reg_t;
/** Type of cfg_uhs1_int_mode register
* configure int to start and end ahead of time in uhs1 mode
*/
typedef union {
struct {
/** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
* intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_end_ahead_mode:2;
/** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
* int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_end_ahead_mode:2;
/** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
* intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t intoe_st_ahead_mode:2;
/** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
* int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
*/
uint32_t int_st_ahead_mode:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hinf_cfg_uhs1_int_mode_reg_t;
/** Type of sdio_slave_ldo_conf register
* sdio slave ldo control register
*/
typedef union {
struct {
/** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
* control ldo ready signal by sdio slave itself
*/
uint32_t ldo_ready_ctl_in_en:1;
/** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
* configure ldo ready counting threshold value, the actual counting target is
* 2^(ldo_ready_thres)-1
*/
uint32_t ldo_ready_thres:5;
/** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
* ignore ldo ready signal
*/
uint32_t ldo_ready_ignore_en:1;
uint32_t reserved_7:25;
};
uint32_t val;
} hinf_sdio_slave_ldo_conf_reg_t;
/** Group: Status registers */
/** Type of conf_status register
* func0 config0 status
*/
typedef union {
struct {
/** func0_config0 : RO; bitpos: [7:0]; default: 0;
* func0 config0 (addr: 0x20f0 ) status
*/
uint32_t func0_config0:8;
/** sdr25_st : RO; bitpos: [8]; default: 0;
* sdr25 status
*/
uint32_t sdr25_st:1;
/** sdr50_st : RO; bitpos: [9]; default: 0;
* sdr50 status
*/
uint32_t sdr50_st:1;
/** sdr104_st : RO; bitpos: [10]; default: 0;
* sdr104 status
*/
uint32_t sdr104_st:1;
/** ddr50_st : RO; bitpos: [11]; default: 0;
* ddr50 status
*/
uint32_t ddr50_st:1;
/** tune_st : RO; bitpos: [14:12]; default: 0;
* tune_st fsm status
*/
uint32_t tune_st:3;
/** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
* sdio switch voltage status:0-3.3V, 1-1.8V.
*/
uint32_t sdio_switch_volt_st:1;
/** sdio_switch_end : RO; bitpos: [16]; default: 0;
* sdio switch voltage ldo ready
*/
uint32_t sdio_switch_end:1;
uint32_t reserved_17:15;
};
uint32_t val;
} hinf_conf_status_reg_t;
/** Group: Version register */
/** Type of sdio_date register
* ******* Description ***********
*/
typedef union {
struct {
/** sdio_date : R/W; bitpos: [31:0]; default: 35664208;
* sdio version date.
*/
uint32_t sdio_date:32;
};
uint32_t val;
} hinf_sdio_date_reg_t;
typedef struct {
volatile hinf_cfg_data0_reg_t cfg_data0;
volatile hinf_cfg_data1_reg_t cfg_data1;
volatile hinf_cfg_timing_reg_t cfg_timing;
volatile hinf_cfg_update_reg_t cfg_update;
uint32_t reserved_010[3];
volatile hinf_cfg_data7_reg_t cfg_data7;
volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
volatile hinf_cfg_data16_reg_t cfg_data16;
volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
uint32_t reserved_048[3];
volatile hinf_conf_status_reg_t conf_status;
uint32_t reserved_058[22];
volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
uint32_t reserved_0b4[18];
volatile hinf_sdio_date_reg_t sdio_date;
} hinf_dev_t;
extern hinf_dev_t HINF;
#ifndef __cplusplus
_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

4301
components/soc/esp32c5/include/soc/sdio_slc_reg.h
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3253
components/soc/esp32c5/include/soc/sdio_slc_struct.h
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2
components/soc/esp32c5/include/soc/sha_struct.h
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@ -160,7 +160,7 @@ typedef union {
/** Group: memory type */
typedef struct {
typedef struct sha_dev_t {
volatile sha_mode_reg_t mode;
uint32_t reserved_004[2];
volatile sha_dma_block_num_reg_t dma_block_num;

1499
components/soc/esp32c5/include/soc/soc_etm_struct.h
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29
components/soc/esp32c5/include/soc/spi1_mem_struct.h
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@ -639,18 +639,18 @@ typedef union {
/** Group: Memory data buffer register */
/** Type of w0 register
* SPI1 memory data buffer0
/** Type of wn register
* SPI1 memory data buffer n
*/
typedef union {
struct {
/** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
/** buf : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf0:32;
uint32_t buf:32;
};
uint32_t val;
} spi1_mem_w0_reg_t;
} spi1_mem_wn_reg_t;
/** Type of w1 register
* SPI1 memory data buffer1
@ -1036,7 +1036,7 @@ typedef union {
} spi1_mem_date_reg_t;
typedef struct {
typedef struct spi1_mem_dev_t {
volatile spi1_mem_cmd_reg_t cmd;
volatile spi1_mem_addr_reg_t addr;
volatile spi1_mem_ctrl_reg_t ctrl;
@ -1052,22 +1052,7 @@ typedef struct {
uint32_t reserved_030;
volatile spi1_mem_misc_reg_t misc;
uint32_t reserved_038[8];
volatile spi1_mem_w0_reg_t w0;
volatile spi1_mem_w1_reg_t w1;
volatile spi1_mem_w2_reg_t w2;
volatile spi1_mem_w3_reg_t w3;
volatile spi1_mem_w4_reg_t w4;
volatile spi1_mem_w5_reg_t w5;
volatile spi1_mem_w6_reg_t w6;
volatile spi1_mem_w7_reg_t w7;
volatile spi1_mem_w8_reg_t w8;
volatile spi1_mem_w9_reg_t w9;
volatile spi1_mem_w10_reg_t w10;
volatile spi1_mem_w11_reg_t w11;
volatile spi1_mem_w12_reg_t w12;
volatile spi1_mem_w13_reg_t w13;
volatile spi1_mem_w14_reg_t w14;
volatile spi1_mem_w15_reg_t w15;
volatile spi1_mem_wn_reg_t data_buf[16];
volatile spi1_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
volatile spi1_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
volatile spi1_mem_flash_sus_cmd_reg_t flash_sus_cmd;

2
components/soc/esp32c5/include/soc/spi_mem_struct.h
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@ -1946,7 +1946,7 @@ typedef union {
} spi_mem_date_reg_t;
typedef struct {
typedef struct spi_mem_dev_t {
volatile spi_mem_cmd_reg_t mem_cmd;
uint32_t reserved_004;
volatile spi_mem_ctrl_reg_t mem_ctrl;

29
components/soc/esp32c5/include/soc/spi_struct.h
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@ -1335,18 +1335,18 @@ typedef union {
/** Group: CPU-controlled data buffer */
/** Type of w0 register
* SPI CPU-controlled buffer0
/** Type of wn register
* SPI CPU-controlled buffer n
*/
typedef union {
struct {
/** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
/** buf : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
uint32_t buf0:32;
uint32_t buf:32;
};
uint32_t val;
} spi_w0_reg_t;
} spi_wn_reg_t;
/** Type of w1 register
* SPI CPU-controlled buffer1
@ -1560,7 +1560,7 @@ typedef union {
} spi_date_reg_t;
typedef struct {
typedef struct spi_dev_t {
volatile spi_cmd_reg_t cmd;
volatile spi_addr_reg_t addr;
volatile spi_ctrl_reg_t ctrl;
@ -1580,22 +1580,7 @@ typedef struct {
volatile spi_dma_int_st_reg_t dma_int_st;
volatile spi_dma_int_set_reg_t dma_int_set;
uint32_t reserved_048[20];
volatile spi_w0_reg_t w0;
volatile spi_w1_reg_t w1;
volatile spi_w2_reg_t w2;
volatile spi_w3_reg_t w3;
volatile spi_w4_reg_t w4;
volatile spi_w5_reg_t w5;
volatile spi_w6_reg_t w6;
volatile spi_w7_reg_t w7;
volatile spi_w8_reg_t w8;
volatile spi_w9_reg_t w9;
volatile spi_w10_reg_t w10;
volatile spi_w11_reg_t w11;
volatile spi_w12_reg_t w12;
volatile spi_w13_reg_t w13;
volatile spi_w14_reg_t w14;
volatile spi_w15_reg_t w15;
volatile spi_wn_reg_t data_buf[16];
uint32_t reserved_0d8[2];
volatile spi_slave_reg_t slave;
volatile spi_slave1_reg_t slave1;

2
components/soc/esp32c5/include/soc/systimer_struct.h
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@ -632,7 +632,7 @@ typedef union {
} systimer_date_reg_t;
typedef struct {
typedef struct systimer_dev_t {
volatile systimer_conf_reg_t conf;
volatile systimer_unit0_op_reg_t unit0_op;
volatile systimer_unit1_op_reg_t unit1_op;

2
components/soc/esp32c5/include/soc/tee_struct.h
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@ -652,7 +652,7 @@ typedef union {
} tee_date_reg_t;
typedef struct {
typedef struct tee_dev_t {
volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl;
volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl;

52
components/soc/esp32c5/include/soc/timer_group_reg.h
View File

@ -14,7 +14,7 @@ extern "C" {
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
@ -63,7 +63,7 @@ extern "C" {
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
@ -76,7 +76,7 @@ extern "C" {
/** TIMG_T0HI_REG register
* Timer 0 current value, high 22 bits
*/
#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
* of timer 0 can be read here.
@ -89,7 +89,7 @@ extern "C" {
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
*/
#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
*/
@ -101,7 +101,7 @@ extern "C" {
/** TIMG_T0ALARMLO_REG register
* Timer 0 alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer 0 alarm trigger time-base counter value, low 32 bits.
*/
@ -113,7 +113,7 @@ extern "C" {
/** TIMG_T0ALARMHI_REG register
* Timer 0 alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer 0 alarm trigger time-base counter value, high 22 bits.
*/
@ -125,7 +125,7 @@ extern "C" {
/** TIMG_T0LOADLO_REG register
* Timer 0 reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer 0 time-base
* Counter.
@ -138,7 +138,7 @@ extern "C" {
/** TIMG_T0LOADHI_REG register
* Timer 0 reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer 0 time-base
* counter.
@ -151,7 +151,7 @@ extern "C" {
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
*/
#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer 0 time-base counter reload.
@ -164,7 +164,7 @@ extern "C" {
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
@ -248,7 +248,7 @@ extern "C" {
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
@ -268,7 +268,7 @@ extern "C" {
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
@ -280,7 +280,7 @@ extern "C" {
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
@ -292,7 +292,7 @@ extern "C" {
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
@ -304,7 +304,7 @@ extern "C" {
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
@ -316,7 +316,7 @@ extern "C" {
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
@ -328,7 +328,7 @@ extern "C" {
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
@ -341,7 +341,7 @@ extern "C" {
/** TIMG_RTCCALICFG_REG register
* RTC calibration configure register
*/
#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68)
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* 0: one-shot frequency calculation,1: periodic frequency calculation,
*/
@ -381,7 +381,7 @@ extern "C" {
/** TIMG_RTCCALICFG1_REG register
* RTC calibration configure1 register
*/
#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c)
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* indicate periodic frequency calculation is done.
*/
@ -401,7 +401,7 @@ extern "C" {
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
@ -420,7 +420,7 @@ extern "C" {
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
@ -439,7 +439,7 @@ extern "C" {
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
@ -458,7 +458,7 @@ extern "C" {
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
@ -477,7 +477,7 @@ extern "C" {
/** TIMG_RTCCALICFG2_REG register
* Timer group calibration register
*/
#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80)
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
@ -504,7 +504,7 @@ extern "C" {
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
* Timer version control register
*/
@ -516,7 +516,7 @@ extern "C" {
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
* enable timer's etm task and event
*/

2
components/soc/esp32c5/include/soc/timer_group_struct.h
View File

@ -509,7 +509,7 @@ typedef union {
} timg_regclk_reg_t;
typedef struct {
typedef struct timg_dev_t {
volatile timg_txconfig_reg_t t0config;
volatile timg_txlo_reg_t t0lo;
volatile timg_txhi_reg_t t0hi;

3
components/soc/esp32c5/include/soc/trace_struct.h
View File

@ -428,7 +428,7 @@ typedef union {
} trace_date_reg_t;
typedef struct {
typedef struct trace_dev_t {
volatile trace_mem_start_addr_reg_t mem_start_addr;
volatile trace_mem_end_addr_reg_t mem_end_addr;
volatile trace_mem_current_addr_reg_t mem_current_addr;
@ -451,6 +451,7 @@ typedef struct {
volatile trace_date_reg_t date;
} trace_dev_t;
extern trace_dev_t TRACE;
#ifndef __cplusplus
_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");

70
components/soc/esp32c5/include/soc/twai_reg.h
View File

@ -14,7 +14,7 @@ extern "C" {
/** TWAI_MODE_REG register
* TWAI mode register.
*/
#define TWAI_MODE_REG (DR_REG_TWAI_BASE + 0x0)
#define TWAI_MODE_REG(i) (REG_TWAI_BASE(i) + 0x0)
/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1;
* 1: reset, detection of a set reset mode bit results in aborting the current
* transmission/reception of a message and entering the reset mode. 0: normal, on the
@ -57,7 +57,7 @@ extern "C" {
/** TWAI_CMD_REG register
* TWAI command register.
*/
#define TWAI_CMD_REG (DR_REG_TWAI_BASE + 0x4)
#define TWAI_CMD_REG(i) (REG_TWAI_BASE(i) + 0x4)
/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0;
* 1: present, a message shall be transmitted. 0: absent
*/
@ -99,7 +99,7 @@ extern "C" {
/** TWAI_STATUS_REG register
* TWAI status register.
*/
#define TWAI_STATUS_REG (DR_REG_TWAI_BASE + 0x8)
#define TWAI_STATUS_REG(i) (REG_TWAI_BASE(i) + 0x8)
/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0;
* 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
* message is available
@ -176,7 +176,7 @@ extern "C" {
/** TWAI_INTERRUPT_REG register
* Interrupt signals' register.
*/
#define TWAI_INTERRUPT_REG (DR_REG_TWAI_BASE + 0xc)
#define TWAI_INTERRUPT_REG(i) (REG_TWAI_BASE(i) + 0xc)
/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0;
* 1: this bit is set while the receive FIFO is not empty and the RIE bit is set
* within the interrupt enable register. 0: reset
@ -256,7 +256,7 @@ extern "C" {
/** TWAI_INTERRUPT_ENABLE_REG register
* Interrupt enable register.
*/
#define TWAI_INTERRUPT_ENABLE_REG (DR_REG_TWAI_BASE + 0x10)
#define TWAI_INTERRUPT_ENABLE_REG(i) (REG_TWAI_BASE(i) + 0x10)
/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0;
* 1: enabled, when the receive buffer status is 'full' the TWAI controller requests
* the respective interrupt. 0: disable
@ -333,7 +333,7 @@ extern "C" {
/** TWAI_BUS_TIMING_0_REG register
* Bit timing configuration register 0.
*/
#define TWAI_BUS_TIMING_0_REG (DR_REG_TWAI_BASE + 0x18)
#define TWAI_BUS_TIMING_0_REG(i) (REG_TWAI_BASE(i) + 0x18)
/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0;
* The period of the TWAI system clock is programmable and determines the individual
* bit timing. Software has R/W permission in reset mode and RO permission in
@ -356,7 +356,7 @@ extern "C" {
/** TWAI_BUS_TIMING_1_REG register
* Bit timing configuration register 1.
*/
#define TWAI_BUS_TIMING_1_REG (DR_REG_TWAI_BASE + 0x1c)
#define TWAI_BUS_TIMING_1_REG(i) (REG_TWAI_BASE(i) + 0x1c)
/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0;
* The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
* reset mode and RO in operation mode.
@ -385,7 +385,7 @@ extern "C" {
/** TWAI_ARB_LOST_CAP_REG register
* TWAI arbiter lost capture register.
*/
#define TWAI_ARB_LOST_CAP_REG (DR_REG_TWAI_BASE + 0x2c)
#define TWAI_ARB_LOST_CAP_REG(i) (REG_TWAI_BASE(i) + 0x2c)
/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0;
* This register contains information about the bit position of losing arbitration.
*/
@ -397,7 +397,7 @@ extern "C" {
/** TWAI_ERR_CODE_CAP_REG register
* TWAI error info capture register.
*/
#define TWAI_ERR_CODE_CAP_REG (DR_REG_TWAI_BASE + 0x30)
#define TWAI_ERR_CODE_CAP_REG(i) (REG_TWAI_BASE(i) + 0x30)
/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0;
* This register contains information about the location of errors on the bus.
*/
@ -423,7 +423,7 @@ extern "C" {
/** TWAI_ERR_WARNING_LIMIT_REG register
* TWAI error threshold configuration register.
*/
#define TWAI_ERR_WARNING_LIMIT_REG (DR_REG_TWAI_BASE + 0x34)
#define TWAI_ERR_WARNING_LIMIT_REG(i) (REG_TWAI_BASE(i) + 0x34)
/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96;
* The threshold that trigger error warning interrupt when this interrupt is enabled.
* Software has R/W permission in reset mode and RO in operation mode.
@ -436,7 +436,7 @@ extern "C" {
/** TWAI_RX_ERR_CNT_REG register
* Rx error counter register.
*/
#define TWAI_RX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x38)
#define TWAI_RX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x38)
/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
* The RX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
@ -449,7 +449,7 @@ extern "C" {
/** TWAI_TX_ERR_CNT_REG register
* Tx error counter register.
*/
#define TWAI_TX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x3c)
#define TWAI_TX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x3c)
/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
* The TX error counter register reflects the current value of the transmit error
* counter. Software has R/W permission in reset mode and RO in operation mode.
@ -462,7 +462,7 @@ extern "C" {
/** TWAI_DATA_0_REG register
* Data register 0.
*/
#define TWAI_DATA_0_REG (DR_REG_TWAI_BASE + 0x40)
#define TWAI_DATA_0_REG(i) (REG_TWAI_BASE(i) + 0x40)
/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 0 and when
@ -476,7 +476,7 @@ extern "C" {
/** TWAI_DATA_1_REG register
* Data register 1.
*/
#define TWAI_DATA_1_REG (DR_REG_TWAI_BASE + 0x44)
#define TWAI_DATA_1_REG(i) (REG_TWAI_BASE(i) + 0x44)
/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 1 and when
@ -490,7 +490,7 @@ extern "C" {
/** TWAI_DATA_2_REG register
* Data register 2.
*/
#define TWAI_DATA_2_REG (DR_REG_TWAI_BASE + 0x48)
#define TWAI_DATA_2_REG(i) (REG_TWAI_BASE(i) + 0x48)
/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 2 and when
@ -504,7 +504,7 @@ extern "C" {
/** TWAI_DATA_3_REG register
* Data register 3.
*/
#define TWAI_DATA_3_REG (DR_REG_TWAI_BASE + 0x4c)
#define TWAI_DATA_3_REG(i) (REG_TWAI_BASE(i) + 0x4c)
/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 3 and when
@ -518,7 +518,7 @@ extern "C" {
/** TWAI_DATA_4_REG register
* Data register 4.
*/
#define TWAI_DATA_4_REG (DR_REG_TWAI_BASE + 0x50)
#define TWAI_DATA_4_REG(i) (REG_TWAI_BASE(i) + 0x50)
/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 4 and when
@ -532,7 +532,7 @@ extern "C" {
/** TWAI_DATA_5_REG register
* Data register 5.
*/
#define TWAI_DATA_5_REG (DR_REG_TWAI_BASE + 0x54)
#define TWAI_DATA_5_REG(i) (REG_TWAI_BASE(i) + 0x54)
/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 5 and when
@ -546,7 +546,7 @@ extern "C" {
/** TWAI_DATA_6_REG register
* Data register 6.
*/
#define TWAI_DATA_6_REG (DR_REG_TWAI_BASE + 0x58)
#define TWAI_DATA_6_REG(i) (REG_TWAI_BASE(i) + 0x58)
/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 6 and when
@ -560,7 +560,7 @@ extern "C" {
/** TWAI_DATA_7_REG register
* Data register 7.
*/
#define TWAI_DATA_7_REG (DR_REG_TWAI_BASE + 0x5c)
#define TWAI_DATA_7_REG(i) (REG_TWAI_BASE(i) + 0x5c)
/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 7 and when
@ -574,7 +574,7 @@ extern "C" {
/** TWAI_DATA_8_REG register
* Data register 8.
*/
#define TWAI_DATA_8_REG (DR_REG_TWAI_BASE + 0x60)
#define TWAI_DATA_8_REG(i) (REG_TWAI_BASE(i) + 0x60)
/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 8 and when software initiate read operation, it
@ -588,7 +588,7 @@ extern "C" {
/** TWAI_DATA_9_REG register
* Data register 9.
*/
#define TWAI_DATA_9_REG (DR_REG_TWAI_BASE + 0x64)
#define TWAI_DATA_9_REG(i) (REG_TWAI_BASE(i) + 0x64)
/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 9 and when software initiate read operation, it
@ -602,7 +602,7 @@ extern "C" {
/** TWAI_DATA_10_REG register
* Data register 10.
*/
#define TWAI_DATA_10_REG (DR_REG_TWAI_BASE + 0x68)
#define TWAI_DATA_10_REG(i) (REG_TWAI_BASE(i) + 0x68)
/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 10 and when software initiate read operation, it
@ -616,7 +616,7 @@ extern "C" {
/** TWAI_DATA_11_REG register
* Data register 11.
*/
#define TWAI_DATA_11_REG (DR_REG_TWAI_BASE + 0x6c)
#define TWAI_DATA_11_REG(i) (REG_TWAI_BASE(i) + 0x6c)
/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 11 and when software initiate read operation, it
@ -630,7 +630,7 @@ extern "C" {
/** TWAI_DATA_12_REG register
* Data register 12.
*/
#define TWAI_DATA_12_REG (DR_REG_TWAI_BASE + 0x70)
#define TWAI_DATA_12_REG(i) (REG_TWAI_BASE(i) + 0x70)
/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 12 and when software initiate read operation, it
@ -644,7 +644,7 @@ extern "C" {
/** TWAI_RX_MESSAGE_COUNTER_REG register
* Received message counter register.
*/
#define TWAI_RX_MESSAGE_COUNTER_REG (DR_REG_TWAI_BASE + 0x74)
#define TWAI_RX_MESSAGE_COUNTER_REG(i) (REG_TWAI_BASE(i) + 0x74)
/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0;
* Reflects the number of messages available within the RXFIFO. The value is
* incremented with each receive event and decremented by the release receive buffer
@ -658,7 +658,7 @@ extern "C" {
/** TWAI_CLOCK_DIVIDER_REG register
* Clock divider register.
*/
#define TWAI_CLOCK_DIVIDER_REG (DR_REG_TWAI_BASE + 0x7c)
#define TWAI_CLOCK_DIVIDER_REG(i) (REG_TWAI_BASE(i) + 0x7c)
/** TWAI_CD : R/W; bitpos: [7:0]; default: 0;
* These bits are used to define the frequency at the external CLKOUT pin.
*/
@ -678,7 +678,7 @@ extern "C" {
/** TWAI_SW_STANDBY_CFG_REG register
* Software configure standby pin directly.
*/
#define TWAI_SW_STANDBY_CFG_REG (DR_REG_TWAI_BASE + 0x80)
#define TWAI_SW_STANDBY_CFG_REG(i) (REG_TWAI_BASE(i) + 0x80)
/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
* Enable standby pin.
*/
@ -697,7 +697,7 @@ extern "C" {
/** TWAI_HW_CFG_REG register
* Hardware configure standby pin.
*/
#define TWAI_HW_CFG_REG (DR_REG_TWAI_BASE + 0x84)
#define TWAI_HW_CFG_REG(i) (REG_TWAI_BASE(i) + 0x84)
/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
* Enable function that hardware control standby pin.
*/
@ -709,7 +709,7 @@ extern "C" {
/** TWAI_HW_STANDBY_CNT_REG register
* Configure standby counter.
*/
#define TWAI_HW_STANDBY_CNT_REG (DR_REG_TWAI_BASE + 0x88)
#define TWAI_HW_STANDBY_CNT_REG(i) (REG_TWAI_BASE(i) + 0x88)
/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
* is enabled.
@ -722,7 +722,7 @@ extern "C" {
/** TWAI_IDLE_INTR_CNT_REG register
* Configure idle interrupt counter.
*/
#define TWAI_IDLE_INTR_CNT_REG (DR_REG_TWAI_BASE + 0x8c)
#define TWAI_IDLE_INTR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x8c)
/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1;
* Configure the number of cycles before triggering idle interrupt.
*/
@ -734,7 +734,7 @@ extern "C" {
/** TWAI_ECO_CFG_REG register
* ECO configuration register.
*/
#define TWAI_ECO_CFG_REG (DR_REG_TWAI_BASE + 0x90)
#define TWAI_ECO_CFG_REG(i) (REG_TWAI_BASE(i) + 0x90)
/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0;
* Enable eco module.
*/
@ -753,7 +753,7 @@ extern "C" {
/** TWAI_TIMESTAMP_DATA_REG register
* Timestamp data register
*/
#define TWAI_TIMESTAMP_DATA_REG (DR_REG_TWAI_BASE + 0x94)
#define TWAI_TIMESTAMP_DATA_REG(i) (REG_TWAI_BASE(i) + 0x94)
/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0;
* Data of timestamp of a CAN frame.
*/
@ -765,7 +765,7 @@ extern "C" {
/** TWAI_TIMESTAMP_PRESCALER_REG register
* Timestamp configuration register
*/
#define TWAI_TIMESTAMP_PRESCALER_REG (DR_REG_TWAI_BASE + 0x98)
#define TWAI_TIMESTAMP_PRESCALER_REG(i) (REG_TWAI_BASE(i) + 0x98)
/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31;
* Configures the clock division number of timestamp counter.
*/
@ -777,7 +777,7 @@ extern "C" {
/** TWAI_TIMESTAMP_CFG_REG register
* Timestamp configuration register
*/
#define TWAI_TIMESTAMP_CFG_REG (DR_REG_TWAI_BASE + 0x9c)
#define TWAI_TIMESTAMP_CFG_REG(i) (REG_TWAI_BASE(i) + 0x9c)
/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0;
* enable the timestamp collection function.
*/

238
components/soc/esp32c5/include/soc/twai_struct.h
View File

@ -493,213 +493,21 @@ typedef union {
/** Group: Data Registers */
/** Type of data_0 register
* Data register 0.
/** Type of tx_rx_buffer register
* Data register.
*/
typedef union {
struct {
/** data_0 : R/W; bitpos: [7:0]; default: 0;
/** byte : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 0 and when
* software initiate read operation, it is rx data register 0.
*/
uint32_t data_0:8;
uint32_t byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_0_reg_t;
/** Type of data_1 register
* Data register 1.
*/
typedef union {
struct {
/** data_1 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 1 and when
* software initiate read operation, it is rx data register 1.
*/
uint32_t data_1:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_1_reg_t;
/** Type of data_2 register
* Data register 2.
*/
typedef union {
struct {
/** data_2 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 2 and when
* software initiate read operation, it is rx data register 2.
*/
uint32_t data_2:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_2_reg_t;
/** Type of data_3 register
* Data register 3.
*/
typedef union {
struct {
/** data_3 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance code register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 3 and when
* software initiate read operation, it is rx data register 3.
*/
uint32_t data_3:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_3_reg_t;
/** Type of data_4 register
* Data register 4.
*/
typedef union {
struct {
/** data_4 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 4 and when
* software initiate read operation, it is rx data register 4.
*/
uint32_t data_4:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_4_reg_t;
/** Type of data_5 register
* Data register 5.
*/
typedef union {
struct {
/** data_5 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 5 and when
* software initiate read operation, it is rx data register 5.
*/
uint32_t data_5:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_5_reg_t;
/** Type of data_6 register
* Data register 6.
*/
typedef union {
struct {
/** data_6 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 6 and when
* software initiate read operation, it is rx data register 6.
*/
uint32_t data_6:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_6_reg_t;
/** Type of data_7 register
* Data register 7.
*/
typedef union {
struct {
/** data_7 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
* mode, when software initiate write operation, it is tx data register 7 and when
* software initiate read operation, it is rx data register 7.
*/
uint32_t data_7:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_7_reg_t;
/** Type of data_8 register
* Data register 8.
*/
typedef union {
struct {
/** data_8 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 8 and when software initiate read operation, it
* is rx data register 8.
*/
uint32_t data_8:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_8_reg_t;
/** Type of data_9 register
* Data register 9.
*/
typedef union {
struct {
/** data_9 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 9 and when software initiate read operation, it
* is rx data register 9.
*/
uint32_t data_9:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_9_reg_t;
/** Type of data_10 register
* Data register 10.
*/
typedef union {
struct {
/** data_10 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 10 and when software initiate read operation, it
* is rx data register 10.
*/
uint32_t data_10:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_10_reg_t;
/** Type of data_11 register
* Data register 11.
*/
typedef union {
struct {
/** data_11 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 11 and when software initiate read operation, it
* is rx data register 11.
*/
uint32_t data_11:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_11_reg_t;
/** Type of data_12 register
* Data register 12.
*/
typedef union {
struct {
/** data_12 : R/W; bitpos: [7:0]; default: 0;
* In reset mode, reserved with RO. In operation mode, when software initiate write
* operation, it is tx data register 12 and when software initiate read operation, it
* is rx data register 12.
*/
uint32_t data_12:8;
uint32_t reserved_8:24;
};
uint32_t val;
} twai_data_12_reg_t;
} twai_tx_rx_buffer_reg_t;
/** Group: Timestamp Register */
@ -744,8 +552,25 @@ typedef union {
uint32_t val;
} twai_timestamp_cfg_reg_t;
typedef struct {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved_60[5];
} acceptance_filter_reg_t;
typedef struct twai_dev_t {
volatile twai_mode_reg_t mode;
volatile twai_cmd_reg_t cmd;
volatile twai_status_reg_t status;
@ -760,19 +585,10 @@ typedef struct {
volatile twai_err_warning_limit_reg_t err_warning_limit;
volatile twai_rx_err_cnt_reg_t rx_err_cnt;
volatile twai_tx_err_cnt_reg_t tx_err_cnt;
volatile twai_data_0_reg_t data_0;
volatile twai_data_1_reg_t data_1;
volatile twai_data_2_reg_t data_2;
volatile twai_data_3_reg_t data_3;
volatile twai_data_4_reg_t data_4;
volatile twai_data_5_reg_t data_5;
volatile twai_data_6_reg_t data_6;
volatile twai_data_7_reg_t data_7;
volatile twai_data_8_reg_t data_8;
volatile twai_data_9_reg_t data_9;
volatile twai_data_10_reg_t data_10;
volatile twai_data_11_reg_t data_11;
volatile twai_data_12_reg_t data_12;
volatile union {
acceptance_filter_reg_t acceptance_filter;
twai_tx_rx_buffer_reg_t tx_rx_buffer[13];
};
volatile twai_rx_message_counter_reg_t rx_message_counter;
uint32_t reserved_078;
volatile twai_clock_divider_reg_t clock_divider;

76
components/soc/esp32c5/include/soc/uart_reg.h
View File

@ -14,7 +14,7 @@ extern "C" {
/** UART_FIFO_REG register
* FIFO data register
*/
#define UART_FIFO_REG (DR_REG_UART_BASE + 0x0)
#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
* UART $n accesses FIFO via this register.
*/
@ -26,7 +26,7 @@ extern "C" {
/** UART_INT_RAW_REG register
* Raw interrupt status
*/
#define UART_INT_RAW_REG (DR_REG_UART_BASE + 0x4)
#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when receiver receives more data than
* what rxfifo_full_thrhd specifies.
@ -191,7 +191,7 @@ extern "C" {
/** UART_INT_ST_REG register
* Masked interrupt status
*/
#define UART_INT_ST_REG (DR_REG_UART_BASE + 0x8)
#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
* This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
*/
@ -341,7 +341,7 @@ extern "C" {
/** UART_INT_ENA_REG register
* Interrupt enable bits
*/
#define UART_INT_ENA_REG (DR_REG_UART_BASE + 0xc)
#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
* This is the enable bit for rxfifo_full_int_st register.
*/
@ -486,7 +486,7 @@ extern "C" {
/** UART_INT_CLR_REG register
* Interrupt clear bits
*/
#define UART_INT_CLR_REG (DR_REG_UART_BASE + 0x10)
#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the rxfifo_full_int_raw interrupt.
*/
@ -631,7 +631,7 @@ extern "C" {
/** UART_CLKDIV_SYNC_REG register
* Clock divider configuration
*/
#define UART_CLKDIV_SYNC_REG (DR_REG_UART_BASE + 0x14)
#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
* The integral part of the frequency divider factor.
*/
@ -650,7 +650,7 @@ extern "C" {
/** UART_RX_FILT_REG register
* Rx Filter configuration
*/
#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18)
#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
* when input pulse width is lower than this value the pulse is ignored.
*/
@ -669,7 +669,7 @@ extern "C" {
/** UART_STATUS_REG register
* UART status register
*/
#define UART_STATUS_REG (DR_REG_UART_BASE + 0x1c)
#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
* Stores the byte number of valid data in Rx-FIFO.
*/
@ -730,7 +730,7 @@ extern "C" {
/** UART_CONF0_SYNC_REG register
* a
*/
#define UART_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x20)
#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
/** UART_PARITY : R/W; bitpos: [0]; default: 0;
* This register is used to configure the parity check mode.
*/
@ -893,7 +893,7 @@ extern "C" {
/** UART_CONF1_REG register
* Configuration register 1
*/
#define UART_CONF1_REG (DR_REG_UART_BASE + 0x24)
#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
* It will produce rxfifo_full_int interrupt when receiver receives more data than
* this register value.
@ -958,7 +958,7 @@ extern "C" {
/** UART_HWFC_CONF_SYNC_REG register
* Hardware flow-control configuration
*/
#define UART_HWFC_CONF_SYNC_REG (DR_REG_UART_BASE + 0x2c)
#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
* This register is used to configure the maximum amount of data that can be received
* when hardware flow control works.
@ -978,7 +978,7 @@ extern "C" {
/** UART_SLEEP_CONF0_REG register
* UART sleep configure register 0
*/
#define UART_SLEEP_CONF0_REG (DR_REG_UART_BASE + 0x30)
#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
* This register restores the specified wake up char1 to wake up
*/
@ -1011,7 +1011,7 @@ extern "C" {
/** UART_SLEEP_CONF1_REG register
* UART sleep configure register 1
*/
#define UART_SLEEP_CONF1_REG (DR_REG_UART_BASE + 0x34)
#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
* This register restores the specified char0 to wake up
*/
@ -1023,7 +1023,7 @@ extern "C" {
/** UART_SLEEP_CONF2_REG register
* UART sleep configure register 2
*/
#define UART_SLEEP_CONF2_REG (DR_REG_UART_BASE + 0x38)
#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
* The uart is activated from light sleeping mode when the input rxd edge changes more
* times than this register value.
@ -1066,7 +1066,7 @@ extern "C" {
/** UART_SWFC_CONF0_SYNC_REG register
* Software flow-control character configuration
*/
#define UART_SWFC_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x3c)
#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
* This register stores the Xon flow control char.
*/
@ -1138,7 +1138,7 @@ extern "C" {
/** UART_SWFC_CONF1_REG register
* Software flow-control character configuration
*/
#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40)
#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
* When the data amount in Rx-FIFO is less than this register value with
* uart_sw_flow_con_en set to 1 it will send a Xon char.
@ -1159,7 +1159,7 @@ extern "C" {
/** UART_TXBRK_CONF_SYNC_REG register
* Tx Break character configuration
*/
#define UART_TXBRK_CONF_SYNC_REG (DR_REG_UART_BASE + 0x44)
#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
* This register is used to configure the number of 0 to be sent after the process of
* sending data is done. It is active when txd_brk is set to 1.
@ -1172,7 +1172,7 @@ extern "C" {
/** UART_IDLE_CONF_SYNC_REG register
* Frame-end idle configuration
*/
#define UART_IDLE_CONF_SYNC_REG (DR_REG_UART_BASE + 0x48)
#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
* It will produce frame end signal when receiver takes more time to receive one byte
* data than this register value.
@ -1192,7 +1192,7 @@ extern "C" {
/** UART_RS485_CONF_SYNC_REG register
* RS485 mode configuration
*/
#define UART_RS485_CONF_SYNC_REG (DR_REG_UART_BASE + 0x4c)
#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
* Set this bit to choose the rs485 mode.
*/
@ -1247,7 +1247,7 @@ extern "C" {
/** UART_AT_CMD_PRECNT_SYNC_REG register
* Pre-sequence timing configuration
*/
#define UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_UART_BASE + 0x50)
#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
* This register is used to configure the idle duration time before the first at_cmd
* is received by receiver.
@ -1260,7 +1260,7 @@ extern "C" {
/** UART_AT_CMD_POSTCNT_SYNC_REG register
* Post-sequence timing configuration
*/
#define UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_UART_BASE + 0x54)
#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
* This register is used to configure the duration time between the last at_cmd and
* the next data.
@ -1273,7 +1273,7 @@ extern "C" {
/** UART_AT_CMD_GAPTOUT_SYNC_REG register
* Timeout configuration
*/
#define UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_UART_BASE + 0x58)
#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
* This register is used to configure the duration time between the at_cmd chars.
*/
@ -1285,7 +1285,7 @@ extern "C" {
/** UART_AT_CMD_CHAR_SYNC_REG register
* AT escape sequence detection configuration
*/
#define UART_AT_CMD_CHAR_SYNC_REG (DR_REG_UART_BASE + 0x5c)
#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
* This register is used to configure the content of at_cmd char.
*/
@ -1305,7 +1305,7 @@ extern "C" {
/** UART_MEM_CONF_REG register
* UART memory power configuration
*/
#define UART_MEM_CONF_REG (DR_REG_UART_BASE + 0x60)
#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
* Set this bit to force power down UART memory.
*/
@ -1324,7 +1324,7 @@ extern "C" {
/** UART_TOUT_CONF_SYNC_REG register
* UART threshold and allocation configuration
*/
#define UART_TOUT_CONF_SYNC_REG (DR_REG_UART_BASE + 0x64)
#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
* This is the enble bit for uart receiver's timeout function.
*/
@ -1352,7 +1352,7 @@ extern "C" {
/** UART_MEM_TX_STATUS_REG register
* Tx-SRAM write and read offset address.
*/
#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x68)
#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
* This register stores the offset write address in Tx-SRAM.
*/
@ -1371,7 +1371,7 @@ extern "C" {
/** UART_MEM_RX_STATUS_REG register
* Rx-SRAM write and read offset address.
*/
#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x6c)
#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
* This register stores the offset read address in RX-SRAM.
*/
@ -1390,7 +1390,7 @@ extern "C" {
/** UART_FSM_STATUS_REG register
* UART transmit and receive status.
*/
#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x70)
#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
* This is the status register of receiver.
*/
@ -1409,7 +1409,7 @@ extern "C" {
/** UART_POSPULSE_REG register
* Autobaud high pulse register
*/
#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x74)
#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the minimal input clock count between two positive edges. It
* is used in boudrate-detect process.
@ -1422,7 +1422,7 @@ extern "C" {
/** UART_NEGPULSE_REG register
* Autobaud low pulse register
*/
#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x78)
#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the minimal input clock count between two negative edges. It
* is used in boudrate-detect process.
@ -1435,7 +1435,7 @@ extern "C" {
/** UART_LOWPULSE_REG register
* Autobaud minimum low pulse duration register
*/
#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x7c)
#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the value of the minimum duration time of the low level pulse.
* It is used in baud rate-detect process.
@ -1448,7 +1448,7 @@ extern "C" {
/** UART_HIGHPULSE_REG register
* Autobaud minimum high pulse duration register
*/
#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x80)
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the value of the maxinum duration time for the high level
* pulse. It is used in baud rate-detect process.
@ -1461,7 +1461,7 @@ extern "C" {
/** UART_RXD_CNT_REG register
* Autobaud edge change count register
*/
#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x84)
#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
* This register stores the count of rxd edge change. It is used in baud rate-detect
* process.
@ -1474,7 +1474,7 @@ extern "C" {
/** UART_CLK_CONF_REG register
* UART core clock configuration
*/
#define UART_CLK_CONF_REG (DR_REG_UART_BASE + 0x88)
#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/
@ -1507,7 +1507,7 @@ extern "C" {
/** UART_DATE_REG register
* UART Version register
*/
#define UART_DATE_REG (DR_REG_UART_BASE + 0x8c)
#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
/** UART_DATE : R/W; bitpos: [31:0]; default: 35680848;
* This is the version register.
*/
@ -1519,7 +1519,7 @@ extern "C" {
/** UART_AFIFO_STATUS_REG register
* UART AFIFO Status
*/
#define UART_AFIFO_STATUS_REG (DR_REG_UART_BASE + 0x90)
#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
* Full signal of APB TX AFIFO.
*/
@ -1552,7 +1552,7 @@ extern "C" {
/** UART_REG_UPDATE_REG register
* UART Registers Configuration Update register
*/
#define UART_REG_UPDATE_REG (DR_REG_UART_BASE + 0x98)
#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
* Software write 1 would synchronize registers into UART Core clock domain and would
* be cleared by hardware after synchronization is done.
@ -1565,7 +1565,7 @@ extern "C" {
/** UART_ID_REG register
* UART ID register
*/
#define UART_ID_REG (DR_REG_UART_BASE + 0x9c)
#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
* This register is used to configure the uart_id.
*/

2
components/soc/esp32c5/include/soc/uart_struct.h
View File

@ -1216,7 +1216,7 @@ typedef union {
} uart_id_reg_t;
typedef struct {
typedef struct uart_dev_t {
volatile uart_fifo_reg_t fifo;
volatile uart_int_raw_reg_t int_raw;
volatile uart_int_st_reg_t int_st;

208
components/soc/esp32c5/include/soc/uhci_struct.h
View File

@ -238,201 +238,33 @@ typedef union {
uint32_t val;
} uhci_quick_sent_reg_t;
/** Type of reg_q0_word0 register
* UHCI Q0_WORD0 Quick Send Register
/** Type of reg_qn_word0 register
* UHCI QN_WORD0 Quick Send Register
*/
typedef union {
struct {
/** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
/** send_word0 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q0_word0:32;
uint32_t send_word0:32;
};
uint32_t val;
} uhci_reg_q0_word0_reg_t;
} uhci_reg_qn_word0_reg_t;
/** Type of reg_q0_word1 register
* UHCI Q0_WORD1 Quick Send Register
/** Type of reg_qn_word1 register
* UHCI QN_WORD1 Quick Send Register
*/
typedef union {
struct {
/** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
/** send_word1 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q0_word1:32;
uint32_t send_word1:32;
};
uint32_t val;
} uhci_reg_q0_word1_reg_t;
/** Type of reg_q1_word0 register
* UHCI Q1_WORD0 Quick Send Register
*/
typedef union {
struct {
/** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q1_word0:32;
};
uint32_t val;
} uhci_reg_q1_word0_reg_t;
/** Type of reg_q1_word1 register
* UHCI Q1_WORD1 Quick Send Register
*/
typedef union {
struct {
/** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q1_word1:32;
};
uint32_t val;
} uhci_reg_q1_word1_reg_t;
/** Type of reg_q2_word0 register
* UHCI Q2_WORD0 Quick Send Register
*/
typedef union {
struct {
/** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q2_word0:32;
};
uint32_t val;
} uhci_reg_q2_word0_reg_t;
/** Type of reg_q2_word1 register
* UHCI Q2_WORD1 Quick Send Register
*/
typedef union {
struct {
/** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q2_word1:32;
};
uint32_t val;
} uhci_reg_q2_word1_reg_t;
/** Type of reg_q3_word0 register
* UHCI Q3_WORD0 Quick Send Register
*/
typedef union {
struct {
/** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q3_word0:32;
};
uint32_t val;
} uhci_reg_q3_word0_reg_t;
/** Type of reg_q3_word1 register
* UHCI Q3_WORD1 Quick Send Register
*/
typedef union {
struct {
/** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q3_word1:32;
};
uint32_t val;
} uhci_reg_q3_word1_reg_t;
/** Type of reg_q4_word0 register
* UHCI Q4_WORD0 Quick Send Register
*/
typedef union {
struct {
/** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q4_word0:32;
};
uint32_t val;
} uhci_reg_q4_word0_reg_t;
/** Type of reg_q4_word1 register
* UHCI Q4_WORD1 Quick Send Register
*/
typedef union {
struct {
/** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q4_word1:32;
};
uint32_t val;
} uhci_reg_q4_word1_reg_t;
/** Type of reg_q5_word0 register
* UHCI Q5_WORD0 Quick Send Register
*/
typedef union {
struct {
/** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q5_word0:32;
};
uint32_t val;
} uhci_reg_q5_word0_reg_t;
/** Type of reg_q5_word1 register
* UHCI Q5_WORD1 Quick Send Register
*/
typedef union {
struct {
/** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q5_word1:32;
};
uint32_t val;
} uhci_reg_q5_word1_reg_t;
/** Type of reg_q6_word0 register
* UHCI Q6_WORD0 Quick Send Register
*/
typedef union {
struct {
/** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q6_word0:32;
};
uint32_t val;
} uhci_reg_q6_word0_reg_t;
/** Type of reg_q6_word1 register
* UHCI Q6_WORD1 Quick Send Register
*/
typedef union {
struct {
/** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
* Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
* UHCI_SINGLE_SEND_NUM.
*/
uint32_t send_q6_word1:32;
};
uint32_t val;
} uhci_reg_q6_word1_reg_t;
} uhci_reg_qn_word1_reg_t;
/** Type of esc_conf0 register
* UHCI Escapes Sequence Configuration Register0
@ -797,7 +629,7 @@ typedef union {
} uhci_date_reg_t;
typedef struct {
typedef struct uhci_dev_t {
volatile uhci_conf0_reg_t conf0;
volatile uhci_int_raw_reg_t int_raw;
volatile uhci_int_st_reg_t int_st;
@ -811,20 +643,10 @@ typedef struct {
volatile uhci_ack_num_reg_t ack_num;
volatile uhci_rx_head_reg_t rx_head;
volatile uhci_quick_sent_reg_t quick_sent;
volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
volatile struct {
uhci_reg_qn_word0_reg_t word0;
uhci_reg_qn_word1_reg_t word1;
} q_data[7];
volatile uhci_esc_conf0_reg_t esc_conf0;
volatile uhci_esc_conf1_reg_t esc_conf1;
volatile uhci_esc_conf2_reg_t esc_conf2;

421
components/soc/esp32c5/include/soc/usb_otg_misc_reg.h
View File

@ -1,421 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** USB_OTG_MISC_CLK_EN0_REG register
* Reserved
*/
#define USB_OTG_MISC_CLK_EN0_REG (DR_REG_USB_OTG_MISC_BASE + 0x0)
/** USB_OTG_MISC_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* Reserved
*/
#define USB_OTG_MISC_REG_CLK_EN (BIT(0))
#define USB_OTG_MISC_REG_CLK_EN_M (USB_OTG_MISC_REG_CLK_EN_V << USB_OTG_MISC_REG_CLK_EN_S)
#define USB_OTG_MISC_REG_CLK_EN_V 0x00000001U
#define USB_OTG_MISC_REG_CLK_EN_S 0
/** USB_OTG_MISC_DATE0_REG register
* Reserved
*/
#define USB_OTG_MISC_DATE0_REG (DR_REG_USB_OTG_MISC_BASE + 0x4)
/** USB_OTG_MISC_REG_DATE : R/W; bitpos: [31:0]; default: 23050900;
* Reserved
*/
#define USB_OTG_MISC_REG_DATE 0xFFFFFFFFU
#define USB_OTG_MISC_REG_DATE_M (USB_OTG_MISC_REG_DATE_V << USB_OTG_MISC_REG_DATE_S)
#define USB_OTG_MISC_REG_DATE_V 0xFFFFFFFFU
#define USB_OTG_MISC_REG_DATE_S 0
/** USB_OTG_MISC_CORE_AHB_CTRL0_REG register
* USB OTG core AHB bus control.
*/
#define USB_OTG_MISC_CORE_AHB_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x8)
/** USB_OTG_MISC_REG_CORE_S_HBIGENDIAN : R/W; bitpos: [0]; default: 0;
* USB OTG core AHB slave big endian mode. 1'b0: Little, 1'b1: Big.
*/
#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN (BIT(0))
#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_M (USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_V << USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_S)
#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_V 0x00000001U
#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_S 0
/** USB_OTG_MISC_REG_CORE_M_HBIGENDIAN : R/W; bitpos: [1]; default: 0;
* USB OTG core AHB master big endian mode. 1'b0: Little, 1'b1: Big.
*/
#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN (BIT(1))
#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_M (USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_V << USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_S)
#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_V 0x00000001U
#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_S 1
/** USB_OTG_MISC_DFIFO_CTRL0_REG register
* dfifo control.
*/
#define USB_OTG_MISC_DFIFO_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0xc)
/** USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
* enable dfifo hclk always on.
*/
#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON (BIT(0))
#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_M (USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_V << USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_S)
#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_V 0x00000001U
#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_S 0
/** USB_OTG_MISC_CORE_SS_CTRL0_REG register
* USB OTG core simulation scale control.
*/
#define USB_OTG_MISC_CORE_SS_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x10)
/** USB_OTG_MISC_REG_SS_SCALEDOWN_MODE : R/W; bitpos: [1:0]; default: 0;
* USB OTG 2.0 Core Simulation Scale Down Mode, Scale-down timing values, resulting in
* <faster> simulations.
*/
#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE 0x00000003U
#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_M (USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_V << USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_S)
#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_V 0x00000003U
#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_S 0
/** USB_OTG_MISC_PHY_CTRL0_REG register
* USB PHY auxiliary control.
*/
#define USB_OTG_MISC_PHY_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x14)
/** USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE : R/W; bitpos: [0]; default: 0;
* Use software to override phy_pll_en.
*/
#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE (BIT(0))
#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_M (USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_V << USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_S)
#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_S 0
/** USB_OTG_MISC_REG_PHY_PLL_EN : R/W; bitpos: [1]; default: 0;
* Software phy_pll_en.
*/
#define USB_OTG_MISC_REG_PHY_PLL_EN (BIT(1))
#define USB_OTG_MISC_REG_PHY_PLL_EN_M (USB_OTG_MISC_REG_PHY_PLL_EN_V << USB_OTG_MISC_REG_PHY_PLL_EN_S)
#define USB_OTG_MISC_REG_PHY_PLL_EN_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_PLL_EN_S 1
/** USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE : R/W; bitpos: [2]; default: 0;
* Use software to override phy_suspendm.
*/
#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE (BIT(2))
#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_M (USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_V << USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_S)
#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_S 2
/** USB_OTG_MISC_REG_PHY_SUSPENDM : R/W; bitpos: [3]; default: 0;
* Software phy_suspendm.
*/
#define USB_OTG_MISC_REG_PHY_SUSPENDM (BIT(3))
#define USB_OTG_MISC_REG_PHY_SUSPENDM_M (USB_OTG_MISC_REG_PHY_SUSPENDM_V << USB_OTG_MISC_REG_PHY_SUSPENDM_S)
#define USB_OTG_MISC_REG_PHY_SUSPENDM_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_SUSPENDM_S 3
/** USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE : R/W; bitpos: [4]; default: 0;
* Use software to override phy_reset_n.
*/
#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE (BIT(4))
#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_M (USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_V << USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_S)
#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_S 4
/** USB_OTG_MISC_REG_PHY_RESET_N : R/W; bitpos: [5]; default: 0;
* Software phy_reset_n.
*/
#define USB_OTG_MISC_REG_PHY_RESET_N (BIT(5))
#define USB_OTG_MISC_REG_PHY_RESET_N_M (USB_OTG_MISC_REG_PHY_RESET_N_V << USB_OTG_MISC_REG_PHY_RESET_N_S)
#define USB_OTG_MISC_REG_PHY_RESET_N_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_RESET_N_S 5
/** USB_OTG_MISC_REG_PHY_BIST_OK : RO; bitpos: [6]; default: 0;
* USB PHY self test done.
*/
#define USB_OTG_MISC_REG_PHY_BIST_OK (BIT(6))
#define USB_OTG_MISC_REG_PHY_BIST_OK_M (USB_OTG_MISC_REG_PHY_BIST_OK_V << USB_OTG_MISC_REG_PHY_BIST_OK_S)
#define USB_OTG_MISC_REG_PHY_BIST_OK_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_BIST_OK_S 6
/** USB_OTG_MISC_REG_PHY_OTG_SUSPENDM : R/W; bitpos: [7]; default: 0;
* USB PHY otg_suspendm.
*/
#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM (BIT(7))
#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_M (USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_V << USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_S)
#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_S 7
/** USB_OTG_MISC_REG_PHY_REFCLK_MODE : R/W; bitpos: [8]; default: 1;
* Select USB PHY refclk mode. 0: refclk is 25MHz, 1: refclk is 12MHz.
*/
#define USB_OTG_MISC_REG_PHY_REFCLK_MODE (BIT(8))
#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_M (USB_OTG_MISC_REG_PHY_REFCLK_MODE_V << USB_OTG_MISC_REG_PHY_REFCLK_MODE_S)
#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_S 8
/** USB_OTG_MISC_REG_PHY_SELF_TEST : R/W; bitpos: [9]; default: 0;
* USB PHY self test enable.
*/
#define USB_OTG_MISC_REG_PHY_SELF_TEST (BIT(9))
#define USB_OTG_MISC_REG_PHY_SELF_TEST_M (USB_OTG_MISC_REG_PHY_SELF_TEST_V << USB_OTG_MISC_REG_PHY_SELF_TEST_S)
#define USB_OTG_MISC_REG_PHY_SELF_TEST_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_SELF_TEST_S 9
/** USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE : R/W; bitpos: [10]; default: 0;
* USB PHY tx bitstuff enable.
*/
#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE (BIT(10))
#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_M (USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_V << USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_S)
#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_S 10
/** USB_OTG_MISC_PHY_DBG_PROBE0_REG register
* USB PHY debug probe register.
*/
#define USB_OTG_MISC_PHY_DBG_PROBE0_REG (DR_REG_USB_OTG_MISC_BASE + 0x18)
/** USB_OTG_MISC_REG_PHY_DBG_LINE_STATE : RO; bitpos: [1:0]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE 0x00000003U
#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_M (USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_V << USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_S)
#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_V 0x00000003U
#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_S 0
/** USB_OTG_MISC_REG_PHY_DBG_RX_VALID : RO; bitpos: [2]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID (BIT(2))
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_M (USB_OTG_MISC_REG_PHY_DBG_RX_VALID_V << USB_OTG_MISC_REG_PHY_DBG_RX_VALID_S)
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_S 2
/** USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH : RO; bitpos: [3]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH (BIT(3))
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_M (USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_V << USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_S)
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_S 3
/** USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE : RO; bitpos: [4]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE (BIT(4))
#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_M (USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_V << USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_S)
#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_S 4
/** USB_OTG_MISC_REG_PHY_DBG_RX_ERROR : RO; bitpos: [5]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR (BIT(5))
#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_M (USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_V << USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_S)
#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_S 5
/** USB_OTG_MISC_REG_PHY_DBG_TX_READY : RO; bitpos: [6]; default: 0;
* Reserved.
*/
#define USB_OTG_MISC_REG_PHY_DBG_TX_READY (BIT(6))
#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_M (USB_OTG_MISC_REG_PHY_DBG_TX_READY_V << USB_OTG_MISC_REG_PHY_DBG_TX_READY_S)
#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_V 0x00000001U
#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_S 6
/** USB_OTG_MISC_PHY_INT_RAW_REG register
* Interrupt raw of USB PHY interrupt register.
*/
#define USB_OTG_MISC_PHY_INT_RAW_REG (DR_REG_USB_OTG_MISC_BASE + 0x1c)
/** USB_OTG_MISC_REG_IDDIG_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* Interrupt raw of reg_iddig_int_st
*/
#define USB_OTG_MISC_REG_IDDIG_INT_RAW (BIT(0))
#define USB_OTG_MISC_REG_IDDIG_INT_RAW_M (USB_OTG_MISC_REG_IDDIG_INT_RAW_V << USB_OTG_MISC_REG_IDDIG_INT_RAW_S)
#define USB_OTG_MISC_REG_IDDIG_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_IDDIG_INT_RAW_S 0
/** USB_OTG_MISC_REG_VBUS_VALID_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* Interrupt raw of reg_vbus_valid_int_st
*/
#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW (BIT(1))
#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_M (USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_V << USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_S)
#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_S 1
/** USB_OTG_MISC_REG_SESSVALID_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* Interrupt raw of reg_sessvalid_int_st
*/
#define USB_OTG_MISC_REG_SESSVALID_INT_RAW (BIT(2))
#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_M (USB_OTG_MISC_REG_SESSVALID_INT_RAW_V << USB_OTG_MISC_REG_SESSVALID_INT_RAW_S)
#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_S 2
/** USB_OTG_MISC_REG_SESSEND_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
* Interrupt raw of reg_sessend_int_st
*/
#define USB_OTG_MISC_REG_SESSEND_INT_RAW (BIT(3))
#define USB_OTG_MISC_REG_SESSEND_INT_RAW_M (USB_OTG_MISC_REG_SESSEND_INT_RAW_V << USB_OTG_MISC_REG_SESSEND_INT_RAW_S)
#define USB_OTG_MISC_REG_SESSEND_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_SESSEND_INT_RAW_S 3
/** USB_OTG_MISC_REG_BVALID_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
* Interrupt raw of reg_bvalid_int_st
*/
#define USB_OTG_MISC_REG_BVALID_INT_RAW (BIT(4))
#define USB_OTG_MISC_REG_BVALID_INT_RAW_M (USB_OTG_MISC_REG_BVALID_INT_RAW_V << USB_OTG_MISC_REG_BVALID_INT_RAW_S)
#define USB_OTG_MISC_REG_BVALID_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_BVALID_INT_RAW_S 4
/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
* Interrupt raw of reg_host_disconnect_int_st
*/
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW (BIT(5))
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_S)
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_V 0x00000001U
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_S 5
/** USB_OTG_MISC_PHY_INT_CLR_REG register
* Interrupt clear of USB PHY interrupt register.
*/
#define USB_OTG_MISC_PHY_INT_CLR_REG (DR_REG_USB_OTG_MISC_BASE + 0x20)
/** USB_OTG_MISC_REG_IDDIG_INT_CLR : WT; bitpos: [0]; default: 0;
* Interrupt clear of reg_iddig_int_st
*/
#define USB_OTG_MISC_REG_IDDIG_INT_CLR (BIT(0))
#define USB_OTG_MISC_REG_IDDIG_INT_CLR_M (USB_OTG_MISC_REG_IDDIG_INT_CLR_V << USB_OTG_MISC_REG_IDDIG_INT_CLR_S)
#define USB_OTG_MISC_REG_IDDIG_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_IDDIG_INT_CLR_S 0
/** USB_OTG_MISC_REG_VBUS_VALID_INT_CLR : WT; bitpos: [1]; default: 0;
* Interrupt clear of reg_vbus_valid_int_st
*/
#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR (BIT(1))
#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_M (USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_V << USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_S)
#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_S 1
/** USB_OTG_MISC_REG_SESSVALID_INT_CLR : WT; bitpos: [2]; default: 0;
* Interrupt clear of reg_sessvalid_int_st
*/
#define USB_OTG_MISC_REG_SESSVALID_INT_CLR (BIT(2))
#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_M (USB_OTG_MISC_REG_SESSVALID_INT_CLR_V << USB_OTG_MISC_REG_SESSVALID_INT_CLR_S)
#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_S 2
/** USB_OTG_MISC_REG_SESSEND_INT_CLR : WT; bitpos: [3]; default: 0;
* Interrupt clear of reg_sessend_int_st
*/
#define USB_OTG_MISC_REG_SESSEND_INT_CLR (BIT(3))
#define USB_OTG_MISC_REG_SESSEND_INT_CLR_M (USB_OTG_MISC_REG_SESSEND_INT_CLR_V << USB_OTG_MISC_REG_SESSEND_INT_CLR_S)
#define USB_OTG_MISC_REG_SESSEND_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_SESSEND_INT_CLR_S 3
/** USB_OTG_MISC_REG_BVALID_INT_CLR : WT; bitpos: [4]; default: 0;
* Interrupt clear of reg_bvalid_int_st
*/
#define USB_OTG_MISC_REG_BVALID_INT_CLR (BIT(4))
#define USB_OTG_MISC_REG_BVALID_INT_CLR_M (USB_OTG_MISC_REG_BVALID_INT_CLR_V << USB_OTG_MISC_REG_BVALID_INT_CLR_S)
#define USB_OTG_MISC_REG_BVALID_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_BVALID_INT_CLR_S 4
/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR : WT; bitpos: [5]; default: 0;
* Interrupt clear of reg_host_disconnect_int_st
*/
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR (BIT(5))
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_S)
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_S 5
/** USB_OTG_MISC_PHY_INT_ENA_REG register
* Interrupt enable of USB PHY interrupt register.
*/
#define USB_OTG_MISC_PHY_INT_ENA_REG (DR_REG_USB_OTG_MISC_BASE + 0x24)
/** USB_OTG_MISC_REG_IDDIG_INT_ENA : R/W; bitpos: [0]; default: 0;
* Interrupt enable of reg_iddig_int_st
*/
#define USB_OTG_MISC_REG_IDDIG_INT_ENA (BIT(0))
#define USB_OTG_MISC_REG_IDDIG_INT_ENA_M (USB_OTG_MISC_REG_IDDIG_INT_ENA_V << USB_OTG_MISC_REG_IDDIG_INT_ENA_S)
#define USB_OTG_MISC_REG_IDDIG_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_IDDIG_INT_ENA_S 0
/** USB_OTG_MISC_REG_VBUS_VALID_INT_ENA : R/W; bitpos: [1]; default: 0;
* Interrupt enable of reg_vbus_valid_int_st
*/
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA (BIT(1))
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_M (USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_V << USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_S)
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_S 1
/** USB_OTG_MISC_REG_SESSVALID_INT_ENA : R/W; bitpos: [2]; default: 0;
* Interrupt enable of reg_sessvalid_int_st
*/
#define USB_OTG_MISC_REG_SESSVALID_INT_ENA (BIT(2))
#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_M (USB_OTG_MISC_REG_SESSVALID_INT_ENA_V << USB_OTG_MISC_REG_SESSVALID_INT_ENA_S)
#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_S 2
/** USB_OTG_MISC_REG_SESSEND_INT_ENA : R/W; bitpos: [3]; default: 0;
* Interrupt enable of reg_sessend_int_st
*/
#define USB_OTG_MISC_REG_SESSEND_INT_ENA (BIT(3))
#define USB_OTG_MISC_REG_SESSEND_INT_ENA_M (USB_OTG_MISC_REG_SESSEND_INT_ENA_V << USB_OTG_MISC_REG_SESSEND_INT_ENA_S)
#define USB_OTG_MISC_REG_SESSEND_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_SESSEND_INT_ENA_S 3
/** USB_OTG_MISC_REG_BVALID_INT_ENA : R/W; bitpos: [4]; default: 0;
* Interrupt enable of reg_bvalid_int_st
*/
#define USB_OTG_MISC_REG_BVALID_INT_ENA (BIT(4))
#define USB_OTG_MISC_REG_BVALID_INT_ENA_M (USB_OTG_MISC_REG_BVALID_INT_ENA_V << USB_OTG_MISC_REG_BVALID_INT_ENA_S)
#define USB_OTG_MISC_REG_BVALID_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_BVALID_INT_ENA_S 4
/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA : R/W; bitpos: [5]; default: 0;
* Interrupt enable of reg_host_disconnect_int_st
*/
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA (BIT(5))
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_S)
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_V 0x00000001U
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_S 5
/** USB_OTG_MISC_PHY_INT_ST_REG register
* USB PHY interrupt register.
*/
#define USB_OTG_MISC_PHY_INT_ST_REG (DR_REG_USB_OTG_MISC_BASE + 0x28)
/** USB_OTG_MISC_REG_IDDIG_INT_ST : RO; bitpos: [0]; default: 0;
* indicates connected plug is a mini-A or mini-B.
*/
#define USB_OTG_MISC_REG_IDDIG_INT_ST (BIT(0))
#define USB_OTG_MISC_REG_IDDIG_INT_ST_M (USB_OTG_MISC_REG_IDDIG_INT_ST_V << USB_OTG_MISC_REG_IDDIG_INT_ST_S)
#define USB_OTG_MISC_REG_IDDIG_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_IDDIG_INT_ST_S 0
/** USB_OTG_MISC_REG_VBUS_VALID_INT_ST : RO; bitpos: [1]; default: 0;
* indicates if the voltage on VBUS is at a valid level for operation, 0: VBUS < 4.4V,
* 1: VBUS > 4.75V.
*/
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST (BIT(1))
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_M (USB_OTG_MISC_REG_VBUS_VALID_INT_ST_V << USB_OTG_MISC_REG_VBUS_VALID_INT_ST_S)
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_S 1
/** USB_OTG_MISC_REG_SESSVALID_INT_ST : RO; bitpos: [2]; default: 0;
* indicates if the session for an peripheral is valid, 0: VBUS < 0.8V, 1: VBUS > 2.0V.
*/
#define USB_OTG_MISC_REG_SESSVALID_INT_ST (BIT(2))
#define USB_OTG_MISC_REG_SESSVALID_INT_ST_M (USB_OTG_MISC_REG_SESSVALID_INT_ST_V << USB_OTG_MISC_REG_SESSVALID_INT_ST_S)
#define USB_OTG_MISC_REG_SESSVALID_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_SESSVALID_INT_ST_S 2
/** USB_OTG_MISC_REG_SESSEND_INT_ST : RO; bitpos: [3]; default: 0;
* indicates the voltage on VBUS, 1: VBUS < 0.2V, 0: VBUS > 0.8V.
*/
#define USB_OTG_MISC_REG_SESSEND_INT_ST (BIT(3))
#define USB_OTG_MISC_REG_SESSEND_INT_ST_M (USB_OTG_MISC_REG_SESSEND_INT_ST_V << USB_OTG_MISC_REG_SESSEND_INT_ST_S)
#define USB_OTG_MISC_REG_SESSEND_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_SESSEND_INT_ST_S 3
/** USB_OTG_MISC_REG_BVALID_INT_ST : RO; bitpos: [4]; default: 0;
* indicates the voltage on VBUS, 0: VBUS < 0.8V, 1: VBUS > 4.0V.
*/
#define USB_OTG_MISC_REG_BVALID_INT_ST (BIT(4))
#define USB_OTG_MISC_REG_BVALID_INT_ST_M (USB_OTG_MISC_REG_BVALID_INT_ST_V << USB_OTG_MISC_REG_BVALID_INT_ST_S)
#define USB_OTG_MISC_REG_BVALID_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_BVALID_INT_ST_S 4
/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST : RO; bitpos: [5]; default: 0;
* host disconnect.
*/
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST (BIT(5))
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_M (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_S)
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_V 0x00000001U
#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_S 5
/** USB_OTG_MISC_WAKEUP_CTRL0_REG register
* USB wakeup control.
*/
#define USB_OTG_MISC_WAKEUP_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x2c)
/** USB_OTG_MISC_REG_USB_IN_SUSPEND : R/W; bitpos: [0]; default: 0;
* indicate usb is in suspend state
*/
#define USB_OTG_MISC_REG_USB_IN_SUSPEND (BIT(0))
#define USB_OTG_MISC_REG_USB_IN_SUSPEND_M (USB_OTG_MISC_REG_USB_IN_SUSPEND_V << USB_OTG_MISC_REG_USB_IN_SUSPEND_S)
#define USB_OTG_MISC_REG_USB_IN_SUSPEND_V 0x00000001U
#define USB_OTG_MISC_REG_USB_IN_SUSPEND_S 0
/** USB_OTG_MISC_REG_USB_WKUP_CLR : WT; bitpos: [1]; default: 0;
* clear usb wakeup signals.
*/
#define USB_OTG_MISC_REG_USB_WKUP_CLR (BIT(1))
#define USB_OTG_MISC_REG_USB_WKUP_CLR_M (USB_OTG_MISC_REG_USB_WKUP_CLR_V << USB_OTG_MISC_REG_USB_WKUP_CLR_S)
#define USB_OTG_MISC_REG_USB_WKUP_CLR_V 0x00000001U
#define USB_OTG_MISC_REG_USB_WKUP_CLR_S 1
#ifdef __cplusplus
}
#endif

370
components/soc/esp32c5/include/soc/usb_otg_misc_struct.h
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@ -1,370 +0,0 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: clk_en */
/** Type of clk_en0 register
* Reserved
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t reg_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_otg_misc_clk_en0_reg_t;
/** Group: date */
/** Type of date0 register
* Reserved
*/
typedef union {
struct {
/** reg_date : R/W; bitpos: [31:0]; default: 23050900;
* Reserved
*/
uint32_t reg_date:32;
};
uint32_t val;
} usb_otg_misc_date0_reg_t;
/** Group: core_ahb_ctrl */
/** Type of core_ahb_ctrl0 register
* USB OTG core AHB bus control.
*/
typedef union {
struct {
/** reg_core_s_hbigendian : R/W; bitpos: [0]; default: 0;
* USB OTG core AHB slave big endian mode. 1'b0: Little, 1'b1: Big.
*/
uint32_t reg_core_s_hbigendian:1;
/** reg_core_m_hbigendian : R/W; bitpos: [1]; default: 0;
* USB OTG core AHB master big endian mode. 1'b0: Little, 1'b1: Big.
*/
uint32_t reg_core_m_hbigendian:1;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_otg_misc_core_ahb_ctrl0_reg_t;
/** Group: dfifo_ctrl */
/** Type of dfifo_ctrl0 register
* dfifo control.
*/
typedef union {
struct {
/** reg_dfifo_hclk_force_on : R/W; bitpos: [0]; default: 0;
* enable dfifo hclk always on.
*/
uint32_t reg_dfifo_hclk_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_otg_misc_dfifo_ctrl0_reg_t;
/** Group: core_ss_ctrl */
/** Type of core_ss_ctrl0 register
* USB OTG core simulation scale control.
*/
typedef union {
struct {
/** reg_ss_scaledown_mode : R/W; bitpos: [1:0]; default: 0;
* USB OTG 2.0 Core Simulation Scale Down Mode, Scale-down timing values, resulting in
* <faster> simulations.
*/
uint32_t reg_ss_scaledown_mode:2;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_otg_misc_core_ss_ctrl0_reg_t;
/** Group: phy_ctrl */
/** Type of phy_ctrl0 register
* USB PHY auxiliary control.
*/
typedef union {
struct {
/** reg_phy_pll_en_override : R/W; bitpos: [0]; default: 0;
* Use software to override phy_pll_en.
*/
uint32_t reg_phy_pll_en_override:1;
/** reg_phy_pll_en : R/W; bitpos: [1]; default: 0;
* Software phy_pll_en.
*/
uint32_t reg_phy_pll_en:1;
/** reg_phy_suspendm_override : R/W; bitpos: [2]; default: 0;
* Use software to override phy_suspendm.
*/
uint32_t reg_phy_suspendm_override:1;
/** reg_phy_suspendm : R/W; bitpos: [3]; default: 0;
* Software phy_suspendm.
*/
uint32_t reg_phy_suspendm:1;
/** reg_phy_reset_n_override : R/W; bitpos: [4]; default: 0;
* Use software to override phy_reset_n.
*/
uint32_t reg_phy_reset_n_override:1;
/** reg_phy_reset_n : R/W; bitpos: [5]; default: 0;
* Software phy_reset_n.
*/
uint32_t reg_phy_reset_n:1;
/** reg_phy_bist_ok : RO; bitpos: [6]; default: 0;
* USB PHY self test done.
*/
uint32_t reg_phy_bist_ok:1;
/** reg_phy_otg_suspendm : R/W; bitpos: [7]; default: 0;
* USB PHY otg_suspendm.
*/
uint32_t reg_phy_otg_suspendm:1;
/** reg_phy_refclk_mode : R/W; bitpos: [8]; default: 1;
* Select USB PHY refclk mode. 0: refclk is 25MHz, 1: refclk is 12MHz.
*/
uint32_t reg_phy_refclk_mode:1;
/** reg_phy_self_test : R/W; bitpos: [9]; default: 0;
* USB PHY self test enable.
*/
uint32_t reg_phy_self_test:1;
/** reg_phy_txbitstuff_enable : R/W; bitpos: [10]; default: 0;
* USB PHY tx bitstuff enable.
*/
uint32_t reg_phy_txbitstuff_enable:1;
uint32_t reserved_11:21;
};
uint32_t val;
} usb_otg_misc_phy_ctrl0_reg_t;
/** Group: phy_dbg_probe */
/** Type of phy_dbg_probe0 register
* USB PHY debug probe register.
*/
typedef union {
struct {
/** reg_phy_dbg_line_state : RO; bitpos: [1:0]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_line_state:2;
/** reg_phy_dbg_rx_valid : RO; bitpos: [2]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_rx_valid:1;
/** reg_phy_dbg_rx_validh : RO; bitpos: [3]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_rx_validh:1;
/** reg_phy_dbg_rx_active : RO; bitpos: [4]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_rx_active:1;
/** reg_phy_dbg_rx_error : RO; bitpos: [5]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_rx_error:1;
/** reg_phy_dbg_tx_ready : RO; bitpos: [6]; default: 0;
* Reserved.
*/
uint32_t reg_phy_dbg_tx_ready:1;
uint32_t reserved_7:25;
};
uint32_t val;
} usb_otg_misc_phy_dbg_probe0_reg_t;
/** Group: Interrupt */
/** Type of phy_int_raw register
* Interrupt raw of USB PHY interrupt register.
*/
typedef union {
struct {
/** reg_iddig_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* Interrupt raw of reg_iddig_int_st
*/
uint32_t reg_iddig_int_raw:1;
/** reg_vbus_valid_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* Interrupt raw of reg_vbus_valid_int_st
*/
uint32_t reg_vbus_valid_int_raw:1;
/** reg_sessvalid_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* Interrupt raw of reg_sessvalid_int_st
*/
uint32_t reg_sessvalid_int_raw:1;
/** reg_sessend_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
* Interrupt raw of reg_sessend_int_st
*/
uint32_t reg_sessend_int_raw:1;
/** reg_bvalid_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
* Interrupt raw of reg_bvalid_int_st
*/
uint32_t reg_bvalid_int_raw:1;
/** reg_host_disconnect_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
* Interrupt raw of reg_host_disconnect_int_st
*/
uint32_t reg_host_disconnect_int_raw:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_otg_misc_phy_int_raw_reg_t;
/** Type of phy_int_clr register
* Interrupt clear of USB PHY interrupt register.
*/
typedef union {
struct {
/** reg_iddig_int_clr : WT; bitpos: [0]; default: 0;
* Interrupt clear of reg_iddig_int_st
*/
uint32_t reg_iddig_int_clr:1;
/** reg_vbus_valid_int_clr : WT; bitpos: [1]; default: 0;
* Interrupt clear of reg_vbus_valid_int_st
*/
uint32_t reg_vbus_valid_int_clr:1;
/** reg_sessvalid_int_clr : WT; bitpos: [2]; default: 0;
* Interrupt clear of reg_sessvalid_int_st
*/
uint32_t reg_sessvalid_int_clr:1;
/** reg_sessend_int_clr : WT; bitpos: [3]; default: 0;
* Interrupt clear of reg_sessend_int_st
*/
uint32_t reg_sessend_int_clr:1;
/** reg_bvalid_int_clr : WT; bitpos: [4]; default: 0;
* Interrupt clear of reg_bvalid_int_st
*/
uint32_t reg_bvalid_int_clr:1;
/** reg_host_disconnect_int_clr : WT; bitpos: [5]; default: 0;
* Interrupt clear of reg_host_disconnect_int_st
*/
uint32_t reg_host_disconnect_int_clr:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_otg_misc_phy_int_clr_reg_t;
/** Type of phy_int_ena register
* Interrupt enable of USB PHY interrupt register.
*/
typedef union {
struct {
/** reg_iddig_int_ena : R/W; bitpos: [0]; default: 0;
* Interrupt enable of reg_iddig_int_st
*/
uint32_t reg_iddig_int_ena:1;
/** reg_vbus_valid_int_ena : R/W; bitpos: [1]; default: 0;
* Interrupt enable of reg_vbus_valid_int_st
*/
uint32_t reg_vbus_valid_int_ena:1;
/** reg_sessvalid_int_ena : R/W; bitpos: [2]; default: 0;
* Interrupt enable of reg_sessvalid_int_st
*/
uint32_t reg_sessvalid_int_ena:1;
/** reg_sessend_int_ena : R/W; bitpos: [3]; default: 0;
* Interrupt enable of reg_sessend_int_st
*/
uint32_t reg_sessend_int_ena:1;
/** reg_bvalid_int_ena : R/W; bitpos: [4]; default: 0;
* Interrupt enable of reg_bvalid_int_st
*/
uint32_t reg_bvalid_int_ena:1;
/** reg_host_disconnect_int_ena : R/W; bitpos: [5]; default: 0;
* Interrupt enable of reg_host_disconnect_int_st
*/
uint32_t reg_host_disconnect_int_ena:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_otg_misc_phy_int_ena_reg_t;
/** Type of phy_int_st register
* USB PHY interrupt register.
*/
typedef union {
struct {
/** reg_iddig_int_st : RO; bitpos: [0]; default: 0;
* indicates connected plug is a mini-A or mini-B.
*/
uint32_t reg_iddig_int_st:1;
/** reg_vbus_valid_int_st : RO; bitpos: [1]; default: 0;
* indicates if the voltage on VBUS is at a valid level for operation, 0: VBUS < 4.4V,
* 1: VBUS > 4.75V.
*/
uint32_t reg_vbus_valid_int_st:1;
/** reg_sessvalid_int_st : RO; bitpos: [2]; default: 0;
* indicates if the session for an peripheral is valid, 0: VBUS < 0.8V, 1: VBUS > 2.0V.
*/
uint32_t reg_sessvalid_int_st:1;
/** reg_sessend_int_st : RO; bitpos: [3]; default: 0;
* indicates the voltage on VBUS, 1: VBUS < 0.2V, 0: VBUS > 0.8V.
*/
uint32_t reg_sessend_int_st:1;
/** reg_bvalid_int_st : RO; bitpos: [4]; default: 0;
* indicates the voltage on VBUS, 0: VBUS < 0.8V, 1: VBUS > 4.0V.
*/
uint32_t reg_bvalid_int_st:1;
/** reg_host_disconnect_int_st : RO; bitpos: [5]; default: 0;
* host disconnect.
*/
uint32_t reg_host_disconnect_int_st:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_otg_misc_phy_int_st_reg_t;
/** Group: wakeup_ctrl */
/** Type of wakeup_ctrl0 register
* USB wakeup control.
*/
typedef union {
struct {
/** reg_usb_in_suspend : R/W; bitpos: [0]; default: 0;
* indicate usb is in suspend state
*/
uint32_t reg_usb_in_suspend:1;
/** reg_usb_wkup_clr : WT; bitpos: [1]; default: 0;
* clear usb wakeup signals.
*/
uint32_t reg_usb_wkup_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_otg_misc_wakeup_ctrl0_reg_t;
typedef struct {
volatile usb_otg_misc_clk_en0_reg_t clk_en0;
volatile usb_otg_misc_date0_reg_t date0;
volatile usb_otg_misc_core_ahb_ctrl0_reg_t core_ahb_ctrl0;
volatile usb_otg_misc_dfifo_ctrl0_reg_t dfifo_ctrl0;
volatile usb_otg_misc_core_ss_ctrl0_reg_t core_ss_ctrl0;
volatile usb_otg_misc_phy_ctrl0_reg_t phy_ctrl0;
volatile usb_otg_misc_phy_dbg_probe0_reg_t phy_dbg_probe0;
volatile usb_otg_misc_phy_int_raw_reg_t phy_int_raw;
volatile usb_otg_misc_phy_int_clr_reg_t phy_int_clr;
volatile usb_otg_misc_phy_int_ena_reg_t phy_int_ena;
volatile usb_otg_misc_phy_int_st_reg_t phy_int_st;
volatile usb_otg_misc_wakeup_ctrl0_reg_t wakeup_ctrl0;
} usb_otg_misc_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(usb_otg_misc_dev_t) == 0x30, "Invalid size of usb_otg_misc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

2
components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
View File

@ -898,7 +898,7 @@ typedef union {
} usb_serial_jtag_date_reg_t;
typedef struct {
typedef struct usb_serial_jtag_dev_t {
volatile usb_serial_jtag_ep1_reg_t ep1;
volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
volatile usb_serial_jtag_int_raw_reg_t int_raw;

138
components/soc/esp32c5/ld/esp32c5.peripherals.ld
View File

@ -1,78 +1,82 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
PROVIDE ( UART0 = 0x60000000 );
PROVIDE ( UART1 = 0x60001000 );
PROVIDE ( SPIMEM0 = 0x60002000 );
PROVIDE ( SPIMEM1 = 0x60003000 );
PROVIDE ( I2C0 = 0x60004000 );
PROVIDE ( UHCI0 = 0x60005000 );
PROVIDE ( RMT = 0x60006000 );
PROVIDE ( RMTMEM = 0x60006400 );
PROVIDE ( LEDC = 0x60007000 );
PROVIDE ( TIMERG0 = 0x60008000 );
PROVIDE ( TIMERG1 = 0x60009000 );
PROVIDE ( SYSTIMER = 0x6000A000 );
PROVIDE ( TWAI0 = 0x6000B000 );
PROVIDE ( I2S0 = 0x6000C000 );
PROVIDE ( TWAI1 = 0x6000D000 );
PROVIDE ( APB_SARADC = 0x6000E000 );
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
PROVIDE ( UART0 = 0x60000000 );
PROVIDE ( UART1 = 0x60001000 );
PROVIDE ( SPIMEM0 = 0x60002000 );
PROVIDE ( SPIMEM1 = 0x60003000 );
PROVIDE ( I2C0 = 0x60004000 );
PROVIDE ( UHCI0 = 0x60005000 );
PROVIDE ( RMT = 0x60006000 );
PROVIDE ( LEDC = 0x60007000 );
PROVIDE ( TIMERG0 = 0x60008000 );
PROVIDE ( TIMERG1 = 0x60009000 );
PROVIDE ( SYSTIMER = 0x6000A000 );
PROVIDE ( TWAI0 = 0x6000B000 );
PROVIDE ( I2S = 0x6000C000 );
PROVIDE ( TWAI1 = 0x6000D000 );
PROVIDE ( APB_SARADC = 0x6000E000 );
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
PROVIDE ( INTMTX = 0x60010000 );
PROVIDE ( I2C1 = 0x60011000 );
PROVIDE ( PCNT = 0x60012000 );
PROVIDE ( SOC_ETM = 0x60013000 );
PROVIDE ( MCPWM = 0x60014000 );
PROVIDE ( PARL_IO = 0x60015000 );
PROVIDE ( PVT_MONITOR = 0x60019000 );
PROVIDE ( INTMTX = 0x60010000 );
PROVIDE ( ATOMIC_LOCKER = 0x60011000 );
PROVIDE ( PCNT = 0x60012000 );
PROVIDE ( SOC_ETM = 0x60013000 );
PROVIDE ( MCPWM0 = 0x60014000 );
PROVIDE ( PARL_IO = 0x60015000 );
PROVIDE ( HINF = 0x60016000 );
PROVIDE ( SLC = 0x60017000 );
PROVIDE ( HOST = 0x60018000 );
PROVIDE ( PVT_MONITOR = 0x60019000 );
PROVIDE ( GDMA = 0x60080000 );
PROVIDE ( GPSPI2 = 0x60081000 );
PROVIDE ( BITSCRAMBLER = 0x60082000 );
PROVIDE ( KEYMNG = 0x60087000 );
PROVIDE ( AES = 0x60088000 );
PROVIDE ( SHA = 0x60089000 );
PROVIDE ( RSA = 0x6008A000 );
PROVIDE ( ECC = 0x6008B000 );
PROVIDE ( DS = 0x6008C000 );
PROVIDE ( HMAC = 0x6008D000 );
PROVIDE ( ECDSA = 0x6008E000 );
PROVIDE ( GDMA = 0x60080000 );
PROVIDE ( GPSPI2 = 0x60081000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091f00 );
PROVIDE ( SDM = 0x60091f00 );
PROVIDE ( GLITCH_FILTER = 0x60091f30 );
PROVIDE ( GPIO_ETM = 0x60091f60 );
PROVIDE ( MEM_MONITOR = 0x60092000 );
PROVIDE ( PAU = 0x60093000 );
PROVIDE ( HP_SYSTEM = 0x60095000 );
PROVIDE ( PCR = 0x60096000 );
PROVIDE ( TEE = 0x60098000 );
PROVIDE ( HP_APM = 0x60099000 );
PROVIDE ( LP_APM0 = 0x60099800 );
PROVIDE ( MISC = 0x6009F000 );
PROVIDE ( AES = 0x60088000 );
PROVIDE ( SHA = 0x60089000 );
PROVIDE ( RSA = 0x6008A000 );
PROVIDE ( ECC = 0x6008B000 );
PROVIDE ( DS = 0x6008C000 );
PROVIDE ( HMAC = 0x6008D000 );
PROVIDE ( MODEM = 0x600A4000 );
PROVIDE ( MODEM_PWR = 0x600AD000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091f00 );
PROVIDE ( SDM = 0x60091f00 );
PROVIDE ( GLITCH_FILTER = 0x60091f30 );
PROVIDE ( GPIO_ETM = 0x60091f60 );
PROVIDE ( PMU = 0x600B0000 );
PROVIDE ( LP_CLKRST = 0x600B0400 );
PROVIDE ( EFUSE = 0x600B0800 );
PROVIDE ( LP_TIMER = 0x600B0C00 );
PROVIDE ( LP_AON = 0x600B1000 );
PROVIDE ( LP_UART = 0x600B1400 );
PROVIDE ( LP_I2C = 0x600B1800 );
PROVIDE ( LP_WDT = 0x600B1C00 );
PROVIDE ( LP_IO = 0x600B2000 );
PROVIDE ( LP_I2C_ANA_MST = 0x600B2400 );
PROVIDE ( LPPERI = 0x600B2800 );
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
PROVIDE ( HUK = 0x600B3000 );
PROVIDE ( LP_TEE = 0x600B3400 );
PROVIDE ( LP_APM = 0x600B3800 );
PROVIDE ( OTP_DEBUG = 0x600B3C00 );
PROVIDE ( MEM_MONITOR = 0x60092000 );
PROVIDE ( PAU = 0x60093000 );
PROVIDE ( HP_SYSTEM = 0x60095000 );
PROVIDE ( PCR = 0x60096000 );
PROVIDE ( TEE = 0x60098000 );
PROVIDE ( HP_APM = 0x60099000 );
PROVIDE ( IEEE802154 = 0x600A3000 );
PROVIDE ( MODEM_SYSCON = 0x600A9800 );
PROVIDE ( MODEM_LPCON = 0x600AF000 );
PROVIDE ( PMU = 0x600B0000 );
PROVIDE ( LP_CLKRST = 0x600B0400 );
PROVIDE ( EFUSE = 0x600B0800 );
PROVIDE ( LP_TIMER = 0x600B0C00 );
PROVIDE ( LP_AON = 0x600B1000 );
PROVIDE ( LP_UART = 0x600B1400 );
PROVIDE ( LP_I2C = 0x600B1800 );
PROVIDE ( LP_WDT = 0x600B1C00 );
PROVIDE ( LP_IO = 0x600B2000 );
PROVIDE ( LP_I2C_ANA_MST = 0x600B2400 );
PROVIDE ( LPPERI = 0x600B2800 );
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
PROVIDE ( LP_APM = 0x600B3800 );
PROVIDE ( OTP_DEBUG = 0x600B3C00 );
PROVIDE ( TRACE = 0x600C0000 );
PROVIDE ( ASSIST_DEBUG = 0x600C2000 );
PROVIDE ( INTPRI = 0x600C5000 );
PROVIDE ( CACHE = 0x600C8000 );