From 9b319791075f7a957fd023d842127b8a28eab1db Mon Sep 17 00:00:00 2001
From: laokaiyao <laokaiyao@espressif.com>
Date: Thu, 30 Nov 2023 15:47:03 +0800
Subject: [PATCH 1/2] feat(esp32c5): add struct name and reformat struct
 headers (part3)

---
 .../soc/esp32c5/include/soc/aes_struct.h      |    2 +-
 .../esp32c5/include/soc/apb_saradc_struct.h   |    2 +-
 .../esp32c5/include/soc/assist_debug_struct.h |    3 +-
 .../esp32c5/include/soc/bitscrambler_struct.h |    3 +-
 .../soc/esp32c5/include/soc/cache_struct.h    |    3 +-
 .../soc/esp32c5/include/soc/ds_struct.h       |    2 +-
 .../soc/esp32c5/include/soc/ecc_mult_struct.h |    2 +-
 .../soc/esp32c5/include/soc/ecdsa_struct.h    |    3 +-
 .../soc/esp32c5/include/soc/efuse_struct.h    |    2 +-
 .../soc/esp32c5/include/soc/gdma_struct.h     |    2 +-
 .../soc/esp32c5/include/soc/gpio_struct.h     |    2 +-
 .../include/soc/hardware_lock_struct.h        |    3 +-
 .../soc/esp32c5/include/soc/hmac_struct.h     |    2 +-
 components/soc/esp32c5/include/soc/host_reg.h | 3883 ---------------
 .../soc/esp32c5/include/soc/host_struct.h     | 2738 -----------
 .../soc/esp32c5/include/soc/hp_apm_struct.h   |    2 +-
 .../esp32c5/include/soc/hp_system_struct.h    |    2 +-
 .../soc/esp32c5/include/soc/huk_struct.h      |    3 +-
 components/soc/esp32c5/include/soc/i2c_reg.h  |   70 +-
 .../soc/esp32c5/include/soc/i2c_struct.h      |  172 +-
 .../soc/esp32c5/include/soc/i2s_struct.h      |    2 +-
 .../include/soc/interrupt_matrix_struct.h     |    2 +-
 .../soc/esp32c5/include/soc/intpri_struct.h   |    3 +-
 .../soc/esp32c5/include/soc/io_mux_struct.h   |    2 +-
 .../soc/esp32c5/include/soc/keymng_struct.h   |    3 +-
 .../soc/esp32c5/include/soc/ledc_struct.h     |   78 +-
 .../include/soc/lp_analog_peri_struct.h       |    2 +-
 .../soc/esp32c5/include/soc/lp_aon_struct.h   |  138 +-
 .../soc/esp32c5/include/soc/lp_apm0_struct.h  |    3 +-
 .../soc/esp32c5/include/soc/lp_apm_struct.h   |    2 +-
 .../esp32c5/include/soc/lp_clkrst_struct.h    |    2 +-
 .../include/soc/lp_i2c_ana_mst_struct.h       |    2 +-
 .../soc/esp32c5/include/soc/lp_i2c_struct.h   |  175 +-
 .../soc/esp32c5/include/soc/lp_io_struct.h    |  341 +-
 .../soc/esp32c5/include/soc/lp_tee_struct.h   |    3 +-
 .../soc/esp32c5/include/soc/lp_timer_struct.h |   87 +-
 .../soc/esp32c5/include/soc/lp_uart_struct.h  |    2 +-
 .../soc/esp32c5/include/soc/lp_wdt_struct.h   |    3 +-
 .../soc/esp32c5/include/soc/lpperi_struct.h   |    2 +-
 .../soc/esp32c5/include/soc/mcpwm_struct.h    |    2 +-
 .../esp32c5/include/soc/mem_monitor_struct.h  |    2 +-
 .../esp32c5/include/soc/otp_debug_struct.h    |    2 +-
 .../soc/esp32c5/include/soc/parl_io_struct.h  |    2 +-
 .../soc/esp32c5/include/soc/pau_struct.h      |    2 +-
 .../soc/esp32c5/include/soc/pcnt_struct.h     |    2 +-
 .../soc/esp32c5/include/soc/pcr_struct.h      |    2 +-
 .../soc/esp32c5/include/soc/pmu_struct.h      |    2 +-
 components/soc/esp32c5/include/soc/reg_base.h |  101 +
 .../soc/esp32c5/include/soc/rmt_struct.h      |   26 +-
 .../soc/esp32c5/include/soc/rsa_struct.h      |    2 +-
 .../soc/esp32c5/include/soc/sdio_hinf_reg.h   |  576 ---
 .../esp32c5/include/soc/sdio_hinf_struct.h    |  492 --
 .../soc/esp32c5/include/soc/sdio_slc_reg.h    | 4301 -----------------
 .../soc/esp32c5/include/soc/sdio_slc_struct.h | 3253 -------------
 .../soc/esp32c5/include/soc/sha_struct.h      |    2 +-
 .../soc/esp32c5/include/soc/soc_etm_struct.h  | 1499 +-----
 .../soc/esp32c5/include/soc/spi1_mem_struct.h |   29 +-
 .../soc/esp32c5/include/soc/spi_mem_struct.h  |    2 +-
 .../soc/esp32c5/include/soc/spi_struct.h      |   29 +-
 .../soc/esp32c5/include/soc/systimer_struct.h |    2 +-
 .../soc/esp32c5/include/soc/tee_struct.h      |    2 +-
 .../esp32c5/include/soc/timer_group_struct.h  |    2 +-
 .../soc/esp32c5/include/soc/trace_struct.h    |    3 +-
 components/soc/esp32c5/include/soc/twai_reg.h |   70 +-
 .../soc/esp32c5/include/soc/twai_struct.h     |    2 +-
 .../soc/esp32c5/include/soc/uart_struct.h     |    2 +-
 .../soc/esp32c5/include/soc/uhci_struct.h     |  208 +-
 .../esp32c5/include/soc/usb_otg_misc_reg.h    |  421 --
 .../esp32c5/include/soc/usb_otg_misc_struct.h |  370 --
 .../include/soc/usb_serial_jtag_struct.h      |    2 +-
 .../soc/esp32c5/ld/esp32c5.peripherals.ld     |  138 +-
 71 files changed, 498 insertions(+), 18805 deletions(-)
 delete mode 100644 components/soc/esp32c5/include/soc/host_reg.h
 delete mode 100644 components/soc/esp32c5/include/soc/host_struct.h
 create mode 100644 components/soc/esp32c5/include/soc/reg_base.h
 delete mode 100644 components/soc/esp32c5/include/soc/sdio_hinf_reg.h
 delete mode 100644 components/soc/esp32c5/include/soc/sdio_hinf_struct.h
 delete mode 100644 components/soc/esp32c5/include/soc/sdio_slc_reg.h
 delete mode 100644 components/soc/esp32c5/include/soc/sdio_slc_struct.h
 delete mode 100644 components/soc/esp32c5/include/soc/usb_otg_misc_reg.h
 delete mode 100644 components/soc/esp32c5/include/soc/usb_otg_misc_struct.h

diff --git a/components/soc/esp32c5/include/soc/aes_struct.h b/components/soc/esp32c5/include/soc/aes_struct.h
index 04f89f619b..c337d9ceec 100644
--- a/components/soc/esp32c5/include/soc/aes_struct.h
+++ b/components/soc/esp32c5/include/soc/aes_struct.h
@@ -391,7 +391,7 @@ typedef union {
 } aes_date_reg_t;
 
 
-typedef struct {
+typedef struct aes_dev_t {
     volatile aes_key_0_reg_t key_0;
     volatile aes_key_1_reg_t key_1;
     volatile aes_key_2_reg_t key_2;
diff --git a/components/soc/esp32c5/include/soc/apb_saradc_struct.h b/components/soc/esp32c5/include/soc/apb_saradc_struct.h
index 47fc369928..9f89d6c729 100644
--- a/components/soc/esp32c5/include/soc/apb_saradc_struct.h
+++ b/components/soc/esp32c5/include/soc/apb_saradc_struct.h
@@ -655,7 +655,7 @@ typedef union {
 } apb_saradc_ctrl_date_reg_t;
 
 
-typedef struct {
+typedef struct apb_dev_t {
     volatile apb_saradc_ctrl_reg_t saradc_ctrl;
     volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
     volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
diff --git a/components/soc/esp32c5/include/soc/assist_debug_struct.h b/components/soc/esp32c5/include/soc/assist_debug_struct.h
index a85202837e..d4c634d060 100644
--- a/components/soc/esp32c5/include/soc/assist_debug_struct.h
+++ b/components/soc/esp32c5/include/soc/assist_debug_struct.h
@@ -508,7 +508,7 @@ typedef union {
 } assist_debug_date_reg_t;
 
 
-typedef struct {
+typedef struct assist_debug_dev_t {
     volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
     volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
     volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
@@ -538,6 +538,7 @@ typedef struct {
     volatile assist_debug_date_reg_t date;
 } assist_debug_dev_t;
 
+extern assist_debug_dev_t ASSIST_DEBUG;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/bitscrambler_struct.h b/components/soc/esp32c5/include/soc/bitscrambler_struct.h
index 007c244d50..cfcca328ae 100644
--- a/components/soc/esp32c5/include/soc/bitscrambler_struct.h
+++ b/components/soc/esp32c5/include/soc/bitscrambler_struct.h
@@ -406,7 +406,7 @@ typedef union {
 } bitscrambler_version_reg_t;
 
 
-typedef struct {
+typedef struct bitscrambler_dev_t {
     volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
     volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
     volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
@@ -426,6 +426,7 @@ typedef struct {
     volatile bitscrambler_version_reg_t version;
 } bitscrambler_dev_t;
 
+extern bitscrambler_dev_t BITSCRAMBLER;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/cache_struct.h b/components/soc/esp32c5/include/soc/cache_struct.h
index b0e181fc17..871f93c19e 100644
--- a/components/soc/esp32c5/include/soc/cache_struct.h
+++ b/components/soc/esp32c5/include/soc/cache_struct.h
@@ -1319,7 +1319,7 @@ typedef union {
 } cache_date_reg_t;
 
 
-typedef struct {
+typedef struct cache_dev_t {
     uint32_t reserved_000;
     volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl;
     uint32_t reserved_008[6];
@@ -1399,6 +1399,7 @@ typedef struct {
     volatile cache_date_reg_t date;
 } cache_dev_t;
 
+extern cache_dev_t CACHE;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/ds_struct.h b/components/soc/esp32c5/include/soc/ds_struct.h
index 3069fb58ed..74682d8e17 100644
--- a/components/soc/esp32c5/include/soc/ds_struct.h
+++ b/components/soc/esp32c5/include/soc/ds_struct.h
@@ -118,7 +118,7 @@ typedef union {
 } ds_date_reg_t;
 
 
-typedef struct {
+typedef struct ds_dev_t {
     volatile uint32_t y[128];
     volatile uint32_t m[128];
     volatile uint32_t rb[128];
diff --git a/components/soc/esp32c5/include/soc/ecc_mult_struct.h b/components/soc/esp32c5/include/soc/ecc_mult_struct.h
index a2a02f7f8a..da6e103063 100644
--- a/components/soc/esp32c5/include/soc/ecc_mult_struct.h
+++ b/components/soc/esp32c5/include/soc/ecc_mult_struct.h
@@ -139,7 +139,7 @@ typedef union {
 } ecc_mult_date_reg_t;
 
 
-typedef struct {
+typedef struct ecc_mult_dev_t {
     uint32_t reserved_000[3];
     volatile ecc_mult_int_raw_reg_t int_raw;
     volatile ecc_mult_int_st_reg_t int_st;
diff --git a/components/soc/esp32c5/include/soc/ecdsa_struct.h b/components/soc/esp32c5/include/soc/ecdsa_struct.h
index 1d39f1ad04..c319499a4d 100644
--- a/components/soc/esp32c5/include/soc/ecdsa_struct.h
+++ b/components/soc/esp32c5/include/soc/ecdsa_struct.h
@@ -284,7 +284,7 @@ typedef union {
 } ecdsa_date_reg_t;
 
 
-typedef struct {
+typedef struct ecdsa_dev_t {
     uint32_t reserved_000;
     volatile ecdsa_conf_reg_t conf;
     volatile ecdsa_clk_reg_t clk;
@@ -313,6 +313,7 @@ typedef struct {
     volatile uint32_t qay[8];
 } ecdsa_dev_t;
 
+extern ecdsa_dev_t ECDSA;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/efuse_struct.h b/components/soc/esp32c5/include/soc/efuse_struct.h
index f0fb593e5b..56b2222b83 100644
--- a/components/soc/esp32c5/include/soc/efuse_struct.h
+++ b/components/soc/esp32c5/include/soc/efuse_struct.h
@@ -2112,7 +2112,7 @@ typedef union {
 } efuse_date_reg_t;
 
 
-typedef struct {
+typedef struct efuse_dev_t {
     volatile efuse_pgm_data0_reg_t pgm_data0;
     volatile efuse_pgm_data1_reg_t pgm_data1;
     volatile efuse_pgm_data2_reg_t pgm_data2;
diff --git a/components/soc/esp32c5/include/soc/gdma_struct.h b/components/soc/esp32c5/include/soc/gdma_struct.h
index c06e41c011..429106c9e0 100644
--- a/components/soc/esp32c5/include/soc/gdma_struct.h
+++ b/components/soc/esp32c5/include/soc/gdma_struct.h
@@ -2040,7 +2040,7 @@ typedef union {
 } gdma_bt_rx_sel_reg_t;
 
 
-typedef struct {
+typedef struct gdma_dev_t {
     volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0;
     volatile gdma_in_int_st_chn_reg_t in_int_st_ch0;
     volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0;
diff --git a/components/soc/esp32c5/include/soc/gpio_struct.h b/components/soc/esp32c5/include/soc/gpio_struct.h
index afccace39d..0044e173fc 100644
--- a/components/soc/esp32c5/include/soc/gpio_struct.h
+++ b/components/soc/esp32c5/include/soc/gpio_struct.h
@@ -2512,7 +2512,7 @@ typedef union {
 } gpio_date_reg_t;
 
 
-typedef struct {
+typedef struct gpio_dev_t {
     volatile gpio_bt_select_reg_t bt_select;
     volatile gpio_out_reg_t out;
     volatile gpio_out_w1ts_reg_t out_w1ts;
diff --git a/components/soc/esp32c5/include/soc/hardware_lock_struct.h b/components/soc/esp32c5/include/soc/hardware_lock_struct.h
index 2e6b7f2cf2..799d6b4ba9 100644
--- a/components/soc/esp32c5/include/soc/hardware_lock_struct.h
+++ b/components/soc/esp32c5/include/soc/hardware_lock_struct.h
@@ -80,7 +80,7 @@ typedef union {
 } atomic_counter_reg_t;
 
 
-typedef struct {
+typedef struct atomic_dev_t {
     volatile atomic_addr_lock_reg_t addr_lock;
     volatile atomic_lr_addr_reg_t lr_addr;
     volatile atomic_lr_value_reg_t lr_value;
@@ -88,7 +88,6 @@ typedef struct {
     volatile atomic_counter_reg_t counter;
 } atomic_dev_t;
 
-extern atomic_dev_t ATOMIC_LOCKER;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/hmac_struct.h b/components/soc/esp32c5/include/soc/hmac_struct.h
index 59aee85a2b..088c652c51 100644
--- a/components/soc/esp32c5/include/soc/hmac_struct.h
+++ b/components/soc/esp32c5/include/soc/hmac_struct.h
@@ -255,7 +255,7 @@ typedef union {
 } hmac_date_reg_t;
 
 
-typedef struct {
+typedef struct hmac_dev_t {
     uint32_t reserved_000[16];
     volatile hmac_set_start_reg_t set_start;
     volatile hmac_set_para_purpose_reg_t set_para_purpose;
diff --git a/components/soc/esp32c5/include/soc/host_reg.h b/components/soc/esp32c5/include/soc/host_reg.h
deleted file mode 100644
index 484da3d260..0000000000
--- a/components/soc/esp32c5/include/soc/host_reg.h
+++ /dev/null
@@ -1,3883 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SLCHOST_FUNC2_0_REG register
- *  *******Description***********
- */
-#define SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10)
-/** SLCHOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_FUNC2_INT    (BIT(24))
-#define SLCHOST_SLC_FUNC2_INT_M  (SLCHOST_SLC_FUNC2_INT_V << SLCHOST_SLC_FUNC2_INT_S)
-#define SLCHOST_SLC_FUNC2_INT_V  0x00000001U
-#define SLCHOST_SLC_FUNC2_INT_S  24
-
-/** SLCHOST_FUNC2_1_REG register
- *  *******Description***********
- */
-#define SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14)
-/** SLCHOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_FUNC2_INT_EN    (BIT(0))
-#define SLCHOST_SLC_FUNC2_INT_EN_M  (SLCHOST_SLC_FUNC2_INT_EN_V << SLCHOST_SLC_FUNC2_INT_EN_S)
-#define SLCHOST_SLC_FUNC2_INT_EN_V  0x00000001U
-#define SLCHOST_SLC_FUNC2_INT_EN_S  0
-
-/** SLCHOST_FUNC2_2_REG register
- *  *******Description***********
- */
-#define SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20)
-/** SLCHOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1;
- *  *******Description***********
- */
-#define SLCHOST_SLC_FUNC1_MDSTAT    (BIT(0))
-#define SLCHOST_SLC_FUNC1_MDSTAT_M  (SLCHOST_SLC_FUNC1_MDSTAT_V << SLCHOST_SLC_FUNC1_MDSTAT_S)
-#define SLCHOST_SLC_FUNC1_MDSTAT_V  0x00000001U
-#define SLCHOST_SLC_FUNC1_MDSTAT_S  0
-
-/** SLCHOST_GPIO_STATUS0_REG register
- *  *******Description***********
- */
-#define SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34)
-/** SLCHOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT0    0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_INT0_M  (SLCHOST_GPIO_SDIO_INT0_V << SLCHOST_GPIO_SDIO_INT0_S)
-#define SLCHOST_GPIO_SDIO_INT0_V  0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_INT0_S  0
-
-/** SLCHOST_GPIO_STATUS1_REG register
- *  *******Description***********
- */
-#define SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
-/** SLCHOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT1    0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_INT1_M  (SLCHOST_GPIO_SDIO_INT1_V << SLCHOST_GPIO_SDIO_INT1_S)
-#define SLCHOST_GPIO_SDIO_INT1_V  0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_INT1_S  0
-
-/** SLCHOST_GPIO_IN0_REG register
- *  *******Description***********
- */
-#define SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3c)
-/** SLCHOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_IN0    0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_IN0_M  (SLCHOST_GPIO_SDIO_IN0_V << SLCHOST_GPIO_SDIO_IN0_S)
-#define SLCHOST_GPIO_SDIO_IN0_V  0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_IN0_S  0
-
-/** SLCHOST_GPIO_IN1_REG register
- *  *******Description***********
- */
-#define SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40)
-/** SLCHOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_IN1    0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_IN1_M  (SLCHOST_GPIO_SDIO_IN1_V << SLCHOST_GPIO_SDIO_IN1_S)
-#define SLCHOST_GPIO_SDIO_IN1_V  0xFFFFFFFFU
-#define SLCHOST_GPIO_SDIO_IN1_S  0
-
-/** SLCHOST_SLC0HOST_TOKEN_RDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
-/** SLCHOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0    0x00000FFFU
-#define SLCHOST_SLC0_TOKEN0_M  (SLCHOST_SLC0_TOKEN0_V << SLCHOST_SLC0_TOKEN0_S)
-#define SLCHOST_SLC0_TOKEN0_V  0x00000FFFU
-#define SLCHOST_SLC0_TOKEN0_S  0
-/** SLCHOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID    (BIT(12))
-#define SLCHOST_SLC0_RX_PF_VALID_M  (SLCHOST_SLC0_RX_PF_VALID_V << SLCHOST_SLC0_RX_PF_VALID_S)
-#define SLCHOST_SLC0_RX_PF_VALID_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_S  12
-/** SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_M  (SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S  16
-/** SLCHOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_EOF    0x0000000FU
-#define SLCHOST_SLC0_RX_PF_EOF_M  (SLCHOST_SLC0_RX_PF_EOF_V << SLCHOST_SLC0_RX_PF_EOF_S)
-#define SLCHOST_SLC0_RX_PF_EOF_V  0x0000000FU
-#define SLCHOST_SLC0_RX_PF_EOF_S  28
-
-/** SLCHOST_SLC0_HOST_PF_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
-/** SLCHOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_PF_DATA    0xFFFFFFFFU
-#define SLCHOST_SLC0_PF_DATA_M  (SLCHOST_SLC0_PF_DATA_V << SLCHOST_SLC0_PF_DATA_S)
-#define SLCHOST_SLC0_PF_DATA_V  0xFFFFFFFFU
-#define SLCHOST_SLC0_PF_DATA_S  0
-
-/** SLCHOST_SLC1_HOST_PF_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4c)
-/** SLCHOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_PF_DATA    0xFFFFFFFFU
-#define SLCHOST_SLC1_PF_DATA_M  (SLCHOST_SLC1_PF_DATA_V << SLCHOST_SLC1_PF_DATA_S)
-#define SLCHOST_SLC1_PF_DATA_V  0xFFFFFFFFU
-#define SLCHOST_SLC1_PF_DATA_S  0
-
-/** SLCHOST_SLC0HOST_INT_RAW_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_M  (SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_M  (SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_RAW    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_RAW_M  (SLCHOST_SLC0HOST_RX_START_INT_RAW_V << SLCHOST_SLC0HOST_RX_START_INT_RAW_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_RAW_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_RAW    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_RAW_M  (SLCHOST_SLC0HOST_TX_START_INT_RAW_V << SLCHOST_SLC0HOST_TX_START_INT_RAW_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_RAW_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_RAW    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_RAW_M  (SLCHOST_SLC0_RX_UDF_INT_RAW_V << SLCHOST_SLC0_RX_UDF_INT_RAW_S)
-#define SLCHOST_SLC0_RX_UDF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_RAW_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_RAW    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_RAW_M  (SLCHOST_SLC0_TX_OVF_INT_RAW_V << SLCHOST_SLC0_TX_OVF_INT_RAW_S)
-#define SLCHOST_SLC0_TX_OVF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_RAW_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_M  (SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_RAW    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT0_INT_RAW_V << SLCHOST_SLC0_EXT_BIT0_INT_RAW_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_RAW_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_RAW    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT1_INT_RAW_V << SLCHOST_SLC0_EXT_BIT1_INT_RAW_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_RAW_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_RAW    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT2_INT_RAW_V << SLCHOST_SLC0_EXT_BIT2_INT_RAW_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_RAW_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_RAW    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_M  (SLCHOST_SLC0_EXT_BIT3_INT_RAW_V << SLCHOST_SLC0_EXT_BIT3_INT_RAW_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_RAW_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S  24
-/** SLCHOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_RAW    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_RAW_M  (SLCHOST_GPIO_SDIO_INT_RAW_V << SLCHOST_GPIO_SDIO_INT_RAW_S)
-#define SLCHOST_GPIO_SDIO_INT_RAW_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_RAW_S  25
-
-/** SLCHOST_SLC1HOST_INT_RAW_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V << SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_M  (SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_M  (SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V << SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_RAW    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_RAW_M  (SLCHOST_SLC1HOST_RX_START_INT_RAW_V << SLCHOST_SLC1HOST_RX_START_INT_RAW_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_RAW_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_RAW    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_RAW_M  (SLCHOST_SLC1HOST_TX_START_INT_RAW_V << SLCHOST_SLC1HOST_TX_START_INT_RAW_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_RAW_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_RAW    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_RAW_M  (SLCHOST_SLC1_RX_UDF_INT_RAW_V << SLCHOST_SLC1_RX_UDF_INT_RAW_S)
-#define SLCHOST_SLC1_RX_UDF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_RAW_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_RAW    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_RAW_M  (SLCHOST_SLC1_TX_OVF_INT_RAW_V << SLCHOST_SLC1_TX_OVF_INT_RAW_S)
-#define SLCHOST_SLC1_TX_OVF_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_RAW_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_M  (SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V << SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_RAW    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT0_INT_RAW_V << SLCHOST_SLC1_EXT_BIT0_INT_RAW_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_RAW_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_RAW    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT1_INT_RAW_V << SLCHOST_SLC1_EXT_BIT1_INT_RAW_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_RAW_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_RAW    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT2_INT_RAW_V << SLCHOST_SLC1_EXT_BIT2_INT_RAW_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_RAW_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_RAW    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_M  (SLCHOST_SLC1_EXT_BIT3_INT_RAW_V << SLCHOST_SLC1_EXT_BIT3_INT_RAW_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_RAW_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S  25
-
-/** SLCHOST_SLC0HOST_INT_ST_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ST    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ST_V << SLCHOST_SLC0HOST_RX_SOF_INT_ST_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ST_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ST    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ST_V << SLCHOST_SLC0HOST_RX_EOF_INT_ST_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ST_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_ST    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_ST_M  (SLCHOST_SLC0HOST_RX_START_INT_ST_V << SLCHOST_SLC0HOST_RX_START_INT_ST_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_ST_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_ST    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_ST_M  (SLCHOST_SLC0HOST_TX_START_INT_ST_V << SLCHOST_SLC0HOST_TX_START_INT_ST_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_ST_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_ST    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_ST_M  (SLCHOST_SLC0_RX_UDF_INT_ST_V << SLCHOST_SLC0_RX_UDF_INT_ST_S)
-#define SLCHOST_SLC0_RX_UDF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_ST_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_ST    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_ST_M  (SLCHOST_SLC0_TX_OVF_INT_ST_V << SLCHOST_SLC0_TX_OVF_INT_ST_S)
-#define SLCHOST_SLC0_TX_OVF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_ST_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ST    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ST_V << SLCHOST_SLC0_RX_PF_VALID_INT_ST_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ST_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_ST    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_ST_M  (SLCHOST_SLC0_EXT_BIT0_INT_ST_V << SLCHOST_SLC0_EXT_BIT0_INT_ST_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_ST_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_ST    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_ST_M  (SLCHOST_SLC0_EXT_BIT1_INT_ST_V << SLCHOST_SLC0_EXT_BIT1_INT_ST_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_ST_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_ST    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_ST_M  (SLCHOST_SLC0_EXT_BIT2_INT_ST_V << SLCHOST_SLC0_EXT_BIT2_INT_ST_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_ST_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_ST    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_ST_M  (SLCHOST_SLC0_EXT_BIT3_INT_ST_V << SLCHOST_SLC0_EXT_BIT3_INT_ST_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_ST_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S  24
-/** SLCHOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_ST    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_ST_M  (SLCHOST_GPIO_SDIO_INT_ST_V << SLCHOST_GPIO_SDIO_INT_ST_S)
-#define SLCHOST_GPIO_SDIO_INT_ST_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_ST_S  25
-
-/** SLCHOST_SLC1HOST_INT_ST_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5c)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ST    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ST_V << SLCHOST_SLC1HOST_RX_SOF_INT_ST_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ST_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ST    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ST_V << SLCHOST_SLC1HOST_RX_EOF_INT_ST_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ST_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_ST    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_ST_M  (SLCHOST_SLC1HOST_RX_START_INT_ST_V << SLCHOST_SLC1HOST_RX_START_INT_ST_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_ST_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_ST    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_ST_M  (SLCHOST_SLC1HOST_TX_START_INT_ST_V << SLCHOST_SLC1HOST_TX_START_INT_ST_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_ST_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_ST    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_ST_M  (SLCHOST_SLC1_RX_UDF_INT_ST_V << SLCHOST_SLC1_RX_UDF_INT_ST_S)
-#define SLCHOST_SLC1_RX_UDF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_ST_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_ST    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_ST_M  (SLCHOST_SLC1_TX_OVF_INT_ST_V << SLCHOST_SLC1_TX_OVF_INT_ST_S)
-#define SLCHOST_SLC1_TX_OVF_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_ST_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ST    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ST_V << SLCHOST_SLC1_RX_PF_VALID_INT_ST_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ST_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_ST    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_ST_M  (SLCHOST_SLC1_EXT_BIT0_INT_ST_V << SLCHOST_SLC1_EXT_BIT0_INT_ST_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_ST_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_ST    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_ST_M  (SLCHOST_SLC1_EXT_BIT1_INT_ST_V << SLCHOST_SLC1_EXT_BIT1_INT_ST_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_ST_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_ST    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_ST_M  (SLCHOST_SLC1_EXT_BIT2_INT_ST_V << SLCHOST_SLC1_EXT_BIT2_INT_ST_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_ST_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_ST    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_ST_M  (SLCHOST_SLC1_EXT_BIT3_INT_ST_V << SLCHOST_SLC1_EXT_BIT3_INT_ST_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_ST_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S  25
-
-/** SLCHOST_PKT_LEN_REG register
- *  *******Description***********
- */
-#define SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN    0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_V  0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_S  0
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S  20
-
-/** SLCHOST_STATE_W0_REG register
- *  *******Description***********
- */
-#define SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64)
-/** SLCHOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE0    0x000000FFU
-#define SLCHOST_SLCHOST_STATE0_M  (SLCHOST_SLCHOST_STATE0_V << SLCHOST_SLCHOST_STATE0_S)
-#define SLCHOST_SLCHOST_STATE0_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE0_S  0
-/** SLCHOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE1    0x000000FFU
-#define SLCHOST_SLCHOST_STATE1_M  (SLCHOST_SLCHOST_STATE1_V << SLCHOST_SLCHOST_STATE1_S)
-#define SLCHOST_SLCHOST_STATE1_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE1_S  8
-/** SLCHOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE2    0x000000FFU
-#define SLCHOST_SLCHOST_STATE2_M  (SLCHOST_SLCHOST_STATE2_V << SLCHOST_SLCHOST_STATE2_S)
-#define SLCHOST_SLCHOST_STATE2_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE2_S  16
-/** SLCHOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE3    0x000000FFU
-#define SLCHOST_SLCHOST_STATE3_M  (SLCHOST_SLCHOST_STATE3_V << SLCHOST_SLCHOST_STATE3_S)
-#define SLCHOST_SLCHOST_STATE3_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE3_S  24
-
-/** SLCHOST_STATE_W1_REG register
- *  *******Description***********
- */
-#define SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68)
-/** SLCHOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE4    0x000000FFU
-#define SLCHOST_SLCHOST_STATE4_M  (SLCHOST_SLCHOST_STATE4_V << SLCHOST_SLCHOST_STATE4_S)
-#define SLCHOST_SLCHOST_STATE4_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE4_S  0
-/** SLCHOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE5    0x000000FFU
-#define SLCHOST_SLCHOST_STATE5_M  (SLCHOST_SLCHOST_STATE5_V << SLCHOST_SLCHOST_STATE5_S)
-#define SLCHOST_SLCHOST_STATE5_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE5_S  8
-/** SLCHOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE6    0x000000FFU
-#define SLCHOST_SLCHOST_STATE6_M  (SLCHOST_SLCHOST_STATE6_V << SLCHOST_SLCHOST_STATE6_S)
-#define SLCHOST_SLCHOST_STATE6_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE6_S  16
-/** SLCHOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_STATE7    0x000000FFU
-#define SLCHOST_SLCHOST_STATE7_M  (SLCHOST_SLCHOST_STATE7_V << SLCHOST_SLCHOST_STATE7_S)
-#define SLCHOST_SLCHOST_STATE7_V  0x000000FFU
-#define SLCHOST_SLCHOST_STATE7_S  24
-
-/** SLCHOST_CONF_W0_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6c)
-/** SLCHOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF0    0x000000FFU
-#define SLCHOST_SLCHOST_CONF0_M  (SLCHOST_SLCHOST_CONF0_V << SLCHOST_SLCHOST_CONF0_S)
-#define SLCHOST_SLCHOST_CONF0_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF0_S  0
-/** SLCHOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF1    0x000000FFU
-#define SLCHOST_SLCHOST_CONF1_M  (SLCHOST_SLCHOST_CONF1_V << SLCHOST_SLCHOST_CONF1_S)
-#define SLCHOST_SLCHOST_CONF1_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF1_S  8
-/** SLCHOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF2    0x000000FFU
-#define SLCHOST_SLCHOST_CONF2_M  (SLCHOST_SLCHOST_CONF2_V << SLCHOST_SLCHOST_CONF2_S)
-#define SLCHOST_SLCHOST_CONF2_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF2_S  16
-/** SLCHOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF3    0x000000FFU
-#define SLCHOST_SLCHOST_CONF3_M  (SLCHOST_SLCHOST_CONF3_V << SLCHOST_SLCHOST_CONF3_S)
-#define SLCHOST_SLCHOST_CONF3_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF3_S  24
-
-/** SLCHOST_CONF_W1_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70)
-/** SLCHOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF4    0x000000FFU
-#define SLCHOST_SLCHOST_CONF4_M  (SLCHOST_SLCHOST_CONF4_V << SLCHOST_SLCHOST_CONF4_S)
-#define SLCHOST_SLCHOST_CONF4_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF4_S  0
-/** SLCHOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF5    0x000000FFU
-#define SLCHOST_SLCHOST_CONF5_M  (SLCHOST_SLCHOST_CONF5_V << SLCHOST_SLCHOST_CONF5_S)
-#define SLCHOST_SLCHOST_CONF5_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF5_S  8
-/** SLCHOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF6    0x000000FFU
-#define SLCHOST_SLCHOST_CONF6_M  (SLCHOST_SLCHOST_CONF6_V << SLCHOST_SLCHOST_CONF6_S)
-#define SLCHOST_SLCHOST_CONF6_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF6_S  16
-/** SLCHOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF7    0x000000FFU
-#define SLCHOST_SLCHOST_CONF7_M  (SLCHOST_SLCHOST_CONF7_V << SLCHOST_SLCHOST_CONF7_S)
-#define SLCHOST_SLCHOST_CONF7_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF7_S  24
-
-/** SLCHOST_CONF_W2_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74)
-/** SLCHOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF8    0x000000FFU
-#define SLCHOST_SLCHOST_CONF8_M  (SLCHOST_SLCHOST_CONF8_V << SLCHOST_SLCHOST_CONF8_S)
-#define SLCHOST_SLCHOST_CONF8_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF8_S  0
-/** SLCHOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF9    0x000000FFU
-#define SLCHOST_SLCHOST_CONF9_M  (SLCHOST_SLCHOST_CONF9_V << SLCHOST_SLCHOST_CONF9_S)
-#define SLCHOST_SLCHOST_CONF9_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF9_S  8
-/** SLCHOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF10    0x000000FFU
-#define SLCHOST_SLCHOST_CONF10_M  (SLCHOST_SLCHOST_CONF10_V << SLCHOST_SLCHOST_CONF10_S)
-#define SLCHOST_SLCHOST_CONF10_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF10_S  16
-/** SLCHOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF11    0x000000FFU
-#define SLCHOST_SLCHOST_CONF11_M  (SLCHOST_SLCHOST_CONF11_V << SLCHOST_SLCHOST_CONF11_S)
-#define SLCHOST_SLCHOST_CONF11_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF11_S  24
-
-/** SLCHOST_CONF_W3_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78)
-/** SLCHOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF12    0x000000FFU
-#define SLCHOST_SLCHOST_CONF12_M  (SLCHOST_SLCHOST_CONF12_V << SLCHOST_SLCHOST_CONF12_S)
-#define SLCHOST_SLCHOST_CONF12_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF12_S  0
-/** SLCHOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF13    0x000000FFU
-#define SLCHOST_SLCHOST_CONF13_M  (SLCHOST_SLCHOST_CONF13_V << SLCHOST_SLCHOST_CONF13_S)
-#define SLCHOST_SLCHOST_CONF13_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF13_S  8
-/** SLCHOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF14    0x000000FFU
-#define SLCHOST_SLCHOST_CONF14_M  (SLCHOST_SLCHOST_CONF14_V << SLCHOST_SLCHOST_CONF14_S)
-#define SLCHOST_SLCHOST_CONF14_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF14_S  16
-/** SLCHOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF15    0x000000FFU
-#define SLCHOST_SLCHOST_CONF15_M  (SLCHOST_SLCHOST_CONF15_V << SLCHOST_SLCHOST_CONF15_S)
-#define SLCHOST_SLCHOST_CONF15_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF15_S  24
-
-/** SLCHOST_CONF_W4_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7c)
-/** SLCHOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF16    0x000000FFU
-#define SLCHOST_SLCHOST_CONF16_M  (SLCHOST_SLCHOST_CONF16_V << SLCHOST_SLCHOST_CONF16_S)
-#define SLCHOST_SLCHOST_CONF16_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF16_S  0
-/** SLCHOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF17    0x000000FFU
-#define SLCHOST_SLCHOST_CONF17_M  (SLCHOST_SLCHOST_CONF17_V << SLCHOST_SLCHOST_CONF17_S)
-#define SLCHOST_SLCHOST_CONF17_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF17_S  8
-/** SLCHOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF18    0x000000FFU
-#define SLCHOST_SLCHOST_CONF18_M  (SLCHOST_SLCHOST_CONF18_V << SLCHOST_SLCHOST_CONF18_S)
-#define SLCHOST_SLCHOST_CONF18_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF18_S  16
-/** SLCHOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF19    0x000000FFU
-#define SLCHOST_SLCHOST_CONF19_M  (SLCHOST_SLCHOST_CONF19_V << SLCHOST_SLCHOST_CONF19_S)
-#define SLCHOST_SLCHOST_CONF19_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF19_S  24
-
-/** SLCHOST_CONF_W5_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80)
-/** SLCHOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF20    0x000000FFU
-#define SLCHOST_SLCHOST_CONF20_M  (SLCHOST_SLCHOST_CONF20_V << SLCHOST_SLCHOST_CONF20_S)
-#define SLCHOST_SLCHOST_CONF20_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF20_S  0
-/** SLCHOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF21    0x000000FFU
-#define SLCHOST_SLCHOST_CONF21_M  (SLCHOST_SLCHOST_CONF21_V << SLCHOST_SLCHOST_CONF21_S)
-#define SLCHOST_SLCHOST_CONF21_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF21_S  8
-/** SLCHOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF22    0x000000FFU
-#define SLCHOST_SLCHOST_CONF22_M  (SLCHOST_SLCHOST_CONF22_V << SLCHOST_SLCHOST_CONF22_S)
-#define SLCHOST_SLCHOST_CONF22_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF22_S  16
-/** SLCHOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF23    0x000000FFU
-#define SLCHOST_SLCHOST_CONF23_M  (SLCHOST_SLCHOST_CONF23_V << SLCHOST_SLCHOST_CONF23_S)
-#define SLCHOST_SLCHOST_CONF23_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF23_S  24
-
-/** SLCHOST_WIN_CMD_REG register
- *  *******Description***********
- */
-#define SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84)
-/** SLCHOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_WIN_CMD    0x0000FFFFU
-#define SLCHOST_SLCHOST_WIN_CMD_M  (SLCHOST_SLCHOST_WIN_CMD_V << SLCHOST_SLCHOST_WIN_CMD_S)
-#define SLCHOST_SLCHOST_WIN_CMD_V  0x0000FFFFU
-#define SLCHOST_SLCHOST_WIN_CMD_S  0
-
-/** SLCHOST_CONF_W6_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88)
-/** SLCHOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF24    0x000000FFU
-#define SLCHOST_SLCHOST_CONF24_M  (SLCHOST_SLCHOST_CONF24_V << SLCHOST_SLCHOST_CONF24_S)
-#define SLCHOST_SLCHOST_CONF24_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF24_S  0
-/** SLCHOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF25    0x000000FFU
-#define SLCHOST_SLCHOST_CONF25_M  (SLCHOST_SLCHOST_CONF25_V << SLCHOST_SLCHOST_CONF25_S)
-#define SLCHOST_SLCHOST_CONF25_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF25_S  8
-/** SLCHOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF26    0x000000FFU
-#define SLCHOST_SLCHOST_CONF26_M  (SLCHOST_SLCHOST_CONF26_V << SLCHOST_SLCHOST_CONF26_S)
-#define SLCHOST_SLCHOST_CONF26_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF26_S  16
-/** SLCHOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF27    0x000000FFU
-#define SLCHOST_SLCHOST_CONF27_M  (SLCHOST_SLCHOST_CONF27_V << SLCHOST_SLCHOST_CONF27_S)
-#define SLCHOST_SLCHOST_CONF27_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF27_S  24
-
-/** SLCHOST_CONF_W7_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8c)
-/** SLCHOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF28    0x000000FFU
-#define SLCHOST_SLCHOST_CONF28_M  (SLCHOST_SLCHOST_CONF28_V << SLCHOST_SLCHOST_CONF28_S)
-#define SLCHOST_SLCHOST_CONF28_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF28_S  0
-/** SLCHOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF29    0x000000FFU
-#define SLCHOST_SLCHOST_CONF29_M  (SLCHOST_SLCHOST_CONF29_V << SLCHOST_SLCHOST_CONF29_S)
-#define SLCHOST_SLCHOST_CONF29_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF29_S  8
-/** SLCHOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF30    0x000000FFU
-#define SLCHOST_SLCHOST_CONF30_M  (SLCHOST_SLCHOST_CONF30_V << SLCHOST_SLCHOST_CONF30_S)
-#define SLCHOST_SLCHOST_CONF30_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF30_S  16
-/** SLCHOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF31    0x000000FFU
-#define SLCHOST_SLCHOST_CONF31_M  (SLCHOST_SLCHOST_CONF31_V << SLCHOST_SLCHOST_CONF31_S)
-#define SLCHOST_SLCHOST_CONF31_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF31_S  24
-
-/** SLCHOST_PKT_LEN0_REG register
- *  *******Description***********
- */
-#define SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90)
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0    0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN0_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_V  0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_S  0
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S  20
-
-/** SLCHOST_PKT_LEN1_REG register
- *  *******Description***********
- */
-#define SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94)
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1    0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN1_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_V  0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_S  0
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S  20
-
-/** SLCHOST_PKT_LEN2_REG register
- *  *******Description***********
- */
-#define SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98)
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2    0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN2_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_V  0x000FFFFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_S  0
-/** SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M  (SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S)
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S  20
-
-/** SLCHOST_CONF_W8_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9c)
-/** SLCHOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF32    0x000000FFU
-#define SLCHOST_SLCHOST_CONF32_M  (SLCHOST_SLCHOST_CONF32_V << SLCHOST_SLCHOST_CONF32_S)
-#define SLCHOST_SLCHOST_CONF32_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF32_S  0
-/** SLCHOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF33    0x000000FFU
-#define SLCHOST_SLCHOST_CONF33_M  (SLCHOST_SLCHOST_CONF33_V << SLCHOST_SLCHOST_CONF33_S)
-#define SLCHOST_SLCHOST_CONF33_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF33_S  8
-/** SLCHOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF34    0x000000FFU
-#define SLCHOST_SLCHOST_CONF34_M  (SLCHOST_SLCHOST_CONF34_V << SLCHOST_SLCHOST_CONF34_S)
-#define SLCHOST_SLCHOST_CONF34_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF34_S  16
-/** SLCHOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF35    0x000000FFU
-#define SLCHOST_SLCHOST_CONF35_M  (SLCHOST_SLCHOST_CONF35_V << SLCHOST_SLCHOST_CONF35_S)
-#define SLCHOST_SLCHOST_CONF35_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF35_S  24
-
-/** SLCHOST_CONF_W9_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xa0)
-/** SLCHOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF36    0x000000FFU
-#define SLCHOST_SLCHOST_CONF36_M  (SLCHOST_SLCHOST_CONF36_V << SLCHOST_SLCHOST_CONF36_S)
-#define SLCHOST_SLCHOST_CONF36_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF36_S  0
-/** SLCHOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF37    0x000000FFU
-#define SLCHOST_SLCHOST_CONF37_M  (SLCHOST_SLCHOST_CONF37_V << SLCHOST_SLCHOST_CONF37_S)
-#define SLCHOST_SLCHOST_CONF37_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF37_S  8
-/** SLCHOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF38    0x000000FFU
-#define SLCHOST_SLCHOST_CONF38_M  (SLCHOST_SLCHOST_CONF38_V << SLCHOST_SLCHOST_CONF38_S)
-#define SLCHOST_SLCHOST_CONF38_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF38_S  16
-/** SLCHOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF39    0x000000FFU
-#define SLCHOST_SLCHOST_CONF39_M  (SLCHOST_SLCHOST_CONF39_V << SLCHOST_SLCHOST_CONF39_S)
-#define SLCHOST_SLCHOST_CONF39_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF39_S  24
-
-/** SLCHOST_CONF_W10_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xa4)
-/** SLCHOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF40    0x000000FFU
-#define SLCHOST_SLCHOST_CONF40_M  (SLCHOST_SLCHOST_CONF40_V << SLCHOST_SLCHOST_CONF40_S)
-#define SLCHOST_SLCHOST_CONF40_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF40_S  0
-/** SLCHOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF41    0x000000FFU
-#define SLCHOST_SLCHOST_CONF41_M  (SLCHOST_SLCHOST_CONF41_V << SLCHOST_SLCHOST_CONF41_S)
-#define SLCHOST_SLCHOST_CONF41_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF41_S  8
-/** SLCHOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF42    0x000000FFU
-#define SLCHOST_SLCHOST_CONF42_M  (SLCHOST_SLCHOST_CONF42_V << SLCHOST_SLCHOST_CONF42_S)
-#define SLCHOST_SLCHOST_CONF42_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF42_S  16
-/** SLCHOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF43    0x000000FFU
-#define SLCHOST_SLCHOST_CONF43_M  (SLCHOST_SLCHOST_CONF43_V << SLCHOST_SLCHOST_CONF43_S)
-#define SLCHOST_SLCHOST_CONF43_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF43_S  24
-
-/** SLCHOST_CONF_W11_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xa8)
-/** SLCHOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF44    0x000000FFU
-#define SLCHOST_SLCHOST_CONF44_M  (SLCHOST_SLCHOST_CONF44_V << SLCHOST_SLCHOST_CONF44_S)
-#define SLCHOST_SLCHOST_CONF44_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF44_S  0
-/** SLCHOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF45    0x000000FFU
-#define SLCHOST_SLCHOST_CONF45_M  (SLCHOST_SLCHOST_CONF45_V << SLCHOST_SLCHOST_CONF45_S)
-#define SLCHOST_SLCHOST_CONF45_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF45_S  8
-/** SLCHOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF46    0x000000FFU
-#define SLCHOST_SLCHOST_CONF46_M  (SLCHOST_SLCHOST_CONF46_V << SLCHOST_SLCHOST_CONF46_S)
-#define SLCHOST_SLCHOST_CONF46_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF46_S  16
-/** SLCHOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF47    0x000000FFU
-#define SLCHOST_SLCHOST_CONF47_M  (SLCHOST_SLCHOST_CONF47_V << SLCHOST_SLCHOST_CONF47_S)
-#define SLCHOST_SLCHOST_CONF47_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF47_S  24
-
-/** SLCHOST_CONF_W12_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xac)
-/** SLCHOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF48    0x000000FFU
-#define SLCHOST_SLCHOST_CONF48_M  (SLCHOST_SLCHOST_CONF48_V << SLCHOST_SLCHOST_CONF48_S)
-#define SLCHOST_SLCHOST_CONF48_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF48_S  0
-/** SLCHOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF49    0x000000FFU
-#define SLCHOST_SLCHOST_CONF49_M  (SLCHOST_SLCHOST_CONF49_V << SLCHOST_SLCHOST_CONF49_S)
-#define SLCHOST_SLCHOST_CONF49_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF49_S  8
-/** SLCHOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF50    0x000000FFU
-#define SLCHOST_SLCHOST_CONF50_M  (SLCHOST_SLCHOST_CONF50_V << SLCHOST_SLCHOST_CONF50_S)
-#define SLCHOST_SLCHOST_CONF50_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF50_S  16
-/** SLCHOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF51    0x000000FFU
-#define SLCHOST_SLCHOST_CONF51_M  (SLCHOST_SLCHOST_CONF51_V << SLCHOST_SLCHOST_CONF51_S)
-#define SLCHOST_SLCHOST_CONF51_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF51_S  24
-
-/** SLCHOST_CONF_W13_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xb0)
-/** SLCHOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF52    0x000000FFU
-#define SLCHOST_SLCHOST_CONF52_M  (SLCHOST_SLCHOST_CONF52_V << SLCHOST_SLCHOST_CONF52_S)
-#define SLCHOST_SLCHOST_CONF52_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF52_S  0
-/** SLCHOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF53    0x000000FFU
-#define SLCHOST_SLCHOST_CONF53_M  (SLCHOST_SLCHOST_CONF53_V << SLCHOST_SLCHOST_CONF53_S)
-#define SLCHOST_SLCHOST_CONF53_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF53_S  8
-/** SLCHOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF54    0x000000FFU
-#define SLCHOST_SLCHOST_CONF54_M  (SLCHOST_SLCHOST_CONF54_V << SLCHOST_SLCHOST_CONF54_S)
-#define SLCHOST_SLCHOST_CONF54_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF54_S  16
-/** SLCHOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF55    0x000000FFU
-#define SLCHOST_SLCHOST_CONF55_M  (SLCHOST_SLCHOST_CONF55_V << SLCHOST_SLCHOST_CONF55_S)
-#define SLCHOST_SLCHOST_CONF55_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF55_S  24
-
-/** SLCHOST_CONF_W14_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xb4)
-/** SLCHOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF56    0x000000FFU
-#define SLCHOST_SLCHOST_CONF56_M  (SLCHOST_SLCHOST_CONF56_V << SLCHOST_SLCHOST_CONF56_S)
-#define SLCHOST_SLCHOST_CONF56_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF56_S  0
-/** SLCHOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF57    0x000000FFU
-#define SLCHOST_SLCHOST_CONF57_M  (SLCHOST_SLCHOST_CONF57_V << SLCHOST_SLCHOST_CONF57_S)
-#define SLCHOST_SLCHOST_CONF57_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF57_S  8
-/** SLCHOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF58    0x000000FFU
-#define SLCHOST_SLCHOST_CONF58_M  (SLCHOST_SLCHOST_CONF58_V << SLCHOST_SLCHOST_CONF58_S)
-#define SLCHOST_SLCHOST_CONF58_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF58_S  16
-/** SLCHOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF59    0x000000FFU
-#define SLCHOST_SLCHOST_CONF59_M  (SLCHOST_SLCHOST_CONF59_V << SLCHOST_SLCHOST_CONF59_S)
-#define SLCHOST_SLCHOST_CONF59_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF59_S  24
-
-/** SLCHOST_CONF_W15_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xb8)
-/** SLCHOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF60    0x000000FFU
-#define SLCHOST_SLCHOST_CONF60_M  (SLCHOST_SLCHOST_CONF60_V << SLCHOST_SLCHOST_CONF60_S)
-#define SLCHOST_SLCHOST_CONF60_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF60_S  0
-/** SLCHOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF61    0x000000FFU
-#define SLCHOST_SLCHOST_CONF61_M  (SLCHOST_SLCHOST_CONF61_V << SLCHOST_SLCHOST_CONF61_S)
-#define SLCHOST_SLCHOST_CONF61_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF61_S  8
-/** SLCHOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF62    0x000000FFU
-#define SLCHOST_SLCHOST_CONF62_M  (SLCHOST_SLCHOST_CONF62_V << SLCHOST_SLCHOST_CONF62_S)
-#define SLCHOST_SLCHOST_CONF62_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF62_S  16
-/** SLCHOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CONF63    0x000000FFU
-#define SLCHOST_SLCHOST_CONF63_M  (SLCHOST_SLCHOST_CONF63_V << SLCHOST_SLCHOST_CONF63_S)
-#define SLCHOST_SLCHOST_CONF63_V  0x000000FFU
-#define SLCHOST_SLCHOST_CONF63_S  24
-
-/** SLCHOST_CHECK_SUM0_REG register
- *  *******Description***********
- */
-#define SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xbc)
-/** SLCHOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CHECK_SUM0    0xFFFFFFFFU
-#define SLCHOST_SLCHOST_CHECK_SUM0_M  (SLCHOST_SLCHOST_CHECK_SUM0_V << SLCHOST_SLCHOST_CHECK_SUM0_S)
-#define SLCHOST_SLCHOST_CHECK_SUM0_V  0xFFFFFFFFU
-#define SLCHOST_SLCHOST_CHECK_SUM0_S  0
-
-/** SLCHOST_CHECK_SUM1_REG register
- *  *******Description***********
- */
-#define SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xc0)
-/** SLCHOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_CHECK_SUM1    0xFFFFFFFFU
-#define SLCHOST_SLCHOST_CHECK_SUM1_M  (SLCHOST_SLCHOST_CHECK_SUM1_V << SLCHOST_SLCHOST_CHECK_SUM1_S)
-#define SLCHOST_SLCHOST_CHECK_SUM1_V  0xFFFFFFFFU
-#define SLCHOST_SLCHOST_CHECK_SUM1_S  0
-
-/** SLCHOST_SLC1HOST_TOKEN_RDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xc4)
-/** SLCHOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0    0x00000FFFU
-#define SLCHOST_SLC1_TOKEN0_M  (SLCHOST_SLC1_TOKEN0_V << SLCHOST_SLC1_TOKEN0_S)
-#define SLCHOST_SLC1_TOKEN0_V  0x00000FFFU
-#define SLCHOST_SLC1_TOKEN0_S  0
-/** SLCHOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID    (BIT(12))
-#define SLCHOST_SLC1_RX_PF_VALID_M  (SLCHOST_SLC1_RX_PF_VALID_V << SLCHOST_SLC1_RX_PF_VALID_S)
-#define SLCHOST_SLC1_RX_PF_VALID_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_S  12
-/** SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1    0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_M  (SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V << SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S)
-#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V  0x00000FFFU
-#define SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S  16
-/** SLCHOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_EOF    0x0000000FU
-#define SLCHOST_SLC1_RX_PF_EOF_M  (SLCHOST_SLC1_RX_PF_EOF_V << SLCHOST_SLC1_RX_PF_EOF_S)
-#define SLCHOST_SLC1_RX_PF_EOF_V  0x0000000FU
-#define SLCHOST_SLC1_RX_PF_EOF_S  28
-
-/** SLCHOST_SLC0HOST_TOKEN_WDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xc8)
-/** SLCHOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN0_WD    0x00000FFFU
-#define SLCHOST_SLC0HOST_TOKEN0_WD_M  (SLCHOST_SLC0HOST_TOKEN0_WD_V << SLCHOST_SLC0HOST_TOKEN0_WD_S)
-#define SLCHOST_SLC0HOST_TOKEN0_WD_V  0x00000FFFU
-#define SLCHOST_SLC0HOST_TOKEN0_WD_S  0
-/** SLCHOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN1_WD    0x00000FFFU
-#define SLCHOST_SLC0HOST_TOKEN1_WD_M  (SLCHOST_SLC0HOST_TOKEN1_WD_V << SLCHOST_SLC0HOST_TOKEN1_WD_S)
-#define SLCHOST_SLC0HOST_TOKEN1_WD_V  0x00000FFFU
-#define SLCHOST_SLC0HOST_TOKEN1_WD_S  16
-
-/** SLCHOST_SLC1HOST_TOKEN_WDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xcc)
-/** SLCHOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN0_WD    0x00000FFFU
-#define SLCHOST_SLC1HOST_TOKEN0_WD_M  (SLCHOST_SLC1HOST_TOKEN0_WD_V << SLCHOST_SLC1HOST_TOKEN0_WD_S)
-#define SLCHOST_SLC1HOST_TOKEN0_WD_V  0x00000FFFU
-#define SLCHOST_SLC1HOST_TOKEN0_WD_S  0
-/** SLCHOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN1_WD    0x00000FFFU
-#define SLCHOST_SLC1HOST_TOKEN1_WD_M  (SLCHOST_SLC1HOST_TOKEN1_WD_V << SLCHOST_SLC1HOST_TOKEN1_WD_S)
-#define SLCHOST_SLC1HOST_TOKEN1_WD_V  0x00000FFFU
-#define SLCHOST_SLC1HOST_TOKEN1_WD_S  16
-
-/** SLCHOST_TOKEN_CON_REG register
- *  *******Description***********
- */
-#define SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xd0)
-/** SLCHOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN0_DEC    (BIT(0))
-#define SLCHOST_SLC0HOST_TOKEN0_DEC_M  (SLCHOST_SLC0HOST_TOKEN0_DEC_V << SLCHOST_SLC0HOST_TOKEN0_DEC_S)
-#define SLCHOST_SLC0HOST_TOKEN0_DEC_V  0x00000001U
-#define SLCHOST_SLC0HOST_TOKEN0_DEC_S  0
-/** SLCHOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN1_DEC    (BIT(1))
-#define SLCHOST_SLC0HOST_TOKEN1_DEC_M  (SLCHOST_SLC0HOST_TOKEN1_DEC_V << SLCHOST_SLC0HOST_TOKEN1_DEC_S)
-#define SLCHOST_SLC0HOST_TOKEN1_DEC_V  0x00000001U
-#define SLCHOST_SLC0HOST_TOKEN1_DEC_S  1
-/** SLCHOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN0_WR    (BIT(2))
-#define SLCHOST_SLC0HOST_TOKEN0_WR_M  (SLCHOST_SLC0HOST_TOKEN0_WR_V << SLCHOST_SLC0HOST_TOKEN0_WR_S)
-#define SLCHOST_SLC0HOST_TOKEN0_WR_V  0x00000001U
-#define SLCHOST_SLC0HOST_TOKEN0_WR_S  2
-/** SLCHOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TOKEN1_WR    (BIT(3))
-#define SLCHOST_SLC0HOST_TOKEN1_WR_M  (SLCHOST_SLC0HOST_TOKEN1_WR_V << SLCHOST_SLC0HOST_TOKEN1_WR_S)
-#define SLCHOST_SLC0HOST_TOKEN1_WR_V  0x00000001U
-#define SLCHOST_SLC0HOST_TOKEN1_WR_S  3
-/** SLCHOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN0_DEC    (BIT(4))
-#define SLCHOST_SLC1HOST_TOKEN0_DEC_M  (SLCHOST_SLC1HOST_TOKEN0_DEC_V << SLCHOST_SLC1HOST_TOKEN0_DEC_S)
-#define SLCHOST_SLC1HOST_TOKEN0_DEC_V  0x00000001U
-#define SLCHOST_SLC1HOST_TOKEN0_DEC_S  4
-/** SLCHOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN1_DEC    (BIT(5))
-#define SLCHOST_SLC1HOST_TOKEN1_DEC_M  (SLCHOST_SLC1HOST_TOKEN1_DEC_V << SLCHOST_SLC1HOST_TOKEN1_DEC_S)
-#define SLCHOST_SLC1HOST_TOKEN1_DEC_V  0x00000001U
-#define SLCHOST_SLC1HOST_TOKEN1_DEC_S  5
-/** SLCHOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN0_WR    (BIT(6))
-#define SLCHOST_SLC1HOST_TOKEN0_WR_M  (SLCHOST_SLC1HOST_TOKEN0_WR_V << SLCHOST_SLC1HOST_TOKEN0_WR_S)
-#define SLCHOST_SLC1HOST_TOKEN0_WR_V  0x00000001U
-#define SLCHOST_SLC1HOST_TOKEN0_WR_S  6
-/** SLCHOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TOKEN1_WR    (BIT(7))
-#define SLCHOST_SLC1HOST_TOKEN1_WR_M  (SLCHOST_SLC1HOST_TOKEN1_WR_V << SLCHOST_SLC1HOST_TOKEN1_WR_S)
-#define SLCHOST_SLC1HOST_TOKEN1_WR_V  0x00000001U
-#define SLCHOST_SLC1HOST_TOKEN1_WR_S  7
-/** SLCHOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_LEN_WR    (BIT(8))
-#define SLCHOST_SLC0HOST_LEN_WR_M  (SLCHOST_SLC0HOST_LEN_WR_V << SLCHOST_SLC0HOST_LEN_WR_S)
-#define SLCHOST_SLC0HOST_LEN_WR_V  0x00000001U
-#define SLCHOST_SLC0HOST_LEN_WR_S  8
-
-/** SLCHOST_SLC0HOST_INT_CLR_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd4)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_M  (SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_M  (SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_CLR    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_CLR_M  (SLCHOST_SLC0HOST_RX_START_INT_CLR_V << SLCHOST_SLC0HOST_RX_START_INT_CLR_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_CLR_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_CLR    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_CLR_M  (SLCHOST_SLC0HOST_TX_START_INT_CLR_V << SLCHOST_SLC0HOST_TX_START_INT_CLR_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_CLR_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_CLR    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_CLR_M  (SLCHOST_SLC0_RX_UDF_INT_CLR_V << SLCHOST_SLC0_RX_UDF_INT_CLR_S)
-#define SLCHOST_SLC0_RX_UDF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_CLR_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_CLR    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_CLR_M  (SLCHOST_SLC0_TX_OVF_INT_CLR_V << SLCHOST_SLC0_TX_OVF_INT_CLR_S)
-#define SLCHOST_SLC0_TX_OVF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_CLR_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_M  (SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_CLR    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT0_INT_CLR_V << SLCHOST_SLC0_EXT_BIT0_INT_CLR_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_CLR_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_CLR    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT1_INT_CLR_V << SLCHOST_SLC0_EXT_BIT1_INT_CLR_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_CLR_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_CLR    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT2_INT_CLR_V << SLCHOST_SLC0_EXT_BIT2_INT_CLR_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_CLR_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_CLR    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_M  (SLCHOST_SLC0_EXT_BIT3_INT_CLR_V << SLCHOST_SLC0_EXT_BIT3_INT_CLR_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_CLR_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S  24
-/** SLCHOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_CLR    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_CLR_M  (SLCHOST_GPIO_SDIO_INT_CLR_V << SLCHOST_GPIO_SDIO_INT_CLR_S)
-#define SLCHOST_GPIO_SDIO_INT_CLR_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_CLR_S  25
-
-/** SLCHOST_SLC1HOST_INT_CLR_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd8)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V << SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_M  (SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_M  (SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V << SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_CLR    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_CLR_M  (SLCHOST_SLC1HOST_RX_START_INT_CLR_V << SLCHOST_SLC1HOST_RX_START_INT_CLR_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_CLR_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_CLR    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_CLR_M  (SLCHOST_SLC1HOST_TX_START_INT_CLR_V << SLCHOST_SLC1HOST_TX_START_INT_CLR_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_CLR_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_CLR    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_CLR_M  (SLCHOST_SLC1_RX_UDF_INT_CLR_V << SLCHOST_SLC1_RX_UDF_INT_CLR_S)
-#define SLCHOST_SLC1_RX_UDF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_CLR_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_CLR    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_CLR_M  (SLCHOST_SLC1_TX_OVF_INT_CLR_V << SLCHOST_SLC1_TX_OVF_INT_CLR_S)
-#define SLCHOST_SLC1_TX_OVF_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_CLR_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_M  (SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V << SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_CLR    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT0_INT_CLR_V << SLCHOST_SLC1_EXT_BIT0_INT_CLR_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_CLR_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_CLR    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT1_INT_CLR_V << SLCHOST_SLC1_EXT_BIT1_INT_CLR_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_CLR_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_CLR    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT2_INT_CLR_V << SLCHOST_SLC1_EXT_BIT2_INT_CLR_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_CLR_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_CLR    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_M  (SLCHOST_SLC1_EXT_BIT3_INT_CLR_V << SLCHOST_SLC1_EXT_BIT3_INT_CLR_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_CLR_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S  25
-
-/** SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xdc)
-/** SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S)
-#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S)
-#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S  16
-/** SLCHOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S  17
-/** SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_GPIO_SDIO_INT_ENA    (BIT(25))
-#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_M  (SLCHOST_FN1_GPIO_SDIO_INT_ENA_V << SLCHOST_FN1_GPIO_SDIO_INT_ENA_S)
-#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_GPIO_SDIO_INT_ENA_S  25
-
-/** SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe0)
-/** SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S)
-#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S)
-#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S  16
-/** SLCHOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S  17
-/** SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
-#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-
-/** SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe4)
-/** SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S)
-#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S)
-#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S  16
-/** SLCHOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S  17
-/** SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_GPIO_SDIO_INT_ENA    (BIT(25))
-#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_M  (SLCHOST_FN2_GPIO_SDIO_INT_ENA_V << SLCHOST_FN2_GPIO_SDIO_INT_ENA_S)
-#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_GPIO_SDIO_INT_ENA_S  25
-
-/** SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe8)
-/** SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S)
-#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S)
-#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V << SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S  16
-/** SLCHOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V << SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S  17
-/** SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
-#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-
-/** SLCHOST_SLC0HOST_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xec)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA_M  (SLCHOST_SLC0HOST_RX_START_INT_ENA_V << SLCHOST_SLC0HOST_RX_START_INT_ENA_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA_M  (SLCHOST_SLC0HOST_TX_START_INT_ENA_V << SLCHOST_SLC0HOST_TX_START_INT_ENA_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_ENA_M  (SLCHOST_SLC0_RX_UDF_INT_ENA_V << SLCHOST_SLC0_RX_UDF_INT_ENA_S)
-#define SLCHOST_SLC0_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_ENA_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_ENA_M  (SLCHOST_SLC0_TX_OVF_INT_ENA_V << SLCHOST_SLC0_TX_OVF_INT_ENA_S)
-#define SLCHOST_SLC0_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_ENA_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT0_INT_ENA_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT1_INT_ENA_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT2_INT_ENA_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_M  (SLCHOST_SLC0_EXT_BIT3_INT_ENA_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_ENA    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_ENA_M  (SLCHOST_GPIO_SDIO_INT_ENA_V << SLCHOST_GPIO_SDIO_INT_ENA_S)
-#define SLCHOST_GPIO_SDIO_INT_ENA_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_ENA_S  25
-
-/** SLCHOST_SLC1HOST_INT_ENA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xf0)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA_M  (SLCHOST_SLC1HOST_RX_START_INT_ENA_V << SLCHOST_SLC1HOST_RX_START_INT_ENA_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA_M  (SLCHOST_SLC1HOST_TX_START_INT_ENA_V << SLCHOST_SLC1HOST_TX_START_INT_ENA_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_ENA    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_ENA_M  (SLCHOST_SLC1_RX_UDF_INT_ENA_V << SLCHOST_SLC1_RX_UDF_INT_ENA_S)
-#define SLCHOST_SLC1_RX_UDF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_ENA_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_ENA    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_ENA_M  (SLCHOST_SLC1_TX_OVF_INT_ENA_V << SLCHOST_SLC1_TX_OVF_INT_ENA_S)
-#define SLCHOST_SLC1_TX_OVF_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_ENA_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT0_INT_ENA_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT1_INT_ENA_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT2_INT_ENA_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_M  (SLCHOST_SLC1_EXT_BIT3_INT_ENA_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-
-/** SLCHOST_SLC0HOST_RX_INFOR_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf4)
-/** SLCHOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_INFOR    0x000FFFFFU
-#define SLCHOST_SLC0HOST_RX_INFOR_M  (SLCHOST_SLC0HOST_RX_INFOR_V << SLCHOST_SLC0HOST_RX_INFOR_S)
-#define SLCHOST_SLC0HOST_RX_INFOR_V  0x000FFFFFU
-#define SLCHOST_SLC0HOST_RX_INFOR_S  0
-
-/** SLCHOST_SLC1HOST_RX_INFOR_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf8)
-/** SLCHOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_INFOR    0x000FFFFFU
-#define SLCHOST_SLC1HOST_RX_INFOR_M  (SLCHOST_SLC1HOST_RX_INFOR_V << SLCHOST_SLC1HOST_RX_INFOR_S)
-#define SLCHOST_SLC1HOST_RX_INFOR_V  0x000FFFFFU
-#define SLCHOST_SLC1HOST_RX_INFOR_S  0
-
-/** SLCHOST_SLC0HOST_LEN_WD_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xfc)
-/** SLCHOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_LEN_WD    0xFFFFFFFFU
-#define SLCHOST_SLC0HOST_LEN_WD_M  (SLCHOST_SLC0HOST_LEN_WD_V << SLCHOST_SLC0HOST_LEN_WD_S)
-#define SLCHOST_SLC0HOST_LEN_WD_V  0xFFFFFFFFU
-#define SLCHOST_SLC0HOST_LEN_WD_S  0
-
-/** SLCHOST_SLC_APBWIN_WDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100)
-/** SLCHOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_WDATA    0xFFFFFFFFU
-#define SLCHOST_SLC_APBWIN_WDATA_M  (SLCHOST_SLC_APBWIN_WDATA_V << SLCHOST_SLC_APBWIN_WDATA_S)
-#define SLCHOST_SLC_APBWIN_WDATA_V  0xFFFFFFFFU
-#define SLCHOST_SLC_APBWIN_WDATA_S  0
-
-/** SLCHOST_SLC_APBWIN_CONF_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104)
-/** SLCHOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_ADDR    0x0FFFFFFFU
-#define SLCHOST_SLC_APBWIN_ADDR_M  (SLCHOST_SLC_APBWIN_ADDR_V << SLCHOST_SLC_APBWIN_ADDR_S)
-#define SLCHOST_SLC_APBWIN_ADDR_V  0x0FFFFFFFU
-#define SLCHOST_SLC_APBWIN_ADDR_S  0
-/** SLCHOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_WR    (BIT(28))
-#define SLCHOST_SLC_APBWIN_WR_M  (SLCHOST_SLC_APBWIN_WR_V << SLCHOST_SLC_APBWIN_WR_S)
-#define SLCHOST_SLC_APBWIN_WR_V  0x00000001U
-#define SLCHOST_SLC_APBWIN_WR_S  28
-/** SLCHOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_START    (BIT(29))
-#define SLCHOST_SLC_APBWIN_START_M  (SLCHOST_SLC_APBWIN_START_V << SLCHOST_SLC_APBWIN_START_S)
-#define SLCHOST_SLC_APBWIN_START_V  0x00000001U
-#define SLCHOST_SLC_APBWIN_START_S  29
-
-/** SLCHOST_SLC_APBWIN_RDATA_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108)
-/** SLCHOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC_APBWIN_RDATA    0xFFFFFFFFU
-#define SLCHOST_SLC_APBWIN_RDATA_M  (SLCHOST_SLC_APBWIN_RDATA_V << SLCHOST_SLC_APBWIN_RDATA_S)
-#define SLCHOST_SLC_APBWIN_RDATA_V  0xFFFFFFFFU
-#define SLCHOST_SLC_APBWIN_RDATA_S  0
-
-/** SLCHOST_RDCLR0_REG register
- *  *******Description***********
- */
-#define SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10c)
-/** SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR    0x000001FFU
-#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_M  (SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S)
-#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V  0x000001FFU
-#define SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S  0
-/** SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR    0x000001FFU
-#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_M  (SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S)
-#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V  0x000001FFU
-#define SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S  9
-
-/** SLCHOST_RDCLR1_REG register
- *  *******Description***********
- */
-#define SLCHOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110)
-/** SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR    0x000001FFU
-#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_M  (SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S)
-#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V  0x000001FFU
-#define SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S  0
-/** SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR    0x000001FFU
-#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_M  (SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S)
-#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V  0x000001FFU
-#define SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S  9
-
-/** SLCHOST_SLC0HOST_INT_ENA1_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114)
-/** SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1    (BIT(0))
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S  0
-/** SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1    (BIT(1))
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S  1
-/** SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1    (BIT(2))
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S  2
-/** SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1    (BIT(3))
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S  3
-/** SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1    (BIT(4))
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S  4
-/** SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1    (BIT(5))
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S  5
-/** SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1    (BIT(6))
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S  6
-/** SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1    (BIT(7))
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_M  (SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S)
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S  7
-/** SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(8))
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_M  (SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S)
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S  8
-/** SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(9))
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_M  (SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S)
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S  9
-/** SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1    (BIT(10))
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_M  (SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S)
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S  10
-/** SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1    (BIT(11))
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_M  (SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S)
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S  11
-/** SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1    (BIT(12))
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S)
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S  12
-/** SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1    (BIT(13))
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S)
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S  13
-/** SLCHOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA1    (BIT(14))
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_M  (SLCHOST_SLC0HOST_RX_START_INT_ENA1_V << SLCHOST_SLC0HOST_RX_START_INT_ENA1_S)
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0HOST_RX_START_INT_ENA1_S  14
-/** SLCHOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA1    (BIT(15))
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_M  (SLCHOST_SLC0HOST_TX_START_INT_ENA1_V << SLCHOST_SLC0HOST_TX_START_INT_ENA1_S)
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0HOST_TX_START_INT_ENA1_S  15
-/** SLCHOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_UDF_INT_ENA1    (BIT(16))
-#define SLCHOST_SLC0_RX_UDF_INT_ENA1_M  (SLCHOST_SLC0_RX_UDF_INT_ENA1_V << SLCHOST_SLC0_RX_UDF_INT_ENA1_S)
-#define SLCHOST_SLC0_RX_UDF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_RX_UDF_INT_ENA1_S  16
-/** SLCHOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_TX_OVF_INT_ENA1    (BIT(17))
-#define SLCHOST_SLC0_TX_OVF_INT_ENA1_M  (SLCHOST_SLC0_TX_OVF_INT_ENA1_V << SLCHOST_SLC0_TX_OVF_INT_ENA1_S)
-#define SLCHOST_SLC0_TX_OVF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_TX_OVF_INT_ENA1_S  17
-/** SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1    (BIT(18))
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_M  (SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S)
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S  18
-/** SLCHOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1    (BIT(19))
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S)
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S  19
-/** SLCHOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1    (BIT(20))
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S)
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S  20
-/** SLCHOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1    (BIT(21))
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S)
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S  21
-/** SLCHOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1    (BIT(22))
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_M  (SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S)
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S  22
-/** SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1    (BIT(23))
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S)
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S  23
-/** SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1    (BIT(24))
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_M  (SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S)
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S  24
-/** SLCHOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_GPIO_SDIO_INT_ENA1    (BIT(25))
-#define SLCHOST_GPIO_SDIO_INT_ENA1_M  (SLCHOST_GPIO_SDIO_INT_ENA1_V << SLCHOST_GPIO_SDIO_INT_ENA1_S)
-#define SLCHOST_GPIO_SDIO_INT_ENA1_V  0x00000001U
-#define SLCHOST_GPIO_SDIO_INT_ENA1_S  25
-
-/** SLCHOST_SLC1HOST_INT_ENA1_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118)
-/** SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1    (BIT(0))
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S  0
-/** SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1    (BIT(1))
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S  1
-/** SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1    (BIT(2))
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S  2
-/** SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1    (BIT(3))
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S  3
-/** SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1    (BIT(4))
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S  4
-/** SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1    (BIT(5))
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S  5
-/** SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1    (BIT(6))
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S  6
-/** SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1    (BIT(7))
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_M  (SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S)
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S  7
-/** SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1    (BIT(8))
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_M  (SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S)
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S  8
-/** SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1    (BIT(9))
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_M  (SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S)
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S  9
-/** SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1    (BIT(10))
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_M  (SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S)
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S  10
-/** SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1    (BIT(11))
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_M  (SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S)
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S  11
-/** SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1    (BIT(12))
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S)
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S  12
-/** SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1    (BIT(13))
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V << SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S)
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S  13
-/** SLCHOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA1    (BIT(14))
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_M  (SLCHOST_SLC1HOST_RX_START_INT_ENA1_V << SLCHOST_SLC1HOST_RX_START_INT_ENA1_S)
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1HOST_RX_START_INT_ENA1_S  14
-/** SLCHOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA1    (BIT(15))
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_M  (SLCHOST_SLC1HOST_TX_START_INT_ENA1_V << SLCHOST_SLC1HOST_TX_START_INT_ENA1_S)
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1HOST_TX_START_INT_ENA1_S  15
-/** SLCHOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_UDF_INT_ENA1    (BIT(16))
-#define SLCHOST_SLC1_RX_UDF_INT_ENA1_M  (SLCHOST_SLC1_RX_UDF_INT_ENA1_V << SLCHOST_SLC1_RX_UDF_INT_ENA1_S)
-#define SLCHOST_SLC1_RX_UDF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_RX_UDF_INT_ENA1_S  16
-/** SLCHOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_TX_OVF_INT_ENA1    (BIT(17))
-#define SLCHOST_SLC1_TX_OVF_INT_ENA1_M  (SLCHOST_SLC1_TX_OVF_INT_ENA1_V << SLCHOST_SLC1_TX_OVF_INT_ENA1_S)
-#define SLCHOST_SLC1_TX_OVF_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_TX_OVF_INT_ENA1_S  17
-/** SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1    (BIT(18))
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_M  (SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V << SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S)
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S  18
-/** SLCHOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1    (BIT(19))
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S)
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S  19
-/** SLCHOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1    (BIT(20))
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S)
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S  20
-/** SLCHOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1    (BIT(21))
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S)
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S  21
-/** SLCHOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1    (BIT(22))
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_M  (SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V << SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S)
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S  22
-/** SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1    (BIT(23))
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S)
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S  23
-/** SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1    (BIT(24))
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_M  (SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S)
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S  24
-/** SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1    (BIT(25))
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M  (SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S)
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V  0x00000001U
-#define SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S  25
-
-/** SLCHOST_SLCHOSTDATE_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178)
-/** SLCHOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_DATE    0xFFFFFFFFU
-#define SLCHOST_SLCHOST_DATE_M  (SLCHOST_SLCHOST_DATE_V << SLCHOST_SLCHOST_DATE_S)
-#define SLCHOST_SLCHOST_DATE_V  0xFFFFFFFFU
-#define SLCHOST_SLCHOST_DATE_S  0
-
-/** SLCHOST_SLCHOSTID_REG register
- *  *******Description***********
- */
-#define SLCHOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17c)
-/** SLCHOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536;
- *  *******Description***********
- */
-#define SLCHOST_SLCHOST_ID    0xFFFFFFFFU
-#define SLCHOST_SLCHOST_ID_M  (SLCHOST_SLCHOST_ID_V << SLCHOST_SLCHOST_ID_S)
-#define SLCHOST_SLCHOST_ID_V  0xFFFFFFFFU
-#define SLCHOST_SLCHOST_ID_S  0
-
-/** SLCHOST_CONF_REG register
- *  *******Description***********
- */
-#define SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1f0)
-/** SLCHOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_SDIO11    0x0000001FU
-#define SLCHOST_FRC_SDIO11_M  (SLCHOST_FRC_SDIO11_V << SLCHOST_FRC_SDIO11_S)
-#define SLCHOST_FRC_SDIO11_V  0x0000001FU
-#define SLCHOST_FRC_SDIO11_S  0
-/** SLCHOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_SDIO20    0x0000001FU
-#define SLCHOST_FRC_SDIO20_M  (SLCHOST_FRC_SDIO20_V << SLCHOST_FRC_SDIO20_S)
-#define SLCHOST_FRC_SDIO20_V  0x0000001FU
-#define SLCHOST_FRC_SDIO20_S  5
-/** SLCHOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_NEG_SAMP    0x0000001FU
-#define SLCHOST_FRC_NEG_SAMP_M  (SLCHOST_FRC_NEG_SAMP_V << SLCHOST_FRC_NEG_SAMP_S)
-#define SLCHOST_FRC_NEG_SAMP_V  0x0000001FU
-#define SLCHOST_FRC_NEG_SAMP_S  10
-/** SLCHOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_POS_SAMP    0x0000001FU
-#define SLCHOST_FRC_POS_SAMP_M  (SLCHOST_FRC_POS_SAMP_V << SLCHOST_FRC_POS_SAMP_S)
-#define SLCHOST_FRC_POS_SAMP_V  0x0000001FU
-#define SLCHOST_FRC_POS_SAMP_S  15
-/** SLCHOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_FRC_QUICK_IN    0x0000001FU
-#define SLCHOST_FRC_QUICK_IN_M  (SLCHOST_FRC_QUICK_IN_V << SLCHOST_FRC_QUICK_IN_S)
-#define SLCHOST_FRC_QUICK_IN_V  0x0000001FU
-#define SLCHOST_FRC_QUICK_IN_S  20
-/** SLCHOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO20_INT_DELAY    (BIT(25))
-#define SLCHOST_SDIO20_INT_DELAY_M  (SLCHOST_SDIO20_INT_DELAY_V << SLCHOST_SDIO20_INT_DELAY_S)
-#define SLCHOST_SDIO20_INT_DELAY_V  0x00000001U
-#define SLCHOST_SDIO20_INT_DELAY_S  25
-/** SLCHOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO_PAD_PULLUP    (BIT(26))
-#define SLCHOST_SDIO_PAD_PULLUP_M  (SLCHOST_SDIO_PAD_PULLUP_V << SLCHOST_SDIO_PAD_PULLUP_S)
-#define SLCHOST_SDIO_PAD_PULLUP_V  0x00000001U
-#define SLCHOST_SDIO_PAD_PULLUP_S  26
-/** SLCHOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_HSPEED_CON_EN    (BIT(27))
-#define SLCHOST_HSPEED_CON_EN_M  (SLCHOST_HSPEED_CON_EN_V << SLCHOST_HSPEED_CON_EN_S)
-#define SLCHOST_HSPEED_CON_EN_V  0x00000001U
-#define SLCHOST_HSPEED_CON_EN_S  27
-
-/** SLCHOST_INF_ST_REG register
- *  *******Description***********
- */
-#define SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1f4)
-/** SLCHOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO20_MODE    0x0000001FU
-#define SLCHOST_SDIO20_MODE_M  (SLCHOST_SDIO20_MODE_V << SLCHOST_SDIO20_MODE_S)
-#define SLCHOST_SDIO20_MODE_V  0x0000001FU
-#define SLCHOST_SDIO20_MODE_S  0
-/** SLCHOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO_NEG_SAMP    0x0000001FU
-#define SLCHOST_SDIO_NEG_SAMP_M  (SLCHOST_SDIO_NEG_SAMP_V << SLCHOST_SDIO_NEG_SAMP_S)
-#define SLCHOST_SDIO_NEG_SAMP_V  0x0000001FU
-#define SLCHOST_SDIO_NEG_SAMP_S  5
-/** SLCHOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0;
- *  *******Description***********
- */
-#define SLCHOST_SDIO_QUICK_IN    0x0000001FU
-#define SLCHOST_SDIO_QUICK_IN_M  (SLCHOST_SDIO_QUICK_IN_V << SLCHOST_SDIO_QUICK_IN_S)
-#define SLCHOST_SDIO_QUICK_IN_V  0x0000001FU
-#define SLCHOST_SDIO_QUICK_IN_S  10
-/** SLCHOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0;
- *  dll is controlled by software
- */
-#define SLCHOST_DLL_ON_SW    (BIT(15))
-#define SLCHOST_DLL_ON_SW_M  (SLCHOST_DLL_ON_SW_V << SLCHOST_DLL_ON_SW_S)
-#define SLCHOST_DLL_ON_SW_V  0x00000001U
-#define SLCHOST_DLL_ON_SW_S  15
-/** SLCHOST_DLL_ON : R/W; bitpos: [16]; default: 0;
- *  Software dll on
- */
-#define SLCHOST_DLL_ON    (BIT(16))
-#define SLCHOST_DLL_ON_M  (SLCHOST_DLL_ON_V << SLCHOST_DLL_ON_S)
-#define SLCHOST_DLL_ON_V  0x00000001U
-#define SLCHOST_DLL_ON_S  16
-/** SLCHOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0;
- *  dll clock mode is controlled by software
- */
-#define SLCHOST_CLK_MODE_SW    (BIT(17))
-#define SLCHOST_CLK_MODE_SW_M  (SLCHOST_CLK_MODE_SW_V << SLCHOST_CLK_MODE_SW_S)
-#define SLCHOST_CLK_MODE_SW_V  0x00000001U
-#define SLCHOST_CLK_MODE_SW_S  17
-/** SLCHOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0;
- *  Software set clock mode
- */
-#define SLCHOST_CLK_MODE    0x00000003U
-#define SLCHOST_CLK_MODE_M  (SLCHOST_CLK_MODE_V << SLCHOST_CLK_MODE_S)
-#define SLCHOST_CLK_MODE_V  0x00000003U
-#define SLCHOST_CLK_MODE_S  18
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/host_struct.h b/components/soc/esp32c5/include/soc/host_struct.h
deleted file mode 100644
index e14afe78f2..0000000000
--- a/components/soc/esp32c5/include/soc/host_struct.h
+++ /dev/null
@@ -1,2738 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: ********Registers */
-/** Type of func2_0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** slc_func2_int : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_func2_int:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} slchost_func2_0_reg_t;
-
-/** Type of func2_1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_func2_int_en : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_func2_int_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} slchost_func2_1_reg_t;
-
-/** Type of func2_2 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_func1_mdstat : R/W; bitpos: [0]; default: 1;
-         *  *******Description***********
-         */
-        uint32_t slc_func1_mdstat:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} slchost_func2_2_reg_t;
-
-/** Type of gpio_status0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int0:32;
-    };
-    uint32_t val;
-} slchost_gpio_status0_reg_t;
-
-/** Type of gpio_status1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int1:32;
-    };
-    uint32_t val;
-} slchost_gpio_status1_reg_t;
-
-/** Type of gpio_in0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_in0:32;
-    };
-    uint32_t val;
-} slchost_gpio_in0_reg_t;
-
-/** Type of gpio_in1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_in1:32;
-    };
-    uint32_t val;
-} slchost_gpio_in1_reg_t;
-
-/** Type of slc0host_token_rdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_token0 : RO; bitpos: [11:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0:12;
-        /** slc0_rx_pf_valid : RO; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid:1;
-        uint32_t reserved_13:3;
-        /** hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_token1:12;
-        /** slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_eof:4;
-    };
-    uint32_t val;
-} slchost_slc0host_token_rdata_reg_t;
-
-/** Type of slc0_host_pf register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_pf_data : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_pf_data:32;
-    };
-    uint32_t val;
-} slchost_slc0_host_pf_reg_t;
-
-/** Type of slc1_host_pf register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_pf_data : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_pf_data:32;
-    };
-    uint32_t val;
-} slchost_slc1_host_pf_reg_t;
-
-/** Type of slc0host_int_raw register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_raw:1;
-        /** slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_raw:1;
-        /** slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_raw:1;
-        /** slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_raw:1;
-        /** slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_raw:1;
-        /** slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_raw:1;
-        /** slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_raw:1;
-        /** slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_raw:1;
-        /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_raw:1;
-        /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_raw:1;
-        /** slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_raw:1;
-        /** slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_raw:1;
-        /** slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_raw:1;
-        /** slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_raw:1;
-        /** slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_raw:1;
-        /** slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_raw:1;
-        /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_raw:1;
-        /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_raw:1;
-        /** slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_raw:1;
-        /** slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_raw:1;
-        /** slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_raw:1;
-        /** slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_raw:1;
-        /** slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_raw:1;
-        /** slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_raw:1;
-        /** slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_raw:1;
-        /** gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_raw:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_raw_reg_t;
-
-/** Type of slc1host_int_raw register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_raw:1;
-        /** slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_raw:1;
-        /** slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_raw:1;
-        /** slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_raw:1;
-        /** slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_raw:1;
-        /** slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_raw:1;
-        /** slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_raw:1;
-        /** slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_raw:1;
-        /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_raw:1;
-        /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_raw:1;
-        /** slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_raw:1;
-        /** slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_raw:1;
-        /** slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_raw:1;
-        /** slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_raw:1;
-        /** slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_raw:1;
-        /** slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_raw:1;
-        /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_raw:1;
-        /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_raw:1;
-        /** slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_raw:1;
-        /** slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_raw:1;
-        /** slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_raw:1;
-        /** slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_raw:1;
-        /** slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_raw:1;
-        /** slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_raw:1;
-        /** slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_raw:1;
-        /** slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_raw:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_raw_reg_t;
-
-/** Type of slc0host_int_st register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_st:1;
-        /** slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_st:1;
-        /** slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_st:1;
-        /** slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_st:1;
-        /** slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_st:1;
-        /** slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_st:1;
-        /** slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_st:1;
-        /** slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_st:1;
-        /** slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_st:1;
-        /** slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_st:1;
-        /** slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_st:1;
-        /** slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_st:1;
-        /** slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_st:1;
-        /** slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_st:1;
-        /** slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_st:1;
-        /** slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_st:1;
-        /** slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_st:1;
-        /** slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_st:1;
-        /** slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_st:1;
-        /** slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_st:1;
-        /** slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_st:1;
-        /** slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_st:1;
-        /** slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_st:1;
-        /** slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_st:1;
-        /** slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_st:1;
-        /** gpio_sdio_int_st : RO; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_st:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_st_reg_t;
-
-/** Type of slc1host_int_st register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_st:1;
-        /** slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_st:1;
-        /** slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_st:1;
-        /** slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_st:1;
-        /** slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_st:1;
-        /** slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_st:1;
-        /** slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_st:1;
-        /** slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_st:1;
-        /** slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_st:1;
-        /** slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_st:1;
-        /** slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_st:1;
-        /** slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_st:1;
-        /** slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_st:1;
-        /** slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_st:1;
-        /** slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_st:1;
-        /** slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_st:1;
-        /** slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_st:1;
-        /** slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_st:1;
-        /** slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_st:1;
-        /** slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_st:1;
-        /** slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_st:1;
-        /** slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_st:1;
-        /** slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_st:1;
-        /** slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_st:1;
-        /** slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_st:1;
-        /** slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_st:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_st_reg_t;
-
-/** Type of pkt_len register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len:20;
-        /** hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len_check:12;
-    };
-    uint32_t val;
-} slchost_pkt_len_reg_t;
-
-/** Type of state_w0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_state0 : RO; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state0:8;
-        /** slchost_state1 : RO; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state1:8;
-        /** slchost_state2 : RO; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state2:8;
-        /** slchost_state3 : RO; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state3:8;
-    };
-    uint32_t val;
-} slchost_state_w0_reg_t;
-
-/** Type of state_w1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_state4 : RO; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state4:8;
-        /** slchost_state5 : RO; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state5:8;
-        /** slchost_state6 : RO; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state6:8;
-        /** slchost_state7 : RO; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_state7:8;
-    };
-    uint32_t val;
-} slchost_state_w1_reg_t;
-
-/** Type of conf_w0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf0 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf0:8;
-        /** slchost_conf1 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf1:8;
-        /** slchost_conf2 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf2:8;
-        /** slchost_conf3 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf3:8;
-    };
-    uint32_t val;
-} slchost_conf_w0_reg_t;
-
-/** Type of conf_w1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf4 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf4:8;
-        /** slchost_conf5 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf5:8;
-        /** slchost_conf6 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf6:8;
-        /** slchost_conf7 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf7:8;
-    };
-    uint32_t val;
-} slchost_conf_w1_reg_t;
-
-/** Type of conf_w2 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf8 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf8:8;
-        /** slchost_conf9 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf9:8;
-        /** slchost_conf10 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf10:8;
-        /** slchost_conf11 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf11:8;
-    };
-    uint32_t val;
-} slchost_conf_w2_reg_t;
-
-/** Type of conf_w3 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf12 : R/W; bitpos: [7:0]; default: 192;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf12:8;
-        /** slchost_conf13 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf13:8;
-        /** slchost_conf14 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf14:8;
-        /** slchost_conf15 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf15:8;
-    };
-    uint32_t val;
-} slchost_conf_w3_reg_t;
-
-/** Type of conf_w4 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf16 : R/W; bitpos: [7:0]; default: 255;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf16:8;
-        /** slchost_conf17 : R/W; bitpos: [15:8]; default: 1;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf17:8;
-        /** slchost_conf18 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf18:8;
-        /** slchost_conf19 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf19:8;
-    };
-    uint32_t val;
-} slchost_conf_w4_reg_t;
-
-/** Type of conf_w5 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf20 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf20:8;
-        /** slchost_conf21 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf21:8;
-        /** slchost_conf22 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf22:8;
-        /** slchost_conf23 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf23:8;
-    };
-    uint32_t val;
-} slchost_conf_w5_reg_t;
-
-/** Type of win_cmd register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_win_cmd : R/W; bitpos: [15:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_win_cmd:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} slchost_win_cmd_reg_t;
-
-/** Type of conf_w6 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf24 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf24:8;
-        /** slchost_conf25 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf25:8;
-        /** slchost_conf26 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf26:8;
-        /** slchost_conf27 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf27:8;
-    };
-    uint32_t val;
-} slchost_conf_w6_reg_t;
-
-/** Type of conf_w7 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf28 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf28:8;
-        /** slchost_conf29 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf29:8;
-        /** slchost_conf30 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf30:8;
-        /** slchost_conf31 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf31:8;
-    };
-    uint32_t val;
-} slchost_conf_w7_reg_t;
-
-/** Type of pkt_len0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len0:20;
-        /** hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len0_check:12;
-    };
-    uint32_t val;
-} slchost_pkt_len0_reg_t;
-
-/** Type of pkt_len1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len1:20;
-        /** hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len1_check:12;
-    };
-    uint32_t val;
-} slchost_pkt_len1_reg_t;
-
-/** Type of pkt_len2 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len2:20;
-        /** hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc0_len2_check:12;
-    };
-    uint32_t val;
-} slchost_pkt_len2_reg_t;
-
-/** Type of conf_w8 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf32 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf32:8;
-        /** slchost_conf33 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf33:8;
-        /** slchost_conf34 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf34:8;
-        /** slchost_conf35 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf35:8;
-    };
-    uint32_t val;
-} slchost_conf_w8_reg_t;
-
-/** Type of conf_w9 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf36 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf36:8;
-        /** slchost_conf37 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf37:8;
-        /** slchost_conf38 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf38:8;
-        /** slchost_conf39 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf39:8;
-    };
-    uint32_t val;
-} slchost_conf_w9_reg_t;
-
-/** Type of conf_w10 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf40 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf40:8;
-        /** slchost_conf41 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf41:8;
-        /** slchost_conf42 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf42:8;
-        /** slchost_conf43 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf43:8;
-    };
-    uint32_t val;
-} slchost_conf_w10_reg_t;
-
-/** Type of conf_w11 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf44 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf44:8;
-        /** slchost_conf45 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf45:8;
-        /** slchost_conf46 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf46:8;
-        /** slchost_conf47 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf47:8;
-    };
-    uint32_t val;
-} slchost_conf_w11_reg_t;
-
-/** Type of conf_w12 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf48 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf48:8;
-        /** slchost_conf49 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf49:8;
-        /** slchost_conf50 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf50:8;
-        /** slchost_conf51 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf51:8;
-    };
-    uint32_t val;
-} slchost_conf_w12_reg_t;
-
-/** Type of conf_w13 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf52 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf52:8;
-        /** slchost_conf53 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf53:8;
-        /** slchost_conf54 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf54:8;
-        /** slchost_conf55 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf55:8;
-    };
-    uint32_t val;
-} slchost_conf_w13_reg_t;
-
-/** Type of conf_w14 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf56 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf56:8;
-        /** slchost_conf57 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf57:8;
-        /** slchost_conf58 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf58:8;
-        /** slchost_conf59 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf59:8;
-    };
-    uint32_t val;
-} slchost_conf_w14_reg_t;
-
-/** Type of conf_w15 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_conf60 : R/W; bitpos: [7:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf60:8;
-        /** slchost_conf61 : R/W; bitpos: [15:8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf61:8;
-        /** slchost_conf62 : R/W; bitpos: [23:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf62:8;
-        /** slchost_conf63 : R/W; bitpos: [31:24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_conf63:8;
-    };
-    uint32_t val;
-} slchost_conf_w15_reg_t;
-
-/** Type of check_sum0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_check_sum0 : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slchost_check_sum0:32;
-    };
-    uint32_t val;
-} slchost_check_sum0_reg_t;
-
-/** Type of check_sum1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_check_sum1 : RO; bitpos: [31:0]; default: 319;
-         *  *******Description***********
-         */
-        uint32_t slchost_check_sum1:32;
-    };
-    uint32_t val;
-} slchost_check_sum1_reg_t;
-
-/** Type of slc1host_token_rdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_token0 : RO; bitpos: [11:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0:12;
-        /** slc1_rx_pf_valid : RO; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid:1;
-        uint32_t reserved_13:3;
-        /** hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hostslchost_slc1_token1:12;
-        /** slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_eof:4;
-    };
-    uint32_t val;
-} slchost_slc1host_token_rdata_reg_t;
-
-/** Type of slc0host_token_wdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token0_wd:12;
-        uint32_t reserved_12:4;
-        /** slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token1_wd:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} slchost_slc0host_token_wdata_reg_t;
-
-/** Type of slc1host_token_wdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token0_wd:12;
-        uint32_t reserved_12:4;
-        /** slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token1_wd:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} slchost_slc1host_token_wdata_reg_t;
-
-/** Type of token_con register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0host_token0_dec : WT; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token0_dec:1;
-        /** slc0host_token1_dec : WT; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token1_dec:1;
-        /** slc0host_token0_wr : WT; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token0_wr:1;
-        /** slc0host_token1_wr : WT; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_token1_wr:1;
-        /** slc1host_token0_dec : WT; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token0_dec:1;
-        /** slc1host_token1_dec : WT; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token1_dec:1;
-        /** slc1host_token0_wr : WT; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token0_wr:1;
-        /** slc1host_token1_wr : WT; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_token1_wr:1;
-        /** slc0host_len_wr : WT; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_len_wr:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} slchost_token_con_reg_t;
-
-/** Type of slc0host_int_clr register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_clr:1;
-        /** slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_clr:1;
-        /** slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_clr:1;
-        /** slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_clr:1;
-        /** slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_clr:1;
-        /** slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_clr:1;
-        /** slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_clr:1;
-        /** slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_clr:1;
-        /** slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_clr:1;
-        /** slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_clr:1;
-        /** slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_clr:1;
-        /** slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_clr:1;
-        /** slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_clr:1;
-        /** slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_clr:1;
-        /** slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_clr:1;
-        /** slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_clr:1;
-        /** slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_clr:1;
-        /** slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_clr:1;
-        /** slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_clr:1;
-        /** slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_clr:1;
-        /** slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_clr:1;
-        /** slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_clr:1;
-        /** slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_clr:1;
-        /** slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_clr:1;
-        /** slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_clr:1;
-        /** gpio_sdio_int_clr : WT; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_clr:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_clr_reg_t;
-
-/** Type of slc1host_int_clr register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_clr:1;
-        /** slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_clr:1;
-        /** slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_clr:1;
-        /** slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_clr:1;
-        /** slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_clr:1;
-        /** slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_clr:1;
-        /** slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_clr:1;
-        /** slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_clr:1;
-        /** slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_clr:1;
-        /** slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_clr:1;
-        /** slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_clr:1;
-        /** slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_clr:1;
-        /** slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_clr:1;
-        /** slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_clr:1;
-        /** slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_clr:1;
-        /** slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_clr:1;
-        /** slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_clr:1;
-        /** slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_clr:1;
-        /** slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_clr:1;
-        /** slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_clr:1;
-        /** slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_clr:1;
-        /** slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_clr:1;
-        /** slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_clr:1;
-        /** slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_clr:1;
-        /** slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_clr:1;
-        /** slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_clr:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_clr_reg_t;
-
-/** Type of slc0host_func1_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit0_int_ena:1;
-        /** fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit1_int_ena:1;
-        /** fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit2_int_ena:1;
-        /** fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit3_int_ena:1;
-        /** fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit4_int_ena:1;
-        /** fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit5_int_ena:1;
-        /** fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit6_int_ena:1;
-        /** fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tohost_bit7_int_ena:1;
-        /** fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_token0_1to0_int_ena:1;
-        /** fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_token1_1to0_int_ena:1;
-        /** fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_token0_0to1_int_ena:1;
-        /** fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_token1_0to1_int_ena:1;
-        /** fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0host_rx_sof_int_ena:1;
-        /** fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0host_rx_eof_int_ena:1;
-        /** fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0host_rx_start_int_ena:1;
-        /** fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0host_tx_start_int_ena:1;
-        /** fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_rx_udf_int_ena:1;
-        /** fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_tx_ovf_int_ena:1;
-        /** fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_rx_pf_valid_int_ena:1;
-        /** fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_ext_bit0_int_ena:1;
-        /** fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_ext_bit1_int_ena:1;
-        /** fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_ext_bit2_int_ena:1;
-        /** fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_ext_bit3_int_ena:1;
-        /** fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_rx_new_packet_int_ena:1;
-        /** fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc0_host_rd_retry_int_ena:1;
-        /** fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_gpio_sdio_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_func1_int_ena_reg_t;
-
-/** Type of slc1host_func1_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit0_int_ena:1;
-        /** fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit1_int_ena:1;
-        /** fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit2_int_ena:1;
-        /** fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit3_int_ena:1;
-        /** fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit4_int_ena:1;
-        /** fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit5_int_ena:1;
-        /** fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit6_int_ena:1;
-        /** fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tohost_bit7_int_ena:1;
-        /** fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_token0_1to0_int_ena:1;
-        /** fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_token1_1to0_int_ena:1;
-        /** fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_token0_0to1_int_ena:1;
-        /** fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_token1_0to1_int_ena:1;
-        /** fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1host_rx_sof_int_ena:1;
-        /** fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1host_rx_eof_int_ena:1;
-        /** fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1host_rx_start_int_ena:1;
-        /** fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1host_tx_start_int_ena:1;
-        /** fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_rx_udf_int_ena:1;
-        /** fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_tx_ovf_int_ena:1;
-        /** fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_rx_pf_valid_int_ena:1;
-        /** fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_ext_bit0_int_ena:1;
-        /** fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_ext_bit1_int_ena:1;
-        /** fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_ext_bit2_int_ena:1;
-        /** fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_ext_bit3_int_ena:1;
-        /** fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_wifi_rx_new_packet_int_ena:1;
-        /** fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_host_rd_retry_int_ena:1;
-        /** fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn1_slc1_bt_rx_new_packet_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_func1_int_ena_reg_t;
-
-/** Type of slc0host_func2_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit0_int_ena:1;
-        /** fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit1_int_ena:1;
-        /** fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit2_int_ena:1;
-        /** fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit3_int_ena:1;
-        /** fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit4_int_ena:1;
-        /** fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit5_int_ena:1;
-        /** fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit6_int_ena:1;
-        /** fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tohost_bit7_int_ena:1;
-        /** fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_token0_1to0_int_ena:1;
-        /** fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_token1_1to0_int_ena:1;
-        /** fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_token0_0to1_int_ena:1;
-        /** fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_token1_0to1_int_ena:1;
-        /** fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0host_rx_sof_int_ena:1;
-        /** fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0host_rx_eof_int_ena:1;
-        /** fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0host_rx_start_int_ena:1;
-        /** fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0host_tx_start_int_ena:1;
-        /** fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_rx_udf_int_ena:1;
-        /** fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_tx_ovf_int_ena:1;
-        /** fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_rx_pf_valid_int_ena:1;
-        /** fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_ext_bit0_int_ena:1;
-        /** fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_ext_bit1_int_ena:1;
-        /** fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_ext_bit2_int_ena:1;
-        /** fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_ext_bit3_int_ena:1;
-        /** fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_rx_new_packet_int_ena:1;
-        /** fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc0_host_rd_retry_int_ena:1;
-        /** fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_gpio_sdio_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_func2_int_ena_reg_t;
-
-/** Type of slc1host_func2_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit0_int_ena:1;
-        /** fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit1_int_ena:1;
-        /** fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit2_int_ena:1;
-        /** fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit3_int_ena:1;
-        /** fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit4_int_ena:1;
-        /** fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit5_int_ena:1;
-        /** fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit6_int_ena:1;
-        /** fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tohost_bit7_int_ena:1;
-        /** fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_token0_1to0_int_ena:1;
-        /** fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_token1_1to0_int_ena:1;
-        /** fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_token0_0to1_int_ena:1;
-        /** fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_token1_0to1_int_ena:1;
-        /** fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1host_rx_sof_int_ena:1;
-        /** fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1host_rx_eof_int_ena:1;
-        /** fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1host_rx_start_int_ena:1;
-        /** fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1host_tx_start_int_ena:1;
-        /** fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_rx_udf_int_ena:1;
-        /** fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_tx_ovf_int_ena:1;
-        /** fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_rx_pf_valid_int_ena:1;
-        /** fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_ext_bit0_int_ena:1;
-        /** fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_ext_bit1_int_ena:1;
-        /** fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_ext_bit2_int_ena:1;
-        /** fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_ext_bit3_int_ena:1;
-        /** fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_wifi_rx_new_packet_int_ena:1;
-        /** fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_host_rd_retry_int_ena:1;
-        /** fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t fn2_slc1_bt_rx_new_packet_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_func2_int_ena_reg_t;
-
-/** Type of slc0host_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_ena:1;
-        /** slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_ena:1;
-        /** slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_ena:1;
-        /** slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_ena:1;
-        /** slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_ena:1;
-        /** slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_ena:1;
-        /** slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_ena:1;
-        /** slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_ena:1;
-        /** slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_ena:1;
-        /** slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_ena:1;
-        /** slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_ena:1;
-        /** slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_ena:1;
-        /** slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_ena:1;
-        /** slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_ena:1;
-        /** slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_ena:1;
-        /** slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_ena:1;
-        /** slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_ena:1;
-        /** slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_ena:1;
-        /** slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_ena:1;
-        /** slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_ena:1;
-        /** slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_ena:1;
-        /** slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_ena:1;
-        /** slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_ena:1;
-        /** slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_ena:1;
-        /** slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_ena:1;
-        /** gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_ena_reg_t;
-
-/** Type of slc1host_int_ena register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_ena:1;
-        /** slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_ena:1;
-        /** slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_ena:1;
-        /** slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_ena:1;
-        /** slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_ena:1;
-        /** slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_ena:1;
-        /** slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_ena:1;
-        /** slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_ena:1;
-        /** slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_ena:1;
-        /** slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_ena:1;
-        /** slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_ena:1;
-        /** slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_ena:1;
-        /** slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_ena:1;
-        /** slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_ena:1;
-        /** slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_ena:1;
-        /** slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_ena:1;
-        /** slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_ena:1;
-        /** slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_ena:1;
-        /** slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_ena:1;
-        /** slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_ena:1;
-        /** slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_ena:1;
-        /** slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_ena:1;
-        /** slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_ena:1;
-        /** slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_ena:1;
-        /** slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_ena:1;
-        /** slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_ena:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_ena_reg_t;
-
-/** Type of slc0host_rx_infor register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_infor:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} slchost_slc0host_rx_infor_reg_t;
-
-/** Type of slc1host_rx_infor register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_infor:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} slchost_slc1host_rx_infor_reg_t;
-
-/** Type of slc0host_len_wd register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0host_len_wd : R/W; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_len_wd:32;
-    };
-    uint32_t val;
-} slchost_slc0host_len_wd_reg_t;
-
-/** Type of slc_apbwin_wdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_wdata:32;
-    };
-    uint32_t val;
-} slchost_slc_apbwin_wdata_reg_t;
-
-/** Type of slc_apbwin_conf register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_addr:28;
-        /** slc_apbwin_wr : R/W; bitpos: [28]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_wr:1;
-        /** slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_start:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} slchost_slc_apbwin_conf_reg_t;
-
-/** Type of slc_apbwin_rdata register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc_apbwin_rdata:32;
-    };
-    uint32_t val;
-} slchost_slc_apbwin_rdata_reg_t;
-
-/** Type of rdclr0 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68;
-         *  *******Description***********
-         */
-        uint32_t slchost_slc0_bit7_clraddr:9;
-        /** slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480;
-         *  *******Description***********
-         */
-        uint32_t slchost_slc0_bit6_clraddr:9;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} slchost_rdclr0_reg_t;
-
-/** Type of rdclr1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480;
-         *  *******Description***********
-         */
-        uint32_t slchost_slc1_bit7_clraddr:9;
-        /** slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480;
-         *  *******Description***********
-         */
-        uint32_t slchost_slc1_bit6_clraddr:9;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} slchost_rdclr1_reg_t;
-
-/** Type of slc0host_int_ena1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit0_int_ena1:1;
-        /** slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit1_int_ena1:1;
-        /** slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit2_int_ena1:1;
-        /** slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit3_int_ena1:1;
-        /** slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit4_int_ena1:1;
-        /** slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit5_int_ena1:1;
-        /** slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit6_int_ena1:1;
-        /** slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tohost_bit7_int_ena1:1;
-        /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_1to0_int_ena1:1;
-        /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_1to0_int_ena1:1;
-        /** slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token0_0to1_int_ena1:1;
-        /** slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_token1_0to1_int_ena1:1;
-        /** slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_sof_int_ena1:1;
-        /** slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_eof_int_ena1:1;
-        /** slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_rx_start_int_ena1:1;
-        /** slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0host_tx_start_int_ena1:1;
-        /** slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_udf_int_ena1:1;
-        /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_tx_ovf_int_ena1:1;
-        /** slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_pf_valid_int_ena1:1;
-        /** slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit0_int_ena1:1;
-        /** slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit1_int_ena1:1;
-        /** slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit2_int_ena1:1;
-        /** slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_ext_bit3_int_ena1:1;
-        /** slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_rx_new_packet_int_ena1:1;
-        /** slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc0_host_rd_retry_int_ena1:1;
-        /** gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t gpio_sdio_int_ena1:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc0host_int_ena1_reg_t;
-
-/** Type of slc1host_int_ena1 register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit0_int_ena1:1;
-        /** slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit1_int_ena1:1;
-        /** slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit2_int_ena1:1;
-        /** slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit3_int_ena1:1;
-        /** slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit4_int_ena1:1;
-        /** slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit5_int_ena1:1;
-        /** slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit6_int_ena1:1;
-        /** slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tohost_bit7_int_ena1:1;
-        /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_1to0_int_ena1:1;
-        /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_1to0_int_ena1:1;
-        /** slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token0_0to1_int_ena1:1;
-        /** slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_token1_0to1_int_ena1:1;
-        /** slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_sof_int_ena1:1;
-        /** slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_eof_int_ena1:1;
-        /** slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_rx_start_int_ena1:1;
-        /** slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1host_tx_start_int_ena1:1;
-        /** slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_udf_int_ena1:1;
-        /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_tx_ovf_int_ena1:1;
-        /** slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_rx_pf_valid_int_ena1:1;
-        /** slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit0_int_ena1:1;
-        /** slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit1_int_ena1:1;
-        /** slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit2_int_ena1:1;
-        /** slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_ext_bit3_int_ena1:1;
-        /** slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_wifi_rx_new_packet_int_ena1:1;
-        /** slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_host_rd_retry_int_ena1:1;
-        /** slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t slc1_bt_rx_new_packet_int_ena1:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} slchost_slc1host_int_ena1_reg_t;
-
-/** Type of slchostdate register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_date : R/W; bitpos: [31:0]; default: 554043136;
-         *  *******Description***********
-         */
-        uint32_t slchost_date:32;
-    };
-    uint32_t val;
-} slchost_slchostdate_reg_t;
-
-/** Type of slchostid register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** slchost_id : R/W; bitpos: [31:0]; default: 1536;
-         *  *******Description***********
-         */
-        uint32_t slchost_id:32;
-    };
-    uint32_t val;
-} slchost_slchostid_reg_t;
-
-/** Type of conf register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** frc_sdio11 : R/W; bitpos: [4:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_sdio11:5;
-        /** frc_sdio20 : R/W; bitpos: [9:5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_sdio20:5;
-        /** frc_neg_samp : R/W; bitpos: [14:10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_neg_samp:5;
-        /** frc_pos_samp : R/W; bitpos: [19:15]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_pos_samp:5;
-        /** frc_quick_in : R/W; bitpos: [24:20]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t frc_quick_in:5;
-        /** sdio20_int_delay : R/W; bitpos: [25]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio20_int_delay:1;
-        /** sdio_pad_pullup : R/W; bitpos: [26]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio_pad_pullup:1;
-        /** hspeed_con_en : R/W; bitpos: [27]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t hspeed_con_en:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} slchost_conf_reg_t;
-
-/** Type of inf_st register
- *  *******Description***********
- */
-typedef union {
-    struct {
-        /** sdio20_mode : RO; bitpos: [4:0]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio20_mode:5;
-        /** sdio_neg_samp : RO; bitpos: [9:5]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio_neg_samp:5;
-        /** sdio_quick_in : RO; bitpos: [14:10]; default: 0;
-         *  *******Description***********
-         */
-        uint32_t sdio_quick_in:5;
-        /** dll_on_sw : R/W; bitpos: [15]; default: 0;
-         *  dll is controlled by software
-         */
-        uint32_t dll_on_sw:1;
-        /** dll_on : R/W; bitpos: [16]; default: 0;
-         *  Software dll on
-         */
-        uint32_t dll_on:1;
-        /** clk_mode_sw : R/W; bitpos: [17]; default: 0;
-         *  dll clock mode is controlled by software
-         */
-        uint32_t clk_mode_sw:1;
-        /** clk_mode : R/W; bitpos: [19:18]; default: 0;
-         *  Software set clock mode
-         */
-        uint32_t clk_mode:2;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} slchost_inf_st_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000[4];
-    volatile slchost_func2_0_reg_t func2_0;
-    volatile slchost_func2_1_reg_t func2_1;
-    uint32_t reserved_018[2];
-    volatile slchost_func2_2_reg_t func2_2;
-    uint32_t reserved_024[4];
-    volatile slchost_gpio_status0_reg_t gpio_status0;
-    volatile slchost_gpio_status1_reg_t gpio_status1;
-    volatile slchost_gpio_in0_reg_t gpio_in0;
-    volatile slchost_gpio_in1_reg_t gpio_in1;
-    volatile slchost_slc0host_token_rdata_reg_t slc0host_token_rdata;
-    volatile slchost_slc0_host_pf_reg_t slc0_host_pf;
-    volatile slchost_slc1_host_pf_reg_t slc1_host_pf;
-    volatile slchost_slc0host_int_raw_reg_t slc0host_int_raw;
-    volatile slchost_slc1host_int_raw_reg_t slc1host_int_raw;
-    volatile slchost_slc0host_int_st_reg_t slc0host_int_st;
-    volatile slchost_slc1host_int_st_reg_t slc1host_int_st;
-    volatile slchost_pkt_len_reg_t pkt_len;
-    volatile slchost_state_w0_reg_t state_w0;
-    volatile slchost_state_w1_reg_t state_w1;
-    volatile slchost_conf_w0_reg_t conf_w0;
-    volatile slchost_conf_w1_reg_t conf_w1;
-    volatile slchost_conf_w2_reg_t conf_w2;
-    volatile slchost_conf_w3_reg_t conf_w3;
-    volatile slchost_conf_w4_reg_t conf_w4;
-    volatile slchost_conf_w5_reg_t conf_w5;
-    volatile slchost_win_cmd_reg_t win_cmd;
-    volatile slchost_conf_w6_reg_t conf_w6;
-    volatile slchost_conf_w7_reg_t conf_w7;
-    volatile slchost_pkt_len0_reg_t pkt_len0;
-    volatile slchost_pkt_len1_reg_t pkt_len1;
-    volatile slchost_pkt_len2_reg_t pkt_len2;
-    volatile slchost_conf_w8_reg_t conf_w8;
-    volatile slchost_conf_w9_reg_t conf_w9;
-    volatile slchost_conf_w10_reg_t conf_w10;
-    volatile slchost_conf_w11_reg_t conf_w11;
-    volatile slchost_conf_w12_reg_t conf_w12;
-    volatile slchost_conf_w13_reg_t conf_w13;
-    volatile slchost_conf_w14_reg_t conf_w14;
-    volatile slchost_conf_w15_reg_t conf_w15;
-    volatile slchost_check_sum0_reg_t check_sum0;
-    volatile slchost_check_sum1_reg_t check_sum1;
-    volatile slchost_slc1host_token_rdata_reg_t slc1host_token_rdata;
-    volatile slchost_slc0host_token_wdata_reg_t slc0host_token_wdata;
-    volatile slchost_slc1host_token_wdata_reg_t slc1host_token_wdata;
-    volatile slchost_token_con_reg_t token_con;
-    volatile slchost_slc0host_int_clr_reg_t slc0host_int_clr;
-    volatile slchost_slc1host_int_clr_reg_t slc1host_int_clr;
-    volatile slchost_slc0host_func1_int_ena_reg_t slc0host_func1_int_ena;
-    volatile slchost_slc1host_func1_int_ena_reg_t slc1host_func1_int_ena;
-    volatile slchost_slc0host_func2_int_ena_reg_t slc0host_func2_int_ena;
-    volatile slchost_slc1host_func2_int_ena_reg_t slc1host_func2_int_ena;
-    volatile slchost_slc0host_int_ena_reg_t slc0host_int_ena;
-    volatile slchost_slc1host_int_ena_reg_t slc1host_int_ena;
-    volatile slchost_slc0host_rx_infor_reg_t slc0host_rx_infor;
-    volatile slchost_slc1host_rx_infor_reg_t slc1host_rx_infor;
-    volatile slchost_slc0host_len_wd_reg_t slc0host_len_wd;
-    volatile slchost_slc_apbwin_wdata_reg_t slc_apbwin_wdata;
-    volatile slchost_slc_apbwin_conf_reg_t slc_apbwin_conf;
-    volatile slchost_slc_apbwin_rdata_reg_t slc_apbwin_rdata;
-    volatile slchost_rdclr0_reg_t rdclr0;
-    volatile slchost_rdclr1_reg_t rdclr1;
-    volatile slchost_slc0host_int_ena1_reg_t slc0host_int_ena1;
-    volatile slchost_slc1host_int_ena1_reg_t slc1host_int_ena1;
-    uint32_t reserved_11c[23];
-    volatile slchost_slchostdate_reg_t slchostdate;
-    volatile slchost_slchostid_reg_t slchostid;
-    uint32_t reserved_180[28];
-    volatile slchost_conf_reg_t conf;
-    volatile slchost_inf_st_reg_t inf_st;
-} slchost_dev_t;
-
-extern slchost_dev_t HOST;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(slchost_dev_t) == 0x1f8, "Invalid size of slchost_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/hp_apm_struct.h b/components/soc/esp32c5/include/soc/hp_apm_struct.h
index b3aea706af..04c89c8a5e 100644
--- a/components/soc/esp32c5/include/soc/hp_apm_struct.h
+++ b/components/soc/esp32c5/include/soc/hp_apm_struct.h
@@ -1650,7 +1650,7 @@ typedef union {
 } hp_apm_date_reg_t;
 
 
-typedef struct {
+typedef struct hp_apm_dev_t {
     volatile hp_apm_region_filter_en_reg_t region_filter_en;
     volatile hp_apm_region0_addr_start_reg_t region0_addr_start;
     volatile hp_apm_region0_addr_end_reg_t region0_addr_end;
diff --git a/components/soc/esp32c5/include/soc/hp_system_struct.h b/components/soc/esp32c5/include/soc/hp_system_struct.h
index 6e39e28bd0..442fa11ecb 100644
--- a/components/soc/esp32c5/include/soc/hp_system_struct.h
+++ b/components/soc/esp32c5/include/soc/hp_system_struct.h
@@ -391,7 +391,7 @@ typedef union {
 } hp_sys_date_reg_t;
 
 
-typedef struct {
+typedef struct hp_sys_dev_t {
     volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
     volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf;
     volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf;
diff --git a/components/soc/esp32c5/include/soc/huk_struct.h b/components/soc/esp32c5/include/soc/huk_struct.h
index e9ba80fbc9..98f7e666b0 100644
--- a/components/soc/esp32c5/include/soc/huk_struct.h
+++ b/components/soc/esp32c5/include/soc/huk_struct.h
@@ -213,7 +213,7 @@ typedef union {
 } huk_date_reg_t;
 
 
-typedef struct {
+typedef struct huk_dev_t {
     uint32_t reserved_000;
     volatile huk_clk_reg_t clk;
     volatile huk_int_raw_reg_t int_raw;
@@ -231,6 +231,7 @@ typedef struct {
     volatile uint32_t info[96];
 } huk_dev_t;
 
+extern huk_dev_t HUK;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/i2c_reg.h b/components/soc/esp32c5/include/soc/i2c_reg.h
index 9cdfdcede6..49f3185e78 100644
--- a/components/soc/esp32c5/include/soc/i2c_reg.h
+++ b/components/soc/esp32c5/include/soc/i2c_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** I2C_SCL_LOW_PERIOD_REG register
  *  Configures the low level width of the SCL Clock.
  */
-#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
+#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
 /** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
  *  Configures the low level width of the SCL Clock.
  *  Measurement unit: i2c_sclk.
@@ -27,7 +27,7 @@ extern "C" {
 /** I2C_CTR_REG register
  *  Transmission setting
  */
-#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
+#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4)
 /** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
  *  Configures the SDA output mode
  *  1: Direct output,
@@ -181,7 +181,7 @@ extern "C" {
 /** I2C_SR_REG register
  *  Describe I2C work status.
  */
-#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
+#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8)
 /** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
  *  Represents the received ACK value in master mode or slave mode.
  *  0: ACK,
@@ -304,7 +304,7 @@ extern "C" {
 /** I2C_TO_REG register
  *  Setting time out control for receiving data.
  */
-#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
+#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc)
 /** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
  *  Configures the timeout threshold period for SCL stucking at high or low level. The
  *  actual period is 2^(reg_time_out_value).
@@ -328,7 +328,7 @@ extern "C" {
 /** I2C_SLAVE_ADDR_REG register
  *  Local slave address setting
  */
-#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
+#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10)
 /** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
  *  Configure the slave address of I2C Slave.
  */
@@ -350,7 +350,7 @@ extern "C" {
 /** I2C_FIFO_ST_REG register
  *  FIFO status register.
  */
-#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
+#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
 /** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
  *  Represents the offset address of the APB reading from RXFIFO
  */
@@ -391,7 +391,7 @@ extern "C" {
 /** I2C_FIFO_CONF_REG register
  *  FIFO configuration register.
  */
-#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
+#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18)
 /** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
  *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
  *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
@@ -464,7 +464,7 @@ extern "C" {
 /** I2C_DATA_REG register
  *  Rx FIFO read data.
  */
-#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
+#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c)
 /** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
  *  Represents the value of RXFIFO read data.
  */
@@ -476,7 +476,7 @@ extern "C" {
 /** I2C_INT_RAW_REG register
  *  Raw interrupt status
  */
-#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
+#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
 /** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
  *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
  */
@@ -614,7 +614,7 @@ extern "C" {
 /** I2C_INT_CLR_REG register
  *  Interrupt clear bits
  */
-#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
+#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24)
 /** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
  */
@@ -752,7 +752,7 @@ extern "C" {
 /** I2C_INT_ENA_REG register
  *  Interrupt enable bits
  */
-#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
+#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28)
 /** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
  */
@@ -890,7 +890,7 @@ extern "C" {
 /** I2C_INT_STATUS_REG register
  *  Status of captured I2C communication events
  */
-#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
+#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c)
 /** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
  *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
  */
@@ -1028,7 +1028,7 @@ extern "C" {
 /** I2C_SDA_HOLD_REG register
  *  Configures the hold time after a negative SCL edge.
  */
-#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
+#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
 /** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
  *  Configures the time to hold the data after the falling edge of SCL.
  *  Measurement unit: i2c_sclk
@@ -1041,7 +1041,7 @@ extern "C" {
 /** I2C_SDA_SAMPLE_REG register
  *  Configures the sample time after a positive SCL edge.
  */
-#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
+#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34)
 /** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
  *  Configures the sample time after a positive SCL edge.
  *  Measurement unit: i2c_sclk
@@ -1054,7 +1054,7 @@ extern "C" {
 /** I2C_SCL_HIGH_PERIOD_REG register
  *  Configures the high level width of SCL
  */
-#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
+#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38)
 /** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
  *  Configures for how long SCL remains high in master mode.
  *  Measurement unit: i2c_sclk
@@ -1075,7 +1075,7 @@ extern "C" {
 /** I2C_SCL_START_HOLD_REG register
  *  Configures the delay between the SDA and SCL negative edge for a start condition
  */
-#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
+#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
 /** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
  *  Configures the time between the falling edge of SDA and the falling edge of SCL for
  *  a START condition.
@@ -1089,7 +1089,7 @@ extern "C" {
 /** I2C_SCL_RSTART_SETUP_REG register
  *  Configures the delay between the positive edge of SCL and the negative edge of SDA
  */
-#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
+#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44)
 /** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
  *  Configures the time between the positive edge of SCL and the negative edge of SDA
  *  for a RESTART condition.
@@ -1103,7 +1103,7 @@ extern "C" {
 /** I2C_SCL_STOP_HOLD_REG register
  *  Configures the delay after the SCL clock edge for a stop condition
  */
-#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
+#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48)
 /** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
  *  Configures the delay after the STOP condition.
  *  Measurement unit: i2c_sclk
@@ -1117,7 +1117,7 @@ extern "C" {
  *  Configures the delay between the SDA and SCL rising edge for a stop condition.
  *  Measurement unit: i2c_sclk
  */
-#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
+#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c)
 /** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
  *  Configures the time between the rising edge of SCL and the rising edge of SDA.
  *  Measurement unit: i2c_sclk
@@ -1130,7 +1130,7 @@ extern "C" {
 /** I2C_FILTER_CFG_REG register
  *  SCL and SDA filter configuration register
  */
-#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
+#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50)
 /** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
  *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
  *  input has smaller width than this register value, the I2C controller will ignore
@@ -1169,7 +1169,7 @@ extern "C" {
 /** I2C_COMD0_REG register
  *  I2C command register 0
  */
-#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
+#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58)
 /** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 0. It consists of three parts:
  *  op_code is the command,
@@ -1201,7 +1201,7 @@ extern "C" {
 /** I2C_COMD1_REG register
  *  I2C command register 1
  */
-#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
+#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c)
 /** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 1. See details in I2C_CMD0_REG[13:0].
  */
@@ -1223,7 +1223,7 @@ extern "C" {
 /** I2C_COMD2_REG register
  *  I2C command register 2
  */
-#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
+#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60)
 /** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 2. See details in I2C_CMD0_REG[13:0].
  */
@@ -1245,7 +1245,7 @@ extern "C" {
 /** I2C_COMD3_REG register
  *  I2C command register 3
  */
-#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
+#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
 /** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 3. See details in I2C_CMD0_REG[13:0].
  */
@@ -1267,7 +1267,7 @@ extern "C" {
 /** I2C_COMD4_REG register
  *  I2C command register 4
  */
-#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
+#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68)
 /** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 4. See details in I2C_CMD0_REG[13:0].
  */
@@ -1289,7 +1289,7 @@ extern "C" {
 /** I2C_COMD5_REG register
  *  I2C command register 5
  */
-#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
+#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c)
 /** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 5. See details in I2C_CMD0_REG[13:0].
  */
@@ -1311,7 +1311,7 @@ extern "C" {
 /** I2C_COMD6_REG register
  *  I2C command register 6
  */
-#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
+#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70)
 /** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 6. See details in I2C_CMD0_REG[13:0].
  */
@@ -1333,7 +1333,7 @@ extern "C" {
 /** I2C_COMD7_REG register
  *  I2C command register 7
  */
-#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
+#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
 /** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 7. See details in I2C_CMD0_REG[13:0].
  */
@@ -1355,7 +1355,7 @@ extern "C" {
 /** I2C_SCL_ST_TIME_OUT_REG register
  *  SCL status time out register
  */
-#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
+#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78)
 /** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
  *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
  *  more than 23.
@@ -1369,7 +1369,7 @@ extern "C" {
 /** I2C_SCL_MAIN_ST_TIME_OUT_REG register
  *  SCL main status time out register
  */
-#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c)
 /** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
  *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
  *  no more than 23.
@@ -1383,7 +1383,7 @@ extern "C" {
 /** I2C_SCL_SP_CONF_REG register
  *  Power configuration register
  */
-#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
+#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
 /** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
  *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
  *  equals to reg_scl_rst_slv_num[4:0].
@@ -1427,7 +1427,7 @@ extern "C" {
 /** I2C_SCL_STRETCH_CONF_REG register
  *  Set SCL stretch of I2C slave
  */
-#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
+#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
 /** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
  *  Configures the time period to release the SCL line from stretching to avoid timing
  *  violation. Usually it should be larger than the SDA setup time.
@@ -1483,7 +1483,7 @@ extern "C" {
 /** I2C_DATE_REG register
  *  Version register
  */
-#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
+#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8)
 /** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050;
  *  Version control register.
  */
@@ -1495,7 +1495,7 @@ extern "C" {
 /** I2C_TXFIFO_START_ADDR_REG register
  *  I2C TXFIFO base address register
  */
-#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
+#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100)
 /** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
  *  Represents the I2C txfifo first address.
  */
@@ -1507,7 +1507,7 @@ extern "C" {
 /** I2C_RXFIFO_START_ADDR_REG register
  *  I2C RXFIFO base address register
  */
-#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
+#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180)
 /** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
  *  Represents the I2C rxfifo first address.
  */
diff --git a/components/soc/esp32c5/include/soc/i2c_struct.h b/components/soc/esp32c5/include/soc/i2c_struct.h
index 9df9e0d41d..ccfc7b278d 100644
--- a/components/soc/esp32c5/include/soc/i2c_struct.h
+++ b/components/soc/esp32c5/include/soc/i2c_struct.h
@@ -1001,8 +1001,8 @@ typedef union {
 
 
 /** Group: Command registers */
-/** Type of comd0 register
- *  I2C command register 0
+/** Type of comd register
+ *  I2C command register n
  */
 typedef union {
     struct {
@@ -1019,166 +1019,18 @@ typedef union {
          *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
          *  structure for more information.
          */
-        uint32_t command0:14;
+        uint32_t command:14;
         uint32_t reserved_14:17;
-        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
+        /** command_done : R/W/SS; bitpos: [31]; default: 0;
          *  Represents whether command 0 is done in I2C Master mode.
          *  0: Not done
          *
          *  1: Done
          */
-        uint32_t command0_done:1;
+        uint32_t command_done:1;
     };
     uint32_t val;
-} i2c_comd0_reg_t;
-
-/** Type of comd1 register
- *  I2C command register 1
- */
-typedef union {
-    struct {
-        /** command1 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 1. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command1:14;
-        uint32_t reserved_14:17;
-        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 1 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command1_done:1;
-    };
-    uint32_t val;
-} i2c_comd1_reg_t;
-
-/** Type of comd2 register
- *  I2C command register 2
- */
-typedef union {
-    struct {
-        /** command2 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 2. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command2:14;
-        uint32_t reserved_14:17;
-        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 2 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command2_done:1;
-    };
-    uint32_t val;
-} i2c_comd2_reg_t;
-
-/** Type of comd3 register
- *  I2C command register 3
- */
-typedef union {
-    struct {
-        /** command3 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 3. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command3:14;
-        uint32_t reserved_14:17;
-        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 3 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command3_done:1;
-    };
-    uint32_t val;
-} i2c_comd3_reg_t;
-
-/** Type of comd4 register
- *  I2C command register 4
- */
-typedef union {
-    struct {
-        /** command4 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 4. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command4:14;
-        uint32_t reserved_14:17;
-        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 4 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command4_done:1;
-    };
-    uint32_t val;
-} i2c_comd4_reg_t;
-
-/** Type of comd5 register
- *  I2C command register 5
- */
-typedef union {
-    struct {
-        /** command5 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 5. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command5:14;
-        uint32_t reserved_14:17;
-        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 5 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command5_done:1;
-    };
-    uint32_t val;
-} i2c_comd5_reg_t;
-
-/** Type of comd6 register
- *  I2C command register 6
- */
-typedef union {
-    struct {
-        /** command6 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 6. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command6:14;
-        uint32_t reserved_14:17;
-        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 6 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command6_done:1;
-    };
-    uint32_t val;
-} i2c_comd6_reg_t;
-
-/** Type of comd7 register
- *  I2C command register 7
- */
-typedef union {
-    struct {
-        /** command7 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 7. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command7:14;
-        uint32_t reserved_14:17;
-        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 7 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command7_done:1;
-    };
-    uint32_t val;
-} i2c_comd7_reg_t;
-
+} i2c_comd_reg_t;
 
 /** Group: Version register */
 /** Type of date register
@@ -1223,7 +1075,7 @@ typedef union {
 } i2c_rxfifo_start_addr_reg_t;
 
 
-typedef struct {
+typedef struct i2c_dev_t {
     volatile i2c_scl_low_period_reg_t scl_low_period;
     volatile i2c_ctr_reg_t ctr;
     volatile i2c_sr_reg_t sr;
@@ -1246,14 +1098,7 @@ typedef struct {
     volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
     volatile i2c_filter_cfg_reg_t filter_cfg;
     uint32_t reserved_054;
-    volatile i2c_comd0_reg_t comd0;
-    volatile i2c_comd1_reg_t comd1;
-    volatile i2c_comd2_reg_t comd2;
-    volatile i2c_comd3_reg_t comd3;
-    volatile i2c_comd4_reg_t comd4;
-    volatile i2c_comd5_reg_t comd5;
-    volatile i2c_comd6_reg_t comd6;
-    volatile i2c_comd7_reg_t comd7;
+    volatile i2c_comd_reg_t comd[8];
     volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
     volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
     volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@@ -1267,6 +1112,7 @@ typedef struct {
 } i2c_dev_t;
 
 extern i2c_dev_t I2C0;
+extern i2c_dev_t I2C1;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/i2s_struct.h b/components/soc/esp32c5/include/soc/i2s_struct.h
index 3d5a63923a..71fc30249c 100644
--- a/components/soc/esp32c5/include/soc/i2s_struct.h
+++ b/components/soc/esp32c5/include/soc/i2s_struct.h
@@ -965,7 +965,7 @@ typedef union {
 } i2s_date_reg_t;
 
 
-typedef struct {
+typedef struct i2s_dev_t {
     uint32_t reserved_000[3];
     volatile i2s_int_raw_reg_t int_raw;
     volatile i2s_int_st_reg_t int_st;
diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h
index fd8641708d..4688fd1cc9 100644
--- a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h
+++ b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h
@@ -1280,7 +1280,7 @@ typedef union {
 } interrupt_core0_interrupt_date_reg_t;
 
 
-typedef struct {
+typedef struct intmtx_core0_dev_t {
     volatile interrupt_core0_wifi_mac_intr_map_reg_t wifi_mac_intr_map;
     volatile interrupt_core0_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map;
     volatile interrupt_core0_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map;
diff --git a/components/soc/esp32c5/include/soc/intpri_struct.h b/components/soc/esp32c5/include/soc/intpri_struct.h
index be97e09506..460811245d 100644
--- a/components/soc/esp32c5/include/soc/intpri_struct.h
+++ b/components/soc/esp32c5/include/soc/intpri_struct.h
@@ -100,7 +100,7 @@ typedef union {
 } intpri_clock_gate_reg_t;
 
 
-typedef struct {
+typedef struct intpri_dev_t {
     uint32_t reserved_000[36];
     volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
     volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
@@ -110,6 +110,7 @@ typedef struct {
     volatile intpri_clock_gate_reg_t clock_gate;
 } intpri_dev_t;
 
+extern intpri_dev_t INTPRI;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(intpri_dev_t) == 0xa8, "Invalid size of intpri_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/io_mux_struct.h b/components/soc/esp32c5/include/soc/io_mux_struct.h
index 33b6319240..85dc6ac907 100644
--- a/components/soc/esp32c5/include/soc/io_mux_struct.h
+++ b/components/soc/esp32c5/include/soc/io_mux_struct.h
@@ -125,7 +125,7 @@ typedef union {
 } io_mux_date_reg_t;
 
 
-typedef struct {
+typedef struct io_mux_dev_t {
     volatile io_mux_pin_ctrl_reg_t pin_ctrl;
     volatile io_mux_gpion_reg_t gpion[27];
     uint32_t reserved_070[35];
diff --git a/components/soc/esp32c5/include/soc/keymng_struct.h b/components/soc/esp32c5/include/soc/keymng_struct.h
index 13b13d1fc3..b809a7ce27 100644
--- a/components/soc/esp32c5/include/soc/keymng_struct.h
+++ b/components/soc/esp32c5/include/soc/keymng_struct.h
@@ -307,7 +307,7 @@ typedef union {
 } keymng_date_reg_t;
 
 
-typedef struct {
+typedef struct keymng_dev_t {
     uint32_t reserved_000;
     volatile keymng_clk_reg_t clk;
     volatile keymng_int_raw_reg_t int_raw;
@@ -329,6 +329,7 @@ typedef struct {
     volatile uint32_t sw_init_key[8];
 } keymng_dev_t;
 
+extern keymng_dev_t KEYMNG;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/ledc_struct.h b/components/soc/esp32c5/include/soc/ledc_struct.h
index 23c38c2eeb..c068877af0 100644
--- a/components/soc/esp32c5/include/soc/ledc_struct.h
+++ b/components/soc/esp32c5/include/soc/ledc_struct.h
@@ -1014,60 +1014,56 @@ typedef union {
     uint32_t val;
 } ledc_date_reg_t;
 
+typedef struct {
+    volatile ledc_chn_conf0_reg_t conf0;
+    volatile ledc_chn_hpoint_reg_t hpoint;
+    volatile ledc_chn_duty_reg_t duty;
+    volatile ledc_chn_conf1_reg_t conf1;
+    volatile ledc_chn_duty_r_reg_t duty_rd;
+} ledc_chn_reg_t;
 
 typedef struct {
-    volatile ledc_chn_conf0_reg_t ch0_conf0;
-    volatile ledc_chn_hpoint_reg_t ch0_hpoint;
-    volatile ledc_chn_duty_reg_t ch0_duty;
-    volatile ledc_chn_conf1_reg_t ch0_conf1;
-    volatile ledc_chn_duty_r_reg_t ch0_duty_r;
-    volatile ledc_chn_conf0_reg_t ch1_conf0;
-    volatile ledc_chn_hpoint_reg_t ch1_hpoint;
-    volatile ledc_chn_duty_reg_t ch1_duty;
-    volatile ledc_chn_conf1_reg_t ch1_conf1;
-    volatile ledc_chn_duty_r_reg_t ch1_duty_r;
-    volatile ledc_chn_conf0_reg_t ch2_conf0;
-    volatile ledc_chn_hpoint_reg_t ch2_hpoint;
-    volatile ledc_chn_duty_reg_t ch2_duty;
-    volatile ledc_chn_conf1_reg_t ch2_conf1;
-    volatile ledc_chn_duty_r_reg_t ch2_duty_r;
-    volatile ledc_chn_conf0_reg_t ch3_conf0;
-    volatile ledc_chn_hpoint_reg_t ch3_hpoint;
-    volatile ledc_chn_duty_reg_t ch3_duty;
-    volatile ledc_chn_conf1_reg_t ch3_conf1;
-    volatile ledc_chn_duty_r_reg_t ch3_duty_r;
-    volatile ledc_chn_conf0_reg_t ch4_conf0;
-    volatile ledc_chn_hpoint_reg_t ch4_hpoint;
-    volatile ledc_chn_duty_reg_t ch4_duty;
-    volatile ledc_chn_conf1_reg_t ch4_conf1;
-    volatile ledc_chn_duty_r_reg_t ch4_duty_r;
-    volatile ledc_chn_conf0_reg_t ch5_conf0;
-    volatile ledc_chn_hpoint_reg_t ch5_hpoint;
-    volatile ledc_chn_duty_reg_t ch5_duty;
-    volatile ledc_chn_conf1_reg_t ch5_conf1;
-    volatile ledc_chn_duty_r_reg_t ch5_duty_r;
+    volatile ledc_chn_reg_t channel[6];
+} ledc_ch_group_reg_t;
+
+typedef struct {
+    volatile ledc_timern_conf_reg_t conf;
+    volatile ledc_timern_value_reg_t value;
+} ledc_timerx_reg_t;
+
+typedef struct {
+    volatile ledc_timerx_reg_t timer[4];
+} ledc_timer_group_reg_t;
+
+typedef struct {
+    volatile ledc_chn_gamma_conf_reg_t gamma_conf[6];
+} ledc_ch_gamma_conf_group_reg_t;
+
+typedef struct {
+    volatile ledc_timern_cmp_reg_t cmp[4];
+} ledc_timer_cmp_group_reg_t;
+
+typedef struct {
+    volatile ledc_timern_cnt_cap_reg_t cnt_cap[4];
+} ledc_timer_cnt_cap_group_reg_t;
+
+typedef struct ledc_dev_t {
+    volatile ledc_ch_group_reg_t channel_group[1];
     uint32_t reserved_078[10];
-    volatile ledc_timern_conf_reg_t timer0_conf;
-    volatile ledc_timern_value_reg_t timer0_value;
-    volatile ledc_timern_conf_reg_t timer1_conf;
-    volatile ledc_timern_value_reg_t timer1_value;
-    volatile ledc_timern_conf_reg_t timer2_conf;
-    volatile ledc_timern_value_reg_t timer2_value;
-    volatile ledc_timern_conf_reg_t timer3_conf;
-    volatile ledc_timern_value_reg_t timer3_value;
+    volatile ledc_timer_group_reg_t timer_group[1];
     volatile ledc_int_raw_reg_t int_raw;
     volatile ledc_int_st_reg_t int_st;
     volatile ledc_int_ena_reg_t int_ena;
     volatile ledc_int_clr_reg_t int_clr;
     uint32_t reserved_0d0[12];
-    volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[6];
+    volatile ledc_ch_gamma_conf_group_reg_t channel_gamma_conf_group[1];
     uint32_t reserved_118[2];
     volatile ledc_evt_task_en0_reg_t evt_task_en0;
     volatile ledc_evt_task_en1_reg_t evt_task_en1;
     volatile ledc_evt_task_en2_reg_t evt_task_en2;
     uint32_t reserved_12c[5];
-    volatile ledc_timern_cmp_reg_t timern_cmp[4];
-    volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4];
+    volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1];
+    volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1];
     uint32_t reserved_160[4];
     volatile ledc_conf_reg_t conf;
     volatile ledc_date_reg_t date;
diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h
index 043f908f7a..a9f5e7dae9 100644
--- a/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h
@@ -224,7 +224,7 @@ typedef union {
 } lp_ana_date_reg_t;
 
 
-typedef struct {
+typedef struct lp_ana_dev_t {
     volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
     volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
     volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
diff --git a/components/soc/esp32c5/include/soc/lp_aon_struct.h b/components/soc/esp32c5/include/soc/lp_aon_struct.h
index b219a17df8..4e3ce38a48 100644
--- a/components/soc/esp32c5/include/soc/lp_aon_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_aon_struct.h
@@ -11,135 +11,18 @@ extern "C" {
 #endif
 
 /** Group: configure_register */
-/** Type of store0 register
+/** Type of store n register
  *  need_des
  */
 typedef union {
     struct {
-        /** lp_aon_store0 : R/W; bitpos: [31:0]; default: 0;
+        /** lp_aon_store : R/W; bitpos: [31:0]; default: 0;
          *  need_des
          */
-        uint32_t lp_aon_store0:32;
+        uint32_t lp_aon_store:32;
     };
     uint32_t val;
-} lp_aon_store0_reg_t;
-
-/** Type of store1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store1 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store1:32;
-    };
-    uint32_t val;
-} lp_aon_store1_reg_t;
-
-/** Type of store2 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store2 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store2:32;
-    };
-    uint32_t val;
-} lp_aon_store2_reg_t;
-
-/** Type of store3 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store3 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store3:32;
-    };
-    uint32_t val;
-} lp_aon_store3_reg_t;
-
-/** Type of store4 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store4 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store4:32;
-    };
-    uint32_t val;
-} lp_aon_store4_reg_t;
-
-/** Type of store5 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store5 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store5:32;
-    };
-    uint32_t val;
-} lp_aon_store5_reg_t;
-
-/** Type of store6 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store6 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store6:32;
-    };
-    uint32_t val;
-} lp_aon_store6_reg_t;
-
-/** Type of store7 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store7 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store7:32;
-    };
-    uint32_t val;
-} lp_aon_store7_reg_t;
-
-/** Type of store8 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store8 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store8:32;
-    };
-    uint32_t val;
-} lp_aon_store8_reg_t;
-
-/** Type of store9 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store9 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store9:32;
-    };
-    uint32_t val;
-} lp_aon_store9_reg_t;
+} lp_aon_store_reg_t;
 
 /** Type of gpio_mux register
  *  need_des
@@ -449,17 +332,8 @@ typedef union {
 } lp_aon_sprf_ctrl_reg_t;
 
 
-typedef struct {
-    volatile lp_aon_store0_reg_t store0;
-    volatile lp_aon_store1_reg_t store1;
-    volatile lp_aon_store2_reg_t store2;
-    volatile lp_aon_store3_reg_t store3;
-    volatile lp_aon_store4_reg_t store4;
-    volatile lp_aon_store5_reg_t store5;
-    volatile lp_aon_store6_reg_t store6;
-    volatile lp_aon_store7_reg_t store7;
-    volatile lp_aon_store8_reg_t store8;
-    volatile lp_aon_store9_reg_t store9;
+typedef struct lp_aon_dev_t {
+    volatile lp_aon_store_reg_t store[10];
     volatile lp_aon_gpio_mux_reg_t gpio_mux;
     volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
     volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
diff --git a/components/soc/esp32c5/include/soc/lp_apm0_struct.h b/components/soc/esp32c5/include/soc/lp_apm0_struct.h
index afffb7456a..72fc8a3b6a 100644
--- a/components/soc/esp32c5/include/soc/lp_apm0_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_apm0_struct.h
@@ -478,7 +478,7 @@ typedef union {
 } lp_apm0_date_reg_t;
 
 
-typedef struct {
+typedef struct lp_apm0_dev_t {
     volatile lp_apm0_region_filter_en_reg_t region_filter_en;
     volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
     volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
@@ -504,6 +504,7 @@ typedef struct {
     volatile lp_apm0_date_reg_t date;
 } lp_apm0_dev_t;
 
+extern lp_apm0_dev_t LP_APM0;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/lp_apm_struct.h b/components/soc/esp32c5/include/soc/lp_apm_struct.h
index b75f8a09e7..8f7c356912 100644
--- a/components/soc/esp32c5/include/soc/lp_apm_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_apm_struct.h
@@ -558,7 +558,7 @@ typedef union {
 } lp_apm_date_reg_t;
 
 
-typedef struct {
+typedef struct lp_apm_dev_t {
     volatile lp_apm_region_filter_en_reg_t region_filter_en;
     volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
     volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_struct.h b/components/soc/esp32c5/include/soc/lp_clkrst_struct.h
index 71c539b8eb..3f348c0cd5 100644
--- a/components/soc/esp32c5/include/soc/lp_clkrst_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_clkrst_struct.h
@@ -326,7 +326,7 @@ typedef union {
 } lp_clkrst_date_reg_t;
 
 
-typedef struct {
+typedef struct lp_clkrst_dev_t {
     volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
     volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
     volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
index a87b4bdcd8..37f45487c3 100644
--- a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
@@ -128,7 +128,7 @@ typedef union {
 } lp_i2c_ana_mst_date_reg_t;
 
 
-typedef struct {
+typedef struct lp_i2c_ana_mst_dev_t {
     volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
     volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
     volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;
diff --git a/components/soc/esp32c5/include/soc/lp_i2c_struct.h b/components/soc/esp32c5/include/soc/lp_i2c_struct.h
index c548c282a1..ad31d58286 100644
--- a/components/soc/esp32c5/include/soc/lp_i2c_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_i2c_struct.h
@@ -843,12 +843,12 @@ typedef union {
 
 
 /** Group: Command registers */
-/** Type of comd0 register
- *  I2C command register 0
+/** Type of comd register
+ *  I2C command register n
  */
 typedef union {
     struct {
-        /** command0 : R/W; bitpos: [13:0]; default: 0;
+        /** command : R/W; bitpos: [13:0]; default: 0;
          *  Configures command 0. It consists of three parts:
          *  op_code is the command,
          *  0: RSTART,
@@ -861,166 +861,18 @@ typedef union {
          *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
          *  structure for more information.
          */
-        uint32_t command0:14;
+        uint32_t command:14;
         uint32_t reserved_14:17;
-        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 0 is done in I2C Master mode.
+        /** command_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command n is done in I2C Master mode.
          *  0: Not done
          *
          *  1: Done
          */
-        uint32_t command0_done:1;
+        uint32_t command_done:1;
     };
     uint32_t val;
-} lp_i2c_comd0_reg_t;
-
-/** Type of comd1 register
- *  I2C command register 1
- */
-typedef union {
-    struct {
-        /** command1 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 1. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command1:14;
-        uint32_t reserved_14:17;
-        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 1 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command1_done:1;
-    };
-    uint32_t val;
-} lp_i2c_comd1_reg_t;
-
-/** Type of comd2 register
- *  I2C command register 2
- */
-typedef union {
-    struct {
-        /** command2 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 2. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command2:14;
-        uint32_t reserved_14:17;
-        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 2 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command2_done:1;
-    };
-    uint32_t val;
-} lp_i2c_comd2_reg_t;
-
-/** Type of comd3 register
- *  I2C command register 3
- */
-typedef union {
-    struct {
-        /** command3 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 3. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command3:14;
-        uint32_t reserved_14:17;
-        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 3 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command3_done:1;
-    };
-    uint32_t val;
-} lp_i2c_comd3_reg_t;
-
-/** Type of comd4 register
- *  I2C command register 4
- */
-typedef union {
-    struct {
-        /** command4 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 4. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command4:14;
-        uint32_t reserved_14:17;
-        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 4 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command4_done:1;
-    };
-    uint32_t val;
-} lp_i2c_comd4_reg_t;
-
-/** Type of comd5 register
- *  I2C command register 5
- */
-typedef union {
-    struct {
-        /** command5 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 5. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command5:14;
-        uint32_t reserved_14:17;
-        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 5 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command5_done:1;
-    };
-    uint32_t val;
-} lp_i2c_comd5_reg_t;
-
-/** Type of comd6 register
- *  I2C command register 6
- */
-typedef union {
-    struct {
-        /** command6 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 6. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command6:14;
-        uint32_t reserved_14:17;
-        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 6 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command6_done:1;
-    };
-    uint32_t val;
-} lp_i2c_comd6_reg_t;
-
-/** Type of comd7 register
- *  I2C command register 7
- */
-typedef union {
-    struct {
-        /** command7 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 7. See details in I2C_CMD0_REG[13:0].
-         */
-        uint32_t command7:14;
-        uint32_t reserved_14:17;
-        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 7 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command7_done:1;
-    };
-    uint32_t val;
-} lp_i2c_comd7_reg_t;
-
+} lp_i2c_comd_reg_t;
 
 /** Group: Version register */
 /** Type of date register
@@ -1065,7 +917,7 @@ typedef union {
 } lp_i2c_rxfifo_start_addr_reg_t;
 
 
-typedef struct {
+typedef struct lp_i2c_dev_t {
     volatile lp_i2c_scl_low_period_reg_t scl_low_period;
     volatile lp_i2c_ctr_reg_t ctr;
     volatile lp_i2c_sr_reg_t sr;
@@ -1088,14 +940,7 @@ typedef struct {
     volatile lp_i2c_scl_stop_setup_reg_t scl_stop_setup;
     volatile lp_i2c_filter_cfg_reg_t filter_cfg;
     volatile lp_i2c_clk_conf_reg_t clk_conf;
-    volatile lp_i2c_comd0_reg_t comd0;
-    volatile lp_i2c_comd1_reg_t comd1;
-    volatile lp_i2c_comd2_reg_t comd2;
-    volatile lp_i2c_comd3_reg_t comd3;
-    volatile lp_i2c_comd4_reg_t comd4;
-    volatile lp_i2c_comd5_reg_t comd5;
-    volatile lp_i2c_comd6_reg_t comd6;
-    volatile lp_i2c_comd7_reg_t comd7;
+    volatile lp_i2c_comd_reg_t comd[8];
     volatile lp_i2c_scl_st_time_out_reg_t scl_st_time_out;
     volatile lp_i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
     volatile lp_i2c_scl_sp_conf_reg_t scl_sp_conf;
diff --git a/components/soc/esp32c5/include/soc/lp_io_struct.h b/components/soc/esp32c5/include/soc/lp_io_struct.h
index bcc0ad2c05..0a8698c5f7 100644
--- a/components/soc/esp32c5/include/soc/lp_io_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_io_struct.h
@@ -151,339 +151,94 @@ typedef union {
     uint32_t val;
 } lp_io_in_reg_t;
 
-/** Type of pin0 register
+/** Type of pin n register
  *  need des
  */
 typedef union {
     struct {
-        /** lp_gpio0_sync_bypass : R/W; bitpos: [1:0]; default: 0;
+        /** lp_gpio_sync_bypass : R/W; bitpos: [1:0]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio0_sync_bypass:2;
-        /** lp_gpio0_pad_driver : R/W; bitpos: [2]; default: 0;
+        uint32_t lp_gpio_sync_bypass:2;
+        /** lp_gpio_pad_driver : R/W; bitpos: [2]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio0_pad_driver:1;
-        /** lp_gpio0_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
+        uint32_t lp_gpio_pad_driver:1;
+        /** lp_gpio_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio0_edge_wakeup_clr:1;
+        uint32_t lp_gpio_edge_wakeup_clr:1;
         uint32_t reserved_4:3;
-        /** lp_gpio0_int_type : R/W; bitpos: [9:7]; default: 0;
+        /** lp_gpio_int_type : R/W; bitpos: [9:7]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio0_int_type:3;
-        /** lp_gpio0_wakeup_enable : R/W; bitpos: [10]; default: 0;
+        uint32_t lp_gpio_int_type:3;
+        /** lp_gpio_wakeup_enable : R/W; bitpos: [10]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio0_wakeup_enable:1;
-        /** lp_gpio0_filter_en : R/W; bitpos: [11]; default: 0;
+        uint32_t lp_gpio_wakeup_enable:1;
+        /** lp_gpio_filter_en : R/W; bitpos: [11]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio0_filter_en:1;
+        uint32_t lp_gpio_filter_en:1;
         uint32_t reserved_12:20;
     };
     uint32_t val;
-} lp_io_pin0_reg_t;
+} lp_io_pin_reg_t;
 
-/** Type of pin1 register
+/** Type of gpio n register
  *  need des
  */
 typedef union {
     struct {
-        /** lp_gpio1_sync_bypass : R/W; bitpos: [1:0]; default: 0;
+        /** lp_gpio_mcu_oe : R/W; bitpos: [0]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio1_sync_bypass:2;
-        /** lp_gpio1_pad_driver : R/W; bitpos: [2]; default: 0;
+        uint32_t lp_gpio_mcu_oe:1;
+        /** lp_gpio_slp_sel : R/W; bitpos: [1]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio1_pad_driver:1;
-        /** lp_gpio1_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
+        uint32_t lp_gpio_slp_sel:1;
+        /** lp_gpio_mcu_wpd : R/W; bitpos: [2]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio1_edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** lp_gpio1_int_type : R/W; bitpos: [9:7]; default: 0;
+        uint32_t lp_gpio_mcu_wpd:1;
+        /** lp_gpio_mcu_wpu : R/W; bitpos: [3]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio1_int_type:3;
-        /** lp_gpio1_wakeup_enable : R/W; bitpos: [10]; default: 0;
+        uint32_t lp_gpio_mcu_wpu:1;
+        /** lp_gpio_mcu_ie : R/W; bitpos: [4]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio1_wakeup_enable:1;
-        /** lp_gpio1_filter_en : R/W; bitpos: [11]; default: 0;
+        uint32_t lp_gpio_mcu_ie:1;
+        /** lp_gpio_mcu_drv : R/W; bitpos: [6:5]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio1_filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin1_reg_t;
-
-/** Type of pin2 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio2_sync_bypass : R/W; bitpos: [1:0]; default: 0;
+        uint32_t lp_gpio_mcu_drv:2;
+        /** lp_gpio_fun_wpd : R/W; bitpos: [7]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio2_sync_bypass:2;
-        /** lp_gpio2_pad_driver : R/W; bitpos: [2]; default: 0;
+        uint32_t lp_gpio_fun_wpd:1;
+        /** lp_gpio_fun_wpu : R/W; bitpos: [8]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio2_pad_driver:1;
-        /** lp_gpio2_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
+        uint32_t lp_gpio_fun_wpu:1;
+        /** lp_gpio_fun_ie : R/W; bitpos: [9]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio2_edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** lp_gpio2_int_type : R/W; bitpos: [9:7]; default: 0;
+        uint32_t lp_gpio_fun_ie:1;
+        /** lp_gpio_fun_drv : R/W; bitpos: [11:10]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio2_int_type:3;
-        /** lp_gpio2_wakeup_enable : R/W; bitpos: [10]; default: 0;
+        uint32_t lp_gpio_fun_drv:2;
+        /** lp_gpio_mcu_sel : R/W; bitpos: [14:12]; default: 0;
          *  need des
          */
-        uint32_t lp_gpio2_wakeup_enable:1;
-        /** lp_gpio2_filter_en : R/W; bitpos: [11]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin2_reg_t;
-
-/** Type of pin3 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio3_sync_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_sync_bypass:2;
-        /** lp_gpio3_pad_driver : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_pad_driver:1;
-        /** lp_gpio3_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** lp_gpio3_int_type : R/W; bitpos: [9:7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_int_type:3;
-        /** lp_gpio3_wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_wakeup_enable:1;
-        /** lp_gpio3_filter_en : R/W; bitpos: [11]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin3_reg_t;
-
-/** Type of pin4 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio4_sync_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_sync_bypass:2;
-        /** lp_gpio4_pad_driver : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_pad_driver:1;
-        /** lp_gpio4_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** lp_gpio4_int_type : R/W; bitpos: [9:7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_int_type:3;
-        /** lp_gpio4_wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_wakeup_enable:1;
-        /** lp_gpio4_filter_en : R/W; bitpos: [11]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin4_reg_t;
-
-/** Type of pin5 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio5_sync_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_sync_bypass:2;
-        /** lp_gpio5_pad_driver : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_pad_driver:1;
-        /** lp_gpio5_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** lp_gpio5_int_type : R/W; bitpos: [9:7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_int_type:3;
-        /** lp_gpio5_wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_wakeup_enable:1;
-        /** lp_gpio5_filter_en : R/W; bitpos: [11]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin5_reg_t;
-
-/** Type of pin6 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio6_sync_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_sync_bypass:2;
-        /** lp_gpio6_pad_driver : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_pad_driver:1;
-        /** lp_gpio6_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** lp_gpio6_int_type : R/W; bitpos: [9:7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_int_type:3;
-        /** lp_gpio6_wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_wakeup_enable:1;
-        /** lp_gpio6_filter_en : R/W; bitpos: [11]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin6_reg_t;
-
-/** Type of pin7 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio7_sync_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_sync_bypass:2;
-        /** lp_gpio7_pad_driver : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_pad_driver:1;
-        /** lp_gpio7_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** lp_gpio7_int_type : R/W; bitpos: [9:7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_int_type:3;
-        /** lp_gpio7_wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_wakeup_enable:1;
-        /** lp_gpio7_filter_en : R/W; bitpos: [11]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin7_reg_t;
-
-/** Type of gpio0 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio0_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_mcu_oe:1;
-        /** lp_gpio0_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_slp_sel:1;
-        /** lp_gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_mcu_wpd:1;
-        /** lp_gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_mcu_wpu:1;
-        /** lp_gpio0_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_mcu_ie:1;
-        /** lp_gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_mcu_drv:2;
-        /** lp_gpio0_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_fun_wpd:1;
-        /** lp_gpio0_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_fun_wpu:1;
-        /** lp_gpio0_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_fun_ie:1;
-        /** lp_gpio0_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_fun_drv:2;
-        /** lp_gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio0_mcu_sel:3;
+        uint32_t lp_gpio_mcu_sel:3;
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} lp_io_gpio0_reg_t;
+} lp_io_gpio_reg_t;
 
 /** Type of gpio1 register
  *  need des
@@ -953,7 +708,7 @@ typedef union {
 } lp_io_date_reg_t;
 
 
-typedef struct {
+typedef struct lp_io_dev_t {
     volatile lp_io_out_data_reg_t out_data;
     volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
     volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
@@ -964,22 +719,8 @@ typedef struct {
     volatile lp_io_status_w1ts_reg_t status_w1ts;
     volatile lp_io_status_w1tc_reg_t status_w1tc;
     volatile lp_io_in_reg_t in;
-    volatile lp_io_pin0_reg_t pin0;
-    volatile lp_io_pin1_reg_t pin1;
-    volatile lp_io_pin2_reg_t pin2;
-    volatile lp_io_pin3_reg_t pin3;
-    volatile lp_io_pin4_reg_t pin4;
-    volatile lp_io_pin5_reg_t pin5;
-    volatile lp_io_pin6_reg_t pin6;
-    volatile lp_io_pin7_reg_t pin7;
-    volatile lp_io_gpio0_reg_t gpio0;
-    volatile lp_io_gpio1_reg_t gpio1;
-    volatile lp_io_gpio2_reg_t gpio2;
-    volatile lp_io_gpio3_reg_t gpio3;
-    volatile lp_io_gpio4_reg_t gpio4;
-    volatile lp_io_gpio5_reg_t gpio5;
-    volatile lp_io_gpio6_reg_t gpio6;
-    volatile lp_io_gpio7_reg_t gpio7;
+    volatile lp_io_pin_reg_t pin[8];
+    volatile lp_io_gpio_reg_t gpio[8];
     volatile lp_io_status_interrupt_reg_t status_interrupt;
     volatile lp_io_debug_sel0_reg_t debug_sel0;
     volatile lp_io_debug_sel1_reg_t debug_sel1;
diff --git a/components/soc/esp32c5/include/soc/lp_tee_struct.h b/components/soc/esp32c5/include/soc/lp_tee_struct.h
index 5b23b3217d..7951c479f2 100644
--- a/components/soc/esp32c5/include/soc/lp_tee_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_tee_struct.h
@@ -79,7 +79,7 @@ typedef union {
 } lp_tee_date_reg_t;
 
 
-typedef struct {
+typedef struct lp_tee_dev_t {
     volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
     volatile lp_tee_clock_gate_reg_t clock_gate;
     uint32_t reserved_008[34];
@@ -88,6 +88,7 @@ typedef struct {
     volatile lp_tee_date_reg_t date;
 } lp_tee_dev_t;
 
+extern lp_tee_dev_t LP_TEE;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/lp_timer_struct.h b/components/soc/esp32c5/include/soc/lp_timer_struct.h
index e5372939b5..75194c69d6 100644
--- a/components/soc/esp32c5/include/soc/lp_timer_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_timer_struct.h
@@ -11,67 +11,36 @@ extern "C" {
 #endif
 
 /** Group: configure_register */
-/** Type of tar0_low register
+/** Type of tar_low register
  *  need_des
  */
 typedef union {
     struct {
-        /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
+        /** main_timer_tar_low : R/W; bitpos: [31:0]; default: 0;
          *  need_des
          */
-        uint32_t main_timer_tar_low0:32;
+        uint32_t main_timer_tar_low:32;
     };
     uint32_t val;
-} lp_timer_tar0_low_reg_t;
+} lp_timer_tar_low_reg_t;
 
-/** Type of tar0_high register
+/** Type of tar_high register
  *  need_des
  */
 typedef union {
     struct {
-        /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
+        /** main_timer_tar_high : R/W; bitpos: [15:0]; default: 0;
          *  need_des
          */
-        uint32_t main_timer_tar_high0:16;
+        uint32_t main_timer_tar_high:16;
         uint32_t reserved_16:15;
-        /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
+        /** main_timer_tar_en : WT; bitpos: [31]; default: 0;
          *  need_des
          */
-        uint32_t main_timer_tar_en0:1;
+        uint32_t main_timer_tar_en:1;
     };
     uint32_t val;
-} lp_timer_tar0_high_reg_t;
-
-/** Type of tar1_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_low1:32;
-    };
-    uint32_t val;
-} lp_timer_tar1_low_reg_t;
-
-/** Type of tar1_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_high1:16;
-        uint32_t reserved_16:15;
-        /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_en1:1;
-    };
-    uint32_t val;
-} lp_timer_tar1_high_reg_t;
+} lp_timer_tar_high_reg_t;
 
 /** Type of update register
  *  need_des
@@ -99,32 +68,32 @@ typedef union {
     uint32_t val;
 } lp_timer_update_reg_t;
 
-/** Type of main_buf0_low register
+/** Type of main_buf_low register
  *  need_des
  */
 typedef union {
     struct {
-        /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
+        /** main_timer_buf_low : RO; bitpos: [31:0]; default: 0;
          *  need_des
          */
-        uint32_t main_timer_buf0_low:32;
+        uint32_t main_timer_buf_low:32;
     };
     uint32_t val;
-} lp_timer_main_buf0_low_reg_t;
+} lp_timer_main_buf_low_reg_t;
 
-/** Type of main_buf0_high register
+/** Type of main_buf_high register
  *  need_des
  */
 typedef union {
     struct {
-        /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
+        /** main_timer_buf_high : RO; bitpos: [15:0]; default: 0;
          *  need_des
          */
-        uint32_t main_timer_buf0_high:16;
+        uint32_t main_timer_buf_high:16;
         uint32_t reserved_16:16;
     };
     uint32_t val;
-} lp_timer_main_buf0_high_reg_t;
+} lp_timer_main_buf_high_reg_t;
 
 /** Type of main_buf1_low register
  *  need_des
@@ -328,18 +297,20 @@ typedef union {
     uint32_t val;
 } lp_timer_date_reg_t;
 
+typedef struct {
+    volatile lp_timer_tar_low_reg_t lo;
+    volatile lp_timer_tar_high_reg_t hi;
+} lp_timer_target_reg_t;
 
 typedef struct {
-    volatile lp_timer_tar0_low_reg_t tar0_low;
-    volatile lp_timer_tar0_high_reg_t tar0_high;
-    volatile lp_timer_tar1_low_reg_t tar1_low;
-    volatile lp_timer_tar1_high_reg_t tar1_high;
+    volatile lp_timer_main_buf_low_reg_t lo;
+    volatile lp_timer_main_buf_high_reg_t hi;
+} lp_timer_counter_reg_t;
+
+typedef struct lp_timer_dev_t {
+    volatile lp_timer_target_reg_t target[2];
     volatile lp_timer_update_reg_t update;
-    volatile lp_timer_main_buf0_low_reg_t main_buf0_low;
-    volatile lp_timer_main_buf0_high_reg_t main_buf0_high;
-    volatile lp_timer_main_buf1_low_reg_t main_buf1_low;
-    volatile lp_timer_main_buf1_high_reg_t main_buf1_high;
-    volatile lp_timer_main_overflow_reg_t main_overflow;
+    volatile lp_timer_counter_reg_t counter[2];
     volatile lp_timer_int_raw_reg_t int_raw;
     volatile lp_timer_int_st_reg_t int_st;
     volatile lp_timer_int_ena_reg_t int_ena;
diff --git a/components/soc/esp32c5/include/soc/lp_uart_struct.h b/components/soc/esp32c5/include/soc/lp_uart_struct.h
index e47a691f22..7500b302af 100644
--- a/components/soc/esp32c5/include/soc/lp_uart_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_uart_struct.h
@@ -1077,7 +1077,7 @@ typedef union {
 } lp_uart_id_reg_t;
 
 
-typedef struct {
+typedef struct lp_uart_dev_t {
     volatile lp_uart_fifo_reg_t fifo;
     volatile lp_uart_int_raw_reg_t int_raw;
     volatile lp_uart_int_st_reg_t int_st;
diff --git a/components/soc/esp32c5/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/include/soc/lp_wdt_struct.h
index 6195024ccb..4e0ee847bd 100644
--- a/components/soc/esp32c5/include/soc/lp_wdt_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_wdt_struct.h
@@ -281,7 +281,7 @@ typedef union {
 } lp_wdt_date_reg_t;
 
 
-typedef struct {
+typedef struct lp_wdt_dev_t {
     volatile lp_wdt_config0_reg_t config0;
     volatile lp_wdt_config1_reg_t config1;
     volatile lp_wdt_config2_reg_t config2;
@@ -299,6 +299,7 @@ typedef struct {
     volatile lp_wdt_date_reg_t date;
 } lp_wdt_dev_t;
 
+extern lp_wdt_dev_t LP_WDT;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/lpperi_struct.h b/components/soc/esp32c5/include/soc/lpperi_struct.h
index 767d0f981f..06e3e023ca 100644
--- a/components/soc/esp32c5/include/soc/lpperi_struct.h
+++ b/components/soc/esp32c5/include/soc/lpperi_struct.h
@@ -263,7 +263,7 @@ typedef union {
 } lpperi_date_reg_t;
 
 
-typedef struct {
+typedef struct lpperi_dev_t {
     volatile lpperi_clk_en_reg_t clk_en;
     volatile lpperi_reset_en_reg_t reset_en;
     volatile lpperi_rng_data_reg_t rng_data;
diff --git a/components/soc/esp32c5/include/soc/mcpwm_struct.h b/components/soc/esp32c5/include/soc/mcpwm_struct.h
index 4eb4e6bc03..dde07979a8 100644
--- a/components/soc/esp32c5/include/soc/mcpwm_struct.h
+++ b/components/soc/esp32c5/include/soc/mcpwm_struct.h
@@ -1938,7 +1938,7 @@ typedef union {
 } mcpwm_version_reg_t;
 
 
-typedef struct {
+typedef struct mcpwm_dev_t {
     volatile mcpwm_clk_cfg_reg_t clk_cfg;
     volatile mcpwm_timern_cfg0_reg_t timer0_cfg0;
     volatile mcpwm_timern_cfg1_reg_t timer0_cfg1;
diff --git a/components/soc/esp32c5/include/soc/mem_monitor_struct.h b/components/soc/esp32c5/include/soc/mem_monitor_struct.h
index f8c3240762..51f731b5ec 100644
--- a/components/soc/esp32c5/include/soc/mem_monitor_struct.h
+++ b/components/soc/esp32c5/include/soc/mem_monitor_struct.h
@@ -193,7 +193,7 @@ typedef union {
 } mem_monitor_date_reg_t;
 
 
-typedef struct {
+typedef struct mem_monitor_dev_t {
     volatile mem_monitor_log_setting_reg_t log_setting;
     volatile mem_monitor_log_check_data_reg_t log_check_data;
     volatile mem_monitor_log_data_mask_reg_t log_data_mask;
diff --git a/components/soc/esp32c5/include/soc/otp_debug_struct.h b/components/soc/esp32c5/include/soc/otp_debug_struct.h
index ff4c13921e..6afed4ae33 100644
--- a/components/soc/esp32c5/include/soc/otp_debug_struct.h
+++ b/components/soc/esp32c5/include/soc/otp_debug_struct.h
@@ -1991,7 +1991,7 @@ typedef union {
 } otp_debug_date_reg_t;
 
 
-typedef struct {
+typedef struct otp_debug_dev_t {
     volatile otp_debug_wr_dis_reg_t wr_dis;
     volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1;
     volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2;
diff --git a/components/soc/esp32c5/include/soc/parl_io_struct.h b/components/soc/esp32c5/include/soc/parl_io_struct.h
index eb0e1c5a31..aea2cb383b 100644
--- a/components/soc/esp32c5/include/soc/parl_io_struct.h
+++ b/components/soc/esp32c5/include/soc/parl_io_struct.h
@@ -472,7 +472,7 @@ typedef union {
 } parl_io_version_reg_t;
 
 
-typedef struct {
+typedef struct parl_io_dev_t {
     volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
     volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
     volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
diff --git a/components/soc/esp32c5/include/soc/pau_struct.h b/components/soc/esp32c5/include/soc/pau_struct.h
index 4328a02144..16c9c62767 100644
--- a/components/soc/esp32c5/include/soc/pau_struct.h
+++ b/components/soc/esp32c5/include/soc/pau_struct.h
@@ -307,7 +307,7 @@ typedef union {
 } pau_date_reg_t;
 
 
-typedef struct {
+typedef struct pau_dev_t {
     volatile pau_regdma_conf_reg_t regdma_conf;
     volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
     volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
diff --git a/components/soc/esp32c5/include/soc/pcnt_struct.h b/components/soc/esp32c5/include/soc/pcnt_struct.h
index abfee16732..65de09bb12 100644
--- a/components/soc/esp32c5/include/soc/pcnt_struct.h
+++ b/components/soc/esp32c5/include/soc/pcnt_struct.h
@@ -465,7 +465,7 @@ typedef union {
 } pcnt_date_reg_t;
 
 
-typedef struct {
+typedef struct pcnt_dev_t {
     volatile pcnt_un_conf0_reg_t u0_conf0;
     volatile pcnt_un_conf1_reg_t u0_conf1;
     volatile pcnt_un_conf2_reg_t u0_conf2;
diff --git a/components/soc/esp32c5/include/soc/pcr_struct.h b/components/soc/esp32c5/include/soc/pcr_struct.h
index 5557b89f1e..d47ae1ad51 100644
--- a/components/soc/esp32c5/include/soc/pcr_struct.h
+++ b/components/soc/esp32c5/include/soc/pcr_struct.h
@@ -2125,7 +2125,7 @@ typedef union {
 } pcr_date_reg_t;
 
 
-typedef struct {
+typedef struct pcr_dev_t {
     volatile pcr_uart0_conf_reg_t uart0_conf;
     volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf;
     volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl;
diff --git a/components/soc/esp32c5/include/soc/pmu_struct.h b/components/soc/esp32c5/include/soc/pmu_struct.h
index 65d00bd8b6..15c140e2c8 100644
--- a/components/soc/esp32c5/include/soc/pmu_struct.h
+++ b/components/soc/esp32c5/include/soc/pmu_struct.h
@@ -2666,7 +2666,7 @@ typedef union {
 } pmu_vdd_spi_status_reg_t;
 
 
-typedef struct {
+typedef struct pmu_dev_t {
     volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power;
     volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func;
     volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb;
diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/include/soc/reg_base.h
new file mode 100644
index 0000000000..d002cd1259
--- /dev/null
+++ b/components/soc/esp32c5/include/soc/reg_base.h
@@ -0,0 +1,101 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Peripheral 0 Modules
+ *
+ */
+#define DR_REG_UART0_BASE                         0x60000000
+#define DR_REG_UART1_BASE                         0x60001000
+#define DR_REG_SPIMEM0_BASE                       0x60002000
+#define DR_REG_SPIMEM1_BASE                       0x60003000
+#define DR_REG_I2C0_BASE                          0x60004000
+#define DR_REG_UHCI0_BASE                         0x60005000
+#define DR_REG_RMT_BASE                           0x60006000
+#define DR_REG_LEDC_BASE                          0x60007000
+#define DR_REG_TIMERG0_BASE                       0x60008000
+#define DR_REG_TIMERG1_BASE                       0x60009000
+#define DR_REG_SYSTIMER_BASE                      0x6000A000
+#define DR_REG_TWAI0_BASE                         0x6000B000
+#define DR_REG_I2S_BASE                           0x6000C000
+#define DR_REG_TWAI1_BASE                         0x6000D000
+#define DR_REG_APB_SARADC_BASE                    0x6000E000
+#define DR_REG_USB_SERIAL_JTAG_BASE               0x6000F000
+#define DR_REG_INTMTX_BASE                        0x60010000
+#define DR_REG_I2C1_BASE                          0x60011000
+#define DR_REG_PCNT_BASE                          0x60012000
+#define DR_REG_SOC_ETM_BASE                       0x60013000
+#define DR_REG_MCPWM_BASE                         0x60014000
+#define DR_REG_PARL_IO_BASE                       0x60015000
+#define DR_REG_PVT_MONITOR_BASE                   0x60019000
+
+/**
+ * @brief Peripheral 1 Modules
+ *
+ */
+#define DR_REG_GDMA_BASE                          0x60080000
+#define DR_REG_GPSPI2_BASE                        0x60081000
+#define DR_REG_BITSCRAMBLER_BASE                  0x60082000
+#define DR_REG_KEYMNG_BASE                        0x60087000
+#define DR_REG_AES_BASE                           0x60088000
+#define DR_REG_SHA_BASE                           0x60089000
+#define DR_REG_RSA_BASE                           0x6008A000
+#define DR_REG_ECC_BASE                           0x6008B000
+#define DR_REG_DS_BASE                            0x6008C000
+#define DR_REG_HMAC_BASE                          0x6008D000
+#define DR_REG_ECDSA_BASE                         0x6008E000
+
+/**
+ * @brief HP Top Peripheral Modules
+ *
+ */
+#define DR_REG_IO_MUX_BASE                        0x60090000
+#define DR_REG_GPIO_BASE                          0x60091000
+#define DR_REG_MEM_MONITOR_BASE                   0x60092000
+#define DR_REG_PAU_BASE                           0x60093000
+#define DR_REG_HP_SYSTEM_BASE                     0x60095000
+#define DR_REG_PCR_BASE                           0x60096000
+#define DR_REG_TEE_BASE                           0x60098000
+#define DR_REG_HP_APM_BASE                        0x60099000
+#define DR_REG_LP_APM0_BASE                       0x60099800
+#define DR_REG_MISC_BASE                          0x6009F000
+
+/**
+ * @brief Modem Module
+ *
+ */
+#define DR_REG_MODEM_BASE                         0x600A4000
+#define DR_REG_MODEM_PWR_BASE                     0x600AD000
+
+/**
+ * @brief LP System (RTC) Modules
+ *
+ */
+#define DR_REG_PMU_BASE                           0x600B0000
+#define DR_REG_LP_CLKRST_BASE                     0x600B0400
+#define DR_REG_EFUSE_BASE                         0x600B0800
+#define DR_REG_LP_TIMER_BASE                      0x600B0C00
+#define DR_REG_LP_AON_BASE                        0x600B1000
+#define DR_REG_LP_UART_BASE                       0x600B1400
+#define DR_REG_LP_I2C_BASE                        0x600B1800
+#define DR_REG_LP_WDT_BASE                        0x600B1C00
+#define DR_REG_LP_IO_BASE                         0x600B2000
+#define DR_REG_LP_I2C_ANA_MST_BASE                0x600B2400
+#define DR_REG_LPPERI_BASE                        0x600B2800
+#define DR_REG_LP_ANA_PERI_BASE                   0x600B2C00
+#define DR_REG_HUK_BASE                           0x600B3000
+#define DR_REG_LP_TEE_BASE                        0x600B3400
+#define DR_REG_LP_APM_BASE                        0x600B3800
+#define DR_REG_OTP_DEBUG_BASE                     0x600B3C00
+
+/**
+ * @brief CPU Peripheral Modules
+ *
+ */
+#define DR_REG_TRACE_BASE                         0x600C0000
+#define DR_REG_ASSIST_DEBUG_BASE                  0x600C2000
+#define DR_REG_INTPRI_BASE                        0x600C5000
+#define DR_REG_CACHE_BASE                         0x600C8000
diff --git a/components/soc/esp32c5/include/soc/rmt_struct.h b/components/soc/esp32c5/include/soc/rmt_struct.h
index 4d5e16e3bc..02d2138a80 100644
--- a/components/soc/esp32c5/include/soc/rmt_struct.h
+++ b/components/soc/esp32c5/include/soc/rmt_struct.h
@@ -24,6 +24,19 @@ typedef union {
     uint32_t val;
 } rmt_chndata_reg_t;
 
+/** Type of chmdata register
+ *  The read and write  data register for CHANNELn by apb fifo access.
+ */
+typedef union {
+    struct {
+        /** chmdata : HRO; bitpos: [31:0]; default: 0;
+         *  Read and write data for channel n via APB FIFO.
+         */
+        uint32_t chmdata:32;
+    };
+    uint32_t val;
+} rmt_chmdata_reg_t;
+
 
 /** Group: Configuration registers */
 /** Type of chnconf0 register
@@ -753,13 +766,14 @@ typedef union {
 } rmt_date_reg_t;
 
 
-typedef struct {
-    volatile rmt_chndata_reg_t chndata[4];
+typedef struct rmt_dev_t {
+    volatile rmt_chndata_reg_t chndata[2];
+    volatile rmt_chmdata_reg_t chmdata[2];
     volatile rmt_chnconf0_reg_t chnconf0[2];
-    volatile rmt_chmconf0_reg_t ch2conf0;
-    volatile rmt_chmconf1_reg_t ch2conf1;
-    volatile rmt_chmconf0_reg_t ch3conf0;
-    volatile rmt_chmconf1_reg_t ch3conf1;
+    volatile struct {
+        rmt_chmconf0_reg_t conf0;
+        rmt_chmconf1_reg_t conf1;
+    } chmconf[2];;
     volatile rmt_chnstatus_reg_t chnstatus[2];
     volatile rmt_chmstatus_reg_t chmstatus[2];
     volatile rmt_int_raw_reg_t int_raw;
diff --git a/components/soc/esp32c5/include/soc/rsa_struct.h b/components/soc/esp32c5/include/soc/rsa_struct.h
index 34e831bc7f..7546b4e713 100644
--- a/components/soc/esp32c5/include/soc/rsa_struct.h
+++ b/components/soc/esp32c5/include/soc/rsa_struct.h
@@ -238,7 +238,7 @@ typedef union {
 } rsa_date_reg_t;
 
 
-typedef struct {
+typedef struct rsa_dev_t {
     volatile uint32_t m[4];
     uint32_t reserved_010[124];
     volatile uint32_t z[4];
diff --git a/components/soc/esp32c5/include/soc/sdio_hinf_reg.h b/components/soc/esp32c5/include/soc/sdio_hinf_reg.h
deleted file mode 100644
index d8f8f45d64..0000000000
--- a/components/soc/esp32c5/include/soc/sdio_hinf_reg.h
+++ /dev/null
@@ -1,576 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HINF_CFG_DATA0_REG register
- *  Configure sdio cis content
- */
-#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
-/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214;
- *  configure device id of function1 in cis
- */
-#define HINF_DEVICE_ID_FN1    0x0000FFFFU
-#define HINF_DEVICE_ID_FN1_M  (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S)
-#define HINF_DEVICE_ID_FN1_V  0x0000FFFFU
-#define HINF_DEVICE_ID_FN1_S  0
-/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146;
- *  configure user id of function1 in cis
- */
-#define HINF_USER_ID_FN1    0x0000FFFFU
-#define HINF_USER_ID_FN1_M  (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S)
-#define HINF_USER_ID_FN1_V  0x0000FFFFU
-#define HINF_USER_ID_FN1_S  16
-
-/** HINF_CFG_DATA1_REG register
- *  SDIO configuration register
- */
-#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
-/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1;
- *  Sdio clock enable
- */
-#define HINF_SDIO_ENABLE    (BIT(0))
-#define HINF_SDIO_ENABLE_M  (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S)
-#define HINF_SDIO_ENABLE_V  0x00000001U
-#define HINF_SDIO_ENABLE_S  0
-/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0;
- *  sdio function1 io ready signal in cis
- */
-#define HINF_SDIO_IOREADY1    (BIT(1))
-#define HINF_SDIO_IOREADY1_M  (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S)
-#define HINF_SDIO_IOREADY1_V  0x00000001U
-#define HINF_SDIO_IOREADY1_S  1
-/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0;
- *  Highspeed enable in cccr
- */
-#define HINF_HIGHSPEED_ENABLE    (BIT(2))
-#define HINF_HIGHSPEED_ENABLE_M  (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S)
-#define HINF_HIGHSPEED_ENABLE_V  0x00000001U
-#define HINF_HIGHSPEED_ENABLE_S  2
-/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0;
- *  highspeed mode status in cccr
- */
-#define HINF_HIGHSPEED_MODE    (BIT(3))
-#define HINF_HIGHSPEED_MODE_M  (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S)
-#define HINF_HIGHSPEED_MODE_V  0x00000001U
-#define HINF_HIGHSPEED_MODE_S  3
-/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1;
- *  sdio card detect enable
- */
-#define HINF_SDIO_CD_ENABLE    (BIT(4))
-#define HINF_SDIO_CD_ENABLE_M  (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S)
-#define HINF_SDIO_CD_ENABLE_V  0x00000001U
-#define HINF_SDIO_CD_ENABLE_S  4
-/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0;
- *  sdio function1 io ready signal in cis
- */
-#define HINF_SDIO_IOREADY2    (BIT(5))
-#define HINF_SDIO_IOREADY2_M  (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S)
-#define HINF_SDIO_IOREADY2_V  0x00000001U
-#define HINF_SDIO_IOREADY2_S  5
-/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0;
- *  mask sdio interrupt in cccr, high active
- */
-#define HINF_SDIO_INT_MASK    (BIT(6))
-#define HINF_SDIO_INT_MASK_M  (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S)
-#define HINF_SDIO_INT_MASK_V  0x00000001U
-#define HINF_SDIO_INT_MASK_S  6
-/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0;
- *  ioe2 status in cccr
- */
-#define HINF_IOENABLE2    (BIT(7))
-#define HINF_IOENABLE2_M  (HINF_IOENABLE2_V << HINF_IOENABLE2_S)
-#define HINF_IOENABLE2_V  0x00000001U
-#define HINF_IOENABLE2_S  7
-/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0;
- *  card disable status in cccr
- */
-#define HINF_CD_DISABLE    (BIT(8))
-#define HINF_CD_DISABLE_M  (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S)
-#define HINF_CD_DISABLE_V  0x00000001U
-#define HINF_CD_DISABLE_S  8
-/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0;
- *  function1 eps status in fbr
- */
-#define HINF_FUNC1_EPS    (BIT(9))
-#define HINF_FUNC1_EPS_M  (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S)
-#define HINF_FUNC1_EPS_V  0x00000001U
-#define HINF_FUNC1_EPS_S  9
-/** HINF_EMP : RO; bitpos: [10]; default: 0;
- *  empc status in cccr
- */
-#define HINF_EMP    (BIT(10))
-#define HINF_EMP_M  (HINF_EMP_V << HINF_EMP_S)
-#define HINF_EMP_V  0x00000001U
-#define HINF_EMP_S  10
-/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0;
- *  ioe1 status in cccr
- */
-#define HINF_IOENABLE1    (BIT(11))
-#define HINF_IOENABLE1_M  (HINF_IOENABLE1_V << HINF_IOENABLE1_S)
-#define HINF_IOENABLE1_V  0x00000001U
-#define HINF_IOENABLE1_S  11
-/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562;
- *  sdio version in cccr
- */
-#define HINF_SDIO_VER    0x00000FFFU
-#define HINF_SDIO_VER_M  (HINF_SDIO_VER_V << HINF_SDIO_VER_S)
-#define HINF_SDIO_VER_V  0x00000FFFU
-#define HINF_SDIO_VER_S  12
-/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0;
- *  function2 eps status in fbr
- */
-#define HINF_FUNC2_EPS    (BIT(24))
-#define HINF_FUNC2_EPS_M  (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S)
-#define HINF_FUNC2_EPS_V  0x00000001U
-#define HINF_FUNC2_EPS_S  24
-/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0;
- *  [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
- *  in delayed cycles control,0:no delay, 1:delay 1 cycle.
- *  [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
- *  mode.
- *  [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
- *  [12]=0,posedge when highspeed mode enable.
- *  [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
- *  [28]: sdio data pad pull up enable
- */
-#define HINF_SDIO20_CONF    0x0000007FU
-#define HINF_SDIO20_CONF_M  (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S)
-#define HINF_SDIO20_CONF_V  0x0000007FU
-#define HINF_SDIO20_CONF_S  25
-
-/** HINF_CFG_TIMING_REG register
- *  Timing configuration registers
- */
-#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
-/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2;
- *  configure Ncrc parameter in sdr50/104 mode, no more than 6.
- */
-#define HINF_NCRC    0x00000007U
-#define HINF_NCRC_M  (HINF_NCRC_V << HINF_NCRC_S)
-#define HINF_NCRC_V  0x00000007U
-#define HINF_NCRC_S  0
-/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2;
- *  configure cycles to lower cmd after voltage is changed to 1.8V.
- */
-#define HINF_PST_END_CMD_LOW_VALUE    0x0000007FU
-#define HINF_PST_END_CMD_LOW_VALUE_M  (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S)
-#define HINF_PST_END_CMD_LOW_VALUE_V  0x0000007FU
-#define HINF_PST_END_CMD_LOW_VALUE_S  3
-/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2;
- *  configure cycles to lower data after voltage is changed to 1.8V.
- */
-#define HINF_PST_END_DATA_LOW_VALUE    0x0000003FU
-#define HINF_PST_END_DATA_LOW_VALUE_M  (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S)
-#define HINF_PST_END_DATA_LOW_VALUE_V  0x0000003FU
-#define HINF_PST_END_DATA_LOW_VALUE_S  10
-/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400;
- *  Configure the number of cycles of module clk to judge sdclk has stopped
- */
-#define HINF_SDCLK_STOP_THRES    0x000007FFU
-#define HINF_SDCLK_STOP_THRES_M  (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S)
-#define HINF_SDCLK_STOP_THRES_V  0x000007FFU
-#define HINF_SDCLK_STOP_THRES_S  16
-/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1;
- *  module clk divider to sample sdclk
- */
-#define HINF_SAMPLE_CLK_DIVIDER    0x0000000FU
-#define HINF_SAMPLE_CLK_DIVIDER_M  (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S)
-#define HINF_SAMPLE_CLK_DIVIDER_V  0x0000000FU
-#define HINF_SAMPLE_CLK_DIVIDER_S  28
-
-/** HINF_CFG_UPDATE_REG register
- *  update sdio configurations
- */
-#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
-/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0;
- *  update the timing configurations
- */
-#define HINF_CONF_UPDATE    (BIT(0))
-#define HINF_CONF_UPDATE_M  (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S)
-#define HINF_CONF_UPDATE_V  0x00000001U
-#define HINF_CONF_UPDATE_S  0
-
-/** HINF_CFG_DATA7_REG register
- *  SDIO configuration register
- */
-#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
-/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0;
- *  configure cis addr 318 and 574
- */
-#define HINF_PIN_STATE    0x000000FFU
-#define HINF_PIN_STATE_M  (HINF_PIN_STATE_V << HINF_PIN_STATE_S)
-#define HINF_PIN_STATE_V  0x000000FFU
-#define HINF_PIN_STATE_S  0
-/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0;
- *  configure cis addr 312, 315, 568 and 571
- */
-#define HINF_CHIP_STATE    0x000000FFU
-#define HINF_CHIP_STATE_M  (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S)
-#define HINF_CHIP_STATE_V  0x000000FFU
-#define HINF_CHIP_STATE_S  8
-/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0;
- *  soft reset control for sdio module
- */
-#define HINF_SDIO_RST    (BIT(16))
-#define HINF_SDIO_RST_M  (HINF_SDIO_RST_V << HINF_SDIO_RST_S)
-#define HINF_SDIO_RST_V  0x00000001U
-#define HINF_SDIO_RST_S  16
-/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1;
- *  sdio io ready, high enable
- */
-#define HINF_SDIO_IOREADY0    (BIT(17))
-#define HINF_SDIO_IOREADY0_M  (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S)
-#define HINF_SDIO_IOREADY0_V  0x00000001U
-#define HINF_SDIO_IOREADY0_S  17
-/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0;
- *  sdio memory power down, high active
- */
-#define HINF_SDIO_MEM_PD    (BIT(18))
-#define HINF_SDIO_MEM_PD_M  (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S)
-#define HINF_SDIO_MEM_PD_V  0x00000001U
-#define HINF_SDIO_MEM_PD_S  18
-/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0;
- *  enable sdio interrupt on data1 line
- */
-#define HINF_ESDIO_DATA1_INT_EN    (BIT(19))
-#define HINF_ESDIO_DATA1_INT_EN_M  (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S)
-#define HINF_ESDIO_DATA1_INT_EN_V  0x00000001U
-#define HINF_ESDIO_DATA1_INT_EN_S  19
-/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0;
- *  control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
- */
-#define HINF_SDIO_SWITCH_VOLT_SW    (BIT(20))
-#define HINF_SDIO_SWITCH_VOLT_SW_M  (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S)
-#define HINF_SDIO_SWITCH_VOLT_SW_V  0x00000001U
-#define HINF_SDIO_SWITCH_VOLT_SW_S  20
-/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0;
- *  enable block length to be fixed to 512 bytes in ddr50 mode
- */
-#define HINF_DDR50_BLK_LEN_FIX_EN    (BIT(21))
-#define HINF_DDR50_BLK_LEN_FIX_EN_M  (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S)
-#define HINF_DDR50_BLK_LEN_FIX_EN_V  0x00000001U
-#define HINF_DDR50_BLK_LEN_FIX_EN_S  21
-/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0;
- *  sdio apb clock for configuration force on control:0-gating,1-force on.
- */
-#define HINF_CLK_EN    (BIT(22))
-#define HINF_CLK_EN_M  (HINF_CLK_EN_V << HINF_CLK_EN_S)
-#define HINF_CLK_EN_V  0x00000001U
-#define HINF_CLK_EN_S  22
-/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1;
- *  configure if support sdr50 mode in cccr
- */
-#define HINF_SDDR50    (BIT(23))
-#define HINF_SDDR50_M  (HINF_SDDR50_V << HINF_SDDR50_S)
-#define HINF_SDDR50_V  0x00000001U
-#define HINF_SDDR50_S  23
-/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1;
- *  configure if support sdr104 mode in cccr
- */
-#define HINF_SSDR104    (BIT(24))
-#define HINF_SSDR104_M  (HINF_SSDR104_V << HINF_SSDR104_S)
-#define HINF_SSDR104_V  0x00000001U
-#define HINF_SSDR104_S  24
-/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1;
- *  configure if support ddr50 mode in cccr
- */
-#define HINF_SSDR50    (BIT(25))
-#define HINF_SSDR50_M  (HINF_SSDR50_V << HINF_SSDR50_S)
-#define HINF_SSDR50_V  0x00000001U
-#define HINF_SSDR50_S  25
-/** HINF_SDTD : R/W; bitpos: [26]; default: 0;
- *  configure if support driver type D in cccr
- */
-#define HINF_SDTD    (BIT(26))
-#define HINF_SDTD_M  (HINF_SDTD_V << HINF_SDTD_S)
-#define HINF_SDTD_V  0x00000001U
-#define HINF_SDTD_S  26
-/** HINF_SDTA : R/W; bitpos: [27]; default: 0;
- *  configure if support driver type A in cccr
- */
-#define HINF_SDTA    (BIT(27))
-#define HINF_SDTA_M  (HINF_SDTA_V << HINF_SDTA_S)
-#define HINF_SDTA_V  0x00000001U
-#define HINF_SDTA_S  27
-/** HINF_SDTC : R/W; bitpos: [28]; default: 0;
- *  configure if support driver type C in cccr
- */
-#define HINF_SDTC    (BIT(28))
-#define HINF_SDTC_M  (HINF_SDTC_V << HINF_SDTC_S)
-#define HINF_SDTC_V  0x00000001U
-#define HINF_SDTC_S  28
-/** HINF_SAI : R/W; bitpos: [29]; default: 1;
- *  configure if support asynchronous interrupt in cccr
- */
-#define HINF_SAI    (BIT(29))
-#define HINF_SAI_M  (HINF_SAI_V << HINF_SAI_S)
-#define HINF_SAI_V  0x00000001U
-#define HINF_SAI_S  29
-/** HINF_SDIO_WAKEUP_CLR : WT; bitpos: [30]; default: 0;
- *  clear sdio_wake_up signal after the chip wakes up
- */
-#define HINF_SDIO_WAKEUP_CLR    (BIT(30))
-#define HINF_SDIO_WAKEUP_CLR_M  (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S)
-#define HINF_SDIO_WAKEUP_CLR_V  0x00000001U
-#define HINF_SDIO_WAKEUP_CLR_S  30
-
-/** HINF_CIS_CONF_W0_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
-/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 39~36
- */
-#define HINF_CIS_CONF_W0    0xFFFFFFFFU
-#define HINF_CIS_CONF_W0_M  (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S)
-#define HINF_CIS_CONF_W0_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W0_S  0
-
-/** HINF_CIS_CONF_W1_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
-/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 43~40
- */
-#define HINF_CIS_CONF_W1    0xFFFFFFFFU
-#define HINF_CIS_CONF_W1_M  (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S)
-#define HINF_CIS_CONF_W1_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W1_S  0
-
-/** HINF_CIS_CONF_W2_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
-/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 47~44
- */
-#define HINF_CIS_CONF_W2    0xFFFFFFFFU
-#define HINF_CIS_CONF_W2_M  (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S)
-#define HINF_CIS_CONF_W2_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W2_S  0
-
-/** HINF_CIS_CONF_W3_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
-/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 51~48
- */
-#define HINF_CIS_CONF_W3    0xFFFFFFFFU
-#define HINF_CIS_CONF_W3_M  (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S)
-#define HINF_CIS_CONF_W3_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W3_S  0
-
-/** HINF_CIS_CONF_W4_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
-/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 55~52
- */
-#define HINF_CIS_CONF_W4    0xFFFFFFFFU
-#define HINF_CIS_CONF_W4_M  (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S)
-#define HINF_CIS_CONF_W4_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W4_S  0
-
-/** HINF_CIS_CONF_W5_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34)
-/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 59~56
- */
-#define HINF_CIS_CONF_W5    0xFFFFFFFFU
-#define HINF_CIS_CONF_W5_M  (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S)
-#define HINF_CIS_CONF_W5_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W5_S  0
-
-/** HINF_CIS_CONF_W6_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38)
-/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 63~60
- */
-#define HINF_CIS_CONF_W6    0xFFFFFFFFU
-#define HINF_CIS_CONF_W6_M  (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S)
-#define HINF_CIS_CONF_W6_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W6_S  0
-
-/** HINF_CIS_CONF_W7_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c)
-/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configure cis addr 67~64
- */
-#define HINF_CIS_CONF_W7    0xFFFFFFFFU
-#define HINF_CIS_CONF_W7_M  (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S)
-#define HINF_CIS_CONF_W7_V  0xFFFFFFFFU
-#define HINF_CIS_CONF_W7_S  0
-
-/** HINF_CFG_DATA16_REG register
- *  SDIO cis configuration register
- */
-#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
-/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583;
- *  configure device id of function2 in cis
- */
-#define HINF_DEVICE_ID_FN2    0x0000FFFFU
-#define HINF_DEVICE_ID_FN2_M  (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S)
-#define HINF_DEVICE_ID_FN2_V  0x0000FFFFU
-#define HINF_DEVICE_ID_FN2_S  0
-/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146;
- *  configure user id of function2 in cis
- */
-#define HINF_USER_ID_FN2    0x0000FFFFU
-#define HINF_USER_ID_FN2_M  (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S)
-#define HINF_USER_ID_FN2_V  0x0000FFFFU
-#define HINF_USER_ID_FN2_S  16
-
-/** HINF_CFG_UHS1_INT_MODE_REG register
- *  configure int to start and end ahead of time in uhs1 mode
- */
-#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44)
-/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0;
- *  intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
- */
-#define HINF_INTOE_END_AHEAD_MODE    0x00000003U
-#define HINF_INTOE_END_AHEAD_MODE_M  (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S)
-#define HINF_INTOE_END_AHEAD_MODE_V  0x00000003U
-#define HINF_INTOE_END_AHEAD_MODE_S  0
-/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0;
- *  int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
- */
-#define HINF_INT_END_AHEAD_MODE    0x00000003U
-#define HINF_INT_END_AHEAD_MODE_M  (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S)
-#define HINF_INT_END_AHEAD_MODE_V  0x00000003U
-#define HINF_INT_END_AHEAD_MODE_S  2
-/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0;
- *  intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
- */
-#define HINF_INTOE_ST_AHEAD_MODE    0x00000003U
-#define HINF_INTOE_ST_AHEAD_MODE_M  (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S)
-#define HINF_INTOE_ST_AHEAD_MODE_V  0x00000003U
-#define HINF_INTOE_ST_AHEAD_MODE_S  4
-/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0;
- *  int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
- */
-#define HINF_INT_ST_AHEAD_MODE    0x00000003U
-#define HINF_INT_ST_AHEAD_MODE_M  (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S)
-#define HINF_INT_ST_AHEAD_MODE_V  0x00000003U
-#define HINF_INT_ST_AHEAD_MODE_S  6
-
-/** HINF_CONF_STATUS_REG register
- *  func0 config0 status
- */
-#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54)
-/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0;
- *  func0 config0 (addr: 0x20f0 ) status
- */
-#define HINF_FUNC0_CONFIG0    0x000000FFU
-#define HINF_FUNC0_CONFIG0_M  (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S)
-#define HINF_FUNC0_CONFIG0_V  0x000000FFU
-#define HINF_FUNC0_CONFIG0_S  0
-/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0;
- *  sdr25 status
- */
-#define HINF_SDR25_ST    (BIT(8))
-#define HINF_SDR25_ST_M  (HINF_SDR25_ST_V << HINF_SDR25_ST_S)
-#define HINF_SDR25_ST_V  0x00000001U
-#define HINF_SDR25_ST_S  8
-/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0;
- *  sdr50 status
- */
-#define HINF_SDR50_ST    (BIT(9))
-#define HINF_SDR50_ST_M  (HINF_SDR50_ST_V << HINF_SDR50_ST_S)
-#define HINF_SDR50_ST_V  0x00000001U
-#define HINF_SDR50_ST_S  9
-/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0;
- *  sdr104 status
- */
-#define HINF_SDR104_ST    (BIT(10))
-#define HINF_SDR104_ST_M  (HINF_SDR104_ST_V << HINF_SDR104_ST_S)
-#define HINF_SDR104_ST_V  0x00000001U
-#define HINF_SDR104_ST_S  10
-/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0;
- *  ddr50 status
- */
-#define HINF_DDR50_ST    (BIT(11))
-#define HINF_DDR50_ST_M  (HINF_DDR50_ST_V << HINF_DDR50_ST_S)
-#define HINF_DDR50_ST_V  0x00000001U
-#define HINF_DDR50_ST_S  11
-/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0;
- *  tune_st fsm status
- */
-#define HINF_TUNE_ST    0x00000007U
-#define HINF_TUNE_ST_M  (HINF_TUNE_ST_V << HINF_TUNE_ST_S)
-#define HINF_TUNE_ST_V  0x00000007U
-#define HINF_TUNE_ST_S  12
-/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0;
- *  sdio switch voltage status:0-3.3V, 1-1.8V.
- */
-#define HINF_SDIO_SWITCH_VOLT_ST    (BIT(15))
-#define HINF_SDIO_SWITCH_VOLT_ST_M  (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S)
-#define HINF_SDIO_SWITCH_VOLT_ST_V  0x00000001U
-#define HINF_SDIO_SWITCH_VOLT_ST_S  15
-/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0;
- *  sdio switch voltage ldo ready
- */
-#define HINF_SDIO_SWITCH_END    (BIT(16))
-#define HINF_SDIO_SWITCH_END_M  (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S)
-#define HINF_SDIO_SWITCH_END_V  0x00000001U
-#define HINF_SDIO_SWITCH_END_S  16
-
-/** HINF_SDIO_SLAVE_LDO_CONF_REG register
- *  sdio slave ldo control register
- */
-#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0)
-/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0;
- *  control ldo ready signal by sdio slave itself
- */
-#define HINF_LDO_READY_CTL_IN_EN    (BIT(0))
-#define HINF_LDO_READY_CTL_IN_EN_M  (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S)
-#define HINF_LDO_READY_CTL_IN_EN_V  0x00000001U
-#define HINF_LDO_READY_CTL_IN_EN_S  0
-/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10;
- *  configure ldo ready counting threshold value, the actual counting target is
- *  2^(ldo_ready_thres)-1
- */
-#define HINF_LDO_READY_THRES    0x0000001FU
-#define HINF_LDO_READY_THRES_M  (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S)
-#define HINF_LDO_READY_THRES_V  0x0000001FU
-#define HINF_LDO_READY_THRES_S  1
-/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0;
- *  ignore ldo ready signal
- */
-#define HINF_LDO_READY_IGNORE_EN    (BIT(6))
-#define HINF_LDO_READY_IGNORE_EN_M  (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S)
-#define HINF_LDO_READY_IGNORE_EN_V  0x00000001U
-#define HINF_LDO_READY_IGNORE_EN_S  6
-
-/** HINF_SDIO_DATE_REG register
- *  ******* Description ***********
- */
-#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc)
-/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 35664208;
- *  sdio version date.
- */
-#define HINF_SDIO_DATE    0xFFFFFFFFU
-#define HINF_SDIO_DATE_M  (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S)
-#define HINF_SDIO_DATE_V  0xFFFFFFFFU
-#define HINF_SDIO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/sdio_hinf_struct.h b/components/soc/esp32c5/include/soc/sdio_hinf_struct.h
deleted file mode 100644
index e75ab3e27d..0000000000
--- a/components/soc/esp32c5/include/soc/sdio_hinf_struct.h
+++ /dev/null
@@ -1,492 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration registers */
-/** Type of cfg_data0 register
- *  Configure sdio cis content
- */
-typedef union {
-    struct {
-        /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214;
-         *  configure device id of function1 in cis
-         */
-        uint32_t device_id_fn1:16;
-        /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146;
-         *  configure user id of function1 in cis
-         */
-        uint32_t user_id_fn1:16;
-    };
-    uint32_t val;
-} hinf_cfg_data0_reg_t;
-
-/** Type of cfg_data1 register
- *  SDIO configuration register
- */
-typedef union {
-    struct {
-        /** sdio_enable : R/W; bitpos: [0]; default: 1;
-         *  Sdio clock enable
-         */
-        uint32_t sdio_enable:1;
-        /** sdio_ioready1 : R/W; bitpos: [1]; default: 0;
-         *  sdio function1 io ready signal in cis
-         */
-        uint32_t sdio_ioready1:1;
-        /** highspeed_enable : R/W; bitpos: [2]; default: 0;
-         *  Highspeed enable in cccr
-         */
-        uint32_t highspeed_enable:1;
-        /** highspeed_mode : RO; bitpos: [3]; default: 0;
-         *  highspeed mode status in cccr
-         */
-        uint32_t highspeed_mode:1;
-        /** sdio_cd_enable : R/W; bitpos: [4]; default: 1;
-         *  sdio card detect enable
-         */
-        uint32_t sdio_cd_enable:1;
-        /** sdio_ioready2 : R/W; bitpos: [5]; default: 0;
-         *  sdio function1 io ready signal in cis
-         */
-        uint32_t sdio_ioready2:1;
-        /** sdio_int_mask : R/W; bitpos: [6]; default: 0;
-         *  mask sdio interrupt in cccr, high active
-         */
-        uint32_t sdio_int_mask:1;
-        /** ioenable2 : RO; bitpos: [7]; default: 0;
-         *  ioe2 status in cccr
-         */
-        uint32_t ioenable2:1;
-        /** cd_disable : RO; bitpos: [8]; default: 0;
-         *  card disable status in cccr
-         */
-        uint32_t cd_disable:1;
-        /** func1_eps : RO; bitpos: [9]; default: 0;
-         *  function1 eps status in fbr
-         */
-        uint32_t func1_eps:1;
-        /** emp : RO; bitpos: [10]; default: 0;
-         *  empc status in cccr
-         */
-        uint32_t emp:1;
-        /** ioenable1 : RO; bitpos: [11]; default: 0;
-         *  ioe1 status in cccr
-         */
-        uint32_t ioenable1:1;
-        /** sdio_ver : R/W; bitpos: [23:12]; default: 562;
-         *  sdio version in cccr
-         */
-        uint32_t sdio_ver:12;
-        /** func2_eps : RO; bitpos: [24]; default: 0;
-         *  function2 eps status in fbr
-         */
-        uint32_t func2_eps:1;
-        /** sdio20_conf : R/W; bitpos: [31:25]; default: 0;
-         *  [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat
-         *  in delayed cycles control,0:no delay, 1:delay 1 cycle.
-         *  [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed
-         *  mode.
-         *  [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when
-         *  [12]=0,posedge when highspeed mode enable.
-         *  [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
-         *  [28]: sdio data pad pull up enable
-         */
-        uint32_t sdio20_conf:7;
-    };
-    uint32_t val;
-} hinf_cfg_data1_reg_t;
-
-/** Type of cfg_timing register
- *  Timing configuration registers
- */
-typedef union {
-    struct {
-        /** ncrc : R/W; bitpos: [2:0]; default: 2;
-         *  configure Ncrc parameter in sdr50/104 mode, no more than 6.
-         */
-        uint32_t ncrc:3;
-        /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2;
-         *  configure cycles to lower cmd after voltage is changed to 1.8V.
-         */
-        uint32_t pst_end_cmd_low_value:7;
-        /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2;
-         *  configure cycles to lower data after voltage is changed to 1.8V.
-         */
-        uint32_t pst_end_data_low_value:6;
-        /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400;
-         *  Configure the number of cycles of module clk to judge sdclk has stopped
-         */
-        uint32_t sdclk_stop_thres:11;
-        uint32_t reserved_27:1;
-        /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1;
-         *  module clk divider to sample sdclk
-         */
-        uint32_t sample_clk_divider:4;
-    };
-    uint32_t val;
-} hinf_cfg_timing_reg_t;
-
-/** Type of cfg_update register
- *  update sdio configurations
- */
-typedef union {
-    struct {
-        /** conf_update : WT; bitpos: [0]; default: 0;
-         *  update the timing configurations
-         */
-        uint32_t conf_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hinf_cfg_update_reg_t;
-
-/** Type of cfg_data7 register
- *  SDIO configuration register
- */
-typedef union {
-    struct {
-        /** pin_state : R/W; bitpos: [7:0]; default: 0;
-         *  configure cis addr 318 and 574
-         */
-        uint32_t pin_state:8;
-        /** chip_state : R/W; bitpos: [15:8]; default: 0;
-         *  configure cis addr 312, 315, 568 and 571
-         */
-        uint32_t chip_state:8;
-        /** sdio_rst : R/W; bitpos: [16]; default: 0;
-         *  soft reset control for sdio module
-         */
-        uint32_t sdio_rst:1;
-        /** sdio_ioready0 : R/W; bitpos: [17]; default: 1;
-         *  sdio io ready, high enable
-         */
-        uint32_t sdio_ioready0:1;
-        /** sdio_mem_pd : R/W; bitpos: [18]; default: 0;
-         *  sdio memory power down, high active
-         */
-        uint32_t sdio_mem_pd:1;
-        /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0;
-         *  enable sdio interrupt on data1 line
-         */
-        uint32_t esdio_data1_int_en:1;
-        /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0;
-         *  control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V
-         */
-        uint32_t sdio_switch_volt_sw:1;
-        /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0;
-         *  enable block length to be fixed to 512 bytes in ddr50 mode
-         */
-        uint32_t ddr50_blk_len_fix_en:1;
-        /** clk_en : R/W; bitpos: [22]; default: 0;
-         *  sdio apb clock for configuration force on control:0-gating,1-force on.
-         */
-        uint32_t clk_en:1;
-        /** sddr50 : R/W; bitpos: [23]; default: 1;
-         *  configure if support sdr50 mode in cccr
-         */
-        uint32_t sddr50:1;
-        /** ssdr104 : R/W; bitpos: [24]; default: 1;
-         *  configure if support sdr104 mode in cccr
-         */
-        uint32_t ssdr104:1;
-        /** ssdr50 : R/W; bitpos: [25]; default: 1;
-         *  configure if support ddr50 mode in cccr
-         */
-        uint32_t ssdr50:1;
-        /** sdtd : R/W; bitpos: [26]; default: 0;
-         *  configure if support driver type D in cccr
-         */
-        uint32_t sdtd:1;
-        /** sdta : R/W; bitpos: [27]; default: 0;
-         *  configure if support driver type A in cccr
-         */
-        uint32_t sdta:1;
-        /** sdtc : R/W; bitpos: [28]; default: 0;
-         *  configure if support driver type C in cccr
-         */
-        uint32_t sdtc:1;
-        /** sai : R/W; bitpos: [29]; default: 1;
-         *  configure if support asynchronous interrupt in cccr
-         */
-        uint32_t sai:1;
-        /** sdio_wakeup_clr : WT; bitpos: [30]; default: 0;
-         *  clear sdio_wake_up signal after the chip wakes up
-         */
-        uint32_t sdio_wakeup_clr:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} hinf_cfg_data7_reg_t;
-
-/** Type of cis_conf_w0 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 39~36
-         */
-        uint32_t cis_conf_w0:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w0_reg_t;
-
-/** Type of cis_conf_w1 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 43~40
-         */
-        uint32_t cis_conf_w1:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w1_reg_t;
-
-/** Type of cis_conf_w2 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 47~44
-         */
-        uint32_t cis_conf_w2:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w2_reg_t;
-
-/** Type of cis_conf_w3 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 51~48
-         */
-        uint32_t cis_conf_w3:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w3_reg_t;
-
-/** Type of cis_conf_w4 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 55~52
-         */
-        uint32_t cis_conf_w4:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w4_reg_t;
-
-/** Type of cis_conf_w5 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 59~56
-         */
-        uint32_t cis_conf_w5:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w5_reg_t;
-
-/** Type of cis_conf_w6 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 63~60
-         */
-        uint32_t cis_conf_w6:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w6_reg_t;
-
-/** Type of cis_conf_w7 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configure cis addr 67~64
-         */
-        uint32_t cis_conf_w7:32;
-    };
-    uint32_t val;
-} hinf_cis_conf_w7_reg_t;
-
-/** Type of cfg_data16 register
- *  SDIO cis configuration register
- */
-typedef union {
-    struct {
-        /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583;
-         *  configure device id of function2 in cis
-         */
-        uint32_t device_id_fn2:16;
-        /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146;
-         *  configure user id of function2 in cis
-         */
-        uint32_t user_id_fn2:16;
-    };
-    uint32_t val;
-} hinf_cfg_data16_reg_t;
-
-/** Type of cfg_uhs1_int_mode register
- *  configure int to start and end ahead of time in uhs1 mode
- */
-typedef union {
-    struct {
-        /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0;
-         *  intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
-         */
-        uint32_t intoe_end_ahead_mode:2;
-        /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0;
-         *  int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
-         */
-        uint32_t int_end_ahead_mode:2;
-        /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0;
-         *  intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
-         */
-        uint32_t intoe_st_ahead_mode:2;
-        /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0;
-         *  int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk
-         */
-        uint32_t int_st_ahead_mode:2;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} hinf_cfg_uhs1_int_mode_reg_t;
-
-/** Type of sdio_slave_ldo_conf register
- *  sdio slave ldo control register
- */
-typedef union {
-    struct {
-        /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0;
-         *  control ldo ready signal by sdio slave itself
-         */
-        uint32_t ldo_ready_ctl_in_en:1;
-        /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10;
-         *  configure ldo ready counting threshold value, the actual counting target is
-         *  2^(ldo_ready_thres)-1
-         */
-        uint32_t ldo_ready_thres:5;
-        /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0;
-         *  ignore ldo ready signal
-         */
-        uint32_t ldo_ready_ignore_en:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hinf_sdio_slave_ldo_conf_reg_t;
-
-
-/** Group: Status registers */
-/** Type of conf_status register
- *  func0 config0 status
- */
-typedef union {
-    struct {
-        /** func0_config0 : RO; bitpos: [7:0]; default: 0;
-         *  func0 config0 (addr: 0x20f0 ) status
-         */
-        uint32_t func0_config0:8;
-        /** sdr25_st : RO; bitpos: [8]; default: 0;
-         *  sdr25 status
-         */
-        uint32_t sdr25_st:1;
-        /** sdr50_st : RO; bitpos: [9]; default: 0;
-         *  sdr50 status
-         */
-        uint32_t sdr50_st:1;
-        /** sdr104_st : RO; bitpos: [10]; default: 0;
-         *  sdr104 status
-         */
-        uint32_t sdr104_st:1;
-        /** ddr50_st : RO; bitpos: [11]; default: 0;
-         *  ddr50 status
-         */
-        uint32_t ddr50_st:1;
-        /** tune_st : RO; bitpos: [14:12]; default: 0;
-         *  tune_st fsm status
-         */
-        uint32_t tune_st:3;
-        /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0;
-         *  sdio switch voltage status:0-3.3V, 1-1.8V.
-         */
-        uint32_t sdio_switch_volt_st:1;
-        /** sdio_switch_end : RO; bitpos: [16]; default: 0;
-         *  sdio switch voltage ldo ready
-         */
-        uint32_t sdio_switch_end:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} hinf_conf_status_reg_t;
-
-
-/** Group: Version register */
-/** Type of sdio_date register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** sdio_date : R/W; bitpos: [31:0]; default: 35664208;
-         *  sdio version date.
-         */
-        uint32_t sdio_date:32;
-    };
-    uint32_t val;
-} hinf_sdio_date_reg_t;
-
-
-typedef struct {
-    volatile hinf_cfg_data0_reg_t cfg_data0;
-    volatile hinf_cfg_data1_reg_t cfg_data1;
-    volatile hinf_cfg_timing_reg_t cfg_timing;
-    volatile hinf_cfg_update_reg_t cfg_update;
-    uint32_t reserved_010[3];
-    volatile hinf_cfg_data7_reg_t cfg_data7;
-    volatile hinf_cis_conf_w0_reg_t cis_conf_w0;
-    volatile hinf_cis_conf_w1_reg_t cis_conf_w1;
-    volatile hinf_cis_conf_w2_reg_t cis_conf_w2;
-    volatile hinf_cis_conf_w3_reg_t cis_conf_w3;
-    volatile hinf_cis_conf_w4_reg_t cis_conf_w4;
-    volatile hinf_cis_conf_w5_reg_t cis_conf_w5;
-    volatile hinf_cis_conf_w6_reg_t cis_conf_w6;
-    volatile hinf_cis_conf_w7_reg_t cis_conf_w7;
-    volatile hinf_cfg_data16_reg_t cfg_data16;
-    volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode;
-    uint32_t reserved_048[3];
-    volatile hinf_conf_status_reg_t conf_status;
-    uint32_t reserved_058[22];
-    volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf;
-    uint32_t reserved_0b4[18];
-    volatile hinf_sdio_date_reg_t sdio_date;
-} hinf_dev_t;
-
-extern hinf_dev_t HINF;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/sdio_slc_reg.h b/components/soc/esp32c5/include/soc/sdio_slc_reg.h
deleted file mode 100644
index 502b77201e..0000000000
--- a/components/soc/esp32c5/include/soc/sdio_slc_reg.h
+++ /dev/null
@@ -1,4301 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SDIO_SLCCONF0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCCONF0_REG (DR_REG_SDIO_BASE + 0x0)
-/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0;
- *  Set 1 to reset tx fsm in dma slc0.
- */
-#define SDIO_SLC0_TX_RST    (BIT(0))
-#define SDIO_SLC0_TX_RST_M  (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S)
-#define SDIO_SLC0_TX_RST_V  0x00000001U
-#define SDIO_SLC0_TX_RST_S  0
-/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0;
- *  Set 1 to reset rx fsm in dma slc0.
- */
-#define SDIO_SLC0_RX_RST    (BIT(1))
-#define SDIO_SLC0_RX_RST_M  (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S)
-#define SDIO_SLC0_RX_RST_V  0x00000001U
-#define SDIO_SLC0_RX_RST_S  1
-/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0;
- *  reset the command fifo of AHB bus of sdio slave
- */
-#define SDIO_SLC_AHBM_FIFO_RST    (BIT(2))
-#define SDIO_SLC_AHBM_FIFO_RST_M  (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S)
-#define SDIO_SLC_AHBM_FIFO_RST_V  0x00000001U
-#define SDIO_SLC_AHBM_FIFO_RST_S  2
-/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0;
- *  reset the AHB bus of sdio slave
- */
-#define SDIO_SLC_AHBM_RST    (BIT(3))
-#define SDIO_SLC_AHBM_RST_M  (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S)
-#define SDIO_SLC_AHBM_RST_V  0x00000001U
-#define SDIO_SLC_AHBM_RST_S  3
-/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0;
- *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
- */
-#define SDIO_SLC0_TX_LOOP_TEST    (BIT(4))
-#define SDIO_SLC0_TX_LOOP_TEST_M  (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S)
-#define SDIO_SLC0_TX_LOOP_TEST_V  0x00000001U
-#define SDIO_SLC0_TX_LOOP_TEST_S  4
-/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0;
- *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
- */
-#define SDIO_SLC0_RX_LOOP_TEST    (BIT(5))
-#define SDIO_SLC0_RX_LOOP_TEST_M  (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S)
-#define SDIO_SLC0_RX_LOOP_TEST_V  0x00000001U
-#define SDIO_SLC0_RX_LOOP_TEST_S  5
-/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0;
- *  Set 1 to enable change the owner bit of rx link descriptor
- */
-#define SDIO_SLC0_RX_AUTO_WRBACK    (BIT(6))
-#define SDIO_SLC0_RX_AUTO_WRBACK_M  (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S)
-#define SDIO_SLC0_RX_AUTO_WRBACK_V  0x00000001U
-#define SDIO_SLC0_RX_AUTO_WRBACK_S  6
-/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_NO_RESTART_CLR    (BIT(7))
-#define SDIO_SLC0_RX_NO_RESTART_CLR_M  (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S)
-#define SDIO_SLC0_RX_NO_RESTART_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_NO_RESTART_CLR_S  7
-/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1;
- *  0- AHB burst type is single when slave read rx-descriptor from memory through
- *  slc0,1-AHB burst type is not single when slave read rx-descriptor from memory
- *  through slc0
- */
-#define SDIO_SLC0_RXDSCR_BURST_EN    (BIT(8))
-#define SDIO_SLC0_RXDSCR_BURST_EN_M  (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S)
-#define SDIO_SLC0_RXDSCR_BURST_EN_V  0x00000001U
-#define SDIO_SLC0_RXDSCR_BURST_EN_S  8
-/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1;
- *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
- *  is not single when slave receives data from memory
- */
-#define SDIO_SLC0_RXDATA_BURST_EN    (BIT(9))
-#define SDIO_SLC0_RXDATA_BURST_EN_M  (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S)
-#define SDIO_SLC0_RXDATA_BURST_EN_V  0x00000001U
-#define SDIO_SLC0_RXDATA_BURST_EN_S  9
-/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1;
- *  enable the function that when host reading packet retries, slc1 will automatically
- *  jump to the start descriptor of the previous packet.
- */
-#define SDIO_SLC0_RXLINK_AUTO_RET    (BIT(10))
-#define SDIO_SLC0_RXLINK_AUTO_RET_M  (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S)
-#define SDIO_SLC0_RXLINK_AUTO_RET_V  0x00000001U
-#define SDIO_SLC0_RXLINK_AUTO_RET_S  10
-/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1;
- *  enable the function that when host sending packet retries, slc1 will automatically
- *  jump to the start descriptor of the previous packet.
- */
-#define SDIO_SLC0_TXLINK_AUTO_RET    (BIT(11))
-#define SDIO_SLC0_TXLINK_AUTO_RET_M  (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S)
-#define SDIO_SLC0_TXLINK_AUTO_RET_V  0x00000001U
-#define SDIO_SLC0_TXLINK_AUTO_RET_S  11
-/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1;
- *  0- AHB burst type is single when slave read tx-descriptor from memory through
- *  slc0,1-AHB burst type is not single when slave read tx-descriptor from memory
- *  through slc0
- */
-#define SDIO_SLC0_TXDSCR_BURST_EN    (BIT(12))
-#define SDIO_SLC0_TXDSCR_BURST_EN_M  (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S)
-#define SDIO_SLC0_TXDSCR_BURST_EN_V  0x00000001U
-#define SDIO_SLC0_TXDSCR_BURST_EN_S  12
-/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1;
- *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
- *  single when slave send data to memory
- */
-#define SDIO_SLC0_TXDATA_BURST_EN    (BIT(13))
-#define SDIO_SLC0_TXDATA_BURST_EN_M  (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S)
-#define SDIO_SLC0_TXDATA_BURST_EN_V  0x00000001U
-#define SDIO_SLC0_TXDATA_BURST_EN_S  13
-/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1;
- *  auto clear slc0_token1 enable
- */
-#define SDIO_SLC0_TOKEN_AUTO_CLR    (BIT(14))
-#define SDIO_SLC0_TOKEN_AUTO_CLR_M  (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S)
-#define SDIO_SLC0_TOKEN_AUTO_CLR_V  0x00000001U
-#define SDIO_SLC0_TOKEN_AUTO_CLR_S  14
-/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN_SEL    (BIT(15))
-#define SDIO_SLC0_TOKEN_SEL_M  (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S)
-#define SDIO_SLC0_TOKEN_SEL_V  0x00000001U
-#define SDIO_SLC0_TOKEN_SEL_S  15
-/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0;
- *  Set 1 to reset tx fsm in dma slc0.
- */
-#define SDIO_SLC1_TX_RST    (BIT(16))
-#define SDIO_SLC1_TX_RST_M  (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S)
-#define SDIO_SLC1_TX_RST_V  0x00000001U
-#define SDIO_SLC1_TX_RST_S  16
-/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0;
- *  Set 1 to reset rx fsm in dma slc0.
- */
-#define SDIO_SLC1_RX_RST    (BIT(17))
-#define SDIO_SLC1_RX_RST_M  (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S)
-#define SDIO_SLC1_RX_RST_V  0x00000001U
-#define SDIO_SLC1_RX_RST_S  17
-/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_MASK_EN    (BIT(18))
-#define SDIO_SLC0_WR_RETRY_MASK_EN_M  (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S)
-#define SDIO_SLC0_WR_RETRY_MASK_EN_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_MASK_EN_S  18
-/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_MASK_EN    (BIT(19))
-#define SDIO_SLC1_WR_RETRY_MASK_EN_M  (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S)
-#define SDIO_SLC1_WR_RETRY_MASK_EN_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_MASK_EN_S  19
-/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1;
- *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
- */
-#define SDIO_SLC1_TX_LOOP_TEST    (BIT(20))
-#define SDIO_SLC1_TX_LOOP_TEST_M  (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S)
-#define SDIO_SLC1_TX_LOOP_TEST_V  0x00000001U
-#define SDIO_SLC1_TX_LOOP_TEST_S  20
-/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1;
- *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
- */
-#define SDIO_SLC1_RX_LOOP_TEST    (BIT(21))
-#define SDIO_SLC1_RX_LOOP_TEST_M  (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S)
-#define SDIO_SLC1_RX_LOOP_TEST_V  0x00000001U
-#define SDIO_SLC1_RX_LOOP_TEST_S  21
-/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0;
- *  Set 1 to enable change the owner bit of rx link descriptor
- */
-#define SDIO_SLC1_RX_AUTO_WRBACK    (BIT(22))
-#define SDIO_SLC1_RX_AUTO_WRBACK_M  (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S)
-#define SDIO_SLC1_RX_AUTO_WRBACK_V  0x00000001U
-#define SDIO_SLC1_RX_AUTO_WRBACK_S  22
-/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0;
- *  ******* Description ***********
- */
-#define SDIO_SLC1_RX_NO_RESTART_CLR    (BIT(23))
-#define SDIO_SLC1_RX_NO_RESTART_CLR_M  (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S)
-#define SDIO_SLC1_RX_NO_RESTART_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_NO_RESTART_CLR_S  23
-/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1;
- *  0- AHB burst type is single when slave read rx-descriptor from memory through
- *  slc1,1-AHB burst type is not single when slave read rx-descriptor from memory
- *  through slc1
- */
-#define SDIO_SLC1_RXDSCR_BURST_EN    (BIT(24))
-#define SDIO_SLC1_RXDSCR_BURST_EN_M  (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S)
-#define SDIO_SLC1_RXDSCR_BURST_EN_V  0x00000001U
-#define SDIO_SLC1_RXDSCR_BURST_EN_S  24
-/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1;
- *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
- *  is not single when slave receives data from memory
- */
-#define SDIO_SLC1_RXDATA_BURST_EN    (BIT(25))
-#define SDIO_SLC1_RXDATA_BURST_EN_M  (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S)
-#define SDIO_SLC1_RXDATA_BURST_EN_V  0x00000001U
-#define SDIO_SLC1_RXDATA_BURST_EN_S  25
-/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1;
- *  enable the function that when host reading packet retries, slc1 will automatically
- *  jump to the start descriptor of the previous packet.
- */
-#define SDIO_SLC1_RXLINK_AUTO_RET    (BIT(26))
-#define SDIO_SLC1_RXLINK_AUTO_RET_M  (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S)
-#define SDIO_SLC1_RXLINK_AUTO_RET_V  0x00000001U
-#define SDIO_SLC1_RXLINK_AUTO_RET_S  26
-/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1;
- *  enable the function that when host sending packet retries, slc1 will automatically
- *  jump to the start descriptor of the previous packet.
- */
-#define SDIO_SLC1_TXLINK_AUTO_RET    (BIT(27))
-#define SDIO_SLC1_TXLINK_AUTO_RET_M  (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S)
-#define SDIO_SLC1_TXLINK_AUTO_RET_V  0x00000001U
-#define SDIO_SLC1_TXLINK_AUTO_RET_S  27
-/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1;
- *  0- AHB burst type is single when slave read tx-descriptor from memory through
- *  slc1,1-AHB burst type is not single when slave read tx-descriptor from memory
- *  through slc1
- */
-#define SDIO_SLC1_TXDSCR_BURST_EN    (BIT(28))
-#define SDIO_SLC1_TXDSCR_BURST_EN_M  (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S)
-#define SDIO_SLC1_TXDSCR_BURST_EN_V  0x00000001U
-#define SDIO_SLC1_TXDSCR_BURST_EN_S  28
-/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1;
- *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
- *  single when slave send data to memory
- */
-#define SDIO_SLC1_TXDATA_BURST_EN    (BIT(29))
-#define SDIO_SLC1_TXDATA_BURST_EN_M  (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S)
-#define SDIO_SLC1_TXDATA_BURST_EN_V  0x00000001U
-#define SDIO_SLC1_TXDATA_BURST_EN_S  29
-/** SDIO_SLC1_TOKEN_AUTO_CLR : R/W; bitpos: [30]; default: 1;
- *  auto clear slc1_token1 enable
- */
-#define SDIO_SLC1_TOKEN_AUTO_CLR    (BIT(30))
-#define SDIO_SLC1_TOKEN_AUTO_CLR_M  (SDIO_SLC1_TOKEN_AUTO_CLR_V << SDIO_SLC1_TOKEN_AUTO_CLR_S)
-#define SDIO_SLC1_TOKEN_AUTO_CLR_V  0x00000001U
-#define SDIO_SLC1_TOKEN_AUTO_CLR_S  30
-/** SDIO_SLC1_TOKEN_SEL : R/W; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN_SEL    (BIT(31))
-#define SDIO_SLC1_TOKEN_SEL_M  (SDIO_SLC1_TOKEN_SEL_V << SDIO_SLC1_TOKEN_SEL_S)
-#define SDIO_SLC1_TOKEN_SEL_V  0x00000001U
-#define SDIO_SLC1_TOKEN_SEL_S  31
-
-/** SDIO_SLC0INT_RAW_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0INT_RAW_REG (DR_REG_SDIO_BASE + 0x4)
-/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_RAW    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M  (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_RAW    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M  (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_RAW    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M  (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_RAW    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M  (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_RAW    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M  (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_RAW    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M  (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_RAW    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M  (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_RAW    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M  (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S  7
-/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_RAW    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_RAW_M  (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S)
-#define SDIO_SLC0_RX_START_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_RAW_S  8
-/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_RAW    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_RAW_M  (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S)
-#define SDIO_SLC0_TX_START_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_RAW_S  9
-/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_RAW    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_RAW_M  (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S)
-#define SDIO_SLC0_RX_UDF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_RAW_S  10
-/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_RAW    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_RAW_M  (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S)
-#define SDIO_SLC0_TX_OVF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_RAW_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M  (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M  (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S  13
-/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit of slc0 finishing receiving data to one buffer
- */
-#define SDIO_SLC0_TX_DONE_INT_RAW    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_RAW_M  (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S)
-#define SDIO_SLC0_TX_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_RAW_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit of slc0 finishing receiving data
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_RAW    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M  (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S  15
-/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw interrupt bit of slc0 finishing sending data from one buffer
- */
-#define SDIO_SLC0_RX_DONE_INT_RAW    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_RAW_M  (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S)
-#define SDIO_SLC0_RX_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_RAW_S  16
-/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw interrupt bit of slc0 finishing sending data
- */
-#define SDIO_SLC0_RX_EOF_INT_RAW    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_RAW_M  (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S)
-#define SDIO_SLC0_RX_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_RAW_S  17
-/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_RAW    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_RAW_M  (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S)
-#define SDIO_SLC0_TOHOST_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_RAW_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw interrupt bit of slc0 tx link descriptor error
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M  (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw interrupt bit of slc0 rx link descriptor error
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M  (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_RAW    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M  (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M  (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_RAW    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M  (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S  24
-/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_RAW    (BIT(25))
-#define SDIO_CMD_DTC_INT_RAW_M  (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S)
-#define SDIO_CMD_DTC_INT_RAW_V  0x00000001U
-#define SDIO_CMD_DTC_INT_RAW_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M  (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S  27
-/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_RAW    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_RAW_M  (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S)
-#define SDIO_HDA_RECV_DONE_INT_RAW_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_RAW_S  28
-
-/** SDIO_SLC0INT_ST_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0INT_ST_REG (DR_REG_SDIO_BASE + 0x8)
-/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_ST    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_ST_M  (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_ST_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_ST    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_ST_M  (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_ST_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_ST    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_ST_M  (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_ST_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_ST    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_ST_M  (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_ST_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_ST    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_ST_M  (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_ST_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_ST    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_ST_M  (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_ST_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_ST    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_ST_M  (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_ST_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_ST    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_ST_M  (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_ST_S  7
-/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_ST    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_ST_M  (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S)
-#define SDIO_SLC0_RX_START_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_ST_S  8
-/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_ST    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_ST_M  (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S)
-#define SDIO_SLC0_TX_START_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_ST_S  9
-/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_ST    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_ST_M  (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S)
-#define SDIO_SLC0_RX_UDF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_ST_S  10
-/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_ST    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_ST_M  (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S)
-#define SDIO_SLC0_TX_OVF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_ST_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S  13
-/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_ST    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_ST_M  (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S)
-#define SDIO_SLC0_TX_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_ST_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M  (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S  15
-/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_ST    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_ST_M  (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S)
-#define SDIO_SLC0_RX_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_ST_S  16
-/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_ST    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_ST_M  (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S)
-#define SDIO_SLC0_RX_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_ST_S  17
-/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_ST    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_ST_M  (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S)
-#define SDIO_SLC0_TOHOST_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_ST_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M  (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M  (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S  24
-/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_ST    (BIT(25))
-#define SDIO_CMD_DTC_INT_ST_M  (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S)
-#define SDIO_CMD_DTC_INT_ST_V  0x00000001U
-#define SDIO_CMD_DTC_INT_ST_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S  27
-/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_ST    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_ST_M  (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S)
-#define SDIO_HDA_RECV_DONE_INT_ST_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_ST_S  28
-
-/** SDIO_SLC0INT_ENA_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0INT_ENA_REG (DR_REG_SDIO_BASE + 0xc)
-/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M  (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M  (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M  (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M  (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M  (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M  (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M  (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M  (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S  7
-/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_ENA    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_ENA_M  (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S)
-#define SDIO_SLC0_RX_START_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_ENA_S  8
-/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_ENA    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_ENA_M  (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S)
-#define SDIO_SLC0_TX_START_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_ENA_S  9
-/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_ENA    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_ENA_M  (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S)
-#define SDIO_SLC0_RX_UDF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_ENA_S  10
-/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_ENA    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_ENA_M  (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S)
-#define SDIO_SLC0_TX_OVF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_ENA_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S  13
-/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_ENA    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_ENA_M  (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S)
-#define SDIO_SLC0_TX_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_ENA_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M  (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S  15
-/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_ENA    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_ENA_M  (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S)
-#define SDIO_SLC0_RX_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_ENA_S  16
-/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_ENA    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_ENA_M  (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S)
-#define SDIO_SLC0_RX_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_ENA_S  17
-/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_ENA    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_ENA_M  (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S)
-#define SDIO_SLC0_TOHOST_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_ENA_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M  (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M  (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S  24
-/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_ENA    (BIT(25))
-#define SDIO_CMD_DTC_INT_ENA_M  (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S)
-#define SDIO_CMD_DTC_INT_ENA_V  0x00000001U
-#define SDIO_CMD_DTC_INT_ENA_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S  27
-/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_ENA    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_ENA_M  (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S)
-#define SDIO_HDA_RECV_DONE_INT_ENA_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_ENA_S  28
-
-/** SDIO_SLC0INT_CLR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0INT_CLR_REG (DR_REG_SDIO_BASE + 0x10)
-/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_CLR    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M  (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_CLR    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M  (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_CLR    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M  (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_CLR    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M  (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_CLR    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M  (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_CLR    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M  (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_CLR    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M  (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_CLR    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M  (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S  7
-/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_CLR    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_CLR_M  (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S)
-#define SDIO_SLC0_RX_START_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_CLR_S  8
-/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_CLR    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_CLR_M  (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S)
-#define SDIO_SLC0_TX_START_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_CLR_S  9
-/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_CLR    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_CLR_M  (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S)
-#define SDIO_SLC0_RX_UDF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_CLR_S  10
-/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_CLR    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_CLR_M  (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S)
-#define SDIO_SLC0_TX_OVF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_CLR_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M  (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M  (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S  13
-/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_CLR    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_CLR_M  (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S)
-#define SDIO_SLC0_TX_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_CLR_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_CLR    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M  (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S  15
-/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_CLR    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_CLR_M  (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S)
-#define SDIO_SLC0_RX_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_CLR_S  16
-/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_CLR    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_CLR_M  (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S)
-#define SDIO_SLC0_RX_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_CLR_S  17
-/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_CLR    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_CLR_M  (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S)
-#define SDIO_SLC0_TOHOST_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_CLR_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M  (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M  (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_CLR    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M  (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M  (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_CLR    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M  (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S  24
-/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_CLR    (BIT(25))
-#define SDIO_CMD_DTC_INT_CLR_M  (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S)
-#define SDIO_CMD_DTC_INT_CLR_V  0x00000001U
-#define SDIO_CMD_DTC_INT_CLR_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M  (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S  27
-/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_CLR    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_CLR_M  (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S)
-#define SDIO_HDA_RECV_DONE_INT_CLR_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_CLR_S  28
-
-/** SDIO_SLC1INT_RAW_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_RAW_REG (DR_REG_SDIO_BASE + 0x14)
-/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_RAW    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M  (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_RAW    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M  (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_RAW    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M  (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_RAW    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M  (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_RAW    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M  (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_RAW    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M  (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_RAW    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M  (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_RAW    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M  (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S  7
-/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_RAW    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_RAW_M  (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S)
-#define SDIO_SLC1_RX_START_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_RAW_S  8
-/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_RAW    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_RAW_M  (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S)
-#define SDIO_SLC1_TX_START_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_RAW_S  9
-/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_RAW    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_RAW_M  (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S)
-#define SDIO_SLC1_RX_UDF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_RAW_S  10
-/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_RAW    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_RAW_M  (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S)
-#define SDIO_SLC1_TX_OVF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_RAW_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M  (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M  (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S  13
-/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_RAW    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_RAW_M  (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S)
-#define SDIO_SLC1_TX_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_RAW_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_RAW    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M  (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S  15
-/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_RAW    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_RAW_M  (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S)
-#define SDIO_SLC1_RX_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_RAW_S  16
-/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_RAW    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_RAW_M  (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S)
-#define SDIO_SLC1_RX_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_RAW_S  17
-/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_RAW    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_RAW_M  (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S)
-#define SDIO_SLC1_TOHOST_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_RAW_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M  (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M  (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_RAW    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M  (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M  (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_RAW    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M  (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S  24
-
-/** SDIO_SLC1INT_ST_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_ST_REG (DR_REG_SDIO_BASE + 0x18)
-/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_ST    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_ST_M  (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_ST_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_ST    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_ST_M  (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_ST_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_ST    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_ST_M  (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_ST_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_ST    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_ST_M  (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_ST_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_ST    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_ST_M  (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_ST_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_ST    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_ST_M  (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_ST_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_ST    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_ST_M  (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_ST_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_ST    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_ST_M  (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_ST_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_ST_S  7
-/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_ST    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_ST_M  (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S)
-#define SDIO_SLC1_RX_START_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_ST_S  8
-/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_ST    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_ST_M  (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S)
-#define SDIO_SLC1_TX_START_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_ST_S  9
-/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_ST    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_ST_M  (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S)
-#define SDIO_SLC1_RX_UDF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_ST_S  10
-/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_ST    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_ST_M  (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S)
-#define SDIO_SLC1_TX_OVF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_ST_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S  13
-/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_ST    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_ST_M  (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S)
-#define SDIO_SLC1_TX_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_ST_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M  (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S  15
-/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_ST    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_ST_M  (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S)
-#define SDIO_SLC1_RX_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_ST_S  16
-/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_ST    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_ST_M  (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S)
-#define SDIO_SLC1_RX_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_ST_S  17
-/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_ST    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_ST_M  (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S)
-#define SDIO_SLC1_TOHOST_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_ST_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M  (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M  (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S  24
-
-/** SDIO_SLC1INT_ENA_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_ENA_REG (DR_REG_SDIO_BASE + 0x1c)
-/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M  (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M  (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M  (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M  (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M  (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M  (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M  (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M  (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S  7
-/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_ENA    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_ENA_M  (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S)
-#define SDIO_SLC1_RX_START_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_ENA_S  8
-/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_ENA    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_ENA_M  (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S)
-#define SDIO_SLC1_TX_START_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_ENA_S  9
-/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_ENA    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_ENA_M  (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S)
-#define SDIO_SLC1_RX_UDF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_ENA_S  10
-/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_ENA    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_ENA_M  (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S)
-#define SDIO_SLC1_TX_OVF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_ENA_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S  13
-/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_ENA    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_ENA_M  (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S)
-#define SDIO_SLC1_TX_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_ENA_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M  (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S  15
-/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_ENA    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_ENA_M  (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S)
-#define SDIO_SLC1_RX_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_ENA_S  16
-/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_ENA    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_ENA_M  (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S)
-#define SDIO_SLC1_RX_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_ENA_S  17
-/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_ENA    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_ENA_M  (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S)
-#define SDIO_SLC1_TOHOST_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_ENA_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M  (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M  (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S  24
-
-/** SDIO_SLC1INT_CLR_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_CLR_REG (DR_REG_SDIO_BASE + 0x20)
-/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_CLR    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M  (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_CLR    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M  (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_CLR    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M  (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_CLR    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M  (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_CLR    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M  (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_CLR    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M  (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_CLR    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M  (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_CLR    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M  (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S  7
-/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_CLR    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_CLR_M  (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S)
-#define SDIO_SLC1_RX_START_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_CLR_S  8
-/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_CLR    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_CLR_M  (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S)
-#define SDIO_SLC1_TX_START_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_CLR_S  9
-/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_CLR    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_CLR_M  (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S)
-#define SDIO_SLC1_RX_UDF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_CLR_S  10
-/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_CLR    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_CLR_M  (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S)
-#define SDIO_SLC1_TX_OVF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_CLR_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M  (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M  (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S  13
-/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_CLR    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_CLR_M  (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S)
-#define SDIO_SLC1_TX_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_CLR_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_CLR    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M  (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S  15
-/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_CLR    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_CLR_M  (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S)
-#define SDIO_SLC1_RX_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_CLR_S  16
-/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_CLR    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_CLR_M  (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S)
-#define SDIO_SLC1_RX_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_CLR_S  17
-/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_CLR    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_CLR_M  (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S)
-#define SDIO_SLC1_TOHOST_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_CLR_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M  (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M  (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_CLR    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M  (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M  (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_CLR    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M  (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S  24
-
-/** SDIO_SLCRX_STATUS_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCRX_STATUS_REG (DR_REG_SDIO_BASE + 0x24)
-/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_FULL    (BIT(0))
-#define SDIO_SLC0_RX_FULL_M  (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S)
-#define SDIO_SLC0_RX_FULL_V  0x00000001U
-#define SDIO_SLC0_RX_FULL_S  0
-/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_RX_EMPTY    (BIT(1))
-#define SDIO_SLC0_RX_EMPTY_M  (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S)
-#define SDIO_SLC0_RX_EMPTY_V  0x00000001U
-#define SDIO_SLC0_RX_EMPTY_S  1
-/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0;
- *  the current buffer length when slc0 reads data from rx link
- */
-#define SDIO_SLC0_RX_BUF_LEN    0x00003FFFU
-#define SDIO_SLC0_RX_BUF_LEN_M  (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S)
-#define SDIO_SLC0_RX_BUF_LEN_V  0x00003FFFU
-#define SDIO_SLC0_RX_BUF_LEN_S  2
-/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_FULL    (BIT(16))
-#define SDIO_SLC1_RX_FULL_M  (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S)
-#define SDIO_SLC1_RX_FULL_V  0x00000001U
-#define SDIO_SLC1_RX_FULL_S  16
-/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_RX_EMPTY    (BIT(17))
-#define SDIO_SLC1_RX_EMPTY_M  (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S)
-#define SDIO_SLC1_RX_EMPTY_V  0x00000001U
-#define SDIO_SLC1_RX_EMPTY_S  17
-/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0;
- *  the current buffer length when slc1 reads data from rx link
- */
-#define SDIO_SLC1_RX_BUF_LEN    0x00003FFFU
-#define SDIO_SLC1_RX_BUF_LEN_M  (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S)
-#define SDIO_SLC1_RX_BUF_LEN_V  0x00003FFFU
-#define SDIO_SLC1_RX_BUF_LEN_S  18
-
-/** SDIO_SLC0RXFIFO_PUSH_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0RXFIFO_PUSH_REG (DR_REG_SDIO_BASE + 0x28)
-/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXFIFO_WDATA    0x000001FFU
-#define SDIO_SLC0_RXFIFO_WDATA_M  (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S)
-#define SDIO_SLC0_RXFIFO_WDATA_V  0x000001FFU
-#define SDIO_SLC0_RXFIFO_WDATA_S  0
-/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXFIFO_PUSH    (BIT(16))
-#define SDIO_SLC0_RXFIFO_PUSH_M  (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S)
-#define SDIO_SLC0_RXFIFO_PUSH_V  0x00000001U
-#define SDIO_SLC0_RXFIFO_PUSH_S  16
-
-/** SDIO_SLC1RXFIFO_PUSH_REG register
- *  reserved
- */
-#define SDIO_SLC1RXFIFO_PUSH_REG (DR_REG_SDIO_BASE + 0x2c)
-/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXFIFO_WDATA    0x000001FFU
-#define SDIO_SLC1_RXFIFO_WDATA_M  (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S)
-#define SDIO_SLC1_RXFIFO_WDATA_V  0x000001FFU
-#define SDIO_SLC1_RXFIFO_WDATA_S  0
-/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXFIFO_PUSH    (BIT(16))
-#define SDIO_SLC1_RXFIFO_PUSH_M  (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S)
-#define SDIO_SLC1_RXFIFO_PUSH_V  0x00000001U
-#define SDIO_SLC1_RXFIFO_PUSH_S  16
-
-/** SDIO_SLCTX_STATUS_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCTX_STATUS_REG (DR_REG_SDIO_BASE + 0x30)
-/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_FULL    (BIT(0))
-#define SDIO_SLC0_TX_FULL_M  (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S)
-#define SDIO_SLC0_TX_FULL_V  0x00000001U
-#define SDIO_SLC0_TX_FULL_S  0
-/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TX_EMPTY    (BIT(1))
-#define SDIO_SLC0_TX_EMPTY_M  (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S)
-#define SDIO_SLC0_TX_EMPTY_V  0x00000001U
-#define SDIO_SLC0_TX_EMPTY_S  1
-/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_FULL    (BIT(16))
-#define SDIO_SLC1_TX_FULL_M  (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S)
-#define SDIO_SLC1_TX_FULL_V  0x00000001U
-#define SDIO_SLC1_TX_FULL_S  16
-/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TX_EMPTY    (BIT(17))
-#define SDIO_SLC1_TX_EMPTY_M  (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S)
-#define SDIO_SLC1_TX_EMPTY_V  0x00000001U
-#define SDIO_SLC1_TX_EMPTY_S  17
-
-/** SDIO_SLC0TXFIFO_POP_REG register
- *  reserved
- */
-#define SDIO_SLC0TXFIFO_POP_REG (DR_REG_SDIO_BASE + 0x34)
-/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024;
- *  reserved
- */
-#define SDIO_SLC0_TXFIFO_RDATA    0x000007FFU
-#define SDIO_SLC0_TXFIFO_RDATA_M  (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S)
-#define SDIO_SLC0_TXFIFO_RDATA_V  0x000007FFU
-#define SDIO_SLC0_TXFIFO_RDATA_S  0
-/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXFIFO_POP    (BIT(16))
-#define SDIO_SLC0_TXFIFO_POP_M  (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S)
-#define SDIO_SLC0_TXFIFO_POP_V  0x00000001U
-#define SDIO_SLC0_TXFIFO_POP_S  16
-
-/** SDIO_SLC1TXFIFO_POP_REG register
- *  reserved
- */
-#define SDIO_SLC1TXFIFO_POP_REG (DR_REG_SDIO_BASE + 0x38)
-/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024;
- *  reserved
- */
-#define SDIO_SLC1_TXFIFO_RDATA    0x000007FFU
-#define SDIO_SLC1_TXFIFO_RDATA_M  (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S)
-#define SDIO_SLC1_TXFIFO_RDATA_V  0x000007FFU
-#define SDIO_SLC1_TXFIFO_RDATA_S  0
-/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXFIFO_POP    (BIT(16))
-#define SDIO_SLC1_TXFIFO_POP_M  (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S)
-#define SDIO_SLC1_TXFIFO_POP_V  0x00000001U
-#define SDIO_SLC1_TXFIFO_POP_S  16
-
-/** SDIO_SLC0RX_LINK_REG register
- *  reserved
- */
-#define SDIO_SLC0RX_LINK_REG (DR_REG_SDIO_BASE + 0x3c)
-/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_STOP    (BIT(28))
-#define SDIO_SLC0_RXLINK_STOP_M  (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S)
-#define SDIO_SLC0_RXLINK_STOP_V  0x00000001U
-#define SDIO_SLC0_RXLINK_STOP_S  28
-/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_START    (BIT(29))
-#define SDIO_SLC0_RXLINK_START_M  (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S)
-#define SDIO_SLC0_RXLINK_START_V  0x00000001U
-#define SDIO_SLC0_RXLINK_START_S  29
-/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_RESTART    (BIT(30))
-#define SDIO_SLC0_RXLINK_RESTART_M  (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S)
-#define SDIO_SLC0_RXLINK_RESTART_V  0x00000001U
-#define SDIO_SLC0_RXLINK_RESTART_S  30
-/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_PARK    (BIT(31))
-#define SDIO_SLC0_RXLINK_PARK_M  (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S)
-#define SDIO_SLC0_RXLINK_PARK_V  0x00000001U
-#define SDIO_SLC0_RXLINK_PARK_S  31
-
-/** SDIO_SLC0RX_LINK_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0RX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x40)
-/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_ADDR_M  (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S)
-#define SDIO_SLC0_RXLINK_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_ADDR_S  0
-
-/** SDIO_SLC0TX_LINK_REG register
- *  reserved
- */
-#define SDIO_SLC0TX_LINK_REG (DR_REG_SDIO_BASE + 0x44)
-/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_STOP    (BIT(28))
-#define SDIO_SLC0_TXLINK_STOP_M  (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S)
-#define SDIO_SLC0_TXLINK_STOP_V  0x00000001U
-#define SDIO_SLC0_TXLINK_STOP_S  28
-/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_START    (BIT(29))
-#define SDIO_SLC0_TXLINK_START_M  (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S)
-#define SDIO_SLC0_TXLINK_START_V  0x00000001U
-#define SDIO_SLC0_TXLINK_START_S  29
-/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_RESTART    (BIT(30))
-#define SDIO_SLC0_TXLINK_RESTART_M  (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S)
-#define SDIO_SLC0_TXLINK_RESTART_V  0x00000001U
-#define SDIO_SLC0_TXLINK_RESTART_S  30
-/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_PARK    (BIT(31))
-#define SDIO_SLC0_TXLINK_PARK_M  (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S)
-#define SDIO_SLC0_TXLINK_PARK_V  0x00000001U
-#define SDIO_SLC0_TXLINK_PARK_S  31
-
-/** SDIO_SLC0TX_LINK_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0TX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x48)
-/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_ADDR_M  (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S)
-#define SDIO_SLC0_TXLINK_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_ADDR_S  0
-
-/** SDIO_SLC1RX_LINK_REG register
- *  reserved
- */
-#define SDIO_SLC1RX_LINK_REG (DR_REG_SDIO_BASE + 0x4c)
-/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_BT_PACKET    (BIT(20))
-#define SDIO_SLC1_BT_PACKET_M  (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S)
-#define SDIO_SLC1_BT_PACKET_V  0x00000001U
-#define SDIO_SLC1_BT_PACKET_S  20
-/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_STOP    (BIT(28))
-#define SDIO_SLC1_RXLINK_STOP_M  (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S)
-#define SDIO_SLC1_RXLINK_STOP_V  0x00000001U
-#define SDIO_SLC1_RXLINK_STOP_S  28
-/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_START    (BIT(29))
-#define SDIO_SLC1_RXLINK_START_M  (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S)
-#define SDIO_SLC1_RXLINK_START_V  0x00000001U
-#define SDIO_SLC1_RXLINK_START_S  29
-/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_RESTART    (BIT(30))
-#define SDIO_SLC1_RXLINK_RESTART_M  (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S)
-#define SDIO_SLC1_RXLINK_RESTART_V  0x00000001U
-#define SDIO_SLC1_RXLINK_RESTART_S  30
-/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_PARK    (BIT(31))
-#define SDIO_SLC1_RXLINK_PARK_M  (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S)
-#define SDIO_SLC1_RXLINK_PARK_V  0x00000001U
-#define SDIO_SLC1_RXLINK_PARK_S  31
-
-/** SDIO_SLC1RX_LINK_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1RX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x50)
-/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_ADDR_M  (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S)
-#define SDIO_SLC1_RXLINK_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_ADDR_S  0
-
-/** SDIO_SLC1TX_LINK_REG register
- *  reserved
- */
-#define SDIO_SLC1TX_LINK_REG (DR_REG_SDIO_BASE + 0x54)
-/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_STOP    (BIT(28))
-#define SDIO_SLC1_TXLINK_STOP_M  (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S)
-#define SDIO_SLC1_TXLINK_STOP_V  0x00000001U
-#define SDIO_SLC1_TXLINK_STOP_S  28
-/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_START    (BIT(29))
-#define SDIO_SLC1_TXLINK_START_M  (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S)
-#define SDIO_SLC1_TXLINK_START_V  0x00000001U
-#define SDIO_SLC1_TXLINK_START_S  29
-/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_RESTART    (BIT(30))
-#define SDIO_SLC1_TXLINK_RESTART_M  (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S)
-#define SDIO_SLC1_TXLINK_RESTART_V  0x00000001U
-#define SDIO_SLC1_TXLINK_RESTART_S  30
-/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_PARK    (BIT(31))
-#define SDIO_SLC1_TXLINK_PARK_M  (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S)
-#define SDIO_SLC1_TXLINK_PARK_V  0x00000001U
-#define SDIO_SLC1_TXLINK_PARK_S  31
-
-/** SDIO_SLC1TX_LINK_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1TX_LINK_ADDR_REG (DR_REG_SDIO_BASE + 0x58)
-/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_ADDR_M  (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S)
-#define SDIO_SLC1_TXLINK_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_ADDR_S  0
-
-/** SDIO_SLCINTVEC_TOHOST_REG register
- *  reserved
- */
-#define SDIO_SLCINTVEC_TOHOST_REG (DR_REG_SDIO_BASE + 0x5c)
-/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INTVEC    0x000000FFU
-#define SDIO_SLC0_TOHOST_INTVEC_M  (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S)
-#define SDIO_SLC0_TOHOST_INTVEC_V  0x000000FFU
-#define SDIO_SLC0_TOHOST_INTVEC_S  0
-/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INTVEC    0x000000FFU
-#define SDIO_SLC1_TOHOST_INTVEC_M  (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S)
-#define SDIO_SLC1_TOHOST_INTVEC_V  0x000000FFU
-#define SDIO_SLC1_TOHOST_INTVEC_S  16
-
-/** SDIO_SLC0TOKEN0_REG register
- *  reserved
- */
-#define SDIO_SLC0TOKEN0_REG (DR_REG_SDIO_BASE + 0x60)
-/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_WDATA    0x00000FFFU
-#define SDIO_SLC0_TOKEN0_WDATA_M  (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S)
-#define SDIO_SLC0_TOKEN0_WDATA_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN0_WDATA_S  0
-/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_WR    (BIT(12))
-#define SDIO_SLC0_TOKEN0_WR_M  (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S)
-#define SDIO_SLC0_TOKEN0_WR_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_WR_S  12
-/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_INC    (BIT(13))
-#define SDIO_SLC0_TOKEN0_INC_M  (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S)
-#define SDIO_SLC0_TOKEN0_INC_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_INC_S  13
-/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_INC_MORE    (BIT(14))
-#define SDIO_SLC0_TOKEN0_INC_MORE_M  (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S)
-#define SDIO_SLC0_TOKEN0_INC_MORE_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_INC_MORE_S  14
-/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0    0x00000FFFU
-#define SDIO_SLC0_TOKEN0_M  (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S)
-#define SDIO_SLC0_TOKEN0_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN0_S  16
-
-/** SDIO_SLC0TOKEN1_REG register
- *  reserved
- */
-#define SDIO_SLC0TOKEN1_REG (DR_REG_SDIO_BASE + 0x64)
-/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0;
- *  slc0 token1 wdata
- */
-#define SDIO_SLC0_TOKEN1_WDATA    0x00000FFFU
-#define SDIO_SLC0_TOKEN1_WDATA_M  (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S)
-#define SDIO_SLC0_TOKEN1_WDATA_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN1_WDATA_S  0
-/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0;
- *  update slc0_token1_wdata into slc0 token1
- */
-#define SDIO_SLC0_TOKEN1_WR    (BIT(12))
-#define SDIO_SLC0_TOKEN1_WR_M  (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S)
-#define SDIO_SLC0_TOKEN1_WR_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_WR_S  12
-/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0;
- *  slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1
- */
-#define SDIO_SLC0_TOKEN1_INC    (BIT(13))
-#define SDIO_SLC0_TOKEN1_INC_M  (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S)
-#define SDIO_SLC0_TOKEN1_INC_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_INC_S  13
-/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0;
- *  slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add
- *  slc0_token1_wdata to slc0_token1
- */
-#define SDIO_SLC0_TOKEN1_INC_MORE    (BIT(14))
-#define SDIO_SLC0_TOKEN1_INC_MORE_M  (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S)
-#define SDIO_SLC0_TOKEN1_INC_MORE_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_INC_MORE_S  14
-/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1    0x00000FFFU
-#define SDIO_SLC0_TOKEN1_M  (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S)
-#define SDIO_SLC0_TOKEN1_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN1_S  16
-
-/** SDIO_SLC1TOKEN0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1TOKEN0_REG (DR_REG_SDIO_BASE + 0x68)
-/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_WDATA    0x00000FFFU
-#define SDIO_SLC1_TOKEN0_WDATA_M  (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S)
-#define SDIO_SLC1_TOKEN0_WDATA_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN0_WDATA_S  0
-/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_WR    (BIT(12))
-#define SDIO_SLC1_TOKEN0_WR_M  (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S)
-#define SDIO_SLC1_TOKEN0_WR_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_WR_S  12
-/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0;
- *  Add 1 to  slc1_token0
- */
-#define SDIO_SLC1_TOKEN0_INC    (BIT(13))
-#define SDIO_SLC1_TOKEN0_INC_M  (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S)
-#define SDIO_SLC1_TOKEN0_INC_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_INC_S  13
-/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0;
- *  Add  slc1_token0_wdata to  slc1_token0
- */
-#define SDIO_SLC1_TOKEN0_INC_MORE    (BIT(14))
-#define SDIO_SLC1_TOKEN0_INC_MORE_M  (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S)
-#define SDIO_SLC1_TOKEN0_INC_MORE_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_INC_MORE_S  14
-/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0    0x00000FFFU
-#define SDIO_SLC1_TOKEN0_M  (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S)
-#define SDIO_SLC1_TOKEN0_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN0_S  16
-
-/** SDIO_SLC1TOKEN1_REG register
- *  reserved
- */
-#define SDIO_SLC1TOKEN1_REG (DR_REG_SDIO_BASE + 0x6c)
-/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_WDATA    0x00000FFFU
-#define SDIO_SLC1_TOKEN1_WDATA_M  (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S)
-#define SDIO_SLC1_TOKEN1_WDATA_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN1_WDATA_S  0
-/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0;
- *  update slc1_token1_wdata into slc1 token1
- */
-#define SDIO_SLC1_TOKEN1_WR    (BIT(12))
-#define SDIO_SLC1_TOKEN1_WR_M  (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S)
-#define SDIO_SLC1_TOKEN1_WR_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_WR_S  12
-/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_INC    (BIT(13))
-#define SDIO_SLC1_TOKEN1_INC_M  (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S)
-#define SDIO_SLC1_TOKEN1_INC_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_INC_S  13
-/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_INC_MORE    (BIT(14))
-#define SDIO_SLC1_TOKEN1_INC_MORE_M  (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S)
-#define SDIO_SLC1_TOKEN1_INC_MORE_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_INC_MORE_S  14
-/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1    0x00000FFFU
-#define SDIO_SLC1_TOKEN1_M  (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S)
-#define SDIO_SLC1_TOKEN1_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN1_S  16
-
-/** SDIO_SLCCONF1_REG register
- *  reserved
- */
-#define SDIO_SLCCONF1_REG (DR_REG_SDIO_BASE + 0x70)
-/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_CHECK_OWNER    (BIT(0))
-#define SDIO_SLC0_CHECK_OWNER_M  (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S)
-#define SDIO_SLC0_CHECK_OWNER_V  0x00000001U
-#define SDIO_SLC0_CHECK_OWNER_S  0
-/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_CHECK_SUM_EN    (BIT(1))
-#define SDIO_SLC0_TX_CHECK_SUM_EN_M  (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S)
-#define SDIO_SLC0_TX_CHECK_SUM_EN_V  0x00000001U
-#define SDIO_SLC0_TX_CHECK_SUM_EN_S  1
-/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_CHECK_SUM_EN    (BIT(2))
-#define SDIO_SLC0_RX_CHECK_SUM_EN_M  (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S)
-#define SDIO_SLC0_RX_CHECK_SUM_EN_V  0x00000001U
-#define SDIO_SLC0_RX_CHECK_SUM_EN_S  2
-/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1;
- *  reserved
- */
-#define SDIO_SDIO_CMD_HOLD_EN    (BIT(3))
-#define SDIO_SDIO_CMD_HOLD_EN_M  (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S)
-#define SDIO_SDIO_CMD_HOLD_EN_V  0x00000001U
-#define SDIO_SDIO_CMD_HOLD_EN_S  3
-/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_LEN_AUTO_CLR    (BIT(4))
-#define SDIO_SLC0_LEN_AUTO_CLR_M  (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S)
-#define SDIO_SLC0_LEN_AUTO_CLR_V  0x00000001U
-#define SDIO_SLC0_LEN_AUTO_CLR_S  4
-/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TX_STITCH_EN    (BIT(5))
-#define SDIO_SLC0_TX_STITCH_EN_M  (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S)
-#define SDIO_SLC0_TX_STITCH_EN_V  0x00000001U
-#define SDIO_SLC0_TX_STITCH_EN_S  5
-/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_RX_STITCH_EN    (BIT(6))
-#define SDIO_SLC0_RX_STITCH_EN_M  (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S)
-#define SDIO_SLC0_RX_STITCH_EN_V  0x00000001U
-#define SDIO_SLC0_RX_STITCH_EN_S  6
-/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_CHECK_OWNER    (BIT(16))
-#define SDIO_SLC1_CHECK_OWNER_M  (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S)
-#define SDIO_SLC1_CHECK_OWNER_V  0x00000001U
-#define SDIO_SLC1_CHECK_OWNER_S  16
-/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_CHECK_SUM_EN    (BIT(17))
-#define SDIO_SLC1_TX_CHECK_SUM_EN_M  (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S)
-#define SDIO_SLC1_TX_CHECK_SUM_EN_V  0x00000001U
-#define SDIO_SLC1_TX_CHECK_SUM_EN_S  17
-/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_CHECK_SUM_EN    (BIT(18))
-#define SDIO_SLC1_RX_CHECK_SUM_EN_M  (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S)
-#define SDIO_SLC1_RX_CHECK_SUM_EN_V  0x00000001U
-#define SDIO_SLC1_RX_CHECK_SUM_EN_S  18
-/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_HOST_INT_LEVEL_SEL    (BIT(19))
-#define SDIO_HOST_INT_LEVEL_SEL_M  (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S)
-#define SDIO_HOST_INT_LEVEL_SEL_V  0x00000001U
-#define SDIO_HOST_INT_LEVEL_SEL_S  19
-/** SDIO_SLC1_TX_STITCH_EN : R/W; bitpos: [20]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TX_STITCH_EN    (BIT(20))
-#define SDIO_SLC1_TX_STITCH_EN_M  (SDIO_SLC1_TX_STITCH_EN_V << SDIO_SLC1_TX_STITCH_EN_S)
-#define SDIO_SLC1_TX_STITCH_EN_V  0x00000001U
-#define SDIO_SLC1_TX_STITCH_EN_S  20
-/** SDIO_SLC1_RX_STITCH_EN : R/W; bitpos: [21]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_RX_STITCH_EN    (BIT(21))
-#define SDIO_SLC1_RX_STITCH_EN_M  (SDIO_SLC1_RX_STITCH_EN_V << SDIO_SLC1_RX_STITCH_EN_S)
-#define SDIO_SLC1_RX_STITCH_EN_V  0x00000001U
-#define SDIO_SLC1_RX_STITCH_EN_S  21
-/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_CLK_EN    (BIT(22))
-#define SDIO_SDIO_CLK_EN_M  (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S)
-#define SDIO_SDIO_CLK_EN_V  0x00000001U
-#define SDIO_SDIO_CLK_EN_S  22
-
-/** SDIO_SLC0_STATE0_REG register
- *  reserved
- */
-#define SDIO_SLC0_STATE0_REG (DR_REG_SDIO_BASE + 0x74)
-/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_STATE0    0xFFFFFFFFU
-#define SDIO_SLC0_STATE0_M  (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S)
-#define SDIO_SLC0_STATE0_V  0xFFFFFFFFU
-#define SDIO_SLC0_STATE0_S  0
-
-/** SDIO_SLC0_STATE1_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_STATE1_REG (DR_REG_SDIO_BASE + 0x78)
-/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0;
- *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
- *  rx_link fsm state, [30:24] rx_fifo_cnt
- */
-#define SDIO_SLC0_STATE1    0xFFFFFFFFU
-#define SDIO_SLC0_STATE1_M  (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S)
-#define SDIO_SLC0_STATE1_V  0xFFFFFFFFU
-#define SDIO_SLC0_STATE1_S  0
-
-/** SDIO_SLC1_STATE0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1_STATE0_REG (DR_REG_SDIO_BASE + 0x7c)
-/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_STATE0    0xFFFFFFFFU
-#define SDIO_SLC1_STATE0_M  (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S)
-#define SDIO_SLC1_STATE0_V  0xFFFFFFFFU
-#define SDIO_SLC1_STATE0_S  0
-
-/** SDIO_SLC1_STATE1_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1_STATE1_REG (DR_REG_SDIO_BASE + 0x80)
-/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0;
- *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
- *  rx_link fsm state, [30:24] rx_fifo_cnt
- */
-#define SDIO_SLC1_STATE1    0xFFFFFFFFU
-#define SDIO_SLC1_STATE1_M  (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S)
-#define SDIO_SLC1_STATE1_V  0xFFFFFFFFU
-#define SDIO_SLC1_STATE1_S  0
-
-/** SDIO_SLCBRIDGE_CONF_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCBRIDGE_CONF_REG (DR_REG_SDIO_BASE + 0x84)
-/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32;
- *  reserved
- */
-#define SDIO_SLC_TXEOF_ENA    0x0000003FU
-#define SDIO_SLC_TXEOF_ENA_M  (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S)
-#define SDIO_SLC_TXEOF_ENA_V  0x0000003FU
-#define SDIO_SLC_TXEOF_ENA_S  0
-/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7;
- *  reserved
- */
-#define SDIO_SLC_FIFO_MAP_ENA    0x0000000FU
-#define SDIO_SLC_FIFO_MAP_ENA_M  (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S)
-#define SDIO_SLC_FIFO_MAP_ENA_V  0x0000000FU
-#define SDIO_SLC_FIFO_MAP_ENA_S  8
-/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TX_DUMMY_MODE    (BIT(12))
-#define SDIO_SLC0_TX_DUMMY_MODE_M  (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S)
-#define SDIO_SLC0_TX_DUMMY_MODE_V  0x00000001U
-#define SDIO_SLC0_TX_DUMMY_MODE_S  12
-/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1;
- *  reserved
- */
-#define SDIO_SLC_HDA_MAP_128K    (BIT(13))
-#define SDIO_SLC_HDA_MAP_128K_M  (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S)
-#define SDIO_SLC_HDA_MAP_128K_V  0x00000001U
-#define SDIO_SLC_HDA_MAP_128K_S  13
-/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TX_DUMMY_MODE    (BIT(14))
-#define SDIO_SLC1_TX_DUMMY_MODE_M  (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S)
-#define SDIO_SLC1_TX_DUMMY_MODE_V  0x00000001U
-#define SDIO_SLC1_TX_DUMMY_MODE_S  14
-/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10;
- *  reserved
- */
-#define SDIO_SLC_TX_PUSH_IDLE_NUM    0x0000FFFFU
-#define SDIO_SLC_TX_PUSH_IDLE_NUM_M  (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S)
-#define SDIO_SLC_TX_PUSH_IDLE_NUM_V  0x0000FFFFU
-#define SDIO_SLC_TX_PUSH_IDLE_NUM_S  16
-
-/** SDIO_SLC0_TO_EOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x88)
-/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TO_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TO_EOF_DES_ADDR_M  (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S)
-#define SDIO_SLC0_TO_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TO_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC0_TX_EOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x8c)
-/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M  (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S)
-#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x90)
-/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M  (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S)
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S  0
-
-/** SDIO_SLC1_TO_EOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x94)
-/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TO_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TO_EOF_DES_ADDR_M  (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S)
-#define SDIO_SLC1_TO_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TO_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC1_TX_EOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x98)
-/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M  (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S)
-#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SDIO_BASE + 0x9c)
-/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M  (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S)
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S  0
-
-/** SDIO_SLC_AHB_TEST_REG register
- *  reserved
- */
-#define SDIO_SLC_AHB_TEST_REG (DR_REG_SDIO_BASE + 0xa0)
-/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_AHB_TESTMODE    0x00000007U
-#define SDIO_SLC_AHB_TESTMODE_M  (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S)
-#define SDIO_SLC_AHB_TESTMODE_V  0x00000007U
-#define SDIO_SLC_AHB_TESTMODE_S  0
-/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_AHB_TESTADDR    0x00000003U
-#define SDIO_SLC_AHB_TESTADDR_M  (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S)
-#define SDIO_SLC_AHB_TESTADDR_V  0x00000003U
-#define SDIO_SLC_AHB_TESTADDR_S  4
-
-/** SDIO_SLC_SDIO_ST_REG register
- *  reserved
- */
-#define SDIO_SLC_SDIO_ST_REG (DR_REG_SDIO_BASE + 0xa4)
-/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_ST    0x00000007U
-#define SDIO_CMD_ST_M  (SDIO_CMD_ST_V << SDIO_CMD_ST_S)
-#define SDIO_CMD_ST_V  0x00000007U
-#define SDIO_CMD_ST_S  0
-/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0;
- *  reserved
- */
-#define SDIO_FUNC_ST    0x0000000FU
-#define SDIO_FUNC_ST_M  (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S)
-#define SDIO_FUNC_ST_V  0x0000000FU
-#define SDIO_FUNC_ST_S  4
-/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_WAKEUP    (BIT(8))
-#define SDIO_SDIO_WAKEUP_M  (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S)
-#define SDIO_SDIO_WAKEUP_V  0x00000001U
-#define SDIO_SDIO_WAKEUP_S  8
-/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0;
- *  reserved
- */
-#define SDIO_BUS_ST    0x00000007U
-#define SDIO_BUS_ST_M  (SDIO_BUS_ST_V << SDIO_BUS_ST_S)
-#define SDIO_BUS_ST_V  0x00000007U
-#define SDIO_BUS_ST_S  12
-/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0;
- *  reserved
- */
-#define SDIO_FUNC1_ACC_STATE    0x0000001FU
-#define SDIO_FUNC1_ACC_STATE_M  (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S)
-#define SDIO_FUNC1_ACC_STATE_V  0x0000001FU
-#define SDIO_FUNC1_ACC_STATE_S  16
-/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0;
- *  reserved
- */
-#define SDIO_FUNC2_ACC_STATE    0x0000001FU
-#define SDIO_FUNC2_ACC_STATE_M  (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S)
-#define SDIO_FUNC2_ACC_STATE_V  0x0000001FU
-#define SDIO_FUNC2_ACC_STATE_S  24
-
-/** SDIO_SLC_RX_DSCR_CONF_REG register
- *  reserved
- */
-#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SDIO_BASE + 0xa8)
-/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN_NO_REPLACE    (BIT(0))
-#define SDIO_SLC0_TOKEN_NO_REPLACE_M  (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S)
-#define SDIO_SLC0_TOKEN_NO_REPLACE_V  0x00000001U
-#define SDIO_SLC0_TOKEN_NO_REPLACE_S  0
-/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_INFOR_NO_REPLACE    (BIT(1))
-#define SDIO_SLC0_INFOR_NO_REPLACE_M  (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S)
-#define SDIO_SLC0_INFOR_NO_REPLACE_V  0x00000001U
-#define SDIO_SLC0_INFOR_NO_REPLACE_S  1
-/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0;
- *  slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next
- *  pop doesn't occur after 255 cycles since the current pop
- */
-#define SDIO_SLC0_RX_FILL_MODE    (BIT(2))
-#define SDIO_SLC0_RX_FILL_MODE_M  (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S)
-#define SDIO_SLC0_RX_FILL_MODE_V  0x00000001U
-#define SDIO_SLC0_RX_FILL_MODE_S  2
-/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1;
- *  0-slc0 rx_push_eof, 1-slc0 rx_pop_eof
- */
-#define SDIO_SLC0_RX_EOF_MODE    (BIT(3))
-#define SDIO_SLC0_RX_EOF_MODE_M  (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S)
-#define SDIO_SLC0_RX_EOF_MODE_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_MODE_S  3
-/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_RX_FILL_EN    (BIT(4))
-#define SDIO_SLC0_RX_FILL_EN_M  (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S)
-#define SDIO_SLC0_RX_FILL_EN_V  0x00000001U
-#define SDIO_SLC0_RX_FILL_EN_S  4
-/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128;
- *  reserved
- */
-#define SDIO_SLC0_RD_RETRY_THRESHOLD    0x000007FFU
-#define SDIO_SLC0_RD_RETRY_THRESHOLD_M  (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S)
-#define SDIO_SLC0_RD_RETRY_THRESHOLD_V  0x000007FFU
-#define SDIO_SLC0_RD_RETRY_THRESHOLD_S  5
-/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN_NO_REPLACE    (BIT(16))
-#define SDIO_SLC1_TOKEN_NO_REPLACE_M  (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S)
-#define SDIO_SLC1_TOKEN_NO_REPLACE_V  0x00000001U
-#define SDIO_SLC1_TOKEN_NO_REPLACE_S  16
-/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_INFOR_NO_REPLACE    (BIT(17))
-#define SDIO_SLC1_INFOR_NO_REPLACE_M  (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S)
-#define SDIO_SLC1_INFOR_NO_REPLACE_V  0x00000001U
-#define SDIO_SLC1_INFOR_NO_REPLACE_S  17
-/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0;
- *  slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next
- *  pop doesn't occur after 255 cycles since the current pop
- */
-#define SDIO_SLC1_RX_FILL_MODE    (BIT(18))
-#define SDIO_SLC1_RX_FILL_MODE_M  (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S)
-#define SDIO_SLC1_RX_FILL_MODE_V  0x00000001U
-#define SDIO_SLC1_RX_FILL_MODE_S  18
-/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1;
- *  0-slc1 rx_push_eof, 1-slc1 rx_pop_eof
- */
-#define SDIO_SLC1_RX_EOF_MODE    (BIT(19))
-#define SDIO_SLC1_RX_EOF_MODE_M  (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S)
-#define SDIO_SLC1_RX_EOF_MODE_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_MODE_S  19
-/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1;
- *  reserved
- */
-#define SDIO_SLC1_RX_FILL_EN    (BIT(20))
-#define SDIO_SLC1_RX_FILL_EN_M  (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S)
-#define SDIO_SLC1_RX_FILL_EN_V  0x00000001U
-#define SDIO_SLC1_RX_FILL_EN_S  20
-/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128;
- *  reserved
- */
-#define SDIO_SLC1_RD_RETRY_THRESHOLD    0x000007FFU
-#define SDIO_SLC1_RD_RETRY_THRESHOLD_M  (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S)
-#define SDIO_SLC1_RD_RETRY_THRESHOLD_V  0x000007FFU
-#define SDIO_SLC1_RD_RETRY_THRESHOLD_S  21
-
-/** SDIO_SLC0_TXLINK_DSCR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_TXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xac)
-/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_DSCR    0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_M  (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S)
-#define SDIO_SLC0_TXLINK_DSCR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_S  0
-
-/** SDIO_SLC0_TXLINK_DSCR_BF0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xb0)
-/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_DSCR_BF0    0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_BF0_M  (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S)
-#define SDIO_SLC0_TXLINK_DSCR_BF0_V  0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_BF0_S  0
-
-/** SDIO_SLC0_TXLINK_DSCR_BF1_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xb4)
-/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TXLINK_DSCR_BF1    0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_BF1_M  (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S)
-#define SDIO_SLC0_TXLINK_DSCR_BF1_V  0xFFFFFFFFU
-#define SDIO_SLC0_TXLINK_DSCR_BF1_S  0
-
-/** SDIO_SLC0_RXLINK_DSCR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_RXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xb8)
-/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- *  the third word of slc0 link descriptor, or known as the next descriptor address
- */
-#define SDIO_SLC0_RXLINK_DSCR    0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_M  (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S)
-#define SDIO_SLC0_RXLINK_DSCR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_S  0
-
-/** SDIO_SLC0_RXLINK_DSCR_BF0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xbc)
-/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_DSCR_BF0    0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_BF0_M  (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S)
-#define SDIO_SLC0_RXLINK_DSCR_BF0_V  0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_BF0_S  0
-
-/** SDIO_SLC0_RXLINK_DSCR_BF1_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xc0)
-/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RXLINK_DSCR_BF1    0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_BF1_M  (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S)
-#define SDIO_SLC0_RXLINK_DSCR_BF1_V  0xFFFFFFFFU
-#define SDIO_SLC0_RXLINK_DSCR_BF1_S  0
-
-/** SDIO_SLC1_TXLINK_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xc4)
-/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR    0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_M  (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S)
-#define SDIO_SLC1_TXLINK_DSCR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_S  0
-
-/** SDIO_SLC1_TXLINK_DSCR_BF0_REG register
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xc8)
-/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_BF0    0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_BF0_M  (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S)
-#define SDIO_SLC1_TXLINK_DSCR_BF0_V  0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_BF0_S  0
-
-/** SDIO_SLC1_TXLINK_DSCR_BF1_REG register
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xcc)
-/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TXLINK_DSCR_BF1    0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_BF1_M  (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S)
-#define SDIO_SLC1_TXLINK_DSCR_BF1_V  0xFFFFFFFFU
-#define SDIO_SLC1_TXLINK_DSCR_BF1_S  0
-
-/** SDIO_SLC1_RXLINK_DSCR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1_RXLINK_DSCR_REG (DR_REG_SDIO_BASE + 0xd0)
-/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0;
- *  the third word of slc1 link descriptor, or known as the next descriptor address
- */
-#define SDIO_SLC1_RXLINK_DSCR    0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_M  (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S)
-#define SDIO_SLC1_RXLINK_DSCR_V  0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_S  0
-
-/** SDIO_SLC1_RXLINK_DSCR_BF0_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SDIO_BASE + 0xd4)
-/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_DSCR_BF0    0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_BF0_M  (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S)
-#define SDIO_SLC1_RXLINK_DSCR_BF0_V  0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_BF0_S  0
-
-/** SDIO_SLC1_RXLINK_DSCR_BF1_REG register
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SDIO_BASE + 0xd8)
-/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RXLINK_DSCR_BF1    0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_BF1_M  (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S)
-#define SDIO_SLC1_RXLINK_DSCR_BF1_V  0xFFFFFFFFU
-#define SDIO_SLC1_RXLINK_DSCR_BF1_S  0
-
-/** SDIO_SLC0_TX_ERREOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0xdc)
-/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M  (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S)
-#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC1_TX_ERREOF_DES_ADDR_REG register
- *  reserved
- */
-#define SDIO_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SDIO_BASE + 0xe0)
-/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M  (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S)
-#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S  0
-
-/** SDIO_SLC_TOKEN_LAT_REG register
- *  reserved
- */
-#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SDIO_BASE + 0xe4)
-/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN    0x00000FFFU
-#define SDIO_SLC0_TOKEN_M  (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S)
-#define SDIO_SLC0_TOKEN_V  0x00000FFFU
-#define SDIO_SLC0_TOKEN_S  0
-/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN    0x00000FFFU
-#define SDIO_SLC1_TOKEN_M  (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S)
-#define SDIO_SLC1_TOKEN_V  0x00000FFFU
-#define SDIO_SLC1_TOKEN_S  16
-
-/** SDIO_SLC_TX_DSCR_CONF_REG register
- *  reserved
- */
-#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SDIO_BASE + 0xe8)
-/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128;
- *  reserved
- */
-#define SDIO_SLC_WR_RETRY_THRESHOLD    0x000007FFU
-#define SDIO_SLC_WR_RETRY_THRESHOLD_M  (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S)
-#define SDIO_SLC_WR_RETRY_THRESHOLD_V  0x000007FFU
-#define SDIO_SLC_WR_RETRY_THRESHOLD_S  0
-
-/** SDIO_SLC_CMD_INFOR0_REG register
- *  reserved
- */
-#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SDIO_BASE + 0xec)
-/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_CONTENT0    0xFFFFFFFFU
-#define SDIO_CMD_CONTENT0_M  (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S)
-#define SDIO_CMD_CONTENT0_V  0xFFFFFFFFU
-#define SDIO_CMD_CONTENT0_S  0
-
-/** SDIO_SLC_CMD_INFOR1_REG register
- *  reserved
- */
-#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SDIO_BASE + 0xf0)
-/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_CONTENT1    0xFFFFFFFFU
-#define SDIO_CMD_CONTENT1_M  (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S)
-#define SDIO_CMD_CONTENT1_V  0xFFFFFFFFU
-#define SDIO_CMD_CONTENT1_S  0
-
-/** SDIO_SLC0_LEN_CONF_REG register
- *  reserved
- */
-#define SDIO_SLC0_LEN_CONF_REG (DR_REG_SDIO_BASE + 0xf4)
-/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN_WDATA    0x000FFFFFU
-#define SDIO_SLC0_LEN_WDATA_M  (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S)
-#define SDIO_SLC0_LEN_WDATA_V  0x000FFFFFU
-#define SDIO_SLC0_LEN_WDATA_S  0
-/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN_WR    (BIT(20))
-#define SDIO_SLC0_LEN_WR_M  (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S)
-#define SDIO_SLC0_LEN_WR_V  0x00000001U
-#define SDIO_SLC0_LEN_WR_S  20
-/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN_INC    (BIT(21))
-#define SDIO_SLC0_LEN_INC_M  (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S)
-#define SDIO_SLC0_LEN_INC_V  0x00000001U
-#define SDIO_SLC0_LEN_INC_S  21
-/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN_INC_MORE    (BIT(22))
-#define SDIO_SLC0_LEN_INC_MORE_M  (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S)
-#define SDIO_SLC0_LEN_INC_MORE_V  0x00000001U
-#define SDIO_SLC0_LEN_INC_MORE_S  22
-/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PACKET_LOAD_EN    (BIT(23))
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_M  (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S)
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_V  0x00000001U
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_S  23
-/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PACKET_LOAD_EN    (BIT(24))
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_M  (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S)
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_V  0x00000001U
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_S  24
-/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_GET_USED_DSCR    (BIT(25))
-#define SDIO_SLC0_RX_GET_USED_DSCR_M  (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S)
-#define SDIO_SLC0_RX_GET_USED_DSCR_V  0x00000001U
-#define SDIO_SLC0_RX_GET_USED_DSCR_S  25
-/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_GET_USED_DSCR    (BIT(26))
-#define SDIO_SLC0_TX_GET_USED_DSCR_M  (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S)
-#define SDIO_SLC0_TX_GET_USED_DSCR_V  0x00000001U
-#define SDIO_SLC0_TX_GET_USED_DSCR_S  26
-/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_NEW_PKT_IND    (BIT(27))
-#define SDIO_SLC0_RX_NEW_PKT_IND_M  (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S)
-#define SDIO_SLC0_RX_NEW_PKT_IND_V  0x00000001U
-#define SDIO_SLC0_RX_NEW_PKT_IND_S  27
-/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1;
- *  reserved
- */
-#define SDIO_SLC0_TX_NEW_PKT_IND    (BIT(28))
-#define SDIO_SLC0_TX_NEW_PKT_IND_M  (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S)
-#define SDIO_SLC0_TX_NEW_PKT_IND_V  0x00000001U
-#define SDIO_SLC0_TX_NEW_PKT_IND_S  28
-/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST    (BIT(29))
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M  (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S)
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V  0x00000001U
-#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S  29
-/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST    (BIT(30))
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M  (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S)
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V  0x00000001U
-#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S  30
-
-/** SDIO_SLC0_LENGTH_REG register
- *  reserved
- */
-#define SDIO_SLC0_LENGTH_REG (DR_REG_SDIO_BASE + 0xf8)
-/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_LEN    0x000FFFFFU
-#define SDIO_SLC0_LEN_M  (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S)
-#define SDIO_SLC0_LEN_V  0x000FFFFFU
-#define SDIO_SLC0_LEN_S  0
-
-/** SDIO_SLC0_TXPKT_H_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXPKT_H_DSCR_REG (DR_REG_SDIO_BASE + 0xfc)
-/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S)
-#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_TXPKT_E_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXPKT_E_DSCR_REG (DR_REG_SDIO_BASE + 0x100)
-/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S)
-#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_RXPKT_H_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXPKT_H_DSCR_REG (DR_REG_SDIO_BASE + 0x104)
-/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_RXPKT_E_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXPKT_E_DSCR_REG (DR_REG_SDIO_BASE + 0x108)
-/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_TXPKTU_H_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SDIO_BASE + 0x10c)
-/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S)
-#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_TXPKTU_E_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SDIO_BASE + 0x110)
-/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M  (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S)
-#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_RXPKTU_H_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SDIO_BASE + 0x114)
-/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_RXPKTU_E_DSCR_REG register
- *  reserved
- */
-#define SDIO_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SDIO_BASE + 0x118)
-/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M  (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S  0
-
-/** SDIO_SLC_SEQ_POSITION_REG register
- *  reserved
- */
-#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SDIO_BASE + 0x11c)
-/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9;
- *  reserved
- */
-#define SDIO_SLC0_SEQ_POSITION    0x000000FFU
-#define SDIO_SLC0_SEQ_POSITION_M  (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S)
-#define SDIO_SLC0_SEQ_POSITION_V  0x000000FFU
-#define SDIO_SLC0_SEQ_POSITION_S  0
-/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5;
- *  reserved
- */
-#define SDIO_SLC1_SEQ_POSITION    0x000000FFU
-#define SDIO_SLC1_SEQ_POSITION_M  (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S)
-#define SDIO_SLC1_SEQ_POSITION_V  0x000000FFU
-#define SDIO_SLC1_SEQ_POSITION_S  8
-
-/** SDIO_SLC0_DSCR_REC_CONF_REG register
- *  reserved
- */
-#define SDIO_SLC0_DSCR_REC_CONF_REG (DR_REG_SDIO_BASE + 0x120)
-/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_REC_LIM    0x000003FFU
-#define SDIO_SLC0_RX_DSCR_REC_LIM_M  (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S)
-#define SDIO_SLC0_RX_DSCR_REC_LIM_V  0x000003FFU
-#define SDIO_SLC0_RX_DSCR_REC_LIM_S  0
-
-/** SDIO_SLC_SDIO_CRC_ST0_REG register
- *  reserved
- */
-#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SDIO_BASE + 0x124)
-/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define SDIO_DAT0_CRC_ERR_CNT    0x000000FFU
-#define SDIO_DAT0_CRC_ERR_CNT_M  (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S)
-#define SDIO_DAT0_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_DAT0_CRC_ERR_CNT_S  0
-/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0;
- *  reserved
- */
-#define SDIO_DAT1_CRC_ERR_CNT    0x000000FFU
-#define SDIO_DAT1_CRC_ERR_CNT_M  (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S)
-#define SDIO_DAT1_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_DAT1_CRC_ERR_CNT_S  8
-/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0;
- *  reserved
- */
-#define SDIO_DAT2_CRC_ERR_CNT    0x000000FFU
-#define SDIO_DAT2_CRC_ERR_CNT_M  (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S)
-#define SDIO_DAT2_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_DAT2_CRC_ERR_CNT_S  16
-/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define SDIO_DAT3_CRC_ERR_CNT    0x000000FFU
-#define SDIO_DAT3_CRC_ERR_CNT_M  (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S)
-#define SDIO_DAT3_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_DAT3_CRC_ERR_CNT_S  24
-
-/** SDIO_SLC_SDIO_CRC_ST1_REG register
- *  reserved
- */
-#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SDIO_BASE + 0x128)
-/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_CRC_ERR_CNT    0x000000FFU
-#define SDIO_CMD_CRC_ERR_CNT_M  (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S)
-#define SDIO_CMD_CRC_ERR_CNT_V  0x000000FFU
-#define SDIO_CMD_CRC_ERR_CNT_S  0
-/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0;
- *  reserved
- */
-#define SDIO_ERR_CNT_CLR    (BIT(31))
-#define SDIO_ERR_CNT_CLR_M  (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S)
-#define SDIO_ERR_CNT_CLR_V  0x00000001U
-#define SDIO_ERR_CNT_CLR_S  31
-
-/** SDIO_SLC0_EOF_START_DES_REG register
- *  reserved
- */
-#define SDIO_SLC0_EOF_START_DES_REG (DR_REG_SDIO_BASE + 0x12c)
-/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_EOF_START_DES_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_EOF_START_DES_ADDR_M  (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S)
-#define SDIO_SLC0_EOF_START_DES_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_EOF_START_DES_ADDR_S  0
-
-/** SDIO_SLC0_PUSH_DSCR_ADDR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SDIO_BASE + 0x130)
-/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
- */
-#define SDIO_SLC0_RX_PUSH_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M  (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_DONE_DSCR_ADDR_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SDIO_BASE + 0x134)
-/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  the current descriptor address when slc0 finishes reading data from one buffer,
- *  aligned with word
- */
-#define SDIO_SLC0_RX_DONE_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M  (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S)
-#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_SUB_START_DES_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_SUB_START_DES_REG (DR_REG_SDIO_BASE + 0x138)
-/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0;
- *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
- */
-#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR    0xFFFFFFFFU
-#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M  (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S)
-#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V  0xFFFFFFFFU
-#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S  0
-
-/** SDIO_SLC0_DSCR_CNT_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_DSCR_CNT_REG (DR_REG_SDIO_BASE + 0x13c)
-/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0;
- *  the number of descriptors got by slc0 when it tries to read data from memory
- */
-#define SDIO_SLC0_RX_DSCR_CNT_LAT    0x000003FFU
-#define SDIO_SLC0_RX_DSCR_CNT_LAT_M  (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S)
-#define SDIO_SLC0_RX_DSCR_CNT_LAT_V  0x000003FFU
-#define SDIO_SLC0_RX_DSCR_CNT_LAT_S  0
-/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_GET_EOF_OCC    (BIT(16))
-#define SDIO_SLC0_RX_GET_EOF_OCC_M  (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S)
-#define SDIO_SLC0_RX_GET_EOF_OCC_V  0x00000001U
-#define SDIO_SLC0_RX_GET_EOF_OCC_S  16
-
-/** SDIO_SLC0_LEN_LIM_CONF_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLC0_LEN_LIM_CONF_REG (DR_REG_SDIO_BASE + 0x140)
-/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504;
- *  reserved
- */
-#define SDIO_SLC0_LEN_LIM    0x000FFFFFU
-#define SDIO_SLC0_LEN_LIM_M  (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S)
-#define SDIO_SLC0_LEN_LIM_V  0x000FFFFFU
-#define SDIO_SLC0_LEN_LIM_S  0
-
-/** SDIO_SLC0INT_ST1_REG register
- *  reserved
- */
-#define SDIO_SLC0INT_ST1_REG (DR_REG_SDIO_BASE + 0x144)
-/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_ST1    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M  (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_ST1    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M  (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_ST1    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M  (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_ST1    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M  (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_ST1    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M  (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_ST1    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M  (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_ST1    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M  (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_ST1    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M  (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S  7
-/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_ST1    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_ST1_M  (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S)
-#define SDIO_SLC0_RX_START_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_ST1_S  8
-/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_ST1    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_ST1_M  (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S)
-#define SDIO_SLC0_TX_START_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_ST1_S  9
-/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_ST1    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_ST1_M  (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S)
-#define SDIO_SLC0_RX_UDF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_ST1_S  10
-/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_ST1    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_ST1_M  (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S)
-#define SDIO_SLC0_TX_OVF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_ST1_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S  13
-/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_ST1    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_ST1_M  (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S)
-#define SDIO_SLC0_TX_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_ST1_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST1    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M  (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S  15
-/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_ST1    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_ST1_M  (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S)
-#define SDIO_SLC0_RX_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_ST1_S  16
-/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_ST1    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_ST1_M  (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S)
-#define SDIO_SLC0_RX_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_ST1_S  17
-/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_ST1    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_ST1_M  (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S)
-#define SDIO_SLC0_TOHOST_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_ST1_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST1    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M  (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST1    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M  (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S  24
-/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_ST1    (BIT(25))
-#define SDIO_CMD_DTC_INT_ST1_M  (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S)
-#define SDIO_CMD_DTC_INT_ST1_V  0x00000001U
-#define SDIO_CMD_DTC_INT_ST1_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S  27
-/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_ST1    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_ST1_M  (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S)
-#define SDIO_HDA_RECV_DONE_INT_ST1_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_ST1_S  28
-
-/** SDIO_SLC0INT_ENA1_REG register
- *  reserved
- */
-#define SDIO_SLC0INT_ENA1_REG (DR_REG_SDIO_BASE + 0x148)
-/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA1    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S  0
-/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA1    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S  1
-/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA1    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S  2
-/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA1    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S  3
-/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA1    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S  4
-/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA1    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S  5
-/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA1    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S  6
-/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA1    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S  7
-/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_START_INT_ENA1    (BIT(8))
-#define SDIO_SLC0_RX_START_INT_ENA1_M  (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S)
-#define SDIO_SLC0_RX_START_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_START_INT_ENA1_S  8
-/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_START_INT_ENA1    (BIT(9))
-#define SDIO_SLC0_TX_START_INT_ENA1_M  (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S)
-#define SDIO_SLC0_TX_START_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_START_INT_ENA1_S  9
-/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_UDF_INT_ENA1    (BIT(10))
-#define SDIO_SLC0_RX_UDF_INT_ENA1_M  (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S)
-#define SDIO_SLC0_RX_UDF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_UDF_INT_ENA1_S  10
-/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_OVF_INT_ENA1    (BIT(11))
-#define SDIO_SLC0_TX_OVF_INT_ENA1_M  (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S)
-#define SDIO_SLC0_TX_OVF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_OVF_INT_ENA1_S  11
-/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1    (BIT(12))
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M  (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S)
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S  12
-/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1    (BIT(13))
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M  (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S)
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S  13
-/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DONE_INT_ENA1    (BIT(14))
-#define SDIO_SLC0_TX_DONE_INT_ENA1_M  (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S)
-#define SDIO_SLC0_TX_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_DONE_INT_ENA1_S  14
-/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1    (BIT(15))
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M  (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S)
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S  15
-/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DONE_INT_ENA1    (BIT(16))
-#define SDIO_SLC0_RX_DONE_INT_ENA1_M  (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S)
-#define SDIO_SLC0_RX_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_DONE_INT_ENA1_S  16
-/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_EOF_INT_ENA1    (BIT(17))
-#define SDIO_SLC0_RX_EOF_INT_ENA1_M  (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S)
-#define SDIO_SLC0_RX_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_EOF_INT_ENA1_S  17
-/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TOHOST_INT_ENA1    (BIT(18))
-#define SDIO_SLC0_TOHOST_INT_ENA1_M  (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S)
-#define SDIO_SLC0_TOHOST_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TOHOST_INT_ENA1_S  18
-/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1    (BIT(19))
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S)
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S  19
-/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1    (BIT(20))
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S)
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S  20
-/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1    (BIT(21))
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M  (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S)
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S  21
-/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1    (BIT(22))
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M  (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S)
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S  22
-/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1    (BIT(23))
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M  (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S)
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S  23
-/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1    (BIT(24))
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M  (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S)
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S  24
-/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0;
- *  reserved
- */
-#define SDIO_CMD_DTC_INT_ENA1    (BIT(25))
-#define SDIO_CMD_DTC_INT_ENA1_M  (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S)
-#define SDIO_CMD_DTC_INT_ENA1_V  0x00000001U
-#define SDIO_CMD_DTC_INT_ENA1_S  25
-/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1    (BIT(26))
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M  (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S)
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S  26
-/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0;
- *  reserved
- */
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1    (BIT(27))
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M  (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S)
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S  27
-/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0;
- *  reserved
- */
-#define SDIO_HDA_RECV_DONE_INT_ENA1    (BIT(28))
-#define SDIO_HDA_RECV_DONE_INT_ENA1_M  (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S)
-#define SDIO_HDA_RECV_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_HDA_RECV_DONE_INT_ENA1_S  28
-
-/** SDIO_SLC1INT_ST1_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_ST1_REG (DR_REG_SDIO_BASE + 0x14c)
-/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_ST1    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M  (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_ST1    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M  (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_ST1    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M  (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_ST1    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M  (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_ST1    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M  (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_ST1    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M  (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_ST1    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M  (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_ST1    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M  (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S  7
-/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_ST1    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_ST1_M  (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S)
-#define SDIO_SLC1_RX_START_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_ST1_S  8
-/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_ST1    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_ST1_M  (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S)
-#define SDIO_SLC1_TX_START_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_ST1_S  9
-/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_ST1    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_ST1_M  (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S)
-#define SDIO_SLC1_RX_UDF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_ST1_S  10
-/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_ST1    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_ST1_M  (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S)
-#define SDIO_SLC1_TX_OVF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_ST1_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S  13
-/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_ST1    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_ST1_M  (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S)
-#define SDIO_SLC1_TX_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_ST1_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST1    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M  (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S  15
-/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_ST1    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_ST1_M  (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S)
-#define SDIO_SLC1_RX_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_ST1_S  16
-/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_ST1    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_ST1_M  (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S)
-#define SDIO_SLC1_RX_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_ST1_S  17
-/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_ST1    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_ST1_M  (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S)
-#define SDIO_SLC1_TOHOST_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_ST1_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST1    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M  (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST1    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M  (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S  24
-
-/** SDIO_SLC1INT_ENA1_REG register
- *  reserved
- */
-#define SDIO_SLC1INT_ENA1_REG (DR_REG_SDIO_BASE + 0x150)
-/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA1    (BIT(0))
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S  0
-/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA1    (BIT(1))
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S  1
-/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA1    (BIT(2))
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S  2
-/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA1    (BIT(3))
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S  3
-/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA1    (BIT(4))
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S  4
-/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA1    (BIT(5))
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S  5
-/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA1    (BIT(6))
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S  6
-/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA1    (BIT(7))
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M  (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S)
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V  0x00000001U
-#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S  7
-/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_START_INT_ENA1    (BIT(8))
-#define SDIO_SLC1_RX_START_INT_ENA1_M  (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S)
-#define SDIO_SLC1_RX_START_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_START_INT_ENA1_S  8
-/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_START_INT_ENA1    (BIT(9))
-#define SDIO_SLC1_TX_START_INT_ENA1_M  (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S)
-#define SDIO_SLC1_TX_START_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_START_INT_ENA1_S  9
-/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_UDF_INT_ENA1    (BIT(10))
-#define SDIO_SLC1_RX_UDF_INT_ENA1_M  (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S)
-#define SDIO_SLC1_RX_UDF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_UDF_INT_ENA1_S  10
-/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_OVF_INT_ENA1    (BIT(11))
-#define SDIO_SLC1_TX_OVF_INT_ENA1_M  (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S)
-#define SDIO_SLC1_TX_OVF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_OVF_INT_ENA1_S  11
-/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1    (BIT(12))
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M  (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S)
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S  12
-/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1    (BIT(13))
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M  (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S)
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S  13
-/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DONE_INT_ENA1    (BIT(14))
-#define SDIO_SLC1_TX_DONE_INT_ENA1_M  (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S)
-#define SDIO_SLC1_TX_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_DONE_INT_ENA1_S  14
-/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1    (BIT(15))
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M  (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S)
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S  15
-/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DONE_INT_ENA1    (BIT(16))
-#define SDIO_SLC1_RX_DONE_INT_ENA1_M  (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S)
-#define SDIO_SLC1_RX_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_DONE_INT_ENA1_S  16
-/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_EOF_INT_ENA1    (BIT(17))
-#define SDIO_SLC1_RX_EOF_INT_ENA1_M  (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S)
-#define SDIO_SLC1_RX_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_EOF_INT_ENA1_S  17
-/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TOHOST_INT_ENA1    (BIT(18))
-#define SDIO_SLC1_TOHOST_INT_ENA1_M  (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S)
-#define SDIO_SLC1_TOHOST_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TOHOST_INT_ENA1_S  18
-/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1    (BIT(19))
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S)
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S  19
-/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1    (BIT(20))
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M  (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S)
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S  20
-/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1    (BIT(21))
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M  (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S)
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S  21
-/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1    (BIT(22))
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M  (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S)
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S  22
-/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1    (BIT(23))
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M  (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S)
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S  23
-/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0;
- *  reserved
- */
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1    (BIT(24))
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M  (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S)
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V  0x00000001U
-#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S  24
-
-/** SDIO_SLC0_TX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_SLC0_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x154)
-/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC0_TX_SHAREMEM_END_REG register
- *  reserved
- */
-#define SDIO_SLC0_TX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x158)
-/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S)
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S  0
-
-/** SDIO_SLC0_RX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_SLC0_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x15c)
-/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC0_RX_SHAREMEM_END_REG register
- *  reserved
- */
-#define SDIO_SLC0_RX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x160)
-/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S)
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S  0
-
-/** SDIO_SLC1_TX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_SLC1_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x164)
-/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC1_TX_SHAREMEM_END_REG register
- *  reserved
- */
-#define SDIO_SLC1_TX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x168)
-/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S)
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S  0
-
-/** SDIO_SLC1_RX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_SLC1_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x16c)
-/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC1_RX_SHAREMEM_END_REG register
- *  reserved
- */
-#define SDIO_SLC1_RX_SHAREMEM_END_REG (DR_REG_SDIO_BASE + 0x170)
-/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M  (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S)
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S  0
-
-/** SDIO_HDA_TX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_HDA_TX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x174)
-/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_HDA_RX_SHAREMEM_START_REG register
- *  reserved
- */
-#define SDIO_HDA_RX_SHAREMEM_START_REG (DR_REG_SDIO_BASE + 0x178)
-/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR    0xFFFFFFFFU
-#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M  (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S)
-#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V  0xFFFFFFFFU
-#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S  0
-
-/** SDIO_SLC_BURST_LEN_REG register
- *  reserved
- */
-#define SDIO_SLC_BURST_LEN_REG (DR_REG_SDIO_BASE + 0x17c)
-/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1;
- *  0-incr4,1-incr8
- */
-#define SDIO_SLC0_TXDATA_BURST_LEN    (BIT(0))
-#define SDIO_SLC0_TXDATA_BURST_LEN_M  (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S)
-#define SDIO_SLC0_TXDATA_BURST_LEN_V  0x00000001U
-#define SDIO_SLC0_TXDATA_BURST_LEN_S  0
-/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1;
- *  0-incr4,1-incr8
- */
-#define SDIO_SLC0_RXDATA_BURST_LEN    (BIT(1))
-#define SDIO_SLC0_RXDATA_BURST_LEN_M  (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S)
-#define SDIO_SLC0_RXDATA_BURST_LEN_V  0x00000001U
-#define SDIO_SLC0_RXDATA_BURST_LEN_S  1
-/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1;
- *  0-incr4,1-incr8
- */
-#define SDIO_SLC1_TXDATA_BURST_LEN    (BIT(2))
-#define SDIO_SLC1_TXDATA_BURST_LEN_M  (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S)
-#define SDIO_SLC1_TXDATA_BURST_LEN_V  0x00000001U
-#define SDIO_SLC1_TXDATA_BURST_LEN_S  2
-/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1;
- *  0-incr4,1-incr8
- */
-#define SDIO_SLC1_RXDATA_BURST_LEN    (BIT(3))
-#define SDIO_SLC1_RXDATA_BURST_LEN_M  (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S)
-#define SDIO_SLC1_RXDATA_BURST_LEN_V  0x00000001U
-#define SDIO_SLC1_RXDATA_BURST_LEN_S  3
-
-/** SDIO_SLCDATE_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCDATE_REG (DR_REG_SDIO_BASE + 0x1f8)
-/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400;
- *  reserved
- */
-#define SDIO_SLC_DATE    0xFFFFFFFFU
-#define SDIO_SLC_DATE_M  (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S)
-#define SDIO_SLC_DATE_V  0xFFFFFFFFU
-#define SDIO_SLC_DATE_S  0
-
-/** SDIO_SLCID_REG register
- *  ******* Description ***********
- */
-#define SDIO_SLCID_REG (DR_REG_SDIO_BASE + 0x1fc)
-/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256;
- *  reserved
- */
-#define SDIO_SLC_ID    0xFFFFFFFFU
-#define SDIO_SLC_ID_M  (SDIO_SLC_ID_V << SDIO_SLC_ID_S)
-#define SDIO_SLC_ID_V  0xFFFFFFFFU
-#define SDIO_SLC_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/sdio_slc_struct.h b/components/soc/esp32c5/include/soc/sdio_slc_struct.h
deleted file mode 100644
index eade8a4ad9..0000000000
--- a/components/soc/esp32c5/include/soc/sdio_slc_struct.h
+++ /dev/null
@@ -1,3253 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration registers */
-/** Type of slcconf0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_tx_rst : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to reset tx fsm in dma slc0.
-         */
-        uint32_t slc0_tx_rst:1;
-        /** slc0_rx_rst : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to reset rx fsm in dma slc0.
-         */
-        uint32_t slc0_rx_rst:1;
-        /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0;
-         *  reset the command fifo of AHB bus of sdio slave
-         */
-        uint32_t slc_ahbm_fifo_rst:1;
-        /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0;
-         *  reset the AHB bus of sdio slave
-         */
-        uint32_t slc_ahbm_rst:1;
-        /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0;
-         *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
-         */
-        uint32_t slc0_tx_loop_test:1;
-        /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0;
-         *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
-         */
-        uint32_t slc0_rx_loop_test:1;
-        /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0;
-         *  Set 1 to enable change the owner bit of rx link descriptor
-         */
-        uint32_t slc0_rx_auto_wrback:1;
-        /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_no_restart_clr:1;
-        /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1;
-         *  0- AHB burst type is single when slave read rx-descriptor from memory through
-         *  slc0,1-AHB burst type is not single when slave read rx-descriptor from memory
-         *  through slc0
-         */
-        uint32_t slc0_rxdscr_burst_en:1;
-        /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1;
-         *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
-         *  is not single when slave receives data from memory
-         */
-        uint32_t slc0_rxdata_burst_en:1;
-        /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1;
-         *  enable the function that when host reading packet retries, slc1 will automatically
-         *  jump to the start descriptor of the previous packet.
-         */
-        uint32_t slc0_rxlink_auto_ret:1;
-        /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1;
-         *  enable the function that when host sending packet retries, slc1 will automatically
-         *  jump to the start descriptor of the previous packet.
-         */
-        uint32_t slc0_txlink_auto_ret:1;
-        /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1;
-         *  0- AHB burst type is single when slave read tx-descriptor from memory through
-         *  slc0,1-AHB burst type is not single when slave read tx-descriptor from memory
-         *  through slc0
-         */
-        uint32_t slc0_txdscr_burst_en:1;
-        /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1;
-         *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
-         *  single when slave send data to memory
-         */
-        uint32_t slc0_txdata_burst_en:1;
-        /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1;
-         *  auto clear slc0_token1 enable
-         */
-        uint32_t slc0_token_auto_clr:1;
-        /** slc0_token_sel : R/W; bitpos: [15]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_token_sel:1;
-        /** slc1_tx_rst : R/W; bitpos: [16]; default: 0;
-         *  Set 1 to reset tx fsm in dma slc0.
-         */
-        uint32_t slc1_tx_rst:1;
-        /** slc1_rx_rst : R/W; bitpos: [17]; default: 0;
-         *  Set 1 to reset rx fsm in dma slc0.
-         */
-        uint32_t slc1_rx_rst:1;
-        /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_mask_en:1;
-        /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_mask_en:1;
-        /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1;
-         *  owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner.
-         */
-        uint32_t slc1_tx_loop_test:1;
-        /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1;
-         *  owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner.
-         */
-        uint32_t slc1_rx_loop_test:1;
-        /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0;
-         *  Set 1 to enable change the owner bit of rx link descriptor
-         */
-        uint32_t slc1_rx_auto_wrback:1;
-        /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0;
-         *  ******* Description ***********
-         */
-        uint32_t slc1_rx_no_restart_clr:1;
-        /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1;
-         *  0- AHB burst type is single when slave read rx-descriptor from memory through
-         *  slc1,1-AHB burst type is not single when slave read rx-descriptor from memory
-         *  through slc1
-         */
-        uint32_t slc1_rxdscr_burst_en:1;
-        /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1;
-         *  0- AHB burst type is single when slave receives data from memory,1-AHB burst type
-         *  is not single when slave receives data from memory
-         */
-        uint32_t slc1_rxdata_burst_en:1;
-        /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1;
-         *  enable the function that when host reading packet retries, slc1 will automatically
-         *  jump to the start descriptor of the previous packet.
-         */
-        uint32_t slc1_rxlink_auto_ret:1;
-        /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1;
-         *  enable the function that when host sending packet retries, slc1 will automatically
-         *  jump to the start descriptor of the previous packet.
-         */
-        uint32_t slc1_txlink_auto_ret:1;
-        /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1;
-         *  0- AHB burst type is single when slave read tx-descriptor from memory through
-         *  slc1,1-AHB burst type is not single when slave read tx-descriptor from memory
-         *  through slc1
-         */
-        uint32_t slc1_txdscr_burst_en:1;
-        /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1;
-         *  0- AHB burst type is single when slave send data to memory,1-AHB burst type is not
-         *  single when slave send data to memory
-         */
-        uint32_t slc1_txdata_burst_en:1;
-        /** slc1_token_auto_clr : R/W; bitpos: [30]; default: 1;
-         *  auto clear slc1_token1 enable
-         */
-        uint32_t slc1_token_auto_clr:1;
-        /** slc1_token_sel : R/W; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_token_sel:1;
-    };
-    uint32_t val;
-} sdio_slcconf0_reg_t;
-
-/** Type of slc0rxfifo_push register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxfifo_wdata:9;
-        uint32_t reserved_9:7;
-        /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxfifo_push:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc0rxfifo_push_reg_t;
-
-/** Type of slc1rxfifo_push register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxfifo_wdata:9;
-        uint32_t reserved_9:7;
-        /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxfifo_push:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc1rxfifo_push_reg_t;
-
-/** Type of slc0rx_link register
- *  reserved
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_stop:1;
-        /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_start:1;
-        /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_restart:1;
-        /** slc0_rxlink_park : RO; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_park:1;
-    };
-    uint32_t val;
-} sdio_slc0rx_link_reg_t;
-
-/** Type of slc0rx_link_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0rx_link_addr_reg_t;
-
-/** Type of slc0tx_link register
- *  reserved
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_stop:1;
-        /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_start:1;
-        /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_restart:1;
-        /** slc0_txlink_park : RO; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_txlink_park:1;
-    };
-    uint32_t val;
-} sdio_slc0tx_link_reg_t;
-
-/** Type of slc0tx_link_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0tx_link_addr_reg_t;
-
-/** Type of slc1rx_link register
- *  reserved
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** slc1_bt_packet : R/W; bitpos: [20]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_bt_packet:1;
-        uint32_t reserved_21:7;
-        /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_stop:1;
-        /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_start:1;
-        /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_restart:1;
-        /** slc1_rxlink_park : RO; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_park:1;
-    };
-    uint32_t val;
-} sdio_slc1rx_link_reg_t;
-
-/** Type of slc1rx_link_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1rx_link_addr_reg_t;
-
-/** Type of slc1tx_link register
- *  reserved
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_stop:1;
-        /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_start:1;
-        /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_restart:1;
-        /** slc1_txlink_park : RO; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_txlink_park:1;
-    };
-    uint32_t val;
-} sdio_slc1tx_link_reg_t;
-
-/** Type of slc1tx_link_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1tx_link_addr_reg_t;
-
-/** Type of slcintvec_tohost register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_intvec:8;
-        uint32_t reserved_8:8;
-        /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_intvec:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} sdio_slcintvec_tohost_reg_t;
-
-/** Type of slc0token0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_wdata:12;
-        /** slc0_token0_wr : WT; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_wr:1;
-        /** slc0_token0_inc : WT; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_inc:1;
-        /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_inc_more:1;
-        uint32_t reserved_15:1;
-        /** slc0_token0 : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc0token0_reg_t;
-
-/** Type of slc0token1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0;
-         *  slc0 token1 wdata
-         */
-        uint32_t slc0_token1_wdata:12;
-        /** slc0_token1_wr : WT; bitpos: [12]; default: 0;
-         *  update slc0_token1_wdata into slc0 token1
-         */
-        uint32_t slc0_token1_wr:1;
-        /** slc0_token1_inc : WT; bitpos: [13]; default: 0;
-         *  slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1
-         */
-        uint32_t slc0_token1_inc:1;
-        /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0;
-         *  slc0_token1 becomes to slc0_token1_wdata when auto clear slc0_token1, else add
-         *  slc0_token1_wdata to slc0_token1
-         */
-        uint32_t slc0_token1_inc_more:1;
-        uint32_t reserved_15:1;
-        /** slc0_token1 : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc0token1_reg_t;
-
-/** Type of slc1token0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_wdata:12;
-        /** slc1_token0_wr : WT; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_wr:1;
-        /** slc1_token0_inc : WT; bitpos: [13]; default: 0;
-         *  Add 1 to  slc1_token0
-         */
-        uint32_t slc1_token0_inc:1;
-        /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0;
-         *  Add  slc1_token0_wdata to  slc1_token0
-         */
-        uint32_t slc1_token0_inc_more:1;
-        uint32_t reserved_15:1;
-        /** slc1_token0 : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc1token0_reg_t;
-
-/** Type of slc1token1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_wdata:12;
-        /** slc1_token1_wr : WT; bitpos: [12]; default: 0;
-         *  update slc1_token1_wdata into slc1 token1
-         */
-        uint32_t slc1_token1_wr:1;
-        /** slc1_token1_inc : WT; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_inc:1;
-        /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_inc_more:1;
-        uint32_t reserved_15:1;
-        /** slc1_token1 : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc1token1_reg_t;
-
-/** Type of slcconf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_check_owner : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_check_owner:1;
-        /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_check_sum_en:1;
-        /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_check_sum_en:1;
-        /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1;
-         *  reserved
-         */
-        uint32_t sdio_cmd_hold_en:1;
-        /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_len_auto_clr:1;
-        /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_tx_stitch_en:1;
-        /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_rx_stitch_en:1;
-        uint32_t reserved_7:9;
-        /** slc1_check_owner : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_check_owner:1;
-        /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_check_sum_en:1;
-        /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_check_sum_en:1;
-        /** host_int_level_sel : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t host_int_level_sel:1;
-        /** slc1_tx_stitch_en : R/W; bitpos: [20]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_tx_stitch_en:1;
-        /** slc1_rx_stitch_en : R/W; bitpos: [21]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_rx_stitch_en:1;
-        /** sdio_clk_en : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} sdio_slcconf1_reg_t;
-
-/** Type of slcbridge_conf register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32;
-         *  reserved
-         */
-        uint32_t slc_txeof_ena:6;
-        uint32_t reserved_6:2;
-        /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7;
-         *  reserved
-         */
-        uint32_t slc_fifo_map_ena:4;
-        /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_tx_dummy_mode:1;
-        /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1;
-         *  reserved
-         */
-        uint32_t slc_hda_map_128k:1;
-        /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_tx_dummy_mode:1;
-        uint32_t reserved_15:1;
-        /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10;
-         *  reserved
-         */
-        uint32_t slc_tx_push_idle_num:16;
-    };
-    uint32_t val;
-} sdio_slcbridge_conf_reg_t;
-
-/** Type of slc0_to_eof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_to_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_to_eof_des_addr_reg_t;
-
-/** Type of slc0_tx_eof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_tx_eof_des_addr_reg_t;
-
-/** Type of slc0_to_eof_bfr_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_to_eof_bfr_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_to_eof_bfr_des_addr_reg_t;
-
-/** Type of slc1_to_eof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_to_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_to_eof_des_addr_reg_t;
-
-/** Type of slc1_tx_eof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_tx_eof_des_addr_reg_t;
-
-/** Type of slc1_to_eof_bfr_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_to_eof_bfr_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_to_eof_bfr_des_addr_reg_t;
-
-/** Type of slc_rx_dscr_conf register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token_no_replace:1;
-        /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_infor_no_replace:1;
-        /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0;
-         *  slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next
-         *  pop doesn't occur after 255 cycles since the current pop
-         */
-        uint32_t slc0_rx_fill_mode:1;
-        /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1;
-         *  0-slc0 rx_push_eof, 1-slc0 rx_pop_eof
-         */
-        uint32_t slc0_rx_eof_mode:1;
-        /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_rx_fill_en:1;
-        /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128;
-         *  reserved
-         */
-        uint32_t slc0_rd_retry_threshold:11;
-        /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_token_no_replace:1;
-        /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_infor_no_replace:1;
-        /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0;
-         *  slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next
-         *  pop doesn't occur after 255 cycles since the current pop
-         */
-        uint32_t slc1_rx_fill_mode:1;
-        /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1;
-         *  0-slc1 rx_push_eof, 1-slc1 rx_pop_eof
-         */
-        uint32_t slc1_rx_eof_mode:1;
-        /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_rx_fill_en:1;
-        /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128;
-         *  reserved
-         */
-        uint32_t slc1_rd_retry_threshold:11;
-    };
-    uint32_t val;
-} sdio_slc_rx_dscr_conf_reg_t;
-
-/** Type of slc_tx_dscr_conf register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128;
-         *  reserved
-         */
-        uint32_t slc_wr_retry_threshold:11;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} sdio_slc_tx_dscr_conf_reg_t;
-
-/** Type of slc0_len_conf register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len_wdata:20;
-        /** slc0_len_wr : WT; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len_wr:1;
-        /** slc0_len_inc : WT; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len_inc:1;
-        /** slc0_len_inc_more : WT; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len_inc_more:1;
-        /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_packet_load_en:1;
-        /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_packet_load_en:1;
-        /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_get_used_dscr:1;
-        /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_get_used_dscr:1;
-        /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_new_pkt_ind:1;
-        /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_tx_new_pkt_ind:1;
-        /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_packet_load_en_st:1;
-        /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_packet_load_en_st:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} sdio_slc0_len_conf_reg_t;
-
-/** Type of slc0_txpkt_h_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_pkt_h_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txpkt_h_dscr_reg_t;
-
-/** Type of slc0_txpkt_e_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_pkt_e_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txpkt_e_dscr_reg_t;
-
-/** Type of slc0_rxpkt_h_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_pkt_h_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxpkt_h_dscr_reg_t;
-
-/** Type of slc0_rxpkt_e_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_pkt_e_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxpkt_e_dscr_reg_t;
-
-/** Type of slc0_txpktu_h_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_pkt_start_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txpktu_h_dscr_reg_t;
-
-/** Type of slc0_txpktu_e_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_pkt_end_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txpktu_e_dscr_reg_t;
-
-/** Type of slc0_rxpktu_h_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_pkt_start_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxpktu_h_dscr_reg_t;
-
-/** Type of slc0_rxpktu_e_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_pkt_end_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxpktu_e_dscr_reg_t;
-
-/** Type of slc_seq_position register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9;
-         *  reserved
-         */
-        uint32_t slc0_seq_position:8;
-        /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5;
-         *  reserved
-         */
-        uint32_t slc1_seq_position:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} sdio_slc_seq_position_reg_t;
-
-/** Type of slc0_dscr_rec_conf register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_rec_lim:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} sdio_slc0_dscr_rec_conf_reg_t;
-
-/** Type of slc_sdio_crc_st1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_crc_err_cnt:8;
-        uint32_t reserved_8:23;
-        /** err_cnt_clr : R/W; bitpos: [31]; default: 0;
-         *  reserved
-         */
-        uint32_t err_cnt_clr:1;
-    };
-    uint32_t val;
-} sdio_slc_sdio_crc_st1_reg_t;
-
-/** Type of slc0_len_lim_conf register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504;
-         *  reserved
-         */
-        uint32_t slc0_len_lim:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} sdio_slc0_len_lim_conf_reg_t;
-
-/** Type of slc0_tx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_slc0_tx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_tx_sharemem_start_reg_t;
-
-/** Type of slc0_tx_sharemem_end register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t sdio_slc0_tx_sharemem_end_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_tx_sharemem_end_reg_t;
-
-/** Type of slc0_rx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_slc0_rx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rx_sharemem_start_reg_t;
-
-/** Type of slc0_rx_sharemem_end register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t sdio_slc0_rx_sharemem_end_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rx_sharemem_end_reg_t;
-
-/** Type of slc1_tx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_slc1_tx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_tx_sharemem_start_reg_t;
-
-/** Type of slc1_tx_sharemem_end register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t sdio_slc1_tx_sharemem_end_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_tx_sharemem_end_reg_t;
-
-/** Type of slc1_rx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_slc1_rx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_rx_sharemem_start_reg_t;
-
-/** Type of slc1_rx_sharemem_end register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t sdio_slc1_rx_sharemem_end_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_rx_sharemem_end_reg_t;
-
-/** Type of hda_tx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_hda_tx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_hda_tx_sharemem_start_reg_t;
-
-/** Type of hda_rx_sharemem_start register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_hda_rx_sharemem_start_addr:32;
-    };
-    uint32_t val;
-} sdio_hda_rx_sharemem_start_reg_t;
-
-/** Type of slc_burst_len register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1;
-         *  0-incr4,1-incr8
-         */
-        uint32_t slc0_txdata_burst_len:1;
-        /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1;
-         *  0-incr4,1-incr8
-         */
-        uint32_t slc0_rxdata_burst_len:1;
-        /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1;
-         *  0-incr4,1-incr8
-         */
-        uint32_t slc1_txdata_burst_len:1;
-        /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1;
-         *  0-incr4,1-incr8
-         */
-        uint32_t slc1_rxdata_burst_len:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} sdio_slc_burst_len_reg_t;
-
-/** Type of slcid register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_id : R/W; bitpos: [31:0]; default: 256;
-         *  reserved
-         */
-        uint32_t slc_id:32;
-    };
-    uint32_t val;
-} sdio_slcid_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of slc0int_raw register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_raw:1;
-        /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_raw:1;
-        /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_raw:1;
-        /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_raw:1;
-        /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_raw:1;
-        /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_raw:1;
-        /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_raw:1;
-        /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_raw:1;
-        /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_raw:1;
-        /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_raw:1;
-        /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_raw:1;
-        /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_raw:1;
-        /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_raw:1;
-        /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_raw:1;
-        /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw interrupt bit of slc0 finishing receiving data to one buffer
-         */
-        uint32_t slc0_tx_done_int_raw:1;
-        /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw interrupt bit of slc0 finishing receiving data
-         */
-        uint32_t slc0_tx_suc_eof_int_raw:1;
-        /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw interrupt bit of slc0 finishing sending data from one buffer
-         */
-        uint32_t slc0_rx_done_int_raw:1;
-        /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw interrupt bit of slc0 finishing sending data
-         */
-        uint32_t slc0_rx_eof_int_raw:1;
-        /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_raw:1;
-        /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw interrupt bit of slc0 tx link descriptor error
-         */
-        uint32_t slc0_tx_dscr_err_int_raw:1;
-        /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw interrupt bit of slc0 rx link descriptor error
-         */
-        uint32_t slc0_rx_dscr_err_int_raw:1;
-        /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_raw:1;
-        /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_raw:1;
-        /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_raw:1;
-        /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_raw:1;
-        /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_raw:1;
-        /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_raw:1;
-        /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_raw:1;
-        /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_raw:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_raw_reg_t;
-
-/** Type of slc0int_st register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_st:1;
-        /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_st:1;
-        /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_st:1;
-        /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_st:1;
-        /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_st:1;
-        /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_st:1;
-        /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_st:1;
-        /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_st:1;
-        /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_st:1;
-        /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_st:1;
-        /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_st:1;
-        /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_st:1;
-        /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_st:1;
-        /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_st:1;
-        /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_st:1;
-        /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_st:1;
-        /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_st:1;
-        /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_st:1;
-        /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_st:1;
-        /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_st:1;
-        /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_st:1;
-        /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_st:1;
-        /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_st:1;
-        /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_st:1;
-        /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_st:1;
-        /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_st:1;
-        /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_st:1;
-        /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_st:1;
-        /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_st:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_st_reg_t;
-
-/** Type of slc0int_ena register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_ena:1;
-        /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_ena:1;
-        /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_ena:1;
-        /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_ena:1;
-        /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_ena:1;
-        /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_ena:1;
-        /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_ena:1;
-        /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_ena:1;
-        /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_ena:1;
-        /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_ena:1;
-        /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_ena:1;
-        /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_ena:1;
-        /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_ena:1;
-        /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_ena:1;
-        /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_ena:1;
-        /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_ena:1;
-        /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_ena:1;
-        /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_ena:1;
-        /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_ena:1;
-        /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_ena:1;
-        /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_ena:1;
-        /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_ena:1;
-        /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_ena:1;
-        /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_ena:1;
-        /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_ena:1;
-        /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_ena:1;
-        /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_ena:1;
-        /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_ena:1;
-        /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_ena:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_ena_reg_t;
-
-/** Type of slc0int_clr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_clr:1;
-        /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_clr:1;
-        /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_clr:1;
-        /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_clr:1;
-        /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_clr:1;
-        /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_clr:1;
-        /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_clr:1;
-        /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_clr:1;
-        /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_clr:1;
-        /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_clr:1;
-        /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_clr:1;
-        /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_clr:1;
-        /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_clr:1;
-        /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_clr:1;
-        /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_clr:1;
-        /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_clr:1;
-        /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_clr:1;
-        /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_clr:1;
-        /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_clr:1;
-        /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_clr:1;
-        /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_clr:1;
-        /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_clr:1;
-        /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_clr:1;
-        /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_clr:1;
-        /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_clr:1;
-        /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_clr:1;
-        /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_clr:1;
-        /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_clr:1;
-        /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_clr:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_clr_reg_t;
-
-/** Type of slc1int_raw register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_raw:1;
-        /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_raw:1;
-        /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_raw:1;
-        /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_raw:1;
-        /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_raw:1;
-        /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_raw:1;
-        /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_raw:1;
-        /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_raw:1;
-        /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_raw:1;
-        /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_raw:1;
-        /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_raw:1;
-        /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_raw:1;
-        /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_raw:1;
-        /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_raw:1;
-        /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_raw:1;
-        /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_raw:1;
-        /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_raw:1;
-        /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_raw:1;
-        /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_raw:1;
-        /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_raw:1;
-        /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_raw:1;
-        /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_raw:1;
-        /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_raw:1;
-        /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_raw:1;
-        /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_raw:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_raw_reg_t;
-
-/** Type of slc1int_st register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_st:1;
-        /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_st:1;
-        /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_st:1;
-        /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_st:1;
-        /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_st:1;
-        /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_st:1;
-        /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_st:1;
-        /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_st:1;
-        /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_st:1;
-        /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_st:1;
-        /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_st:1;
-        /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_st:1;
-        /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_st:1;
-        /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_st:1;
-        /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_st:1;
-        /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_st:1;
-        /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_st:1;
-        /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_st:1;
-        /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_st:1;
-        /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_st:1;
-        /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_st:1;
-        /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_st:1;
-        /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_st:1;
-        /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_st:1;
-        /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_st:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_st_reg_t;
-
-/** Type of slc1int_ena register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_ena:1;
-        /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_ena:1;
-        /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_ena:1;
-        /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_ena:1;
-        /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_ena:1;
-        /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_ena:1;
-        /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_ena:1;
-        /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_ena:1;
-        /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_ena:1;
-        /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_ena:1;
-        /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_ena:1;
-        /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_ena:1;
-        /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_ena:1;
-        /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_ena:1;
-        /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_ena:1;
-        /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_ena:1;
-        /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_ena:1;
-        /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_ena:1;
-        /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_ena:1;
-        /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_ena:1;
-        /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_ena:1;
-        /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_ena:1;
-        /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_ena:1;
-        /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_ena:1;
-        /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_ena:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_ena_reg_t;
-
-/** Type of slc1int_clr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_clr:1;
-        /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_clr:1;
-        /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_clr:1;
-        /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_clr:1;
-        /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_clr:1;
-        /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_clr:1;
-        /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_clr:1;
-        /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_clr:1;
-        /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_clr:1;
-        /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_clr:1;
-        /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_clr:1;
-        /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_clr:1;
-        /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_clr:1;
-        /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_clr:1;
-        /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_clr:1;
-        /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_clr:1;
-        /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_clr:1;
-        /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_clr:1;
-        /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_clr:1;
-        /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_clr:1;
-        /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_clr:1;
-        /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_clr:1;
-        /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_clr:1;
-        /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_clr:1;
-        /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_clr:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_clr_reg_t;
-
-/** Type of slc0int_st1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_st1:1;
-        /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_st1:1;
-        /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_st1:1;
-        /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_st1:1;
-        /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_st1:1;
-        /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_st1:1;
-        /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_st1:1;
-        /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_st1:1;
-        /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_st1:1;
-        /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_st1:1;
-        /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_st1:1;
-        /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_st1:1;
-        /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_st1:1;
-        /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_st1:1;
-        /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_st1:1;
-        /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_st1:1;
-        /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_st1:1;
-        /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_st1:1;
-        /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_st1:1;
-        /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_st1:1;
-        /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_st1:1;
-        /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_st1:1;
-        /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_st1:1;
-        /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_st1:1;
-        /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_st1:1;
-        /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_st1:1;
-        /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_st1:1;
-        /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_st1:1;
-        /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_st1:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_st1_reg_t;
-
-/** Type of slc0int_ena1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit0_int_ena1:1;
-        /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit1_int_ena1:1;
-        /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit2_int_ena1:1;
-        /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit3_int_ena1:1;
-        /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit4_int_ena1:1;
-        /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit5_int_ena1:1;
-        /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit6_int_ena1:1;
-        /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit7_int_ena1:1;
-        /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_start_int_ena1:1;
-        /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_start_int_ena1:1;
-        /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_udf_int_ena1:1;
-        /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_ovf_int_ena1:1;
-        /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token0_1to0_int_ena1:1;
-        /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token1_1to0_int_ena1:1;
-        /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_done_int_ena1:1;
-        /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_suc_eof_int_ena1:1;
-        /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_done_int_ena1:1;
-        /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_eof_int_ena1:1;
-        /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tohost_int_ena1:1;
-        /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_err_int_ena1:1;
-        /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_dscr_err_int_ena1:1;
-        /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_dscr_empty_int_ena1:1;
-        /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_rd_ack_int_ena1:1;
-        /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_wr_retry_done_int_ena1:1;
-        /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_int_ena1:1;
-        /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_dtc_int_ena1:1;
-        /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_quick_eof_int_ena1:1;
-        /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_host_pop_eof_err_int_ena1:1;
-        /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0;
-         *  reserved
-         */
-        uint32_t hda_recv_done_int_ena1:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc0int_ena1_reg_t;
-
-/** Type of slc1int_st1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_st1:1;
-        /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_st1:1;
-        /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_st1:1;
-        /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_st1:1;
-        /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_st1:1;
-        /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_st1:1;
-        /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_st1:1;
-        /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_st1:1;
-        /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_st1:1;
-        /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_st1:1;
-        /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_st1:1;
-        /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_st1:1;
-        /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_st1:1;
-        /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_st1:1;
-        /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_st1:1;
-        /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_st1:1;
-        /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_st1:1;
-        /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_st1:1;
-        /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_st1:1;
-        /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_st1:1;
-        /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_st1:1;
-        /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_st1:1;
-        /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_st1:1;
-        /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_st1:1;
-        /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_st1:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_st1_reg_t;
-
-/** Type of slc1int_ena1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit8_int_ena1:1;
-        /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit9_int_ena1:1;
-        /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit10_int_ena1:1;
-        /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit11_int_ena1:1;
-        /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit12_int_ena1:1;
-        /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit13_int_ena1:1;
-        /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit14_int_ena1:1;
-        /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_frhost_bit15_int_ena1:1;
-        /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_start_int_ena1:1;
-        /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_start_int_ena1:1;
-        /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_udf_int_ena1:1;
-        /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_ovf_int_ena1:1;
-        /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token0_1to0_int_ena1:1;
-        /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token1_1to0_int_ena1:1;
-        /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_done_int_ena1:1;
-        /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_suc_eof_int_ena1:1;
-        /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_done_int_ena1:1;
-        /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_eof_int_ena1:1;
-        /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tohost_int_ena1:1;
-        /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_err_int_ena1:1;
-        /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_dscr_err_int_ena1:1;
-        /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_dscr_empty_int_ena1:1;
-        /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_host_rd_ack_int_ena1:1;
-        /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_wr_retry_done_int_ena1:1;
-        /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_int_ena1:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} sdio_slc1int_ena1_reg_t;
-
-
-/** Group: Status registers */
-/** Type of slcrx_status register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rx_full : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_full:1;
-        /** slc0_rx_empty : RO; bitpos: [1]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_rx_empty:1;
-        /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0;
-         *  the current buffer length when slc0 reads data from rx link
-         */
-        uint32_t slc0_rx_buf_len:14;
-        /** slc1_rx_full : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rx_full:1;
-        /** slc1_rx_empty : RO; bitpos: [17]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_rx_empty:1;
-        /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0;
-         *  the current buffer length when slc1 reads data from rx link
-         */
-        uint32_t slc1_rx_buf_len:14;
-    };
-    uint32_t val;
-} sdio_slcrx_status_reg_t;
-
-/** Type of slctx_status register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_tx_full : RO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_full:1;
-        /** slc0_tx_empty : RO; bitpos: [1]; default: 1;
-         *  reserved
-         */
-        uint32_t slc0_tx_empty:1;
-        uint32_t reserved_2:14;
-        /** slc1_tx_full : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_full:1;
-        /** slc1_tx_empty : RO; bitpos: [17]; default: 1;
-         *  reserved
-         */
-        uint32_t slc1_tx_empty:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} sdio_slctx_status_reg_t;
-
-/** Type of slc0_state0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_state0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_state0:32;
-    };
-    uint32_t val;
-} sdio_slc0_state0_reg_t;
-
-/** Type of slc0_state1 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_state1 : RO; bitpos: [31:0]; default: 0;
-         *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
-         *  rx_link fsm state, [30:24] rx_fifo_cnt
-         */
-        uint32_t slc0_state1:32;
-    };
-    uint32_t val;
-} sdio_slc0_state1_reg_t;
-
-/** Type of slc1_state0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_state0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_state0:32;
-    };
-    uint32_t val;
-} sdio_slc1_state0_reg_t;
-
-/** Type of slc1_state1 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_state1 : RO; bitpos: [31:0]; default: 0;
-         *  [18:0] the current rx descriptor address, [20:19] rx_dscr fsm state, [23:21]
-         *  rx_link fsm state, [30:24] rx_fifo_cnt
-         */
-        uint32_t slc1_state1:32;
-    };
-    uint32_t val;
-} sdio_slc1_state1_reg_t;
-
-/** Type of slc_sdio_st register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cmd_st : RO; bitpos: [2:0]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_st:3;
-        uint32_t reserved_3:1;
-        /** func_st : RO; bitpos: [7:4]; default: 0;
-         *  reserved
-         */
-        uint32_t func_st:4;
-        /** sdio_wakeup : RO; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t sdio_wakeup:1;
-        uint32_t reserved_9:3;
-        /** bus_st : RO; bitpos: [14:12]; default: 0;
-         *  reserved
-         */
-        uint32_t bus_st:3;
-        uint32_t reserved_15:1;
-        /** func1_acc_state : RO; bitpos: [20:16]; default: 0;
-         *  reserved
-         */
-        uint32_t func1_acc_state:5;
-        uint32_t reserved_21:3;
-        /** func2_acc_state : RO; bitpos: [28:24]; default: 0;
-         *  reserved
-         */
-        uint32_t func2_acc_state:5;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} sdio_slc_sdio_st_reg_t;
-
-/** Type of slc0_txlink_dscr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_dscr:32;
-    };
-    uint32_t val;
-} sdio_slc0_txlink_dscr_reg_t;
-
-/** Type of slc0_txlink_dscr_bf0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} sdio_slc0_txlink_dscr_bf0_reg_t;
-
-/** Type of slc0_txlink_dscr_bf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} sdio_slc0_txlink_dscr_bf1_reg_t;
-
-/** Type of slc0_rxlink_dscr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  the third word of slc0 link descriptor, or known as the next descriptor address
-         */
-        uint32_t slc0_rxlink_dscr:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxlink_dscr_reg_t;
-
-/** Type of slc0_rxlink_dscr_bf0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxlink_dscr_bf0_reg_t;
-
-/** Type of slc0_rxlink_dscr_bf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rxlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} sdio_slc0_rxlink_dscr_bf1_reg_t;
-
-/** Type of slc1_txlink_dscr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_dscr:32;
-    };
-    uint32_t val;
-} sdio_slc1_txlink_dscr_reg_t;
-
-/** Type of slc1_txlink_dscr_bf0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} sdio_slc1_txlink_dscr_bf0_reg_t;
-
-/** Type of slc1_txlink_dscr_bf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} sdio_slc1_txlink_dscr_bf1_reg_t;
-
-/** Type of slc1_rxlink_dscr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  the third word of slc1 link descriptor, or known as the next descriptor address
-         */
-        uint32_t slc1_rxlink_dscr:32;
-    };
-    uint32_t val;
-} sdio_slc1_rxlink_dscr_reg_t;
-
-/** Type of slc1_rxlink_dscr_bf0 register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} sdio_slc1_rxlink_dscr_bf0_reg_t;
-
-/** Type of slc1_rxlink_dscr_bf1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_rxlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} sdio_slc1_rxlink_dscr_bf1_reg_t;
-
-/** Type of slc0_tx_erreof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_tx_err_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_tx_erreof_des_addr_reg_t;
-
-/** Type of slc1_tx_erreof_des_addr register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_tx_err_eof_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc1_tx_erreof_des_addr_reg_t;
-
-/** Type of slc_token_lat register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_token : RO; bitpos: [11:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_token:12;
-        uint32_t reserved_12:4;
-        /** slc1_token : RO; bitpos: [27:16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_token:12;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} sdio_slc_token_lat_reg_t;
-
-/** Type of slc_cmd_infor0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cmd_content0 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_content0:32;
-    };
-    uint32_t val;
-} sdio_slc_cmd_infor0_reg_t;
-
-/** Type of slc_cmd_infor1 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cmd_content1 : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t cmd_content1:32;
-    };
-    uint32_t val;
-} sdio_slc_cmd_infor1_reg_t;
-
-/** Type of slc0_length register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_len : RO; bitpos: [19:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_len:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} sdio_slc0_length_reg_t;
-
-/** Type of slc_sdio_crc_st0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t dat0_crc_err_cnt:8;
-        /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0;
-         *  reserved
-         */
-        uint32_t dat1_crc_err_cnt:8;
-        /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0;
-         *  reserved
-         */
-        uint32_t dat2_crc_err_cnt:8;
-        /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t dat3_crc_err_cnt:8;
-    };
-    uint32_t val;
-} sdio_slc_sdio_crc_st0_reg_t;
-
-/** Type of slc0_eof_start_des register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_eof_start_des_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_eof_start_des_reg_t;
-
-/** Type of slc0_push_dscr_addr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
-         */
-        uint32_t slc0_rx_push_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_push_dscr_addr_reg_t;
-
-/** Type of slc0_done_dscr_addr register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  the current descriptor address when slc0 finishes reading data from one buffer,
-         *  aligned with word
-         */
-        uint32_t slc0_rx_done_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_done_dscr_addr_reg_t;
-
-/** Type of slc0_sub_start_des register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0;
-         *  the current descriptor address when slc0 gets  a link descriptor, aligned with word
-         */
-        uint32_t slc0_sub_pac_start_dscr_addr:32;
-    };
-    uint32_t val;
-} sdio_slc0_sub_start_des_reg_t;
-
-/** Type of slc0_dscr_cnt register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0;
-         *  the number of descriptors got by slc0 when it tries to read data from memory
-         */
-        uint32_t slc0_rx_dscr_cnt_lat:10;
-        uint32_t reserved_10:6;
-        /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_rx_get_eof_occ:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc0_dscr_cnt_reg_t;
-
-
-/** Group: Debud registers */
-/** Type of slc0txfifo_pop register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024;
-         *  reserved
-         */
-        uint32_t slc0_txfifo_rdata:11;
-        uint32_t reserved_11:5;
-        /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc0_txfifo_pop:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc0txfifo_pop_reg_t;
-
-/** Type of slc1txfifo_pop register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024;
-         *  reserved
-         */
-        uint32_t slc1_txfifo_rdata:11;
-        uint32_t reserved_11:5;
-        /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0;
-         *  reserved
-         */
-        uint32_t slc1_txfifo_pop:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} sdio_slc1txfifo_pop_reg_t;
-
-/** Type of slc_ahb_test register
- *  reserved
- */
-typedef union {
-    struct {
-        /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_ahb_testmode:3;
-        uint32_t reserved_3:1;
-        /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
-         *  reserved
-         */
-        uint32_t slc_ahb_testaddr:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} sdio_slc_ahb_test_reg_t;
-
-
-/** Group: Version registers */
-/** Type of slcdate register
- *  ******* Description ***********
- */
-typedef union {
-    struct {
-        /** slc_date : R/W; bitpos: [31:0]; default: 554182400;
-         *  reserved
-         */
-        uint32_t slc_date:32;
-    };
-    uint32_t val;
-} sdio_slcdate_reg_t;
-
-
-typedef struct {
-    volatile sdio_slcconf0_reg_t slcconf0;
-    volatile sdio_slc0int_raw_reg_t slc0int_raw;
-    volatile sdio_slc0int_st_reg_t slc0int_st;
-    volatile sdio_slc0int_ena_reg_t slc0int_ena;
-    volatile sdio_slc0int_clr_reg_t slc0int_clr;
-    volatile sdio_slc1int_raw_reg_t slc1int_raw;
-    volatile sdio_slc1int_st_reg_t slc1int_st;
-    volatile sdio_slc1int_ena_reg_t slc1int_ena;
-    volatile sdio_slc1int_clr_reg_t slc1int_clr;
-    volatile sdio_slcrx_status_reg_t slcrx_status;
-    volatile sdio_slc0rxfifo_push_reg_t slc0rxfifo_push;
-    volatile sdio_slc1rxfifo_push_reg_t slc1rxfifo_push;
-    volatile sdio_slctx_status_reg_t slctx_status;
-    volatile sdio_slc0txfifo_pop_reg_t slc0txfifo_pop;
-    volatile sdio_slc1txfifo_pop_reg_t slc1txfifo_pop;
-    volatile sdio_slc0rx_link_reg_t slc0rx_link;
-    volatile sdio_slc0rx_link_addr_reg_t slc0rx_link_addr;
-    volatile sdio_slc0tx_link_reg_t slc0tx_link;
-    volatile sdio_slc0tx_link_addr_reg_t slc0tx_link_addr;
-    volatile sdio_slc1rx_link_reg_t slc1rx_link;
-    volatile sdio_slc1rx_link_addr_reg_t slc1rx_link_addr;
-    volatile sdio_slc1tx_link_reg_t slc1tx_link;
-    volatile sdio_slc1tx_link_addr_reg_t slc1tx_link_addr;
-    volatile sdio_slcintvec_tohost_reg_t slcintvec_tohost;
-    volatile sdio_slc0token0_reg_t slc0token0;
-    volatile sdio_slc0token1_reg_t slc0token1;
-    volatile sdio_slc1token0_reg_t slc1token0;
-    volatile sdio_slc1token1_reg_t slc1token1;
-    volatile sdio_slcconf1_reg_t slcconf1;
-    volatile sdio_slc0_state0_reg_t slc0_state0;
-    volatile sdio_slc0_state1_reg_t slc0_state1;
-    volatile sdio_slc1_state0_reg_t slc1_state0;
-    volatile sdio_slc1_state1_reg_t slc1_state1;
-    volatile sdio_slcbridge_conf_reg_t slcbridge_conf;
-    volatile sdio_slc0_to_eof_des_addr_reg_t slc0_to_eof_des_addr;
-    volatile sdio_slc0_tx_eof_des_addr_reg_t slc0_tx_eof_des_addr;
-    volatile sdio_slc0_to_eof_bfr_des_addr_reg_t slc0_to_eof_bfr_des_addr;
-    volatile sdio_slc1_to_eof_des_addr_reg_t slc1_to_eof_des_addr;
-    volatile sdio_slc1_tx_eof_des_addr_reg_t slc1_tx_eof_des_addr;
-    volatile sdio_slc1_to_eof_bfr_des_addr_reg_t slc1_to_eof_bfr_des_addr;
-    volatile sdio_slc_ahb_test_reg_t slc_ahb_test;
-    volatile sdio_slc_sdio_st_reg_t slc_sdio_st;
-    volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf;
-    volatile sdio_slc0_txlink_dscr_reg_t slc0_txlink_dscr;
-    volatile sdio_slc0_txlink_dscr_bf0_reg_t slc0_txlink_dscr_bf0;
-    volatile sdio_slc0_txlink_dscr_bf1_reg_t slc0_txlink_dscr_bf1;
-    volatile sdio_slc0_rxlink_dscr_reg_t slc0_rxlink_dscr;
-    volatile sdio_slc0_rxlink_dscr_bf0_reg_t slc0_rxlink_dscr_bf0;
-    volatile sdio_slc0_rxlink_dscr_bf1_reg_t slc0_rxlink_dscr_bf1;
-    volatile sdio_slc1_txlink_dscr_reg_t slc1_txlink_dscr;
-    volatile sdio_slc1_txlink_dscr_bf0_reg_t slc1_txlink_dscr_bf0;
-    volatile sdio_slc1_txlink_dscr_bf1_reg_t slc1_txlink_dscr_bf1;
-    volatile sdio_slc1_rxlink_dscr_reg_t slc1_rxlink_dscr;
-    volatile sdio_slc1_rxlink_dscr_bf0_reg_t slc1_rxlink_dscr_bf0;
-    volatile sdio_slc1_rxlink_dscr_bf1_reg_t slc1_rxlink_dscr_bf1;
-    volatile sdio_slc0_tx_erreof_des_addr_reg_t slc0_tx_erreof_des_addr;
-    volatile sdio_slc1_tx_erreof_des_addr_reg_t slc1_tx_erreof_des_addr;
-    volatile sdio_slc_token_lat_reg_t slc_token_lat;
-    volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf;
-    volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0;
-    volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1;
-    volatile sdio_slc0_len_conf_reg_t slc0_len_conf;
-    volatile sdio_slc0_length_reg_t slc0_length;
-    volatile sdio_slc0_txpkt_h_dscr_reg_t slc0_txpkt_h_dscr;
-    volatile sdio_slc0_txpkt_e_dscr_reg_t slc0_txpkt_e_dscr;
-    volatile sdio_slc0_rxpkt_h_dscr_reg_t slc0_rxpkt_h_dscr;
-    volatile sdio_slc0_rxpkt_e_dscr_reg_t slc0_rxpkt_e_dscr;
-    volatile sdio_slc0_txpktu_h_dscr_reg_t slc0_txpktu_h_dscr;
-    volatile sdio_slc0_txpktu_e_dscr_reg_t slc0_txpktu_e_dscr;
-    volatile sdio_slc0_rxpktu_h_dscr_reg_t slc0_rxpktu_h_dscr;
-    volatile sdio_slc0_rxpktu_e_dscr_reg_t slc0_rxpktu_e_dscr;
-    volatile sdio_slc_seq_position_reg_t slc_seq_position;
-    volatile sdio_slc0_dscr_rec_conf_reg_t slc0_dscr_rec_conf;
-    volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0;
-    volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1;
-    volatile sdio_slc0_eof_start_des_reg_t slc0_eof_start_des;
-    volatile sdio_slc0_push_dscr_addr_reg_t slc0_push_dscr_addr;
-    volatile sdio_slc0_done_dscr_addr_reg_t slc0_done_dscr_addr;
-    volatile sdio_slc0_sub_start_des_reg_t slc0_sub_start_des;
-    volatile sdio_slc0_dscr_cnt_reg_t slc0_dscr_cnt;
-    volatile sdio_slc0_len_lim_conf_reg_t slc0_len_lim_conf;
-    volatile sdio_slc0int_st1_reg_t slc0int_st1;
-    volatile sdio_slc0int_ena1_reg_t slc0int_ena1;
-    volatile sdio_slc1int_st1_reg_t slc1int_st1;
-    volatile sdio_slc1int_ena1_reg_t slc1int_ena1;
-    volatile sdio_slc0_tx_sharemem_start_reg_t slc0_tx_sharemem_start;
-    volatile sdio_slc0_tx_sharemem_end_reg_t slc0_tx_sharemem_end;
-    volatile sdio_slc0_rx_sharemem_start_reg_t slc0_rx_sharemem_start;
-    volatile sdio_slc0_rx_sharemem_end_reg_t slc0_rx_sharemem_end;
-    volatile sdio_slc1_tx_sharemem_start_reg_t slc1_tx_sharemem_start;
-    volatile sdio_slc1_tx_sharemem_end_reg_t slc1_tx_sharemem_end;
-    volatile sdio_slc1_rx_sharemem_start_reg_t slc1_rx_sharemem_start;
-    volatile sdio_slc1_rx_sharemem_end_reg_t slc1_rx_sharemem_end;
-    volatile sdio_hda_tx_sharemem_start_reg_t hda_tx_sharemem_start;
-    volatile sdio_hda_rx_sharemem_start_reg_t hda_rx_sharemem_start;
-    volatile sdio_slc_burst_len_reg_t slc_burst_len;
-    uint32_t reserved_180[30];
-    volatile sdio_slcdate_reg_t slcdate;
-    volatile sdio_slcid_reg_t slcid;
-} sdio_dev_t;
-
-extern sdio_dev_t SLC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(sdio_dev_t) == 0x200, "Invalid size of sdio_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/sha_struct.h b/components/soc/esp32c5/include/soc/sha_struct.h
index b5e24d24a8..d65e8e449e 100644
--- a/components/soc/esp32c5/include/soc/sha_struct.h
+++ b/components/soc/esp32c5/include/soc/sha_struct.h
@@ -160,7 +160,7 @@ typedef union {
 
 /** Group: memory type */
 
-typedef struct {
+typedef struct sha_dev_t {
     volatile sha_mode_reg_t mode;
     uint32_t reserved_004[2];
     volatile sha_dma_block_num_reg_t dma_block_num;
diff --git a/components/soc/esp32c5/include/soc/soc_etm_struct.h b/components/soc/esp32c5/include/soc/soc_etm_struct.h
index 3d46175e49..f575255af7 100644
--- a/components/soc/esp32c5/include/soc/soc_etm_struct.h
+++ b/components/soc/esp32c5/include/soc/soc_etm_struct.h
@@ -1985,1405 +1985,34 @@ typedef union {
     uint32_t val;
 } soc_etm_ch_ena_ad1_clr_reg_t;
 
-/** Type of ch0_evt_id register
- *  Channel0 event id register
+/** Type of evt_id register
+ *  Channel event id register
  */
 typedef union {
     struct {
-        /** ch0_evt_id : R/W; bitpos: [7:0]; default: 0;
+        /** evt_id : R/W; bitpos: [7:0]; default: 0;
          *  Configures ch0_evt_id
          */
-        uint32_t ch0_evt_id:8;
+        uint32_t evt_id:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
-} soc_etm_ch0_evt_id_reg_t;
+} soc_etm_ch_evt_id_reg_t;
 
-/** Type of ch0_task_id register
- *  Channel0 task id register
+/** Type of task_id register
+ *  Channel task id register
  */
 typedef union {
     struct {
-        /** ch0_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch0_task_id
+        /** task_id : R/W; bitpos: [7:0]; default: 0;
+         *  Configures task_id
          */
-        uint32_t ch0_task_id:8;
+        uint32_t task_id:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
-} soc_etm_ch0_task_id_reg_t;
+} soc_etm_ch_task_id_reg_t;
 
-/** Type of ch1_evt_id register
- *  Channel1 event id register
- */
-typedef union {
-    struct {
-        /** ch1_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch1_evt_id
-         */
-        uint32_t ch1_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch1_evt_id_reg_t;
-
-/** Type of ch1_task_id register
- *  Channel1 task id register
- */
-typedef union {
-    struct {
-        /** ch1_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch1_task_id
-         */
-        uint32_t ch1_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch1_task_id_reg_t;
-
-/** Type of ch2_evt_id register
- *  Channel2 event id register
- */
-typedef union {
-    struct {
-        /** ch2_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch2_evt_id
-         */
-        uint32_t ch2_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch2_evt_id_reg_t;
-
-/** Type of ch2_task_id register
- *  Channel2 task id register
- */
-typedef union {
-    struct {
-        /** ch2_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch2_task_id
-         */
-        uint32_t ch2_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch2_task_id_reg_t;
-
-/** Type of ch3_evt_id register
- *  Channel3 event id register
- */
-typedef union {
-    struct {
-        /** ch3_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch3_evt_id
-         */
-        uint32_t ch3_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch3_evt_id_reg_t;
-
-/** Type of ch3_task_id register
- *  Channel3 task id register
- */
-typedef union {
-    struct {
-        /** ch3_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch3_task_id
-         */
-        uint32_t ch3_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch3_task_id_reg_t;
-
-/** Type of ch4_evt_id register
- *  Channel4 event id register
- */
-typedef union {
-    struct {
-        /** ch4_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch4_evt_id
-         */
-        uint32_t ch4_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch4_evt_id_reg_t;
-
-/** Type of ch4_task_id register
- *  Channel4 task id register
- */
-typedef union {
-    struct {
-        /** ch4_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch4_task_id
-         */
-        uint32_t ch4_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch4_task_id_reg_t;
-
-/** Type of ch5_evt_id register
- *  Channel5 event id register
- */
-typedef union {
-    struct {
-        /** ch5_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch5_evt_id
-         */
-        uint32_t ch5_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch5_evt_id_reg_t;
-
-/** Type of ch5_task_id register
- *  Channel5 task id register
- */
-typedef union {
-    struct {
-        /** ch5_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch5_task_id
-         */
-        uint32_t ch5_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch5_task_id_reg_t;
-
-/** Type of ch6_evt_id register
- *  Channel6 event id register
- */
-typedef union {
-    struct {
-        /** ch6_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch6_evt_id
-         */
-        uint32_t ch6_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch6_evt_id_reg_t;
-
-/** Type of ch6_task_id register
- *  Channel6 task id register
- */
-typedef union {
-    struct {
-        /** ch6_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch6_task_id
-         */
-        uint32_t ch6_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch6_task_id_reg_t;
-
-/** Type of ch7_evt_id register
- *  Channel7 event id register
- */
-typedef union {
-    struct {
-        /** ch7_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch7_evt_id
-         */
-        uint32_t ch7_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch7_evt_id_reg_t;
-
-/** Type of ch7_task_id register
- *  Channel7 task id register
- */
-typedef union {
-    struct {
-        /** ch7_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch7_task_id
-         */
-        uint32_t ch7_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch7_task_id_reg_t;
-
-/** Type of ch8_evt_id register
- *  Channel8 event id register
- */
-typedef union {
-    struct {
-        /** ch8_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch8_evt_id
-         */
-        uint32_t ch8_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch8_evt_id_reg_t;
-
-/** Type of ch8_task_id register
- *  Channel8 task id register
- */
-typedef union {
-    struct {
-        /** ch8_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch8_task_id
-         */
-        uint32_t ch8_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch8_task_id_reg_t;
-
-/** Type of ch9_evt_id register
- *  Channel9 event id register
- */
-typedef union {
-    struct {
-        /** ch9_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch9_evt_id
-         */
-        uint32_t ch9_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch9_evt_id_reg_t;
-
-/** Type of ch9_task_id register
- *  Channel9 task id register
- */
-typedef union {
-    struct {
-        /** ch9_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch9_task_id
-         */
-        uint32_t ch9_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch9_task_id_reg_t;
-
-/** Type of ch10_evt_id register
- *  Channel10 event id register
- */
-typedef union {
-    struct {
-        /** ch10_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch10_evt_id
-         */
-        uint32_t ch10_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch10_evt_id_reg_t;
-
-/** Type of ch10_task_id register
- *  Channel10 task id register
- */
-typedef union {
-    struct {
-        /** ch10_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch10_task_id
-         */
-        uint32_t ch10_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch10_task_id_reg_t;
-
-/** Type of ch11_evt_id register
- *  Channel11 event id register
- */
-typedef union {
-    struct {
-        /** ch11_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch11_evt_id
-         */
-        uint32_t ch11_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch11_evt_id_reg_t;
-
-/** Type of ch11_task_id register
- *  Channel11 task id register
- */
-typedef union {
-    struct {
-        /** ch11_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch11_task_id
-         */
-        uint32_t ch11_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch11_task_id_reg_t;
-
-/** Type of ch12_evt_id register
- *  Channel12 event id register
- */
-typedef union {
-    struct {
-        /** ch12_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch12_evt_id
-         */
-        uint32_t ch12_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch12_evt_id_reg_t;
-
-/** Type of ch12_task_id register
- *  Channel12 task id register
- */
-typedef union {
-    struct {
-        /** ch12_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch12_task_id
-         */
-        uint32_t ch12_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch12_task_id_reg_t;
-
-/** Type of ch13_evt_id register
- *  Channel13 event id register
- */
-typedef union {
-    struct {
-        /** ch13_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch13_evt_id
-         */
-        uint32_t ch13_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch13_evt_id_reg_t;
-
-/** Type of ch13_task_id register
- *  Channel13 task id register
- */
-typedef union {
-    struct {
-        /** ch13_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch13_task_id
-         */
-        uint32_t ch13_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch13_task_id_reg_t;
-
-/** Type of ch14_evt_id register
- *  Channel14 event id register
- */
-typedef union {
-    struct {
-        /** ch14_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch14_evt_id
-         */
-        uint32_t ch14_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch14_evt_id_reg_t;
-
-/** Type of ch14_task_id register
- *  Channel14 task id register
- */
-typedef union {
-    struct {
-        /** ch14_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch14_task_id
-         */
-        uint32_t ch14_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch14_task_id_reg_t;
-
-/** Type of ch15_evt_id register
- *  Channel15 event id register
- */
-typedef union {
-    struct {
-        /** ch15_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch15_evt_id
-         */
-        uint32_t ch15_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch15_evt_id_reg_t;
-
-/** Type of ch15_task_id register
- *  Channel15 task id register
- */
-typedef union {
-    struct {
-        /** ch15_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch15_task_id
-         */
-        uint32_t ch15_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch15_task_id_reg_t;
-
-/** Type of ch16_evt_id register
- *  Channel16 event id register
- */
-typedef union {
-    struct {
-        /** ch16_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch16_evt_id
-         */
-        uint32_t ch16_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch16_evt_id_reg_t;
-
-/** Type of ch16_task_id register
- *  Channel16 task id register
- */
-typedef union {
-    struct {
-        /** ch16_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch16_task_id
-         */
-        uint32_t ch16_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch16_task_id_reg_t;
-
-/** Type of ch17_evt_id register
- *  Channel17 event id register
- */
-typedef union {
-    struct {
-        /** ch17_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch17_evt_id
-         */
-        uint32_t ch17_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch17_evt_id_reg_t;
-
-/** Type of ch17_task_id register
- *  Channel17 task id register
- */
-typedef union {
-    struct {
-        /** ch17_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch17_task_id
-         */
-        uint32_t ch17_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch17_task_id_reg_t;
-
-/** Type of ch18_evt_id register
- *  Channel18 event id register
- */
-typedef union {
-    struct {
-        /** ch18_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch18_evt_id
-         */
-        uint32_t ch18_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch18_evt_id_reg_t;
-
-/** Type of ch18_task_id register
- *  Channel18 task id register
- */
-typedef union {
-    struct {
-        /** ch18_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch18_task_id
-         */
-        uint32_t ch18_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch18_task_id_reg_t;
-
-/** Type of ch19_evt_id register
- *  Channel19 event id register
- */
-typedef union {
-    struct {
-        /** ch19_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch19_evt_id
-         */
-        uint32_t ch19_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch19_evt_id_reg_t;
-
-/** Type of ch19_task_id register
- *  Channel19 task id register
- */
-typedef union {
-    struct {
-        /** ch19_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch19_task_id
-         */
-        uint32_t ch19_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch19_task_id_reg_t;
-
-/** Type of ch20_evt_id register
- *  Channel20 event id register
- */
-typedef union {
-    struct {
-        /** ch20_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch20_evt_id
-         */
-        uint32_t ch20_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch20_evt_id_reg_t;
-
-/** Type of ch20_task_id register
- *  Channel20 task id register
- */
-typedef union {
-    struct {
-        /** ch20_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch20_task_id
-         */
-        uint32_t ch20_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch20_task_id_reg_t;
-
-/** Type of ch21_evt_id register
- *  Channel21 event id register
- */
-typedef union {
-    struct {
-        /** ch21_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch21_evt_id
-         */
-        uint32_t ch21_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch21_evt_id_reg_t;
-
-/** Type of ch21_task_id register
- *  Channel21 task id register
- */
-typedef union {
-    struct {
-        /** ch21_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch21_task_id
-         */
-        uint32_t ch21_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch21_task_id_reg_t;
-
-/** Type of ch22_evt_id register
- *  Channel22 event id register
- */
-typedef union {
-    struct {
-        /** ch22_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch22_evt_id
-         */
-        uint32_t ch22_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch22_evt_id_reg_t;
-
-/** Type of ch22_task_id register
- *  Channel22 task id register
- */
-typedef union {
-    struct {
-        /** ch22_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch22_task_id
-         */
-        uint32_t ch22_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch22_task_id_reg_t;
-
-/** Type of ch23_evt_id register
- *  Channel23 event id register
- */
-typedef union {
-    struct {
-        /** ch23_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch23_evt_id
-         */
-        uint32_t ch23_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch23_evt_id_reg_t;
-
-/** Type of ch23_task_id register
- *  Channel23 task id register
- */
-typedef union {
-    struct {
-        /** ch23_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch23_task_id
-         */
-        uint32_t ch23_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch23_task_id_reg_t;
-
-/** Type of ch24_evt_id register
- *  Channel24 event id register
- */
-typedef union {
-    struct {
-        /** ch24_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch24_evt_id
-         */
-        uint32_t ch24_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch24_evt_id_reg_t;
-
-/** Type of ch24_task_id register
- *  Channel24 task id register
- */
-typedef union {
-    struct {
-        /** ch24_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch24_task_id
-         */
-        uint32_t ch24_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch24_task_id_reg_t;
-
-/** Type of ch25_evt_id register
- *  Channel25 event id register
- */
-typedef union {
-    struct {
-        /** ch25_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch25_evt_id
-         */
-        uint32_t ch25_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch25_evt_id_reg_t;
-
-/** Type of ch25_task_id register
- *  Channel25 task id register
- */
-typedef union {
-    struct {
-        /** ch25_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch25_task_id
-         */
-        uint32_t ch25_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch25_task_id_reg_t;
-
-/** Type of ch26_evt_id register
- *  Channel26 event id register
- */
-typedef union {
-    struct {
-        /** ch26_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch26_evt_id
-         */
-        uint32_t ch26_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch26_evt_id_reg_t;
-
-/** Type of ch26_task_id register
- *  Channel26 task id register
- */
-typedef union {
-    struct {
-        /** ch26_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch26_task_id
-         */
-        uint32_t ch26_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch26_task_id_reg_t;
-
-/** Type of ch27_evt_id register
- *  Channel27 event id register
- */
-typedef union {
-    struct {
-        /** ch27_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch27_evt_id
-         */
-        uint32_t ch27_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch27_evt_id_reg_t;
-
-/** Type of ch27_task_id register
- *  Channel27 task id register
- */
-typedef union {
-    struct {
-        /** ch27_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch27_task_id
-         */
-        uint32_t ch27_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch27_task_id_reg_t;
-
-/** Type of ch28_evt_id register
- *  Channel28 event id register
- */
-typedef union {
-    struct {
-        /** ch28_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch28_evt_id
-         */
-        uint32_t ch28_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch28_evt_id_reg_t;
-
-/** Type of ch28_task_id register
- *  Channel28 task id register
- */
-typedef union {
-    struct {
-        /** ch28_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch28_task_id
-         */
-        uint32_t ch28_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch28_task_id_reg_t;
-
-/** Type of ch29_evt_id register
- *  Channel29 event id register
- */
-typedef union {
-    struct {
-        /** ch29_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch29_evt_id
-         */
-        uint32_t ch29_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch29_evt_id_reg_t;
-
-/** Type of ch29_task_id register
- *  Channel29 task id register
- */
-typedef union {
-    struct {
-        /** ch29_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch29_task_id
-         */
-        uint32_t ch29_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch29_task_id_reg_t;
-
-/** Type of ch30_evt_id register
- *  Channel30 event id register
- */
-typedef union {
-    struct {
-        /** ch30_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch30_evt_id
-         */
-        uint32_t ch30_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch30_evt_id_reg_t;
-
-/** Type of ch30_task_id register
- *  Channel30 task id register
- */
-typedef union {
-    struct {
-        /** ch30_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch30_task_id
-         */
-        uint32_t ch30_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch30_task_id_reg_t;
-
-/** Type of ch31_evt_id register
- *  Channel31 event id register
- */
-typedef union {
-    struct {
-        /** ch31_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch31_evt_id
-         */
-        uint32_t ch31_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch31_evt_id_reg_t;
-
-/** Type of ch31_task_id register
- *  Channel31 task id register
- */
-typedef union {
-    struct {
-        /** ch31_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch31_task_id
-         */
-        uint32_t ch31_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch31_task_id_reg_t;
-
-/** Type of ch32_evt_id register
- *  Channel32 event id register
- */
-typedef union {
-    struct {
-        /** ch32_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch32_evt_id
-         */
-        uint32_t ch32_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch32_evt_id_reg_t;
-
-/** Type of ch32_task_id register
- *  Channel32 task id register
- */
-typedef union {
-    struct {
-        /** ch32_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch32_task_id
-         */
-        uint32_t ch32_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch32_task_id_reg_t;
-
-/** Type of ch33_evt_id register
- *  Channel33 event id register
- */
-typedef union {
-    struct {
-        /** ch33_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch33_evt_id
-         */
-        uint32_t ch33_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch33_evt_id_reg_t;
-
-/** Type of ch33_task_id register
- *  Channel33 task id register
- */
-typedef union {
-    struct {
-        /** ch33_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch33_task_id
-         */
-        uint32_t ch33_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch33_task_id_reg_t;
-
-/** Type of ch34_evt_id register
- *  Channel34 event id register
- */
-typedef union {
-    struct {
-        /** ch34_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch34_evt_id
-         */
-        uint32_t ch34_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch34_evt_id_reg_t;
-
-/** Type of ch34_task_id register
- *  Channel34 task id register
- */
-typedef union {
-    struct {
-        /** ch34_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch34_task_id
-         */
-        uint32_t ch34_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch34_task_id_reg_t;
-
-/** Type of ch35_evt_id register
- *  Channel35 event id register
- */
-typedef union {
-    struct {
-        /** ch35_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch35_evt_id
-         */
-        uint32_t ch35_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch35_evt_id_reg_t;
-
-/** Type of ch35_task_id register
- *  Channel35 task id register
- */
-typedef union {
-    struct {
-        /** ch35_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch35_task_id
-         */
-        uint32_t ch35_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch35_task_id_reg_t;
-
-/** Type of ch36_evt_id register
- *  Channel36 event id register
- */
-typedef union {
-    struct {
-        /** ch36_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch36_evt_id
-         */
-        uint32_t ch36_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch36_evt_id_reg_t;
-
-/** Type of ch36_task_id register
- *  Channel36 task id register
- */
-typedef union {
-    struct {
-        /** ch36_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch36_task_id
-         */
-        uint32_t ch36_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch36_task_id_reg_t;
-
-/** Type of ch37_evt_id register
- *  Channel37 event id register
- */
-typedef union {
-    struct {
-        /** ch37_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch37_evt_id
-         */
-        uint32_t ch37_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch37_evt_id_reg_t;
-
-/** Type of ch37_task_id register
- *  Channel37 task id register
- */
-typedef union {
-    struct {
-        /** ch37_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch37_task_id
-         */
-        uint32_t ch37_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch37_task_id_reg_t;
-
-/** Type of ch38_evt_id register
- *  Channel38 event id register
- */
-typedef union {
-    struct {
-        /** ch38_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch38_evt_id
-         */
-        uint32_t ch38_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch38_evt_id_reg_t;
-
-/** Type of ch38_task_id register
- *  Channel38 task id register
- */
-typedef union {
-    struct {
-        /** ch38_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch38_task_id
-         */
-        uint32_t ch38_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch38_task_id_reg_t;
-
-/** Type of ch39_evt_id register
- *  Channel39 event id register
- */
-typedef union {
-    struct {
-        /** ch39_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch39_evt_id
-         */
-        uint32_t ch39_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch39_evt_id_reg_t;
-
-/** Type of ch39_task_id register
- *  Channel39 task id register
- */
-typedef union {
-    struct {
-        /** ch39_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch39_task_id
-         */
-        uint32_t ch39_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch39_task_id_reg_t;
-
-/** Type of ch40_evt_id register
- *  Channel40 event id register
- */
-typedef union {
-    struct {
-        /** ch40_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch40_evt_id
-         */
-        uint32_t ch40_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch40_evt_id_reg_t;
-
-/** Type of ch40_task_id register
- *  Channel40 task id register
- */
-typedef union {
-    struct {
-        /** ch40_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch40_task_id
-         */
-        uint32_t ch40_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch40_task_id_reg_t;
-
-/** Type of ch41_evt_id register
- *  Channel41 event id register
- */
-typedef union {
-    struct {
-        /** ch41_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch41_evt_id
-         */
-        uint32_t ch41_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch41_evt_id_reg_t;
-
-/** Type of ch41_task_id register
- *  Channel41 task id register
- */
-typedef union {
-    struct {
-        /** ch41_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch41_task_id
-         */
-        uint32_t ch41_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch41_task_id_reg_t;
-
-/** Type of ch42_evt_id register
- *  Channel42 event id register
- */
-typedef union {
-    struct {
-        /** ch42_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch42_evt_id
-         */
-        uint32_t ch42_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch42_evt_id_reg_t;
-
-/** Type of ch42_task_id register
- *  Channel42 task id register
- */
-typedef union {
-    struct {
-        /** ch42_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch42_task_id
-         */
-        uint32_t ch42_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch42_task_id_reg_t;
-
-/** Type of ch43_evt_id register
- *  Channel43 event id register
- */
-typedef union {
-    struct {
-        /** ch43_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch43_evt_id
-         */
-        uint32_t ch43_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch43_evt_id_reg_t;
-
-/** Type of ch43_task_id register
- *  Channel43 task id register
- */
-typedef union {
-    struct {
-        /** ch43_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch43_task_id
-         */
-        uint32_t ch43_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch43_task_id_reg_t;
-
-/** Type of ch44_evt_id register
- *  Channel44 event id register
- */
-typedef union {
-    struct {
-        /** ch44_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch44_evt_id
-         */
-        uint32_t ch44_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch44_evt_id_reg_t;
-
-/** Type of ch44_task_id register
- *  Channel44 task id register
- */
-typedef union {
-    struct {
-        /** ch44_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch44_task_id
-         */
-        uint32_t ch44_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch44_task_id_reg_t;
-
-/** Type of ch45_evt_id register
- *  Channel45 event id register
- */
-typedef union {
-    struct {
-        /** ch45_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch45_evt_id
-         */
-        uint32_t ch45_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch45_evt_id_reg_t;
-
-/** Type of ch45_task_id register
- *  Channel45 task id register
- */
-typedef union {
-    struct {
-        /** ch45_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch45_task_id
-         */
-        uint32_t ch45_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch45_task_id_reg_t;
-
-/** Type of ch46_evt_id register
- *  Channel46 event id register
- */
-typedef union {
-    struct {
-        /** ch46_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch46_evt_id
-         */
-        uint32_t ch46_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch46_evt_id_reg_t;
-
-/** Type of ch46_task_id register
- *  Channel46 task id register
- */
-typedef union {
-    struct {
-        /** ch46_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch46_task_id
-         */
-        uint32_t ch46_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch46_task_id_reg_t;
-
-/** Type of ch47_evt_id register
- *  Channel47 event id register
- */
-typedef union {
-    struct {
-        /** ch47_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch47_evt_id
-         */
-        uint32_t ch47_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch47_evt_id_reg_t;
-
-/** Type of ch47_task_id register
- *  Channel47 task id register
- */
-typedef union {
-    struct {
-        /** ch47_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch47_task_id
-         */
-        uint32_t ch47_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch47_task_id_reg_t;
-
-/** Type of ch48_evt_id register
- *  Channel48 event id register
- */
-typedef union {
-    struct {
-        /** ch48_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch48_evt_id
-         */
-        uint32_t ch48_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch48_evt_id_reg_t;
-
-/** Type of ch48_task_id register
- *  Channel48 task id register
- */
-typedef union {
-    struct {
-        /** ch48_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch48_task_id
-         */
-        uint32_t ch48_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch48_task_id_reg_t;
-
-/** Type of ch49_evt_id register
- *  Channel49 event id register
- */
-typedef union {
-    struct {
-        /** ch49_evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch49_evt_id
-         */
-        uint32_t ch49_evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch49_evt_id_reg_t;
-
-/** Type of ch49_task_id register
- *  Channel49 task id register
- */
-typedef union {
-    struct {
-        /** ch49_task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch49_task_id
-         */
-        uint32_t ch49_task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_ch49_task_id_reg_t;
 
 /** Type of evt_st0_clr register
  *  Events trigger status clear register
@@ -4974,113 +3603,17 @@ typedef union {
 } soc_etm_date_reg_t;
 
 
-typedef struct {
+typedef struct soc_etm_dev_t {
     volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
     volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
     volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
     volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
     volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
     volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
-    volatile soc_etm_ch0_evt_id_reg_t ch0_evt_id;
-    volatile soc_etm_ch0_task_id_reg_t ch0_task_id;
-    volatile soc_etm_ch1_evt_id_reg_t ch1_evt_id;
-    volatile soc_etm_ch1_task_id_reg_t ch1_task_id;
-    volatile soc_etm_ch2_evt_id_reg_t ch2_evt_id;
-    volatile soc_etm_ch2_task_id_reg_t ch2_task_id;
-    volatile soc_etm_ch3_evt_id_reg_t ch3_evt_id;
-    volatile soc_etm_ch3_task_id_reg_t ch3_task_id;
-    volatile soc_etm_ch4_evt_id_reg_t ch4_evt_id;
-    volatile soc_etm_ch4_task_id_reg_t ch4_task_id;
-    volatile soc_etm_ch5_evt_id_reg_t ch5_evt_id;
-    volatile soc_etm_ch5_task_id_reg_t ch5_task_id;
-    volatile soc_etm_ch6_evt_id_reg_t ch6_evt_id;
-    volatile soc_etm_ch6_task_id_reg_t ch6_task_id;
-    volatile soc_etm_ch7_evt_id_reg_t ch7_evt_id;
-    volatile soc_etm_ch7_task_id_reg_t ch7_task_id;
-    volatile soc_etm_ch8_evt_id_reg_t ch8_evt_id;
-    volatile soc_etm_ch8_task_id_reg_t ch8_task_id;
-    volatile soc_etm_ch9_evt_id_reg_t ch9_evt_id;
-    volatile soc_etm_ch9_task_id_reg_t ch9_task_id;
-    volatile soc_etm_ch10_evt_id_reg_t ch10_evt_id;
-    volatile soc_etm_ch10_task_id_reg_t ch10_task_id;
-    volatile soc_etm_ch11_evt_id_reg_t ch11_evt_id;
-    volatile soc_etm_ch11_task_id_reg_t ch11_task_id;
-    volatile soc_etm_ch12_evt_id_reg_t ch12_evt_id;
-    volatile soc_etm_ch12_task_id_reg_t ch12_task_id;
-    volatile soc_etm_ch13_evt_id_reg_t ch13_evt_id;
-    volatile soc_etm_ch13_task_id_reg_t ch13_task_id;
-    volatile soc_etm_ch14_evt_id_reg_t ch14_evt_id;
-    volatile soc_etm_ch14_task_id_reg_t ch14_task_id;
-    volatile soc_etm_ch15_evt_id_reg_t ch15_evt_id;
-    volatile soc_etm_ch15_task_id_reg_t ch15_task_id;
-    volatile soc_etm_ch16_evt_id_reg_t ch16_evt_id;
-    volatile soc_etm_ch16_task_id_reg_t ch16_task_id;
-    volatile soc_etm_ch17_evt_id_reg_t ch17_evt_id;
-    volatile soc_etm_ch17_task_id_reg_t ch17_task_id;
-    volatile soc_etm_ch18_evt_id_reg_t ch18_evt_id;
-    volatile soc_etm_ch18_task_id_reg_t ch18_task_id;
-    volatile soc_etm_ch19_evt_id_reg_t ch19_evt_id;
-    volatile soc_etm_ch19_task_id_reg_t ch19_task_id;
-    volatile soc_etm_ch20_evt_id_reg_t ch20_evt_id;
-    volatile soc_etm_ch20_task_id_reg_t ch20_task_id;
-    volatile soc_etm_ch21_evt_id_reg_t ch21_evt_id;
-    volatile soc_etm_ch21_task_id_reg_t ch21_task_id;
-    volatile soc_etm_ch22_evt_id_reg_t ch22_evt_id;
-    volatile soc_etm_ch22_task_id_reg_t ch22_task_id;
-    volatile soc_etm_ch23_evt_id_reg_t ch23_evt_id;
-    volatile soc_etm_ch23_task_id_reg_t ch23_task_id;
-    volatile soc_etm_ch24_evt_id_reg_t ch24_evt_id;
-    volatile soc_etm_ch24_task_id_reg_t ch24_task_id;
-    volatile soc_etm_ch25_evt_id_reg_t ch25_evt_id;
-    volatile soc_etm_ch25_task_id_reg_t ch25_task_id;
-    volatile soc_etm_ch26_evt_id_reg_t ch26_evt_id;
-    volatile soc_etm_ch26_task_id_reg_t ch26_task_id;
-    volatile soc_etm_ch27_evt_id_reg_t ch27_evt_id;
-    volatile soc_etm_ch27_task_id_reg_t ch27_task_id;
-    volatile soc_etm_ch28_evt_id_reg_t ch28_evt_id;
-    volatile soc_etm_ch28_task_id_reg_t ch28_task_id;
-    volatile soc_etm_ch29_evt_id_reg_t ch29_evt_id;
-    volatile soc_etm_ch29_task_id_reg_t ch29_task_id;
-    volatile soc_etm_ch30_evt_id_reg_t ch30_evt_id;
-    volatile soc_etm_ch30_task_id_reg_t ch30_task_id;
-    volatile soc_etm_ch31_evt_id_reg_t ch31_evt_id;
-    volatile soc_etm_ch31_task_id_reg_t ch31_task_id;
-    volatile soc_etm_ch32_evt_id_reg_t ch32_evt_id;
-    volatile soc_etm_ch32_task_id_reg_t ch32_task_id;
-    volatile soc_etm_ch33_evt_id_reg_t ch33_evt_id;
-    volatile soc_etm_ch33_task_id_reg_t ch33_task_id;
-    volatile soc_etm_ch34_evt_id_reg_t ch34_evt_id;
-    volatile soc_etm_ch34_task_id_reg_t ch34_task_id;
-    volatile soc_etm_ch35_evt_id_reg_t ch35_evt_id;
-    volatile soc_etm_ch35_task_id_reg_t ch35_task_id;
-    volatile soc_etm_ch36_evt_id_reg_t ch36_evt_id;
-    volatile soc_etm_ch36_task_id_reg_t ch36_task_id;
-    volatile soc_etm_ch37_evt_id_reg_t ch37_evt_id;
-    volatile soc_etm_ch37_task_id_reg_t ch37_task_id;
-    volatile soc_etm_ch38_evt_id_reg_t ch38_evt_id;
-    volatile soc_etm_ch38_task_id_reg_t ch38_task_id;
-    volatile soc_etm_ch39_evt_id_reg_t ch39_evt_id;
-    volatile soc_etm_ch39_task_id_reg_t ch39_task_id;
-    volatile soc_etm_ch40_evt_id_reg_t ch40_evt_id;
-    volatile soc_etm_ch40_task_id_reg_t ch40_task_id;
-    volatile soc_etm_ch41_evt_id_reg_t ch41_evt_id;
-    volatile soc_etm_ch41_task_id_reg_t ch41_task_id;
-    volatile soc_etm_ch42_evt_id_reg_t ch42_evt_id;
-    volatile soc_etm_ch42_task_id_reg_t ch42_task_id;
-    volatile soc_etm_ch43_evt_id_reg_t ch43_evt_id;
-    volatile soc_etm_ch43_task_id_reg_t ch43_task_id;
-    volatile soc_etm_ch44_evt_id_reg_t ch44_evt_id;
-    volatile soc_etm_ch44_task_id_reg_t ch44_task_id;
-    volatile soc_etm_ch45_evt_id_reg_t ch45_evt_id;
-    volatile soc_etm_ch45_task_id_reg_t ch45_task_id;
-    volatile soc_etm_ch46_evt_id_reg_t ch46_evt_id;
-    volatile soc_etm_ch46_task_id_reg_t ch46_task_id;
-    volatile soc_etm_ch47_evt_id_reg_t ch47_evt_id;
-    volatile soc_etm_ch47_task_id_reg_t ch47_task_id;
-    volatile soc_etm_ch48_evt_id_reg_t ch48_evt_id;
-    volatile soc_etm_ch48_task_id_reg_t ch48_task_id;
-    volatile soc_etm_ch49_evt_id_reg_t ch49_evt_id;
-    volatile soc_etm_ch49_task_id_reg_t ch49_task_id;
+    volatile struct {
+        soc_etm_chn_evt_id_reg_t evt_id;
+        soc_etm_chn_task_id_reg_t task_id;
+    } channel[50];
     volatile soc_etm_evt_st0_reg_t evt_st0;
     volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;
     volatile soc_etm_evt_st1_reg_t evt_st1;
diff --git a/components/soc/esp32c5/include/soc/spi1_mem_struct.h b/components/soc/esp32c5/include/soc/spi1_mem_struct.h
index ba4b231859..b4e6306ec2 100644
--- a/components/soc/esp32c5/include/soc/spi1_mem_struct.h
+++ b/components/soc/esp32c5/include/soc/spi1_mem_struct.h
@@ -639,18 +639,18 @@ typedef union {
 
 
 /** Group: Memory data buffer register */
-/** Type of w0 register
- *  SPI1 memory data buffer0
+/** Type of wn register
+ *  SPI1 memory data buffer n
  */
 typedef union {
     struct {
-        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
+        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
          *  data buffer
          */
-        uint32_t buf0:32;
+        uint32_t buf:32;
     };
     uint32_t val;
-} spi1_mem_w0_reg_t;
+} spi1_mem_wn_reg_t;
 
 /** Type of w1 register
  *  SPI1 memory data buffer1
@@ -1036,7 +1036,7 @@ typedef union {
 } spi1_mem_date_reg_t;
 
 
-typedef struct {
+typedef struct spi1_mem_dev_t {
     volatile spi1_mem_cmd_reg_t cmd;
     volatile spi1_mem_addr_reg_t addr;
     volatile spi1_mem_ctrl_reg_t ctrl;
@@ -1052,22 +1052,7 @@ typedef struct {
     uint32_t reserved_030;
     volatile spi1_mem_misc_reg_t misc;
     uint32_t reserved_038[8];
-    volatile spi1_mem_w0_reg_t w0;
-    volatile spi1_mem_w1_reg_t w1;
-    volatile spi1_mem_w2_reg_t w2;
-    volatile spi1_mem_w3_reg_t w3;
-    volatile spi1_mem_w4_reg_t w4;
-    volatile spi1_mem_w5_reg_t w5;
-    volatile spi1_mem_w6_reg_t w6;
-    volatile spi1_mem_w7_reg_t w7;
-    volatile spi1_mem_w8_reg_t w8;
-    volatile spi1_mem_w9_reg_t w9;
-    volatile spi1_mem_w10_reg_t w10;
-    volatile spi1_mem_w11_reg_t w11;
-    volatile spi1_mem_w12_reg_t w12;
-    volatile spi1_mem_w13_reg_t w13;
-    volatile spi1_mem_w14_reg_t w14;
-    volatile spi1_mem_w15_reg_t w15;
+    volatile spi1_mem_wn_reg_t data_buf[16];
     volatile spi1_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
     volatile spi1_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
     volatile spi1_mem_flash_sus_cmd_reg_t flash_sus_cmd;
diff --git a/components/soc/esp32c5/include/soc/spi_mem_struct.h b/components/soc/esp32c5/include/soc/spi_mem_struct.h
index 63de4bc6ee..08cd04f909 100644
--- a/components/soc/esp32c5/include/soc/spi_mem_struct.h
+++ b/components/soc/esp32c5/include/soc/spi_mem_struct.h
@@ -1946,7 +1946,7 @@ typedef union {
 } spi_mem_date_reg_t;
 
 
-typedef struct {
+typedef struct spi_mem_dev_t {
     volatile spi_mem_cmd_reg_t mem_cmd;
     uint32_t reserved_004;
     volatile spi_mem_ctrl_reg_t mem_ctrl;
diff --git a/components/soc/esp32c5/include/soc/spi_struct.h b/components/soc/esp32c5/include/soc/spi_struct.h
index 96c79c5376..6ff9c1e942 100644
--- a/components/soc/esp32c5/include/soc/spi_struct.h
+++ b/components/soc/esp32c5/include/soc/spi_struct.h
@@ -1335,18 +1335,18 @@ typedef union {
 
 
 /** Group: CPU-controlled data buffer */
-/** Type of w0 register
- *  SPI CPU-controlled buffer0
+/** Type of wn register
+ *  SPI CPU-controlled buffer n
  */
 typedef union {
     struct {
-        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
+        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
          *  data buffer
          */
-        uint32_t buf0:32;
+        uint32_t buf:32;
     };
     uint32_t val;
-} spi_w0_reg_t;
+} spi_wn_reg_t;
 
 /** Type of w1 register
  *  SPI CPU-controlled buffer1
@@ -1560,7 +1560,7 @@ typedef union {
 } spi_date_reg_t;
 
 
-typedef struct {
+typedef struct spi_dev_t {
     volatile spi_cmd_reg_t cmd;
     volatile spi_addr_reg_t addr;
     volatile spi_ctrl_reg_t ctrl;
@@ -1580,22 +1580,7 @@ typedef struct {
     volatile spi_dma_int_st_reg_t dma_int_st;
     volatile spi_dma_int_set_reg_t dma_int_set;
     uint32_t reserved_048[20];
-    volatile spi_w0_reg_t w0;
-    volatile spi_w1_reg_t w1;
-    volatile spi_w2_reg_t w2;
-    volatile spi_w3_reg_t w3;
-    volatile spi_w4_reg_t w4;
-    volatile spi_w5_reg_t w5;
-    volatile spi_w6_reg_t w6;
-    volatile spi_w7_reg_t w7;
-    volatile spi_w8_reg_t w8;
-    volatile spi_w9_reg_t w9;
-    volatile spi_w10_reg_t w10;
-    volatile spi_w11_reg_t w11;
-    volatile spi_w12_reg_t w12;
-    volatile spi_w13_reg_t w13;
-    volatile spi_w14_reg_t w14;
-    volatile spi_w15_reg_t w15;
+    volatile spi_wn_reg_t data_buf[16];
     uint32_t reserved_0d8[2];
     volatile spi_slave_reg_t slave;
     volatile spi_slave1_reg_t slave1;
diff --git a/components/soc/esp32c5/include/soc/systimer_struct.h b/components/soc/esp32c5/include/soc/systimer_struct.h
index 1bd6331870..4a987c104f 100644
--- a/components/soc/esp32c5/include/soc/systimer_struct.h
+++ b/components/soc/esp32c5/include/soc/systimer_struct.h
@@ -632,7 +632,7 @@ typedef union {
 } systimer_date_reg_t;
 
 
-typedef struct {
+typedef struct systimer_dev_t {
     volatile systimer_conf_reg_t conf;
     volatile systimer_unit0_op_reg_t unit0_op;
     volatile systimer_unit1_op_reg_t unit1_op;
diff --git a/components/soc/esp32c5/include/soc/tee_struct.h b/components/soc/esp32c5/include/soc/tee_struct.h
index f4fe27cca3..4cdb85c39c 100644
--- a/components/soc/esp32c5/include/soc/tee_struct.h
+++ b/components/soc/esp32c5/include/soc/tee_struct.h
@@ -652,7 +652,7 @@ typedef union {
 } tee_date_reg_t;
 
 
-typedef struct {
+typedef struct tee_dev_t {
     volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
     volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl;
     volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl;
diff --git a/components/soc/esp32c5/include/soc/timer_group_struct.h b/components/soc/esp32c5/include/soc/timer_group_struct.h
index b29bece720..19793e100a 100644
--- a/components/soc/esp32c5/include/soc/timer_group_struct.h
+++ b/components/soc/esp32c5/include/soc/timer_group_struct.h
@@ -509,7 +509,7 @@ typedef union {
 } timg_regclk_reg_t;
 
 
-typedef struct {
+typedef struct timg_dev_t {
     volatile timg_txconfig_reg_t t0config;
     volatile timg_txlo_reg_t t0lo;
     volatile timg_txhi_reg_t t0hi;
diff --git a/components/soc/esp32c5/include/soc/trace_struct.h b/components/soc/esp32c5/include/soc/trace_struct.h
index 08667b8cbc..66d28f93ce 100644
--- a/components/soc/esp32c5/include/soc/trace_struct.h
+++ b/components/soc/esp32c5/include/soc/trace_struct.h
@@ -428,7 +428,7 @@ typedef union {
 } trace_date_reg_t;
 
 
-typedef struct {
+typedef struct trace_dev_t {
     volatile trace_mem_start_addr_reg_t mem_start_addr;
     volatile trace_mem_end_addr_reg_t mem_end_addr;
     volatile trace_mem_current_addr_reg_t mem_current_addr;
@@ -451,6 +451,7 @@ typedef struct {
     volatile trace_date_reg_t date;
 } trace_dev_t;
 
+extern trace_dev_t TRACE;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
diff --git a/components/soc/esp32c5/include/soc/twai_reg.h b/components/soc/esp32c5/include/soc/twai_reg.h
index 9e8be8c78d..2301765caf 100644
--- a/components/soc/esp32c5/include/soc/twai_reg.h
+++ b/components/soc/esp32c5/include/soc/twai_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** TWAI_MODE_REG register
  *  TWAI mode register.
  */
-#define TWAI_MODE_REG (DR_REG_TWAI_BASE + 0x0)
+#define TWAI_MODE_REG(i) (REG_TWAI_BASE(i) + 0x0)
 /** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1;
  *  1: reset, detection of a set reset mode bit results in aborting the current
  *  transmission/reception of a message and entering the reset mode. 0: normal, on the
@@ -57,7 +57,7 @@ extern "C" {
 /** TWAI_CMD_REG register
  *  TWAI command register.
  */
-#define TWAI_CMD_REG (DR_REG_TWAI_BASE + 0x4)
+#define TWAI_CMD_REG(i) (REG_TWAI_BASE(i) + 0x4)
 /** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0;
  *  1: present, a message shall be transmitted. 0: absent
  */
@@ -99,7 +99,7 @@ extern "C" {
 /** TWAI_STATUS_REG register
  *  TWAI status register.
  */
-#define TWAI_STATUS_REG (DR_REG_TWAI_BASE + 0x8)
+#define TWAI_STATUS_REG(i) (REG_TWAI_BASE(i) + 0x8)
 /** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0;
  *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
  *  message is available
@@ -176,7 +176,7 @@ extern "C" {
 /** TWAI_INTERRUPT_REG register
  *  Interrupt signals' register.
  */
-#define TWAI_INTERRUPT_REG (DR_REG_TWAI_BASE + 0xc)
+#define TWAI_INTERRUPT_REG(i) (REG_TWAI_BASE(i) + 0xc)
 /** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0;
  *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
  *  within the interrupt enable register. 0: reset
@@ -256,7 +256,7 @@ extern "C" {
 /** TWAI_INTERRUPT_ENABLE_REG register
  *  Interrupt enable register.
  */
-#define TWAI_INTERRUPT_ENABLE_REG (DR_REG_TWAI_BASE + 0x10)
+#define TWAI_INTERRUPT_ENABLE_REG(i) (REG_TWAI_BASE(i) + 0x10)
 /** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
  *  the respective interrupt. 0: disable
@@ -333,7 +333,7 @@ extern "C" {
 /** TWAI_BUS_TIMING_0_REG register
  *  Bit timing configuration register 0.
  */
-#define TWAI_BUS_TIMING_0_REG (DR_REG_TWAI_BASE + 0x18)
+#define TWAI_BUS_TIMING_0_REG(i) (REG_TWAI_BASE(i) + 0x18)
 /** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0;
  *  The period of the TWAI system clock is programmable and determines the individual
  *  bit timing. Software has R/W permission in reset mode and RO permission in
@@ -356,7 +356,7 @@ extern "C" {
 /** TWAI_BUS_TIMING_1_REG register
  *  Bit timing configuration register 1.
  */
-#define TWAI_BUS_TIMING_1_REG (DR_REG_TWAI_BASE + 0x1c)
+#define TWAI_BUS_TIMING_1_REG(i) (REG_TWAI_BASE(i) + 0x1c)
 /** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0;
  *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
  *  reset mode and RO in operation mode.
@@ -385,7 +385,7 @@ extern "C" {
 /** TWAI_ARB_LOST_CAP_REG register
  *  TWAI arbiter lost capture register.
  */
-#define TWAI_ARB_LOST_CAP_REG (DR_REG_TWAI_BASE + 0x2c)
+#define TWAI_ARB_LOST_CAP_REG(i) (REG_TWAI_BASE(i) + 0x2c)
 /** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0;
  *  This register contains information about the bit position of losing arbitration.
  */
@@ -397,7 +397,7 @@ extern "C" {
 /** TWAI_ERR_CODE_CAP_REG register
  *  TWAI error info capture register.
  */
-#define TWAI_ERR_CODE_CAP_REG (DR_REG_TWAI_BASE + 0x30)
+#define TWAI_ERR_CODE_CAP_REG(i) (REG_TWAI_BASE(i) + 0x30)
 /** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0;
  *  This register contains information about the location of errors on the bus.
  */
@@ -423,7 +423,7 @@ extern "C" {
 /** TWAI_ERR_WARNING_LIMIT_REG register
  *  TWAI error threshold configuration register.
  */
-#define TWAI_ERR_WARNING_LIMIT_REG (DR_REG_TWAI_BASE + 0x34)
+#define TWAI_ERR_WARNING_LIMIT_REG(i) (REG_TWAI_BASE(i) + 0x34)
 /** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96;
  *  The threshold that trigger error warning interrupt when this interrupt is enabled.
  *  Software has R/W permission in reset mode and RO in operation mode.
@@ -436,7 +436,7 @@ extern "C" {
 /** TWAI_RX_ERR_CNT_REG register
  *  Rx error counter register.
  */
-#define TWAI_RX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x38)
+#define TWAI_RX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x38)
 /** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
  *  The RX error counter register reflects the current value of the transmit error
  *  counter. Software has R/W permission in reset mode and RO in operation mode.
@@ -449,7 +449,7 @@ extern "C" {
 /** TWAI_TX_ERR_CNT_REG register
  *  Tx error counter register.
  */
-#define TWAI_TX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x3c)
+#define TWAI_TX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x3c)
 /** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
  *  The TX error counter register reflects the current value of the transmit error
  *  counter. Software has R/W permission in reset mode and RO in operation mode.
@@ -462,7 +462,7 @@ extern "C" {
 /** TWAI_DATA_0_REG register
  *  Data register 0.
  */
-#define TWAI_DATA_0_REG (DR_REG_TWAI_BASE + 0x40)
+#define TWAI_DATA_0_REG(i) (REG_TWAI_BASE(i) + 0x40)
 /** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
  *  mode, when software initiate write operation, it is tx data register 0 and when
@@ -476,7 +476,7 @@ extern "C" {
 /** TWAI_DATA_1_REG register
  *  Data register 1.
  */
-#define TWAI_DATA_1_REG (DR_REG_TWAI_BASE + 0x44)
+#define TWAI_DATA_1_REG(i) (REG_TWAI_BASE(i) + 0x44)
 /** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
  *  mode, when software initiate write operation, it is tx data register 1 and when
@@ -490,7 +490,7 @@ extern "C" {
 /** TWAI_DATA_2_REG register
  *  Data register 2.
  */
-#define TWAI_DATA_2_REG (DR_REG_TWAI_BASE + 0x48)
+#define TWAI_DATA_2_REG(i) (REG_TWAI_BASE(i) + 0x48)
 /** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
  *  mode, when software initiate write operation, it is tx data register 2 and when
@@ -504,7 +504,7 @@ extern "C" {
 /** TWAI_DATA_3_REG register
  *  Data register 3.
  */
-#define TWAI_DATA_3_REG (DR_REG_TWAI_BASE + 0x4c)
+#define TWAI_DATA_3_REG(i) (REG_TWAI_BASE(i) + 0x4c)
 /** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
  *  mode, when software initiate write operation, it is tx data register 3 and when
@@ -518,7 +518,7 @@ extern "C" {
 /** TWAI_DATA_4_REG register
  *  Data register 4.
  */
-#define TWAI_DATA_4_REG (DR_REG_TWAI_BASE + 0x50)
+#define TWAI_DATA_4_REG(i) (REG_TWAI_BASE(i) + 0x50)
 /** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
  *  mode, when software initiate write operation, it is tx data register 4 and when
@@ -532,7 +532,7 @@ extern "C" {
 /** TWAI_DATA_5_REG register
  *  Data register 5.
  */
-#define TWAI_DATA_5_REG (DR_REG_TWAI_BASE + 0x54)
+#define TWAI_DATA_5_REG(i) (REG_TWAI_BASE(i) + 0x54)
 /** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
  *  mode, when software initiate write operation, it is tx data register 5 and when
@@ -546,7 +546,7 @@ extern "C" {
 /** TWAI_DATA_6_REG register
  *  Data register 6.
  */
-#define TWAI_DATA_6_REG (DR_REG_TWAI_BASE + 0x58)
+#define TWAI_DATA_6_REG(i) (REG_TWAI_BASE(i) + 0x58)
 /** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
  *  mode, when software initiate write operation, it is tx data register 6 and when
@@ -560,7 +560,7 @@ extern "C" {
 /** TWAI_DATA_7_REG register
  *  Data register 7.
  */
-#define TWAI_DATA_7_REG (DR_REG_TWAI_BASE + 0x5c)
+#define TWAI_DATA_7_REG(i) (REG_TWAI_BASE(i) + 0x5c)
 /** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
  *  mode, when software initiate write operation, it is tx data register 7 and when
@@ -574,7 +574,7 @@ extern "C" {
 /** TWAI_DATA_8_REG register
  *  Data register 8.
  */
-#define TWAI_DATA_8_REG (DR_REG_TWAI_BASE + 0x60)
+#define TWAI_DATA_8_REG(i) (REG_TWAI_BASE(i) + 0x60)
 /** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, reserved with RO. In operation mode, when software initiate write
  *  operation, it is tx data register 8 and when software initiate read operation, it
@@ -588,7 +588,7 @@ extern "C" {
 /** TWAI_DATA_9_REG register
  *  Data register 9.
  */
-#define TWAI_DATA_9_REG (DR_REG_TWAI_BASE + 0x64)
+#define TWAI_DATA_9_REG(i) (REG_TWAI_BASE(i) + 0x64)
 /** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, reserved with RO. In operation mode, when software initiate write
  *  operation, it is tx data register 9 and when software initiate read operation, it
@@ -602,7 +602,7 @@ extern "C" {
 /** TWAI_DATA_10_REG register
  *  Data register 10.
  */
-#define TWAI_DATA_10_REG (DR_REG_TWAI_BASE + 0x68)
+#define TWAI_DATA_10_REG(i) (REG_TWAI_BASE(i) + 0x68)
 /** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, reserved with RO. In operation mode, when software initiate write
  *  operation, it is tx data register 10 and when software initiate read operation, it
@@ -616,7 +616,7 @@ extern "C" {
 /** TWAI_DATA_11_REG register
  *  Data register 11.
  */
-#define TWAI_DATA_11_REG (DR_REG_TWAI_BASE + 0x6c)
+#define TWAI_DATA_11_REG(i) (REG_TWAI_BASE(i) + 0x6c)
 /** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, reserved with RO. In operation mode, when software initiate write
  *  operation, it is tx data register 11 and when software initiate read operation, it
@@ -630,7 +630,7 @@ extern "C" {
 /** TWAI_DATA_12_REG register
  *  Data register 12.
  */
-#define TWAI_DATA_12_REG (DR_REG_TWAI_BASE + 0x70)
+#define TWAI_DATA_12_REG(i) (REG_TWAI_BASE(i) + 0x70)
 /** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0;
  *  In reset mode, reserved with RO. In operation mode, when software initiate write
  *  operation, it is tx data register 12 and when software initiate read operation, it
@@ -644,7 +644,7 @@ extern "C" {
 /** TWAI_RX_MESSAGE_COUNTER_REG register
  *  Received message counter register.
  */
-#define TWAI_RX_MESSAGE_COUNTER_REG (DR_REG_TWAI_BASE + 0x74)
+#define TWAI_RX_MESSAGE_COUNTER_REG(i) (REG_TWAI_BASE(i) + 0x74)
 /** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0;
  *  Reflects the number of messages available within the RXFIFO. The value is
  *  incremented with each receive event and decremented by the release receive buffer
@@ -658,7 +658,7 @@ extern "C" {
 /** TWAI_CLOCK_DIVIDER_REG register
  *  Clock divider register.
  */
-#define TWAI_CLOCK_DIVIDER_REG (DR_REG_TWAI_BASE + 0x7c)
+#define TWAI_CLOCK_DIVIDER_REG(i) (REG_TWAI_BASE(i) + 0x7c)
 /** TWAI_CD : R/W; bitpos: [7:0]; default: 0;
  *  These bits are used to define the frequency at the external CLKOUT pin.
  */
@@ -678,7 +678,7 @@ extern "C" {
 /** TWAI_SW_STANDBY_CFG_REG register
  *  Software configure standby pin directly.
  */
-#define TWAI_SW_STANDBY_CFG_REG (DR_REG_TWAI_BASE + 0x80)
+#define TWAI_SW_STANDBY_CFG_REG(i) (REG_TWAI_BASE(i) + 0x80)
 /** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
  *  Enable standby pin.
  */
@@ -697,7 +697,7 @@ extern "C" {
 /** TWAI_HW_CFG_REG register
  *  Hardware configure standby pin.
  */
-#define TWAI_HW_CFG_REG (DR_REG_TWAI_BASE + 0x84)
+#define TWAI_HW_CFG_REG(i) (REG_TWAI_BASE(i) + 0x84)
 /** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
  *  Enable function that hardware control standby pin.
  */
@@ -709,7 +709,7 @@ extern "C" {
 /** TWAI_HW_STANDBY_CNT_REG register
  *  Configure standby counter.
  */
-#define TWAI_HW_STANDBY_CNT_REG (DR_REG_TWAI_BASE + 0x88)
+#define TWAI_HW_STANDBY_CNT_REG(i) (REG_TWAI_BASE(i) + 0x88)
 /** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1;
  *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
  *  is enabled.
@@ -722,7 +722,7 @@ extern "C" {
 /** TWAI_IDLE_INTR_CNT_REG register
  *  Configure idle interrupt counter.
  */
-#define TWAI_IDLE_INTR_CNT_REG (DR_REG_TWAI_BASE + 0x8c)
+#define TWAI_IDLE_INTR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x8c)
 /** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1;
  *  Configure the number of cycles before triggering idle interrupt.
  */
@@ -734,7 +734,7 @@ extern "C" {
 /** TWAI_ECO_CFG_REG register
  *  ECO configuration register.
  */
-#define TWAI_ECO_CFG_REG (DR_REG_TWAI_BASE + 0x90)
+#define TWAI_ECO_CFG_REG(i) (REG_TWAI_BASE(i) + 0x90)
 /** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0;
  *  Enable eco module.
  */
@@ -753,7 +753,7 @@ extern "C" {
 /** TWAI_TIMESTAMP_DATA_REG register
  *  Timestamp data register
  */
-#define TWAI_TIMESTAMP_DATA_REG (DR_REG_TWAI_BASE + 0x94)
+#define TWAI_TIMESTAMP_DATA_REG(i) (REG_TWAI_BASE(i) + 0x94)
 /** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0;
  *  Data of timestamp of a CAN frame.
  */
@@ -765,7 +765,7 @@ extern "C" {
 /** TWAI_TIMESTAMP_PRESCALER_REG register
  *  Timestamp configuration register
  */
-#define TWAI_TIMESTAMP_PRESCALER_REG (DR_REG_TWAI_BASE + 0x98)
+#define TWAI_TIMESTAMP_PRESCALER_REG(i) (REG_TWAI_BASE(i) + 0x98)
 /** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31;
  *  Configures the clock division number of timestamp counter.
  */
@@ -777,7 +777,7 @@ extern "C" {
 /** TWAI_TIMESTAMP_CFG_REG register
  *  Timestamp configuration register
  */
-#define TWAI_TIMESTAMP_CFG_REG (DR_REG_TWAI_BASE + 0x9c)
+#define TWAI_TIMESTAMP_CFG_REG(i) (REG_TWAI_BASE(i) + 0x9c)
 /** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0;
  *  enable the timestamp collection function.
  */
diff --git a/components/soc/esp32c5/include/soc/twai_struct.h b/components/soc/esp32c5/include/soc/twai_struct.h
index 2da08a0fe9..e89df67922 100644
--- a/components/soc/esp32c5/include/soc/twai_struct.h
+++ b/components/soc/esp32c5/include/soc/twai_struct.h
@@ -745,7 +745,7 @@ typedef union {
 } twai_timestamp_cfg_reg_t;
 
 
-typedef struct {
+typedef struct twai_dev_t {
     volatile twai_mode_reg_t mode;
     volatile twai_cmd_reg_t cmd;
     volatile twai_status_reg_t status;
diff --git a/components/soc/esp32c5/include/soc/uart_struct.h b/components/soc/esp32c5/include/soc/uart_struct.h
index 696e8918a3..6e3b262d6e 100644
--- a/components/soc/esp32c5/include/soc/uart_struct.h
+++ b/components/soc/esp32c5/include/soc/uart_struct.h
@@ -1216,7 +1216,7 @@ typedef union {
 } uart_id_reg_t;
 
 
-typedef struct {
+typedef struct uart_dev_t {
     volatile uart_fifo_reg_t fifo;
     volatile uart_int_raw_reg_t int_raw;
     volatile uart_int_st_reg_t int_st;
diff --git a/components/soc/esp32c5/include/soc/uhci_struct.h b/components/soc/esp32c5/include/soc/uhci_struct.h
index d6b02a72bc..1d0fa4129f 100644
--- a/components/soc/esp32c5/include/soc/uhci_struct.h
+++ b/components/soc/esp32c5/include/soc/uhci_struct.h
@@ -238,201 +238,33 @@ typedef union {
     uint32_t val;
 } uhci_quick_sent_reg_t;
 
-/** Type of reg_q0_word0 register
- *  UHCI Q0_WORD0 Quick Send Register
+/** Type of reg_qn_word0 register
+ *  UHCI QN_WORD0 Quick Send Register
  */
 typedef union {
     struct {
-        /** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
+        /** send_word0 : R/W; bitpos: [31:0]; default: 0;
          *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
          *  UHCI_SINGLE_SEND_NUM.
          */
-        uint32_t send_q0_word0:32;
+        uint32_t send_word0:32;
     };
     uint32_t val;
-} uhci_reg_q0_word0_reg_t;
+} uhci_reg_qn_word0_reg_t;
 
-/** Type of reg_q0_word1 register
- *  UHCI Q0_WORD1 Quick Send Register
+/** Type of reg_qn_word1 register
+ *  UHCI QN_WORD1 Quick Send Register
  */
 typedef union {
     struct {
-        /** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
+        /** send_word1 : R/W; bitpos: [31:0]; default: 0;
          *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
          *  UHCI_SINGLE_SEND_NUM.
          */
-        uint32_t send_q0_word1:32;
+        uint32_t send_word1:32;
     };
     uint32_t val;
-} uhci_reg_q0_word1_reg_t;
-
-/** Type of reg_q1_word0 register
- *  UHCI Q1_WORD0 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q1_word0:32;
-    };
-    uint32_t val;
-} uhci_reg_q1_word0_reg_t;
-
-/** Type of reg_q1_word1 register
- *  UHCI Q1_WORD1 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q1_word1:32;
-    };
-    uint32_t val;
-} uhci_reg_q1_word1_reg_t;
-
-/** Type of reg_q2_word0 register
- *  UHCI Q2_WORD0 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q2_word0:32;
-    };
-    uint32_t val;
-} uhci_reg_q2_word0_reg_t;
-
-/** Type of reg_q2_word1 register
- *  UHCI Q2_WORD1 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q2_word1:32;
-    };
-    uint32_t val;
-} uhci_reg_q2_word1_reg_t;
-
-/** Type of reg_q3_word0 register
- *  UHCI Q3_WORD0 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q3_word0:32;
-    };
-    uint32_t val;
-} uhci_reg_q3_word0_reg_t;
-
-/** Type of reg_q3_word1 register
- *  UHCI Q3_WORD1 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q3_word1:32;
-    };
-    uint32_t val;
-} uhci_reg_q3_word1_reg_t;
-
-/** Type of reg_q4_word0 register
- *  UHCI Q4_WORD0 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q4_word0:32;
-    };
-    uint32_t val;
-} uhci_reg_q4_word0_reg_t;
-
-/** Type of reg_q4_word1 register
- *  UHCI Q4_WORD1 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q4_word1:32;
-    };
-    uint32_t val;
-} uhci_reg_q4_word1_reg_t;
-
-/** Type of reg_q5_word0 register
- *  UHCI Q5_WORD0 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q5_word0:32;
-    };
-    uint32_t val;
-} uhci_reg_q5_word0_reg_t;
-
-/** Type of reg_q5_word1 register
- *  UHCI Q5_WORD1 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q5_word1:32;
-    };
-    uint32_t val;
-} uhci_reg_q5_word1_reg_t;
-
-/** Type of reg_q6_word0 register
- *  UHCI Q6_WORD0 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q6_word0:32;
-    };
-    uint32_t val;
-} uhci_reg_q6_word0_reg_t;
-
-/** Type of reg_q6_word1 register
- *  UHCI Q6_WORD1 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_q6_word1:32;
-    };
-    uint32_t val;
-} uhci_reg_q6_word1_reg_t;
+} uhci_reg_qn_word1_reg_t;
 
 /** Type of esc_conf0 register
  *  UHCI Escapes Sequence Configuration Register0
@@ -797,7 +629,7 @@ typedef union {
 } uhci_date_reg_t;
 
 
-typedef struct {
+typedef struct uhci_dev_t {
     volatile uhci_conf0_reg_t conf0;
     volatile uhci_int_raw_reg_t int_raw;
     volatile uhci_int_st_reg_t int_st;
@@ -811,20 +643,10 @@ typedef struct {
     volatile uhci_ack_num_reg_t ack_num;
     volatile uhci_rx_head_reg_t rx_head;
     volatile uhci_quick_sent_reg_t quick_sent;
-    volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
-    volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
-    volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
-    volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
-    volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
-    volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
-    volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
-    volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
-    volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
-    volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
-    volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
-    volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
-    volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
-    volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
+    volatile struct {
+        uhci_reg_qn_word0_reg_t word0;
+        uhci_reg_qn_word1_reg_t word1;
+    } q_data[7];
     volatile uhci_esc_conf0_reg_t esc_conf0;
     volatile uhci_esc_conf1_reg_t esc_conf1;
     volatile uhci_esc_conf2_reg_t esc_conf2;
diff --git a/components/soc/esp32c5/include/soc/usb_otg_misc_reg.h b/components/soc/esp32c5/include/soc/usb_otg_misc_reg.h
deleted file mode 100644
index c9720ce5a6..0000000000
--- a/components/soc/esp32c5/include/soc/usb_otg_misc_reg.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** USB_OTG_MISC_CLK_EN0_REG register
- *  Reserved
- */
-#define USB_OTG_MISC_CLK_EN0_REG (DR_REG_USB_OTG_MISC_BASE + 0x0)
-/** USB_OTG_MISC_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Reserved
- */
-#define USB_OTG_MISC_REG_CLK_EN    (BIT(0))
-#define USB_OTG_MISC_REG_CLK_EN_M  (USB_OTG_MISC_REG_CLK_EN_V << USB_OTG_MISC_REG_CLK_EN_S)
-#define USB_OTG_MISC_REG_CLK_EN_V  0x00000001U
-#define USB_OTG_MISC_REG_CLK_EN_S  0
-
-/** USB_OTG_MISC_DATE0_REG register
- *  Reserved
- */
-#define USB_OTG_MISC_DATE0_REG (DR_REG_USB_OTG_MISC_BASE + 0x4)
-/** USB_OTG_MISC_REG_DATE : R/W; bitpos: [31:0]; default: 23050900;
- *  Reserved
- */
-#define USB_OTG_MISC_REG_DATE    0xFFFFFFFFU
-#define USB_OTG_MISC_REG_DATE_M  (USB_OTG_MISC_REG_DATE_V << USB_OTG_MISC_REG_DATE_S)
-#define USB_OTG_MISC_REG_DATE_V  0xFFFFFFFFU
-#define USB_OTG_MISC_REG_DATE_S  0
-
-/** USB_OTG_MISC_CORE_AHB_CTRL0_REG register
- *  USB OTG core AHB bus control.
- */
-#define USB_OTG_MISC_CORE_AHB_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x8)
-/** USB_OTG_MISC_REG_CORE_S_HBIGENDIAN : R/W; bitpos: [0]; default: 0;
- *  USB OTG core AHB slave big endian mode. 1'b0: Little, 1'b1: Big.
- */
-#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN    (BIT(0))
-#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_M  (USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_V << USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_S)
-#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_V  0x00000001U
-#define USB_OTG_MISC_REG_CORE_S_HBIGENDIAN_S  0
-/** USB_OTG_MISC_REG_CORE_M_HBIGENDIAN : R/W; bitpos: [1]; default: 0;
- *  USB OTG core AHB master big endian mode. 1'b0: Little, 1'b1: Big.
- */
-#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN    (BIT(1))
-#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_M  (USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_V << USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_S)
-#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_V  0x00000001U
-#define USB_OTG_MISC_REG_CORE_M_HBIGENDIAN_S  1
-
-/** USB_OTG_MISC_DFIFO_CTRL0_REG register
- *  dfifo control.
- */
-#define USB_OTG_MISC_DFIFO_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0xc)
-/** USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  enable dfifo hclk always on.
- */
-#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON    (BIT(0))
-#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_M  (USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_V << USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_S)
-#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_V  0x00000001U
-#define USB_OTG_MISC_REG_DFIFO_HCLK_FORCE_ON_S  0
-
-/** USB_OTG_MISC_CORE_SS_CTRL0_REG register
- *  USB OTG core simulation scale control.
- */
-#define USB_OTG_MISC_CORE_SS_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x10)
-/** USB_OTG_MISC_REG_SS_SCALEDOWN_MODE : R/W; bitpos: [1:0]; default: 0;
- *  USB OTG 2.0 Core Simulation Scale Down Mode, Scale-down timing values, resulting in
- *  <faster> simulations.
- */
-#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE    0x00000003U
-#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_M  (USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_V << USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_S)
-#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_V  0x00000003U
-#define USB_OTG_MISC_REG_SS_SCALEDOWN_MODE_S  0
-
-/** USB_OTG_MISC_PHY_CTRL0_REG register
- *  USB PHY auxiliary control.
- */
-#define USB_OTG_MISC_PHY_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x14)
-/** USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE : R/W; bitpos: [0]; default: 0;
- *  Use software to override phy_pll_en.
- */
-#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE    (BIT(0))
-#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_M  (USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_V << USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_S)
-#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_PLL_EN_OVERRIDE_S  0
-/** USB_OTG_MISC_REG_PHY_PLL_EN : R/W; bitpos: [1]; default: 0;
- *  Software phy_pll_en.
- */
-#define USB_OTG_MISC_REG_PHY_PLL_EN    (BIT(1))
-#define USB_OTG_MISC_REG_PHY_PLL_EN_M  (USB_OTG_MISC_REG_PHY_PLL_EN_V << USB_OTG_MISC_REG_PHY_PLL_EN_S)
-#define USB_OTG_MISC_REG_PHY_PLL_EN_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_PLL_EN_S  1
-/** USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE : R/W; bitpos: [2]; default: 0;
- *  Use software to override phy_suspendm.
- */
-#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE    (BIT(2))
-#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_M  (USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_V << USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_S)
-#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_SUSPENDM_OVERRIDE_S  2
-/** USB_OTG_MISC_REG_PHY_SUSPENDM : R/W; bitpos: [3]; default: 0;
- *  Software phy_suspendm.
- */
-#define USB_OTG_MISC_REG_PHY_SUSPENDM    (BIT(3))
-#define USB_OTG_MISC_REG_PHY_SUSPENDM_M  (USB_OTG_MISC_REG_PHY_SUSPENDM_V << USB_OTG_MISC_REG_PHY_SUSPENDM_S)
-#define USB_OTG_MISC_REG_PHY_SUSPENDM_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_SUSPENDM_S  3
-/** USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE : R/W; bitpos: [4]; default: 0;
- *  Use software to override phy_reset_n.
- */
-#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE    (BIT(4))
-#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_M  (USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_V << USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_S)
-#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_RESET_N_OVERRIDE_S  4
-/** USB_OTG_MISC_REG_PHY_RESET_N : R/W; bitpos: [5]; default: 0;
- *  Software phy_reset_n.
- */
-#define USB_OTG_MISC_REG_PHY_RESET_N    (BIT(5))
-#define USB_OTG_MISC_REG_PHY_RESET_N_M  (USB_OTG_MISC_REG_PHY_RESET_N_V << USB_OTG_MISC_REG_PHY_RESET_N_S)
-#define USB_OTG_MISC_REG_PHY_RESET_N_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_RESET_N_S  5
-/** USB_OTG_MISC_REG_PHY_BIST_OK : RO; bitpos: [6]; default: 0;
- *  USB PHY self test done.
- */
-#define USB_OTG_MISC_REG_PHY_BIST_OK    (BIT(6))
-#define USB_OTG_MISC_REG_PHY_BIST_OK_M  (USB_OTG_MISC_REG_PHY_BIST_OK_V << USB_OTG_MISC_REG_PHY_BIST_OK_S)
-#define USB_OTG_MISC_REG_PHY_BIST_OK_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_BIST_OK_S  6
-/** USB_OTG_MISC_REG_PHY_OTG_SUSPENDM : R/W; bitpos: [7]; default: 0;
- *  USB PHY otg_suspendm.
- */
-#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM    (BIT(7))
-#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_M  (USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_V << USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_S)
-#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_OTG_SUSPENDM_S  7
-/** USB_OTG_MISC_REG_PHY_REFCLK_MODE : R/W; bitpos: [8]; default: 1;
- *  Select USB PHY refclk mode. 0: refclk is 25MHz, 1: refclk is 12MHz.
- */
-#define USB_OTG_MISC_REG_PHY_REFCLK_MODE    (BIT(8))
-#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_M  (USB_OTG_MISC_REG_PHY_REFCLK_MODE_V << USB_OTG_MISC_REG_PHY_REFCLK_MODE_S)
-#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_REFCLK_MODE_S  8
-/** USB_OTG_MISC_REG_PHY_SELF_TEST : R/W; bitpos: [9]; default: 0;
- *  USB PHY self test enable.
- */
-#define USB_OTG_MISC_REG_PHY_SELF_TEST    (BIT(9))
-#define USB_OTG_MISC_REG_PHY_SELF_TEST_M  (USB_OTG_MISC_REG_PHY_SELF_TEST_V << USB_OTG_MISC_REG_PHY_SELF_TEST_S)
-#define USB_OTG_MISC_REG_PHY_SELF_TEST_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_SELF_TEST_S  9
-/** USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE : R/W; bitpos: [10]; default: 0;
- *  USB PHY tx bitstuff enable.
- */
-#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE    (BIT(10))
-#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_M  (USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_V << USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_S)
-#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_TXBITSTUFF_ENABLE_S  10
-
-/** USB_OTG_MISC_PHY_DBG_PROBE0_REG register
- *  USB PHY debug probe register.
- */
-#define USB_OTG_MISC_PHY_DBG_PROBE0_REG (DR_REG_USB_OTG_MISC_BASE + 0x18)
-/** USB_OTG_MISC_REG_PHY_DBG_LINE_STATE : RO; bitpos: [1:0]; default: 0;
- *  Reserved.
- */
-#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE    0x00000003U
-#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_M  (USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_V << USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_S)
-#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_V  0x00000003U
-#define USB_OTG_MISC_REG_PHY_DBG_LINE_STATE_S  0
-/** USB_OTG_MISC_REG_PHY_DBG_RX_VALID : RO; bitpos: [2]; default: 0;
- *  Reserved.
- */
-#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID    (BIT(2))
-#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_M  (USB_OTG_MISC_REG_PHY_DBG_RX_VALID_V << USB_OTG_MISC_REG_PHY_DBG_RX_VALID_S)
-#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_DBG_RX_VALID_S  2
-/** USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH : RO; bitpos: [3]; default: 0;
- *  Reserved.
- */
-#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH    (BIT(3))
-#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_M  (USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_V << USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_S)
-#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_DBG_RX_VALIDH_S  3
-/** USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE : RO; bitpos: [4]; default: 0;
- *  Reserved.
- */
-#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE    (BIT(4))
-#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_M  (USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_V << USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_S)
-#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_DBG_RX_ACTIVE_S  4
-/** USB_OTG_MISC_REG_PHY_DBG_RX_ERROR : RO; bitpos: [5]; default: 0;
- *  Reserved.
- */
-#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR    (BIT(5))
-#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_M  (USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_V << USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_S)
-#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_DBG_RX_ERROR_S  5
-/** USB_OTG_MISC_REG_PHY_DBG_TX_READY : RO; bitpos: [6]; default: 0;
- *  Reserved.
- */
-#define USB_OTG_MISC_REG_PHY_DBG_TX_READY    (BIT(6))
-#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_M  (USB_OTG_MISC_REG_PHY_DBG_TX_READY_V << USB_OTG_MISC_REG_PHY_DBG_TX_READY_S)
-#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_V  0x00000001U
-#define USB_OTG_MISC_REG_PHY_DBG_TX_READY_S  6
-
-/** USB_OTG_MISC_PHY_INT_RAW_REG register
- *  Interrupt raw of USB PHY interrupt register.
- */
-#define USB_OTG_MISC_PHY_INT_RAW_REG (DR_REG_USB_OTG_MISC_BASE + 0x1c)
-/** USB_OTG_MISC_REG_IDDIG_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  Interrupt raw of reg_iddig_int_st
- */
-#define USB_OTG_MISC_REG_IDDIG_INT_RAW    (BIT(0))
-#define USB_OTG_MISC_REG_IDDIG_INT_RAW_M  (USB_OTG_MISC_REG_IDDIG_INT_RAW_V << USB_OTG_MISC_REG_IDDIG_INT_RAW_S)
-#define USB_OTG_MISC_REG_IDDIG_INT_RAW_V  0x00000001U
-#define USB_OTG_MISC_REG_IDDIG_INT_RAW_S  0
-/** USB_OTG_MISC_REG_VBUS_VALID_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  Interrupt raw of reg_vbus_valid_int_st
- */
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW    (BIT(1))
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_M  (USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_V << USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_S)
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_V  0x00000001U
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_RAW_S  1
-/** USB_OTG_MISC_REG_SESSVALID_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  Interrupt raw of reg_sessvalid_int_st
- */
-#define USB_OTG_MISC_REG_SESSVALID_INT_RAW    (BIT(2))
-#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_M  (USB_OTG_MISC_REG_SESSVALID_INT_RAW_V << USB_OTG_MISC_REG_SESSVALID_INT_RAW_S)
-#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_V  0x00000001U
-#define USB_OTG_MISC_REG_SESSVALID_INT_RAW_S  2
-/** USB_OTG_MISC_REG_SESSEND_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
- *  Interrupt raw of reg_sessend_int_st
- */
-#define USB_OTG_MISC_REG_SESSEND_INT_RAW    (BIT(3))
-#define USB_OTG_MISC_REG_SESSEND_INT_RAW_M  (USB_OTG_MISC_REG_SESSEND_INT_RAW_V << USB_OTG_MISC_REG_SESSEND_INT_RAW_S)
-#define USB_OTG_MISC_REG_SESSEND_INT_RAW_V  0x00000001U
-#define USB_OTG_MISC_REG_SESSEND_INT_RAW_S  3
-/** USB_OTG_MISC_REG_BVALID_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
- *  Interrupt raw of reg_bvalid_int_st
- */
-#define USB_OTG_MISC_REG_BVALID_INT_RAW    (BIT(4))
-#define USB_OTG_MISC_REG_BVALID_INT_RAW_M  (USB_OTG_MISC_REG_BVALID_INT_RAW_V << USB_OTG_MISC_REG_BVALID_INT_RAW_S)
-#define USB_OTG_MISC_REG_BVALID_INT_RAW_V  0x00000001U
-#define USB_OTG_MISC_REG_BVALID_INT_RAW_S  4
-/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
- *  Interrupt raw of reg_host_disconnect_int_st
- */
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW    (BIT(5))
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_M  (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_S)
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_V  0x00000001U
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_RAW_S  5
-
-/** USB_OTG_MISC_PHY_INT_CLR_REG register
- *  Interrupt clear of USB PHY interrupt register.
- */
-#define USB_OTG_MISC_PHY_INT_CLR_REG (DR_REG_USB_OTG_MISC_BASE + 0x20)
-/** USB_OTG_MISC_REG_IDDIG_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Interrupt clear of reg_iddig_int_st
- */
-#define USB_OTG_MISC_REG_IDDIG_INT_CLR    (BIT(0))
-#define USB_OTG_MISC_REG_IDDIG_INT_CLR_M  (USB_OTG_MISC_REG_IDDIG_INT_CLR_V << USB_OTG_MISC_REG_IDDIG_INT_CLR_S)
-#define USB_OTG_MISC_REG_IDDIG_INT_CLR_V  0x00000001U
-#define USB_OTG_MISC_REG_IDDIG_INT_CLR_S  0
-/** USB_OTG_MISC_REG_VBUS_VALID_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Interrupt clear of reg_vbus_valid_int_st
- */
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR    (BIT(1))
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_M  (USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_V << USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_S)
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_V  0x00000001U
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_CLR_S  1
-/** USB_OTG_MISC_REG_SESSVALID_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Interrupt clear of reg_sessvalid_int_st
- */
-#define USB_OTG_MISC_REG_SESSVALID_INT_CLR    (BIT(2))
-#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_M  (USB_OTG_MISC_REG_SESSVALID_INT_CLR_V << USB_OTG_MISC_REG_SESSVALID_INT_CLR_S)
-#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_V  0x00000001U
-#define USB_OTG_MISC_REG_SESSVALID_INT_CLR_S  2
-/** USB_OTG_MISC_REG_SESSEND_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Interrupt clear of reg_sessend_int_st
- */
-#define USB_OTG_MISC_REG_SESSEND_INT_CLR    (BIT(3))
-#define USB_OTG_MISC_REG_SESSEND_INT_CLR_M  (USB_OTG_MISC_REG_SESSEND_INT_CLR_V << USB_OTG_MISC_REG_SESSEND_INT_CLR_S)
-#define USB_OTG_MISC_REG_SESSEND_INT_CLR_V  0x00000001U
-#define USB_OTG_MISC_REG_SESSEND_INT_CLR_S  3
-/** USB_OTG_MISC_REG_BVALID_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Interrupt clear of reg_bvalid_int_st
- */
-#define USB_OTG_MISC_REG_BVALID_INT_CLR    (BIT(4))
-#define USB_OTG_MISC_REG_BVALID_INT_CLR_M  (USB_OTG_MISC_REG_BVALID_INT_CLR_V << USB_OTG_MISC_REG_BVALID_INT_CLR_S)
-#define USB_OTG_MISC_REG_BVALID_INT_CLR_V  0x00000001U
-#define USB_OTG_MISC_REG_BVALID_INT_CLR_S  4
-/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Interrupt clear of reg_host_disconnect_int_st
- */
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR    (BIT(5))
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_M  (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_S)
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_V  0x00000001U
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_CLR_S  5
-
-/** USB_OTG_MISC_PHY_INT_ENA_REG register
- *  Interrupt enable of USB PHY interrupt register.
- */
-#define USB_OTG_MISC_PHY_INT_ENA_REG (DR_REG_USB_OTG_MISC_BASE + 0x24)
-/** USB_OTG_MISC_REG_IDDIG_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Interrupt enable of reg_iddig_int_st
- */
-#define USB_OTG_MISC_REG_IDDIG_INT_ENA    (BIT(0))
-#define USB_OTG_MISC_REG_IDDIG_INT_ENA_M  (USB_OTG_MISC_REG_IDDIG_INT_ENA_V << USB_OTG_MISC_REG_IDDIG_INT_ENA_S)
-#define USB_OTG_MISC_REG_IDDIG_INT_ENA_V  0x00000001U
-#define USB_OTG_MISC_REG_IDDIG_INT_ENA_S  0
-/** USB_OTG_MISC_REG_VBUS_VALID_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Interrupt enable of reg_vbus_valid_int_st
- */
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA    (BIT(1))
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_M  (USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_V << USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_S)
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_V  0x00000001U
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_ENA_S  1
-/** USB_OTG_MISC_REG_SESSVALID_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Interrupt enable of reg_sessvalid_int_st
- */
-#define USB_OTG_MISC_REG_SESSVALID_INT_ENA    (BIT(2))
-#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_M  (USB_OTG_MISC_REG_SESSVALID_INT_ENA_V << USB_OTG_MISC_REG_SESSVALID_INT_ENA_S)
-#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_V  0x00000001U
-#define USB_OTG_MISC_REG_SESSVALID_INT_ENA_S  2
-/** USB_OTG_MISC_REG_SESSEND_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Interrupt enable of reg_sessend_int_st
- */
-#define USB_OTG_MISC_REG_SESSEND_INT_ENA    (BIT(3))
-#define USB_OTG_MISC_REG_SESSEND_INT_ENA_M  (USB_OTG_MISC_REG_SESSEND_INT_ENA_V << USB_OTG_MISC_REG_SESSEND_INT_ENA_S)
-#define USB_OTG_MISC_REG_SESSEND_INT_ENA_V  0x00000001U
-#define USB_OTG_MISC_REG_SESSEND_INT_ENA_S  3
-/** USB_OTG_MISC_REG_BVALID_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Interrupt enable of reg_bvalid_int_st
- */
-#define USB_OTG_MISC_REG_BVALID_INT_ENA    (BIT(4))
-#define USB_OTG_MISC_REG_BVALID_INT_ENA_M  (USB_OTG_MISC_REG_BVALID_INT_ENA_V << USB_OTG_MISC_REG_BVALID_INT_ENA_S)
-#define USB_OTG_MISC_REG_BVALID_INT_ENA_V  0x00000001U
-#define USB_OTG_MISC_REG_BVALID_INT_ENA_S  4
-/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Interrupt enable of reg_host_disconnect_int_st
- */
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA    (BIT(5))
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_M  (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_S)
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_V  0x00000001U
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ENA_S  5
-
-/** USB_OTG_MISC_PHY_INT_ST_REG register
- *  USB PHY interrupt register.
- */
-#define USB_OTG_MISC_PHY_INT_ST_REG (DR_REG_USB_OTG_MISC_BASE + 0x28)
-/** USB_OTG_MISC_REG_IDDIG_INT_ST : RO; bitpos: [0]; default: 0;
- *  indicates connected plug is a mini-A or mini-B.
- */
-#define USB_OTG_MISC_REG_IDDIG_INT_ST    (BIT(0))
-#define USB_OTG_MISC_REG_IDDIG_INT_ST_M  (USB_OTG_MISC_REG_IDDIG_INT_ST_V << USB_OTG_MISC_REG_IDDIG_INT_ST_S)
-#define USB_OTG_MISC_REG_IDDIG_INT_ST_V  0x00000001U
-#define USB_OTG_MISC_REG_IDDIG_INT_ST_S  0
-/** USB_OTG_MISC_REG_VBUS_VALID_INT_ST : RO; bitpos: [1]; default: 0;
- *  indicates if the voltage on VBUS is at a valid level for operation, 0: VBUS < 4.4V,
- *  1: VBUS > 4.75V.
- */
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST    (BIT(1))
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_M  (USB_OTG_MISC_REG_VBUS_VALID_INT_ST_V << USB_OTG_MISC_REG_VBUS_VALID_INT_ST_S)
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_V  0x00000001U
-#define USB_OTG_MISC_REG_VBUS_VALID_INT_ST_S  1
-/** USB_OTG_MISC_REG_SESSVALID_INT_ST : RO; bitpos: [2]; default: 0;
- *  indicates if the session for an peripheral is valid, 0: VBUS < 0.8V, 1: VBUS > 2.0V.
- */
-#define USB_OTG_MISC_REG_SESSVALID_INT_ST    (BIT(2))
-#define USB_OTG_MISC_REG_SESSVALID_INT_ST_M  (USB_OTG_MISC_REG_SESSVALID_INT_ST_V << USB_OTG_MISC_REG_SESSVALID_INT_ST_S)
-#define USB_OTG_MISC_REG_SESSVALID_INT_ST_V  0x00000001U
-#define USB_OTG_MISC_REG_SESSVALID_INT_ST_S  2
-/** USB_OTG_MISC_REG_SESSEND_INT_ST : RO; bitpos: [3]; default: 0;
- *  indicates the voltage on VBUS, 1: VBUS < 0.2V, 0: VBUS > 0.8V.
- */
-#define USB_OTG_MISC_REG_SESSEND_INT_ST    (BIT(3))
-#define USB_OTG_MISC_REG_SESSEND_INT_ST_M  (USB_OTG_MISC_REG_SESSEND_INT_ST_V << USB_OTG_MISC_REG_SESSEND_INT_ST_S)
-#define USB_OTG_MISC_REG_SESSEND_INT_ST_V  0x00000001U
-#define USB_OTG_MISC_REG_SESSEND_INT_ST_S  3
-/** USB_OTG_MISC_REG_BVALID_INT_ST : RO; bitpos: [4]; default: 0;
- *  indicates the voltage on VBUS, 0: VBUS < 0.8V, 1: VBUS > 4.0V.
- */
-#define USB_OTG_MISC_REG_BVALID_INT_ST    (BIT(4))
-#define USB_OTG_MISC_REG_BVALID_INT_ST_M  (USB_OTG_MISC_REG_BVALID_INT_ST_V << USB_OTG_MISC_REG_BVALID_INT_ST_S)
-#define USB_OTG_MISC_REG_BVALID_INT_ST_V  0x00000001U
-#define USB_OTG_MISC_REG_BVALID_INT_ST_S  4
-/** USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST : RO; bitpos: [5]; default: 0;
- *  host disconnect.
- */
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST    (BIT(5))
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_M  (USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_V << USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_S)
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_V  0x00000001U
-#define USB_OTG_MISC_REG_HOST_DISCONNECT_INT_ST_S  5
-
-/** USB_OTG_MISC_WAKEUP_CTRL0_REG register
- *  USB wakeup control.
- */
-#define USB_OTG_MISC_WAKEUP_CTRL0_REG (DR_REG_USB_OTG_MISC_BASE + 0x2c)
-/** USB_OTG_MISC_REG_USB_IN_SUSPEND : R/W; bitpos: [0]; default: 0;
- *  indicate usb is in suspend state
- */
-#define USB_OTG_MISC_REG_USB_IN_SUSPEND    (BIT(0))
-#define USB_OTG_MISC_REG_USB_IN_SUSPEND_M  (USB_OTG_MISC_REG_USB_IN_SUSPEND_V << USB_OTG_MISC_REG_USB_IN_SUSPEND_S)
-#define USB_OTG_MISC_REG_USB_IN_SUSPEND_V  0x00000001U
-#define USB_OTG_MISC_REG_USB_IN_SUSPEND_S  0
-/** USB_OTG_MISC_REG_USB_WKUP_CLR : WT; bitpos: [1]; default: 0;
- *  clear usb wakeup signals.
- */
-#define USB_OTG_MISC_REG_USB_WKUP_CLR    (BIT(1))
-#define USB_OTG_MISC_REG_USB_WKUP_CLR_M  (USB_OTG_MISC_REG_USB_WKUP_CLR_V << USB_OTG_MISC_REG_USB_WKUP_CLR_S)
-#define USB_OTG_MISC_REG_USB_WKUP_CLR_V  0x00000001U
-#define USB_OTG_MISC_REG_USB_WKUP_CLR_S  1
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/usb_otg_misc_struct.h b/components/soc/esp32c5/include/soc/usb_otg_misc_struct.h
deleted file mode 100644
index eaba6c57da..0000000000
--- a/components/soc/esp32c5/include/soc/usb_otg_misc_struct.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: clk_en */
-/** Type of clk_en0 register
- *  Reserved
- */
-typedef union {
-    struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
-         *  Reserved
-         */
-        uint32_t reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_otg_misc_clk_en0_reg_t;
-
-
-/** Group: date */
-/** Type of date0 register
- *  Reserved
- */
-typedef union {
-    struct {
-        /** reg_date : R/W; bitpos: [31:0]; default: 23050900;
-         *  Reserved
-         */
-        uint32_t reg_date:32;
-    };
-    uint32_t val;
-} usb_otg_misc_date0_reg_t;
-
-
-/** Group: core_ahb_ctrl */
-/** Type of core_ahb_ctrl0 register
- *  USB OTG core AHB bus control.
- */
-typedef union {
-    struct {
-        /** reg_core_s_hbigendian : R/W; bitpos: [0]; default: 0;
-         *  USB OTG core AHB slave big endian mode. 1'b0: Little, 1'b1: Big.
-         */
-        uint32_t reg_core_s_hbigendian:1;
-        /** reg_core_m_hbigendian : R/W; bitpos: [1]; default: 0;
-         *  USB OTG core AHB master big endian mode. 1'b0: Little, 1'b1: Big.
-         */
-        uint32_t reg_core_m_hbigendian:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} usb_otg_misc_core_ahb_ctrl0_reg_t;
-
-
-/** Group: dfifo_ctrl */
-/** Type of dfifo_ctrl0 register
- *  dfifo control.
- */
-typedef union {
-    struct {
-        /** reg_dfifo_hclk_force_on : R/W; bitpos: [0]; default: 0;
-         *  enable dfifo hclk always on.
-         */
-        uint32_t reg_dfifo_hclk_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_otg_misc_dfifo_ctrl0_reg_t;
-
-
-/** Group: core_ss_ctrl */
-/** Type of core_ss_ctrl0 register
- *  USB OTG core simulation scale control.
- */
-typedef union {
-    struct {
-        /** reg_ss_scaledown_mode : R/W; bitpos: [1:0]; default: 0;
-         *  USB OTG 2.0 Core Simulation Scale Down Mode, Scale-down timing values, resulting in
-         *  <faster> simulations.
-         */
-        uint32_t reg_ss_scaledown_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} usb_otg_misc_core_ss_ctrl0_reg_t;
-
-
-/** Group: phy_ctrl */
-/** Type of phy_ctrl0 register
- *  USB PHY auxiliary control.
- */
-typedef union {
-    struct {
-        /** reg_phy_pll_en_override : R/W; bitpos: [0]; default: 0;
-         *  Use software to override phy_pll_en.
-         */
-        uint32_t reg_phy_pll_en_override:1;
-        /** reg_phy_pll_en : R/W; bitpos: [1]; default: 0;
-         *  Software phy_pll_en.
-         */
-        uint32_t reg_phy_pll_en:1;
-        /** reg_phy_suspendm_override : R/W; bitpos: [2]; default: 0;
-         *  Use software to override phy_suspendm.
-         */
-        uint32_t reg_phy_suspendm_override:1;
-        /** reg_phy_suspendm : R/W; bitpos: [3]; default: 0;
-         *  Software phy_suspendm.
-         */
-        uint32_t reg_phy_suspendm:1;
-        /** reg_phy_reset_n_override : R/W; bitpos: [4]; default: 0;
-         *  Use software to override phy_reset_n.
-         */
-        uint32_t reg_phy_reset_n_override:1;
-        /** reg_phy_reset_n : R/W; bitpos: [5]; default: 0;
-         *  Software phy_reset_n.
-         */
-        uint32_t reg_phy_reset_n:1;
-        /** reg_phy_bist_ok : RO; bitpos: [6]; default: 0;
-         *  USB PHY self test done.
-         */
-        uint32_t reg_phy_bist_ok:1;
-        /** reg_phy_otg_suspendm : R/W; bitpos: [7]; default: 0;
-         *  USB PHY otg_suspendm.
-         */
-        uint32_t reg_phy_otg_suspendm:1;
-        /** reg_phy_refclk_mode : R/W; bitpos: [8]; default: 1;
-         *  Select USB PHY refclk mode. 0: refclk is 25MHz, 1: refclk is 12MHz.
-         */
-        uint32_t reg_phy_refclk_mode:1;
-        /** reg_phy_self_test : R/W; bitpos: [9]; default: 0;
-         *  USB PHY self test enable.
-         */
-        uint32_t reg_phy_self_test:1;
-        /** reg_phy_txbitstuff_enable : R/W; bitpos: [10]; default: 0;
-         *  USB PHY tx bitstuff enable.
-         */
-        uint32_t reg_phy_txbitstuff_enable:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} usb_otg_misc_phy_ctrl0_reg_t;
-
-
-/** Group: phy_dbg_probe */
-/** Type of phy_dbg_probe0 register
- *  USB PHY debug probe register.
- */
-typedef union {
-    struct {
-        /** reg_phy_dbg_line_state : RO; bitpos: [1:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t reg_phy_dbg_line_state:2;
-        /** reg_phy_dbg_rx_valid : RO; bitpos: [2]; default: 0;
-         *  Reserved.
-         */
-        uint32_t reg_phy_dbg_rx_valid:1;
-        /** reg_phy_dbg_rx_validh : RO; bitpos: [3]; default: 0;
-         *  Reserved.
-         */
-        uint32_t reg_phy_dbg_rx_validh:1;
-        /** reg_phy_dbg_rx_active : RO; bitpos: [4]; default: 0;
-         *  Reserved.
-         */
-        uint32_t reg_phy_dbg_rx_active:1;
-        /** reg_phy_dbg_rx_error : RO; bitpos: [5]; default: 0;
-         *  Reserved.
-         */
-        uint32_t reg_phy_dbg_rx_error:1;
-        /** reg_phy_dbg_tx_ready : RO; bitpos: [6]; default: 0;
-         *  Reserved.
-         */
-        uint32_t reg_phy_dbg_tx_ready:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} usb_otg_misc_phy_dbg_probe0_reg_t;
-
-
-/** Group: Interrupt */
-/** Type of phy_int_raw register
- *  Interrupt raw of USB PHY interrupt register.
- */
-typedef union {
-    struct {
-        /** reg_iddig_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  Interrupt raw of reg_iddig_int_st
-         */
-        uint32_t reg_iddig_int_raw:1;
-        /** reg_vbus_valid_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  Interrupt raw of reg_vbus_valid_int_st
-         */
-        uint32_t reg_vbus_valid_int_raw:1;
-        /** reg_sessvalid_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
-         *  Interrupt raw of reg_sessvalid_int_st
-         */
-        uint32_t reg_sessvalid_int_raw:1;
-        /** reg_sessend_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
-         *  Interrupt raw of reg_sessend_int_st
-         */
-        uint32_t reg_sessend_int_raw:1;
-        /** reg_bvalid_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
-         *  Interrupt raw of reg_bvalid_int_st
-         */
-        uint32_t reg_bvalid_int_raw:1;
-        /** reg_host_disconnect_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
-         *  Interrupt raw of reg_host_disconnect_int_st
-         */
-        uint32_t reg_host_disconnect_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} usb_otg_misc_phy_int_raw_reg_t;
-
-/** Type of phy_int_clr register
- *  Interrupt clear of USB PHY interrupt register.
- */
-typedef union {
-    struct {
-        /** reg_iddig_int_clr : WT; bitpos: [0]; default: 0;
-         *  Interrupt clear of reg_iddig_int_st
-         */
-        uint32_t reg_iddig_int_clr:1;
-        /** reg_vbus_valid_int_clr : WT; bitpos: [1]; default: 0;
-         *  Interrupt clear of reg_vbus_valid_int_st
-         */
-        uint32_t reg_vbus_valid_int_clr:1;
-        /** reg_sessvalid_int_clr : WT; bitpos: [2]; default: 0;
-         *  Interrupt clear of reg_sessvalid_int_st
-         */
-        uint32_t reg_sessvalid_int_clr:1;
-        /** reg_sessend_int_clr : WT; bitpos: [3]; default: 0;
-         *  Interrupt clear of reg_sessend_int_st
-         */
-        uint32_t reg_sessend_int_clr:1;
-        /** reg_bvalid_int_clr : WT; bitpos: [4]; default: 0;
-         *  Interrupt clear of reg_bvalid_int_st
-         */
-        uint32_t reg_bvalid_int_clr:1;
-        /** reg_host_disconnect_int_clr : WT; bitpos: [5]; default: 0;
-         *  Interrupt clear of reg_host_disconnect_int_st
-         */
-        uint32_t reg_host_disconnect_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} usb_otg_misc_phy_int_clr_reg_t;
-
-/** Type of phy_int_ena register
- *  Interrupt enable of USB PHY interrupt register.
- */
-typedef union {
-    struct {
-        /** reg_iddig_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Interrupt enable of reg_iddig_int_st
-         */
-        uint32_t reg_iddig_int_ena:1;
-        /** reg_vbus_valid_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Interrupt enable of reg_vbus_valid_int_st
-         */
-        uint32_t reg_vbus_valid_int_ena:1;
-        /** reg_sessvalid_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Interrupt enable of reg_sessvalid_int_st
-         */
-        uint32_t reg_sessvalid_int_ena:1;
-        /** reg_sessend_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Interrupt enable of reg_sessend_int_st
-         */
-        uint32_t reg_sessend_int_ena:1;
-        /** reg_bvalid_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Interrupt enable of reg_bvalid_int_st
-         */
-        uint32_t reg_bvalid_int_ena:1;
-        /** reg_host_disconnect_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Interrupt enable of reg_host_disconnect_int_st
-         */
-        uint32_t reg_host_disconnect_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} usb_otg_misc_phy_int_ena_reg_t;
-
-/** Type of phy_int_st register
- *  USB PHY interrupt register.
- */
-typedef union {
-    struct {
-        /** reg_iddig_int_st : RO; bitpos: [0]; default: 0;
-         *  indicates connected plug is a mini-A or mini-B.
-         */
-        uint32_t reg_iddig_int_st:1;
-        /** reg_vbus_valid_int_st : RO; bitpos: [1]; default: 0;
-         *  indicates if the voltage on VBUS is at a valid level for operation, 0: VBUS < 4.4V,
-         *  1: VBUS > 4.75V.
-         */
-        uint32_t reg_vbus_valid_int_st:1;
-        /** reg_sessvalid_int_st : RO; bitpos: [2]; default: 0;
-         *  indicates if the session for an peripheral is valid, 0: VBUS < 0.8V, 1: VBUS > 2.0V.
-         */
-        uint32_t reg_sessvalid_int_st:1;
-        /** reg_sessend_int_st : RO; bitpos: [3]; default: 0;
-         *  indicates the voltage on VBUS, 1: VBUS < 0.2V, 0: VBUS > 0.8V.
-         */
-        uint32_t reg_sessend_int_st:1;
-        /** reg_bvalid_int_st : RO; bitpos: [4]; default: 0;
-         *  indicates the voltage on VBUS, 0: VBUS < 0.8V, 1: VBUS > 4.0V.
-         */
-        uint32_t reg_bvalid_int_st:1;
-        /** reg_host_disconnect_int_st : RO; bitpos: [5]; default: 0;
-         *  host disconnect.
-         */
-        uint32_t reg_host_disconnect_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} usb_otg_misc_phy_int_st_reg_t;
-
-
-/** Group: wakeup_ctrl */
-/** Type of wakeup_ctrl0 register
- *  USB wakeup control.
- */
-typedef union {
-    struct {
-        /** reg_usb_in_suspend : R/W; bitpos: [0]; default: 0;
-         *  indicate usb is in suspend state
-         */
-        uint32_t reg_usb_in_suspend:1;
-        /** reg_usb_wkup_clr : WT; bitpos: [1]; default: 0;
-         *  clear usb wakeup signals.
-         */
-        uint32_t reg_usb_wkup_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} usb_otg_misc_wakeup_ctrl0_reg_t;
-
-
-typedef struct {
-    volatile usb_otg_misc_clk_en0_reg_t clk_en0;
-    volatile usb_otg_misc_date0_reg_t date0;
-    volatile usb_otg_misc_core_ahb_ctrl0_reg_t core_ahb_ctrl0;
-    volatile usb_otg_misc_dfifo_ctrl0_reg_t dfifo_ctrl0;
-    volatile usb_otg_misc_core_ss_ctrl0_reg_t core_ss_ctrl0;
-    volatile usb_otg_misc_phy_ctrl0_reg_t phy_ctrl0;
-    volatile usb_otg_misc_phy_dbg_probe0_reg_t phy_dbg_probe0;
-    volatile usb_otg_misc_phy_int_raw_reg_t phy_int_raw;
-    volatile usb_otg_misc_phy_int_clr_reg_t phy_int_clr;
-    volatile usb_otg_misc_phy_int_ena_reg_t phy_int_ena;
-    volatile usb_otg_misc_phy_int_st_reg_t phy_int_st;
-    volatile usb_otg_misc_wakeup_ctrl0_reg_t wakeup_ctrl0;
-} usb_otg_misc_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(usb_otg_misc_dev_t) == 0x30, "Invalid size of usb_otg_misc_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
index 3c3442301b..3c87b7a813 100644
--- a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
+++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
@@ -898,7 +898,7 @@ typedef union {
 } usb_serial_jtag_date_reg_t;
 
 
-typedef struct {
+typedef struct usb_serial_jtag_dev_t {
     volatile usb_serial_jtag_ep1_reg_t ep1;
     volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
     volatile usb_serial_jtag_int_raw_reg_t int_raw;
diff --git a/components/soc/esp32c5/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/ld/esp32c5.peripherals.ld
index eea6217a66..2228855965 100644
--- a/components/soc/esp32c5/ld/esp32c5.peripherals.ld
+++ b/components/soc/esp32c5/ld/esp32c5.peripherals.ld
@@ -1,78 +1,82 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 
-PROVIDE ( UART0             = 0x60000000 );
-PROVIDE ( UART1             = 0x60001000 );
-PROVIDE ( SPIMEM0           = 0x60002000 );
-PROVIDE ( SPIMEM1           = 0x60003000 );
-PROVIDE ( I2C0              = 0x60004000 );
-PROVIDE ( UHCI0             = 0x60005000 );
-PROVIDE ( RMT               = 0x60006000 );
-PROVIDE ( RMTMEM            = 0x60006400 );
-PROVIDE ( LEDC              = 0x60007000 );
-PROVIDE ( TIMERG0           = 0x60008000 );
-PROVIDE ( TIMERG1           = 0x60009000 );
-PROVIDE ( SYSTIMER          = 0x6000A000 );
-PROVIDE ( TWAI0             = 0x6000B000 );
-PROVIDE ( I2S0              = 0x6000C000 );
-PROVIDE ( TWAI1             = 0x6000D000 );
-PROVIDE ( APB_SARADC        = 0x6000E000 );
-PROVIDE ( USB_SERIAL_JTAG   = 0x6000F000 );
+PROVIDE ( UART0               = 0x60000000 );
+PROVIDE ( UART1               = 0x60001000 );
+PROVIDE ( SPIMEM0             = 0x60002000 );
+PROVIDE ( SPIMEM1             = 0x60003000 );
+PROVIDE ( I2C0                = 0x60004000 );
+PROVIDE ( UHCI0               = 0x60005000 );
+PROVIDE ( RMT                 = 0x60006000 );
+PROVIDE ( LEDC                = 0x60007000 );
+PROVIDE ( TIMERG0             = 0x60008000 );
+PROVIDE ( TIMERG1             = 0x60009000 );
+PROVIDE ( SYSTIMER            = 0x6000A000 );
+PROVIDE ( TWAI0               = 0x6000B000 );
+PROVIDE ( I2S                 = 0x6000C000 );
+PROVIDE ( TWAI1               = 0x6000D000 );
+PROVIDE ( APB_SARADC          = 0x6000E000 );
+PROVIDE ( USB_SERIAL_JTAG     = 0x6000F000 );
+PROVIDE ( INTMTX              = 0x60010000 );
+PROVIDE ( I2C1                = 0x60011000 );
+PROVIDE ( PCNT                = 0x60012000 );
+PROVIDE ( SOC_ETM             = 0x60013000 );
+PROVIDE ( MCPWM               = 0x60014000 );
+PROVIDE ( PARL_IO             = 0x60015000 );
+PROVIDE ( PVT_MONITOR         = 0x60019000 );
 
-PROVIDE ( INTMTX        = 0x60010000 );
-PROVIDE ( ATOMIC_LOCKER = 0x60011000 );
-PROVIDE ( PCNT          = 0x60012000 );
-PROVIDE ( SOC_ETM       = 0x60013000 );
-PROVIDE ( MCPWM0        = 0x60014000 );
-PROVIDE ( PARL_IO       = 0x60015000 );
-PROVIDE ( HINF          = 0x60016000 );
-PROVIDE ( SLC           = 0x60017000 );
-PROVIDE ( HOST          = 0x60018000 );
-PROVIDE ( PVT_MONITOR   = 0x60019000 );
+PROVIDE ( GDMA                = 0x60080000 );
+PROVIDE ( GPSPI2              = 0x60081000 );
+PROVIDE ( BITSCRAMBLER        = 0x60082000 );
+PROVIDE ( KEYMNG              = 0x60087000 );
+PROVIDE ( AES                 = 0x60088000 );
+PROVIDE ( SHA                 = 0x60089000 );
+PROVIDE ( RSA                 = 0x6008A000 );
+PROVIDE ( ECC                 = 0x6008B000 );
+PROVIDE ( DS                  = 0x6008C000 );
+PROVIDE ( HMAC                = 0x6008D000 );
+PROVIDE ( ECDSA               = 0x6008E000 );
 
-PROVIDE ( GDMA      = 0x60080000 );
-PROVIDE ( GPSPI2    = 0x60081000 );
+PROVIDE ( IO_MUX              = 0x60090000 );
+PROVIDE ( GPIO                = 0x60091000 );
+PROVIDE ( GPIO_EXT            = 0x60091f00 );
+PROVIDE ( SDM                 = 0x60091f00 );
+PROVIDE ( GLITCH_FILTER       = 0x60091f30 );
+PROVIDE ( GPIO_ETM            = 0x60091f60 );
+PROVIDE ( MEM_MONITOR         = 0x60092000 );
+PROVIDE ( PAU                 = 0x60093000 );
+PROVIDE ( HP_SYSTEM           = 0x60095000 );
+PROVIDE ( PCR                 = 0x60096000 );
+PROVIDE ( TEE                 = 0x60098000 );
+PROVIDE ( HP_APM              = 0x60099000 );
+PROVIDE ( LP_APM0             = 0x60099800 );
+PROVIDE ( MISC                = 0x6009F000 );
 
-PROVIDE ( AES       = 0x60088000 );
-PROVIDE ( SHA       = 0x60089000 );
-PROVIDE ( RSA       = 0x6008A000 );
-PROVIDE ( ECC       = 0x6008B000 );
-PROVIDE ( DS        = 0x6008C000 );
-PROVIDE ( HMAC      = 0x6008D000 );
+PROVIDE ( MODEM               = 0x600A4000 );
+PROVIDE ( MODEM_PWR           = 0x600AD000 );
 
-PROVIDE ( IO_MUX         = 0x60090000 );
-PROVIDE ( GPIO           = 0x60091000 );
-PROVIDE ( GPIO_EXT       = 0x60091f00 );
-PROVIDE ( SDM            = 0x60091f00 );
-PROVIDE ( GLITCH_FILTER  = 0x60091f30 );
-PROVIDE ( GPIO_ETM       = 0x60091f60 );
+PROVIDE ( PMU                 = 0x600B0000 );
+PROVIDE ( LP_CLKRST           = 0x600B0400 );
+PROVIDE ( EFUSE               = 0x600B0800 );
+PROVIDE ( LP_TIMER            = 0x600B0C00 );
+PROVIDE ( LP_AON              = 0x600B1000 );
+PROVIDE ( LP_UART             = 0x600B1400 );
+PROVIDE ( LP_I2C              = 0x600B1800 );
+PROVIDE ( LP_WDT              = 0x600B1C00 );
+PROVIDE ( LP_IO               = 0x600B2000 );
+PROVIDE ( LP_I2C_ANA_MST      = 0x600B2400 );
+PROVIDE ( LPPERI              = 0x600B2800 );
+PROVIDE ( LP_ANA_PERI         = 0x600B2C00 );
+PROVIDE ( HUK                 = 0x600B3000 );
+PROVIDE ( LP_TEE              = 0x600B3400 );
+PROVIDE ( LP_APM              = 0x600B3800 );
+PROVIDE ( OTP_DEBUG           = 0x600B3C00 );
 
-PROVIDE ( MEM_MONITOR       = 0x60092000 );
-PROVIDE ( PAU               = 0x60093000 );
-PROVIDE ( HP_SYSTEM         = 0x60095000 );
-PROVIDE ( PCR               = 0x60096000 );
-PROVIDE ( TEE               = 0x60098000 );
-PROVIDE ( HP_APM            = 0x60099000 );
-
-PROVIDE ( IEEE802154    = 0x600A3000 );
-PROVIDE ( MODEM_SYSCON  = 0x600A9800 );
-PROVIDE ( MODEM_LPCON   = 0x600AF000 );
-
-PROVIDE ( PMU           = 0x600B0000 );
-PROVIDE ( LP_CLKRST     = 0x600B0400 );
-PROVIDE ( EFUSE         = 0x600B0800 );
-PROVIDE ( LP_TIMER      = 0x600B0C00 );
-PROVIDE ( LP_AON        = 0x600B1000 );
-PROVIDE ( LP_UART       = 0x600B1400 );
-PROVIDE ( LP_I2C        = 0x600B1800 );
-PROVIDE ( LP_WDT        = 0x600B1C00 );
-PROVIDE ( LP_IO         = 0x600B2000 );
-PROVIDE ( LP_I2C_ANA_MST = 0x600B2400 );
-PROVIDE ( LPPERI        = 0x600B2800 );
-PROVIDE ( LP_ANA_PERI   = 0x600B2C00 );
-PROVIDE ( LP_APM        = 0x600B3800 );
-PROVIDE ( OTP_DEBUG     = 0x600B3C00 );
+PROVIDE ( TRACE               = 0x600C0000 );
+PROVIDE ( ASSIST_DEBUG        = 0x600C2000 );
+PROVIDE ( INTPRI              = 0x600C5000 );
+PROVIDE ( CACHE               = 0x600C8000 );

From 40bce1334850951388bd2d14a25a422cb9a69d1c Mon Sep 17 00:00:00 2001
From: laokaiyao <laokaiyao@espressif.com>
Date: Thu, 30 Nov 2023 17:43:01 +0800
Subject: [PATCH 2/2] feat(esp32c5): update reg headers for multiple instances
 module (part3)

---
 .../soc/esp32c5/include/soc/pcnt_struct.h     |  86 +------
 .../soc/esp32c5/include/soc/timer_group_reg.h |  52 ++--
 .../soc/esp32c5/include/soc/twai_struct.h     | 236 ++----------------
 components/soc/esp32c5/include/soc/uart_reg.h |  76 +++---
 4 files changed, 102 insertions(+), 348 deletions(-)

diff --git a/components/soc/esp32c5/include/soc/pcnt_struct.h b/components/soc/esp32c5/include/soc/pcnt_struct.h
index 65de09bb12..ce929f709e 100644
--- a/components/soc/esp32c5/include/soc/pcnt_struct.h
+++ b/components/soc/esp32c5/include/soc/pcnt_struct.h
@@ -213,74 +213,22 @@ typedef union {
     uint32_t val;
 } pcnt_ctrl_reg_t;
 
-/** Type of u3_change_conf register
+/** Type of change_conf register
  *  Configuration register for unit $n's step value.
  */
 typedef union {
     struct {
-        /** cnt_step_u3 : R/W; bitpos: [15:0]; default: 0;
+        /** cnt_step : R/W; bitpos: [15:0]; default: 0;
          *  Configures the step value for unit 3.
          */
-        uint32_t cnt_step_u3:16;
-        /** cnt_step_lim_u3 : R/W; bitpos: [31:16]; default: 0;
+        uint32_t cnt_step:16;
+        /** cnt_step_lim : R/W; bitpos: [31:16]; default: 0;
          *  Configures the step limit value for unit 3.
          */
-        uint32_t cnt_step_lim_u3:16;
+        uint32_t cnt_step_lim:16;
     };
     uint32_t val;
-} pcnt_u3_change_conf_reg_t;
-
-/** Type of u2_change_conf register
- *  Configuration register for unit $n's step value.
- */
-typedef union {
-    struct {
-        /** cnt_step_u2 : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the step value for unit 2.
-         */
-        uint32_t cnt_step_u2:16;
-        /** cnt_step_lim_u2 : R/W; bitpos: [31:16]; default: 0;
-         *  Configures the step limit value for unit 2.
-         */
-        uint32_t cnt_step_lim_u2:16;
-    };
-    uint32_t val;
-} pcnt_u2_change_conf_reg_t;
-
-/** Type of u1_change_conf register
- *  Configuration register for unit $n's step value.
- */
-typedef union {
-    struct {
-        /** cnt_step_u1 : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the step value for unit 1.
-         */
-        uint32_t cnt_step_u1:16;
-        /** cnt_step_lim_u1 : R/W; bitpos: [31:16]; default: 0;
-         *  Configures the step limit value for unit 1.
-         */
-        uint32_t cnt_step_lim_u1:16;
-    };
-    uint32_t val;
-} pcnt_u1_change_conf_reg_t;
-
-/** Type of u0_change_conf register
- *  Configuration register for unit $n's step value.
- */
-typedef union {
-    struct {
-        /** cnt_step_u0 : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the step value for unit 0.
-         */
-        uint32_t cnt_step_u0:16;
-        /** cnt_step_lim_u0 : R/W; bitpos: [31:16]; default: 0;
-         *  Configures the step limit value for unit 0.
-         */
-        uint32_t cnt_step_lim_u0:16;
-    };
-    uint32_t val;
-} pcnt_u0_change_conf_reg_t;
-
+} pcnt_un_change_conf_reg_t;
 
 /** Group: Status Register */
 /** Type of un_cnt register
@@ -466,18 +414,11 @@ typedef union {
 
 
 typedef struct pcnt_dev_t {
-    volatile pcnt_un_conf0_reg_t u0_conf0;
-    volatile pcnt_un_conf1_reg_t u0_conf1;
-    volatile pcnt_un_conf2_reg_t u0_conf2;
-    volatile pcnt_un_conf0_reg_t u1_conf0;
-    volatile pcnt_un_conf1_reg_t u1_conf1;
-    volatile pcnt_un_conf2_reg_t u1_conf2;
-    volatile pcnt_un_conf0_reg_t u2_conf0;
-    volatile pcnt_un_conf1_reg_t u2_conf1;
-    volatile pcnt_un_conf2_reg_t u2_conf2;
-    volatile pcnt_un_conf0_reg_t u3_conf0;
-    volatile pcnt_un_conf1_reg_t u3_conf1;
-    volatile pcnt_un_conf2_reg_t u3_conf2;
+    volatile struct {
+        pcnt_un_conf0_reg_t conf0;
+        pcnt_un_conf1_reg_t conf1;
+        pcnt_un_conf2_reg_t conf2;
+    } conf_unit[4];
     volatile pcnt_un_cnt_reg_t un_cnt[4];
     volatile pcnt_int_raw_reg_t int_raw;
     volatile pcnt_int_st_reg_t int_st;
@@ -485,10 +426,7 @@ typedef struct pcnt_dev_t {
     volatile pcnt_int_clr_reg_t int_clr;
     volatile pcnt_un_status_reg_t un_status[4];
     volatile pcnt_ctrl_reg_t ctrl;
-    volatile pcnt_u3_change_conf_reg_t u3_change_conf;
-    volatile pcnt_u2_change_conf_reg_t u2_change_conf;
-    volatile pcnt_u1_change_conf_reg_t u1_change_conf;
-    volatile pcnt_u0_change_conf_reg_t u0_change_conf;
+    volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210
     uint32_t reserved_074[34];
     volatile pcnt_date_reg_t date;
 } pcnt_dev_t;
diff --git a/components/soc/esp32c5/include/soc/timer_group_reg.h b/components/soc/esp32c5/include/soc/timer_group_reg.h
index 4d3f13661b..97a10ff9f0 100644
--- a/components/soc/esp32c5/include/soc/timer_group_reg.h
+++ b/components/soc/esp32c5/include/soc/timer_group_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
  */
-#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
+#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
 /** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
  *  When set, the alarm is enabled. This bit is automatically cleared once an
  *  alarm occurs.
@@ -63,7 +63,7 @@ extern "C" {
 /** TIMG_T0LO_REG register
  *  Timer 0 current value, low 32 bits
  */
-#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
+#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
 /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
  *  of timer 0 can be read here.
@@ -76,7 +76,7 @@ extern "C" {
 /** TIMG_T0HI_REG register
  *  Timer 0 current value, high 22 bits
  */
-#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
+#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
 /** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
  *  After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
  *  of timer 0 can be read here.
@@ -89,7 +89,7 @@ extern "C" {
 /** TIMG_T0UPDATE_REG register
  *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
  */
-#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
+#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
 /** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
  *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
  */
@@ -101,7 +101,7 @@ extern "C" {
 /** TIMG_T0ALARMLO_REG register
  *  Timer 0 alarm value, low 32 bits
  */
-#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
+#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
 /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
  *  Timer 0 alarm trigger time-base counter value, low 32 bits.
  */
@@ -113,7 +113,7 @@ extern "C" {
 /** TIMG_T0ALARMHI_REG register
  *  Timer 0 alarm value, high bits
  */
-#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
+#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
 /** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
  *  Timer 0 alarm trigger time-base counter value, high 22 bits.
  */
@@ -125,7 +125,7 @@ extern "C" {
 /** TIMG_T0LOADLO_REG register
  *  Timer 0 reload value, low 32 bits
  */
-#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
+#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
 /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
  *  Low 32 bits of the value that a reload will load onto timer 0 time-base
  *  Counter.
@@ -138,7 +138,7 @@ extern "C" {
 /** TIMG_T0LOADHI_REG register
  *  Timer 0 reload value, high 22 bits
  */
-#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
+#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
 /** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
  *  High 22 bits of the value that a reload will load onto timer 0 time-base
  *  counter.
@@ -151,7 +151,7 @@ extern "C" {
 /** TIMG_T0LOAD_REG register
  *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
  */
-#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
+#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
 /** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
  *
  *  Write any value to trigger a timer 0 time-base counter reload.
@@ -164,7 +164,7 @@ extern "C" {
 /** TIMG_WDTCONFIG0_REG register
  *  Watchdog timer configuration register
  */
-#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
+#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
 /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
  *  WDT reset CPU enable.
  */
@@ -248,7 +248,7 @@ extern "C" {
 /** TIMG_WDTCONFIG1_REG register
  *  Watchdog timer prescaler register
  */
-#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
+#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
 /** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
  *  When set, WDT 's clock divider counter will be reset.
  */
@@ -268,7 +268,7 @@ extern "C" {
 /** TIMG_WDTCONFIG2_REG register
  *  Watchdog timer stage 0 timeout value
  */
-#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
+#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
 /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
  *  Stage 0 timeout value, in MWDT clock cycles.
  */
@@ -280,7 +280,7 @@ extern "C" {
 /** TIMG_WDTCONFIG3_REG register
  *  Watchdog timer stage 1 timeout value
  */
-#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
+#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
 /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
  *  Stage 1 timeout value, in MWDT clock cycles.
  */
@@ -292,7 +292,7 @@ extern "C" {
 /** TIMG_WDTCONFIG4_REG register
  *  Watchdog timer stage 2 timeout value
  */
-#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
+#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
 /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 2 timeout value, in MWDT clock cycles.
  */
@@ -304,7 +304,7 @@ extern "C" {
 /** TIMG_WDTCONFIG5_REG register
  *  Watchdog timer stage 3 timeout value
  */
-#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
+#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
 /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 3 timeout value, in MWDT clock cycles.
  */
@@ -316,7 +316,7 @@ extern "C" {
 /** TIMG_WDTFEED_REG register
  *  Write to feed the watchdog timer
  */
-#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
+#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
 /** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
  *  Write any value to feed the MWDT. (WO)
  */
@@ -328,7 +328,7 @@ extern "C" {
 /** TIMG_WDTWPROTECT_REG register
  *  Watchdog write protect register
  */
-#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
+#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
 /** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
  *  If the register contains a different value than its reset value, write
  *  protection is enabled.
@@ -341,7 +341,7 @@ extern "C" {
 /** TIMG_RTCCALICFG_REG register
  *  RTC calibration configure register
  */
-#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68)
+#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
 /** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
  *  0: one-shot frequency calculation,1: periodic frequency calculation,
  */
@@ -381,7 +381,7 @@ extern "C" {
 /** TIMG_RTCCALICFG1_REG register
  *  RTC calibration configure1 register
  */
-#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c)
+#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
 /** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
  *  indicate periodic frequency calculation is done.
  */
@@ -401,7 +401,7 @@ extern "C" {
 /** TIMG_INT_ENA_TIMERS_REG register
  *  Interrupt enable bits
  */
-#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
+#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
 /** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
  */
@@ -420,7 +420,7 @@ extern "C" {
 /** TIMG_INT_RAW_TIMERS_REG register
  *  Raw interrupt status
  */
-#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
+#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
 /** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
  *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
  */
@@ -439,7 +439,7 @@ extern "C" {
 /** TIMG_INT_ST_TIMERS_REG register
  *  Masked interrupt status
  */
-#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
+#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
 /** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
  *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
  */
@@ -458,7 +458,7 @@ extern "C" {
 /** TIMG_INT_CLR_TIMERS_REG register
  *  Interrupt clear bits
  */
-#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
+#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
 /** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Set this bit to clear the TIMG_T$x_INT interrupt.
  */
@@ -477,7 +477,7 @@ extern "C" {
 /** TIMG_RTCCALICFG2_REG register
  *  Timer group calibration register
  */
-#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80)
+#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
 /** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
  *  RTC calibration timeout indicator
  */
@@ -504,7 +504,7 @@ extern "C" {
 /** TIMG_NTIMERS_DATE_REG register
  *  Timer version control register
  */
-#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
+#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
 /** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
  *  Timer version control register
  */
@@ -516,7 +516,7 @@ extern "C" {
 /** TIMG_REGCLK_REG register
  *  Timer group clock gate register
  */
-#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
+#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
 /** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
  *  enable timer's etm task and event
  */
diff --git a/components/soc/esp32c5/include/soc/twai_struct.h b/components/soc/esp32c5/include/soc/twai_struct.h
index e89df67922..bc3be7f3f4 100644
--- a/components/soc/esp32c5/include/soc/twai_struct.h
+++ b/components/soc/esp32c5/include/soc/twai_struct.h
@@ -493,213 +493,21 @@ typedef union {
 
 
 /** Group: Data Registers */
-/** Type of data_0 register
- *  Data register 0.
+/** Type of tx_rx_buffer register
+ *  Data register.
  */
 typedef union {
     struct {
-        /** data_0 : R/W; bitpos: [7:0]; default: 0;
+        /** byte : R/W; bitpos: [7:0]; default: 0;
          *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
          *  mode, when software initiate write operation, it is tx data register 0 and when
          *  software initiate read operation, it is rx data register 0.
          */
-        uint32_t data_0:8;
+        uint32_t byte:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
-} twai_data_0_reg_t;
-
-/** Type of data_1 register
- *  Data register 1.
- */
-typedef union {
-    struct {
-        /** data_1 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 1 and when
-         *  software initiate read operation, it is rx data register 1.
-         */
-        uint32_t data_1:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_1_reg_t;
-
-/** Type of data_2 register
- *  Data register 2.
- */
-typedef union {
-    struct {
-        /** data_2 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 2 and when
-         *  software initiate read operation, it is rx data register 2.
-         */
-        uint32_t data_2:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_2_reg_t;
-
-/** Type of data_3 register
- *  Data register 3.
- */
-typedef union {
-    struct {
-        /** data_3 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 3 and when
-         *  software initiate read operation, it is rx data register 3.
-         */
-        uint32_t data_3:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_3_reg_t;
-
-/** Type of data_4 register
- *  Data register 4.
- */
-typedef union {
-    struct {
-        /** data_4 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 4 and when
-         *  software initiate read operation, it is rx data register 4.
-         */
-        uint32_t data_4:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_4_reg_t;
-
-/** Type of data_5 register
- *  Data register 5.
- */
-typedef union {
-    struct {
-        /** data_5 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 5 and when
-         *  software initiate read operation, it is rx data register 5.
-         */
-        uint32_t data_5:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_5_reg_t;
-
-/** Type of data_6 register
- *  Data register 6.
- */
-typedef union {
-    struct {
-        /** data_6 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 6 and when
-         *  software initiate read operation, it is rx data register 6.
-         */
-        uint32_t data_6:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_6_reg_t;
-
-/** Type of data_7 register
- *  Data register 7.
- */
-typedef union {
-    struct {
-        /** data_7 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 7 and when
-         *  software initiate read operation, it is rx data register 7.
-         */
-        uint32_t data_7:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_7_reg_t;
-
-/** Type of data_8 register
- *  Data register 8.
- */
-typedef union {
-    struct {
-        /** data_8 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 8 and when software initiate read operation, it
-         *  is rx data register 8.
-         */
-        uint32_t data_8:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_8_reg_t;
-
-/** Type of data_9 register
- *  Data register 9.
- */
-typedef union {
-    struct {
-        /** data_9 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 9 and when software initiate read operation, it
-         *  is rx data register 9.
-         */
-        uint32_t data_9:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_9_reg_t;
-
-/** Type of data_10 register
- *  Data register 10.
- */
-typedef union {
-    struct {
-        /** data_10 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 10 and when software initiate read operation, it
-         *  is rx data register 10.
-         */
-        uint32_t data_10:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_10_reg_t;
-
-/** Type of data_11 register
- *  Data register 11.
- */
-typedef union {
-    struct {
-        /** data_11 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 11 and when software initiate read operation, it
-         *  is rx data register 11.
-         */
-        uint32_t data_11:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_11_reg_t;
-
-/** Type of data_12 register
- *  Data register 12.
- */
-typedef union {
-    struct {
-        /** data_12 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 12 and when software initiate read operation, it
-         *  is rx data register 12.
-         */
-        uint32_t data_12:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_12_reg_t;
+} twai_tx_rx_buffer_reg_t;
 
 
 /** Group: Timestamp Register */
@@ -744,6 +552,23 @@ typedef union {
     uint32_t val;
 } twai_timestamp_cfg_reg_t;
 
+typedef struct {
+    union {
+        struct {
+            uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
+            uint32_t reserved8: 24;     /* Internal Reserved */
+        };
+        uint32_t val;
+    } acr[4];
+    union {
+        struct {
+            uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
+            uint32_t reserved8: 24;     /* Internal Reserved */
+        };
+        uint32_t val;
+    } amr[4];
+    uint32_t reserved_60[5];
+} acceptance_filter_reg_t;
 
 typedef struct twai_dev_t {
     volatile twai_mode_reg_t mode;
@@ -760,19 +585,10 @@ typedef struct twai_dev_t {
     volatile twai_err_warning_limit_reg_t err_warning_limit;
     volatile twai_rx_err_cnt_reg_t rx_err_cnt;
     volatile twai_tx_err_cnt_reg_t tx_err_cnt;
-    volatile twai_data_0_reg_t data_0;
-    volatile twai_data_1_reg_t data_1;
-    volatile twai_data_2_reg_t data_2;
-    volatile twai_data_3_reg_t data_3;
-    volatile twai_data_4_reg_t data_4;
-    volatile twai_data_5_reg_t data_5;
-    volatile twai_data_6_reg_t data_6;
-    volatile twai_data_7_reg_t data_7;
-    volatile twai_data_8_reg_t data_8;
-    volatile twai_data_9_reg_t data_9;
-    volatile twai_data_10_reg_t data_10;
-    volatile twai_data_11_reg_t data_11;
-    volatile twai_data_12_reg_t data_12;
+    volatile union {
+        acceptance_filter_reg_t acceptance_filter;
+        twai_tx_rx_buffer_reg_t tx_rx_buffer[13];
+    };
     volatile twai_rx_message_counter_reg_t rx_message_counter;
     uint32_t reserved_078;
     volatile twai_clock_divider_reg_t clock_divider;
diff --git a/components/soc/esp32c5/include/soc/uart_reg.h b/components/soc/esp32c5/include/soc/uart_reg.h
index 1be6cb107f..ac864940d8 100644
--- a/components/soc/esp32c5/include/soc/uart_reg.h
+++ b/components/soc/esp32c5/include/soc/uart_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** UART_FIFO_REG register
  *  FIFO data register
  */
-#define UART_FIFO_REG (DR_REG_UART_BASE + 0x0)
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
 /** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
  *  UART $n accesses FIFO via this register.
  */
@@ -26,7 +26,7 @@ extern "C" {
 /** UART_INT_RAW_REG register
  *  Raw interrupt status
  */
-#define UART_INT_RAW_REG (DR_REG_UART_BASE + 0x4)
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
 /** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
  *  This interrupt raw bit turns to high level when receiver receives more data than
  *  what rxfifo_full_thrhd specifies.
@@ -191,7 +191,7 @@ extern "C" {
 /** UART_INT_ST_REG register
  *  Masked interrupt status
  */
-#define UART_INT_ST_REG (DR_REG_UART_BASE + 0x8)
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
 /** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
  *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
  */
@@ -341,7 +341,7 @@ extern "C" {
 /** UART_INT_ENA_REG register
  *  Interrupt enable bits
  */
-#define UART_INT_ENA_REG (DR_REG_UART_BASE + 0xc)
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
 /** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  This is the enable bit for rxfifo_full_int_st register.
  */
@@ -486,7 +486,7 @@ extern "C" {
 /** UART_INT_CLR_REG register
  *  Interrupt clear bits
  */
-#define UART_INT_CLR_REG (DR_REG_UART_BASE + 0x10)
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
 /** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Set this bit to clear the rxfifo_full_int_raw interrupt.
  */
@@ -631,7 +631,7 @@ extern "C" {
 /** UART_CLKDIV_SYNC_REG register
  *  Clock divider configuration
  */
-#define UART_CLKDIV_SYNC_REG (DR_REG_UART_BASE + 0x14)
+#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
 /** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
  *  The integral part of the frequency divider factor.
  */
@@ -650,7 +650,7 @@ extern "C" {
 /** UART_RX_FILT_REG register
  *  Rx Filter configuration
  */
-#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18)
+#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
 /** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
  *  when input pulse width is lower than this value the pulse is ignored.
  */
@@ -669,7 +669,7 @@ extern "C" {
 /** UART_STATUS_REG register
  *  UART status register
  */
-#define UART_STATUS_REG (DR_REG_UART_BASE + 0x1c)
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
 /** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
  *  Stores the byte number of valid data in Rx-FIFO.
  */
@@ -730,7 +730,7 @@ extern "C" {
 /** UART_CONF0_SYNC_REG register
  *  a
  */
-#define UART_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x20)
+#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
 /** UART_PARITY : R/W; bitpos: [0]; default: 0;
  *  This register is used to configure the parity check mode.
  */
@@ -893,7 +893,7 @@ extern "C" {
 /** UART_CONF1_REG register
  *  Configuration register 1
  */
-#define UART_CONF1_REG (DR_REG_UART_BASE + 0x24)
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
 /** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
  *  It will produce rxfifo_full_int interrupt when receiver receives more data than
  *  this register value.
@@ -958,7 +958,7 @@ extern "C" {
 /** UART_HWFC_CONF_SYNC_REG register
  *  Hardware flow-control configuration
  */
-#define UART_HWFC_CONF_SYNC_REG (DR_REG_UART_BASE + 0x2c)
+#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
 /** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
  *  This register is used to configure the maximum amount of data that can be received
  *  when hardware flow control works.
@@ -978,7 +978,7 @@ extern "C" {
 /** UART_SLEEP_CONF0_REG register
  *  UART sleep configure register 0
  */
-#define UART_SLEEP_CONF0_REG (DR_REG_UART_BASE + 0x30)
+#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
 /** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
  *  This register restores the specified wake up char1 to wake up
  */
@@ -1011,7 +1011,7 @@ extern "C" {
 /** UART_SLEEP_CONF1_REG register
  *  UART sleep configure register 1
  */
-#define UART_SLEEP_CONF1_REG (DR_REG_UART_BASE + 0x34)
+#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
 /** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
  *  This register restores the specified char0 to wake up
  */
@@ -1023,7 +1023,7 @@ extern "C" {
 /** UART_SLEEP_CONF2_REG register
  *  UART sleep configure register 2
  */
-#define UART_SLEEP_CONF2_REG (DR_REG_UART_BASE + 0x38)
+#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
 /** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
  *  The uart is activated from light sleeping mode when the input rxd edge changes more
  *  times than this register value.
@@ -1066,7 +1066,7 @@ extern "C" {
 /** UART_SWFC_CONF0_SYNC_REG register
  *  Software flow-control character configuration
  */
-#define UART_SWFC_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x3c)
+#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
 /** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
  *  This register stores the Xon flow control char.
  */
@@ -1138,7 +1138,7 @@ extern "C" {
 /** UART_SWFC_CONF1_REG register
  *  Software flow-control character configuration
  */
-#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40)
+#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
 /** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
  *  When the data amount in Rx-FIFO is less than this register value with
  *  uart_sw_flow_con_en set to 1  it will send a Xon char.
@@ -1159,7 +1159,7 @@ extern "C" {
 /** UART_TXBRK_CONF_SYNC_REG register
  *  Tx Break character configuration
  */
-#define UART_TXBRK_CONF_SYNC_REG (DR_REG_UART_BASE + 0x44)
+#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
 /** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
  *  This register is used to configure the number of 0 to be sent after the process of
  *  sending data is done. It is active when txd_brk is set to 1.
@@ -1172,7 +1172,7 @@ extern "C" {
 /** UART_IDLE_CONF_SYNC_REG register
  *  Frame-end idle configuration
  */
-#define UART_IDLE_CONF_SYNC_REG (DR_REG_UART_BASE + 0x48)
+#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
 /** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
  *  It will produce frame end signal when receiver takes more time to receive one byte
  *  data than this register value.
@@ -1192,7 +1192,7 @@ extern "C" {
 /** UART_RS485_CONF_SYNC_REG register
  *  RS485 mode configuration
  */
-#define UART_RS485_CONF_SYNC_REG (DR_REG_UART_BASE + 0x4c)
+#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
 /** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
  *  Set this bit to choose the rs485 mode.
  */
@@ -1247,7 +1247,7 @@ extern "C" {
 /** UART_AT_CMD_PRECNT_SYNC_REG register
  *  Pre-sequence timing configuration
  */
-#define UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_UART_BASE + 0x50)
+#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
 /** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
  *  This register is used to configure the idle duration time before the first at_cmd
  *  is received by receiver.
@@ -1260,7 +1260,7 @@ extern "C" {
 /** UART_AT_CMD_POSTCNT_SYNC_REG register
  *  Post-sequence timing configuration
  */
-#define UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_UART_BASE + 0x54)
+#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
 /** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
  *  This register is used to configure the duration time between the last at_cmd and
  *  the next data.
@@ -1273,7 +1273,7 @@ extern "C" {
 /** UART_AT_CMD_GAPTOUT_SYNC_REG register
  *  Timeout configuration
  */
-#define UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_UART_BASE + 0x58)
+#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
 /** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
  *  This register is used to configure the duration time between the at_cmd chars.
  */
@@ -1285,7 +1285,7 @@ extern "C" {
 /** UART_AT_CMD_CHAR_SYNC_REG register
  *  AT escape sequence detection configuration
  */
-#define UART_AT_CMD_CHAR_SYNC_REG (DR_REG_UART_BASE + 0x5c)
+#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
 /** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
  *  This register is used to configure the content of at_cmd char.
  */
@@ -1305,7 +1305,7 @@ extern "C" {
 /** UART_MEM_CONF_REG register
  *  UART memory power configuration
  */
-#define UART_MEM_CONF_REG (DR_REG_UART_BASE + 0x60)
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
 /** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
  *  Set this bit to force power down UART memory.
  */
@@ -1324,7 +1324,7 @@ extern "C" {
 /** UART_TOUT_CONF_SYNC_REG register
  *  UART threshold and allocation configuration
  */
-#define UART_TOUT_CONF_SYNC_REG (DR_REG_UART_BASE + 0x64)
+#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
 /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
  *  This is the enble bit for uart receiver's timeout function.
  */
@@ -1352,7 +1352,7 @@ extern "C" {
 /** UART_MEM_TX_STATUS_REG register
  *  Tx-SRAM write and read offset address.
  */
-#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x68)
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
 /** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
  *  This register stores the offset write address in Tx-SRAM.
  */
@@ -1371,7 +1371,7 @@ extern "C" {
 /** UART_MEM_RX_STATUS_REG register
  *  Rx-SRAM write and read offset address.
  */
-#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x6c)
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
 /** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
  *  This register stores the offset read address in RX-SRAM.
  */
@@ -1390,7 +1390,7 @@ extern "C" {
 /** UART_FSM_STATUS_REG register
  *  UART transmit and receive status.
  */
-#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x70)
+#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
 /** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
  *  This is the status register of receiver.
  */
@@ -1409,7 +1409,7 @@ extern "C" {
 /** UART_POSPULSE_REG register
  *  Autobaud high pulse register
  */
-#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x74)
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
 /** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
  *  This register stores the minimal input clock count between two positive edges. It
  *  is used in boudrate-detect process.
@@ -1422,7 +1422,7 @@ extern "C" {
 /** UART_NEGPULSE_REG register
  *  Autobaud low pulse register
  */
-#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x78)
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
 /** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
  *  This register stores the minimal input clock count between two negative edges. It
  *  is used in boudrate-detect process.
@@ -1435,7 +1435,7 @@ extern "C" {
 /** UART_LOWPULSE_REG register
  *  Autobaud minimum low pulse duration register
  */
-#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x7c)
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
 /** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
  *  This register stores the value of the minimum duration time of the low level pulse.
  *  It is used in baud rate-detect process.
@@ -1448,7 +1448,7 @@ extern "C" {
 /** UART_HIGHPULSE_REG register
  *  Autobaud minimum high pulse duration register
  */
-#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x80)
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
 /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
  *  This register stores  the value of the maxinum duration time for the high level
  *  pulse. It is used in baud rate-detect process.
@@ -1461,7 +1461,7 @@ extern "C" {
 /** UART_RXD_CNT_REG register
  *  Autobaud edge change count register
  */
-#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x84)
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
 /** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
  *  This register stores the count of rxd edge change. It is used in baud rate-detect
  *  process.
@@ -1474,7 +1474,7 @@ extern "C" {
 /** UART_CLK_CONF_REG register
  *  UART core clock configuration
  */
-#define UART_CLK_CONF_REG (DR_REG_UART_BASE + 0x88)
+#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
 /** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
  *  Set this bit to enable UART Tx clock.
  */
@@ -1507,7 +1507,7 @@ extern "C" {
 /** UART_DATE_REG register
  *  UART Version register
  */
-#define UART_DATE_REG (DR_REG_UART_BASE + 0x8c)
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
 /** UART_DATE : R/W; bitpos: [31:0]; default: 35680848;
  *  This is the version register.
  */
@@ -1519,7 +1519,7 @@ extern "C" {
 /** UART_AFIFO_STATUS_REG register
  *  UART AFIFO Status
  */
-#define UART_AFIFO_STATUS_REG (DR_REG_UART_BASE + 0x90)
+#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
 /** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
  *  Full signal of APB TX AFIFO.
  */
@@ -1552,7 +1552,7 @@ extern "C" {
 /** UART_REG_UPDATE_REG register
  *  UART Registers Configuration Update register
  */
-#define UART_REG_UPDATE_REG (DR_REG_UART_BASE + 0x98)
+#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
 /** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
  *  Software write 1 would synchronize registers into UART Core clock domain and would
  *  be cleared by hardware after synchronization is done.
@@ -1565,7 +1565,7 @@ extern "C" {
 /** UART_ID_REG register
  *  UART ID register
  */
-#define UART_ID_REG (DR_REG_UART_BASE + 0x9c)
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
 /** UART_ID : R/W; bitpos: [31:0]; default: 1280;
  *  This register is used to configure the uart_id.
  */