2021-10-13 05:10:57 -04:00
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/*
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2022-01-12 01:53:47 -05:00
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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2021-10-13 05:10:57 -04:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2016-10-18 09:49:00 -04:00
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#include <stddef.h>
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#include <stdlib.h>
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#include <stdio.h>
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2017-04-05 09:19:15 -04:00
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#include <string.h>
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2016-10-18 09:49:00 -04:00
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2018-03-29 23:39:42 -04:00
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#include "sdkconfig.h"
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#include "esp_heap_caps.h"
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2017-09-12 10:36:17 -04:00
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#include "esp_heap_caps_init.h"
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2016-10-18 09:49:00 -04:00
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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#include "freertos/semphr.h"
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#include "freertos/xtensa_api.h"
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#include "freertos/portmacro.h"
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2017-10-20 05:09:03 -04:00
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#include "xtensa/core-macros.h"
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2016-10-18 09:49:00 -04:00
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#include "esp_types.h"
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2022-01-12 01:53:47 -05:00
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#include "esp_mac.h"
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#include "esp_random.h"
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2016-10-18 09:49:00 -04:00
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#include "esp_task.h"
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2019-03-26 04:30:43 -04:00
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#include "esp_intr_alloc.h"
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2016-10-18 09:49:00 -04:00
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#include "esp_attr.h"
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2017-02-16 09:06:02 -05:00
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#include "esp_phy_init.h"
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2017-12-07 08:48:27 -05:00
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#include "esp_bt.h"
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2017-09-12 10:36:17 -04:00
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#include "esp_err.h"
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#include "esp_log.h"
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2017-10-09 03:34:31 -04:00
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#include "esp_pm.h"
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2021-11-18 22:42:01 -05:00
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#include "esp_private/esp_clk.h"
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2021-10-25 05:13:46 -04:00
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#include "esp_private/periph_ctrl.h"
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2018-04-08 07:19:47 -04:00
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#include "soc/rtc.h"
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2018-06-15 09:40:51 -04:00
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#include "soc/soc_memory_layout.h"
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2021-09-01 09:55:50 -04:00
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#include "soc/dport_reg.h"
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2019-02-20 08:01:27 -05:00
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#include "esp_coexist_internal.h"
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2019-08-15 03:05:59 -04:00
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#if !CONFIG_FREERTOS_UNICORE
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#include "esp_ipc.h"
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#endif
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2016-10-18 09:49:00 -04:00
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2020-07-21 01:07:34 -04:00
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#include "esp_rom_sys.h"
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2021-09-01 09:55:50 -04:00
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#include "hli_api.h"
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2020-07-21 01:07:34 -04:00
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2016-10-18 09:49:00 -04:00
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#if CONFIG_BT_ENABLED
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2018-06-15 09:40:51 -04:00
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/* Macro definition
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************************************************************************
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*/
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2021-09-01 09:55:50 -04:00
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#define UNUSED(x) (void)(x)
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2017-09-12 10:36:17 -04:00
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#define BTDM_LOG_TAG "BTDM_INIT"
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2017-06-13 05:14:50 -04:00
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#define BTDM_INIT_PERIOD (5000) /* ms */
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2017-02-21 04:46:59 -05:00
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/* Bluetooth system and controller config */
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2017-09-19 08:10:35 -04:00
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#define BTDM_CFG_BT_DATA_RELEASE (1<<0)
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#define BTDM_CFG_HCI_UART (1<<1)
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#define BTDM_CFG_CONTROLLER_RUN_APP_CPU (1<<2)
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2018-05-03 08:22:08 -04:00
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#define BTDM_CFG_SCAN_DUPLICATE_OPTIONS (1<<3)
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#define BTDM_CFG_SEND_ADV_RESERVED_SIZE (1<<4)
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2018-11-28 07:00:40 -05:00
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#define BTDM_CFG_BLE_FULL_SCAN_SUPPORTED (1<<5)
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2018-04-08 07:19:47 -04:00
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2018-06-15 09:40:51 -04:00
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/* Sleep mode */
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2018-04-08 07:19:47 -04:00
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#define BTDM_MODEM_SLEEP_MODE_NONE (0)
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#define BTDM_MODEM_SLEEP_MODE_ORIG (1)
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2018-12-21 06:30:20 -05:00
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#define BTDM_MODEM_SLEEP_MODE_EVED (2) // sleep mode for BLE controller, used only for internal test.
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2018-04-08 07:19:47 -04:00
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2018-06-15 09:40:51 -04:00
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/* Low Power Clock Selection */
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2018-04-08 07:19:47 -04:00
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#define BTDM_LPCLK_SEL_XTAL (0)
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#define BTDM_LPCLK_SEL_XTAL32K (1)
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#define BTDM_LPCLK_SEL_RTC_SLOW (2)
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#define BTDM_LPCLK_SEL_8M (3)
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2018-12-11 03:49:01 -05:00
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/* Sleep and wakeup interval control */
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#define BTDM_MIN_SLEEP_DURATION (12) // threshold of interval in slots to allow to fall into modem sleep
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#define BTDM_MODEM_WAKE_UP_DELAY (4) // delay in slots of modem wake up procedure, including re-enable PHY/RF
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2017-09-19 08:10:35 -04:00
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2016-10-18 09:49:00 -04:00
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#define BT_DEBUG(...)
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#define BT_API_CALL_CHECK(info, api_call, ret) \
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do{\
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esp_err_t __err = (api_call);\
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if ((ret) != __err) {\
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2017-11-06 05:22:45 -05:00
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BT_DEBUG("%s %d %s ret=0x%X\n", __FUNCTION__, __LINE__, (info), __err);\
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2016-10-18 09:49:00 -04:00
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return __err;\
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}\
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} while(0)
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2017-07-11 09:46:17 -04:00
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#define OSI_FUNCS_TIME_BLOCKING 0xffffffff
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2021-09-01 09:55:50 -04:00
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#define OSI_VERSION 0x00010003
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2018-06-15 09:40:51 -04:00
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#define OSI_MAGIC_VALUE 0xFADEBEAD
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2021-09-03 04:51:09 -04:00
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/* SPIRAM Configuration */
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#if CONFIG_SPIRAM_USE_MALLOC
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2021-09-14 07:10:15 -04:00
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#define BTDM_MAX_QUEUE_NUM (6)
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2021-09-03 04:51:09 -04:00
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#endif
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2018-06-15 09:40:51 -04:00
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/* Types definition
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************************************************************************
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*/
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2017-07-11 09:46:17 -04:00
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2018-06-15 09:40:51 -04:00
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/* VHCI function interface */
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typedef struct vhci_host_callback {
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void (*notify_host_send_available)(void); /*!< callback used to notify that the host can send packet to controller */
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int (*notify_host_recv)(uint8_t *data, uint16_t len); /*!< callback used to notify that the controller has a packet to send to the host*/
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} vhci_host_callback_t;
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/* Dram region */
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2017-09-19 08:10:35 -04:00
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typedef struct {
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esp_bt_mode_t mode;
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intptr_t start;
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intptr_t end;
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} btdm_dram_available_region_t;
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2021-09-03 04:51:09 -04:00
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/* PSRAM configuration */
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#if CONFIG_SPIRAM_USE_MALLOC
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typedef struct {
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QueueHandle_t handle;
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void *storage;
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void *buffer;
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} btdm_queue_item_t;
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#endif
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2018-06-15 09:40:51 -04:00
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/* OSI function */
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2016-10-18 09:49:00 -04:00
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struct osi_funcs_t {
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2018-06-15 09:40:51 -04:00
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uint32_t _version;
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2016-10-18 09:49:00 -04:00
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xt_handler (*_set_isr)(int n, xt_handler f, void *arg);
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void (*_ints_on)(unsigned int mask);
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void (*_interrupt_disable)(void);
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void (*_interrupt_restore)(void);
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void (*_task_yield)(void);
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2017-06-07 02:58:17 -04:00
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void (*_task_yield_from_isr)(void);
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2016-10-18 09:49:00 -04:00
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void *(*_semphr_create)(uint32_t max, uint32_t init);
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2017-07-11 09:46:17 -04:00
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void (*_semphr_delete)(void *semphr);
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int32_t (*_semphr_take_from_isr)(void *semphr, void *hptw);
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2016-10-18 09:49:00 -04:00
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int32_t (*_semphr_give_from_isr)(void *semphr, void *hptw);
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int32_t (*_semphr_take)(void *semphr, uint32_t block_time_ms);
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2017-07-11 09:46:17 -04:00
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int32_t (*_semphr_give)(void *semphr);
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2016-10-18 09:49:00 -04:00
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void *(*_mutex_create)(void);
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2017-07-11 09:46:17 -04:00
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void (*_mutex_delete)(void *mutex);
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2016-10-18 09:49:00 -04:00
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int32_t (*_mutex_lock)(void *mutex);
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int32_t (*_mutex_unlock)(void *mutex);
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2017-07-11 09:46:17 -04:00
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void *(* _queue_create)(uint32_t queue_len, uint32_t item_size);
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void (* _queue_delete)(void *queue);
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int32_t (* _queue_send)(void *queue, void *item, uint32_t block_time_ms);
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int32_t (* _queue_send_from_isr)(void *queue, void *item, void *hptw);
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int32_t (* _queue_recv)(void *queue, void *item, uint32_t block_time_ms);
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int32_t (* _queue_recv_from_isr)(void *queue, void *item, void *hptw);
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int32_t (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id);
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void (* _task_delete)(void *task_handle);
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2017-07-25 07:58:39 -04:00
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bool (* _is_in_isr)(void);
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2017-10-20 05:09:03 -04:00
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int (* _cause_sw_intr_to_core)(int core_id, int intr_no);
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2017-07-11 09:46:17 -04:00
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void *(* _malloc)(uint32_t size);
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2018-06-15 09:40:51 -04:00
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void *(* _malloc_internal)(uint32_t size);
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2017-07-11 09:46:17 -04:00
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void (* _free)(void *p);
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2017-03-01 08:04:12 -05:00
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int32_t (* _read_efuse_mac)(uint8_t mac[6]);
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2017-03-24 02:57:07 -04:00
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void (* _srand)(unsigned int seed);
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int (* _rand)(void);
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2018-04-08 07:19:47 -04:00
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uint32_t (* _btdm_lpcycles_2_us)(uint32_t cycles);
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uint32_t (* _btdm_us_2_lpcycles)(uint32_t us);
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bool (* _btdm_sleep_check_duration)(uint32_t *slot_cnt);
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2018-12-11 03:49:01 -05:00
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void (* _btdm_sleep_enter_phase1)(uint32_t lpcycles); /* called when interrupt is disabled */
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void (* _btdm_sleep_enter_phase2)(void);
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void (* _btdm_sleep_exit_phase1)(void); /* called from ISR */
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void (* _btdm_sleep_exit_phase2)(void); /* called from ISR */
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void (* _btdm_sleep_exit_phase3)(void); /* called from task */
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2020-03-20 05:58:05 -04:00
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bool (* _coex_bt_wakeup_request)(void);
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void (* _coex_bt_wakeup_request_end)(void);
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2019-02-20 08:01:27 -05:00
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int (* _coex_bt_request)(uint32_t event, uint32_t latency, uint32_t duration);
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int (* _coex_bt_release)(uint32_t event);
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int (* _coex_register_bt_cb)(coex_func_cb_t cb);
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uint32_t (* _coex_bb_reset_lock)(void);
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void (* _coex_bb_reset_unlock)(uint32_t restore);
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2021-03-23 04:55:30 -04:00
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int (* _coex_schm_register_btdm_callback)(void *callback);
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void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status);
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void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status);
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uint32_t (* _coex_schm_interval_get)(void);
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uint8_t (* _coex_schm_curr_period_get)(void);
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void *(* _coex_schm_curr_phase_get)(void);
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int (* _coex_wifi_channel_get)(uint8_t *primary, uint8_t *secondary);
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int (* _coex_register_wifi_channel_change_callback)(void *cb);
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2021-09-01 09:55:50 -04:00
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xt_handler (*_set_isr_l3)(int n, xt_handler f, void *arg);
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void (*_interrupt_l3_disable)(void);
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void (*_interrupt_l3_restore)(void);
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void *(* _customer_queue_create)(uint32_t queue_len, uint32_t item_size);
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2018-06-15 09:40:51 -04:00
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uint32_t _magic;
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};
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2020-09-03 08:51:19 -04:00
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typedef void (*workitem_handler_t)(void* arg);
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2018-06-15 09:40:51 -04:00
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/* External functions or values
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************************************************************************
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*/
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/* not for user call, so don't put to include file */
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/* OSI */
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extern int btdm_osi_funcs_register(void *osi_funcs);
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/* Initialise and De-initialise */
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extern int btdm_controller_init(uint32_t config_mask, esp_bt_controller_config_t *config_opts);
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extern void btdm_controller_deinit(void);
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extern int btdm_controller_enable(esp_bt_mode_t mode);
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extern void btdm_controller_disable(void);
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extern uint8_t btdm_controller_get_mode(void);
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extern const char *btdm_controller_get_compile_version(void);
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2018-12-11 03:49:01 -05:00
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extern void btdm_rf_bb_init_phase2(void); // shall be called after PHY/RF is enabled
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2020-09-03 08:51:19 -04:00
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extern int btdm_dispatch_work_to_controller(workitem_handler_t callback, void *arg, bool blocking);
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2018-06-15 09:40:51 -04:00
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/* Sleep */
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extern void btdm_controller_enable_sleep(bool enable);
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extern void btdm_controller_set_sleep_mode(uint8_t mode);
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extern uint8_t btdm_controller_get_sleep_mode(void);
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extern bool btdm_power_state_active(void);
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2020-09-03 08:51:19 -04:00
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extern void btdm_wakeup_request(void);
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extern void btdm_in_wakeup_requesting_set(bool in_wakeup_requesting);
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2018-06-15 09:40:51 -04:00
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/* Low Power Clock */
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extern bool btdm_lpclk_select_src(uint32_t sel);
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extern bool btdm_lpclk_set_div(uint32_t div);
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/* VHCI */
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extern bool API_vhci_host_check_send_available(void);
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extern void API_vhci_host_send_packet(uint8_t *data, uint16_t len);
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extern int API_vhci_host_register_callback(const vhci_host_callback_t *callback);
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/* TX power */
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extern int ble_txpwr_set(int power_type, int power_level);
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extern int ble_txpwr_get(int power_type);
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extern int bredr_txpwr_set(int min_power_level, int max_power_level);
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extern int bredr_txpwr_get(int *min_power_level, int *max_power_level);
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extern void bredr_sco_datapath_set(uint8_t data_path);
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2018-08-20 03:04:37 -04:00
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extern void btdm_controller_scan_duplicate_list_clear(void);
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2019-02-20 08:01:27 -05:00
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/* Coexistence */
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2020-08-26 05:51:13 -04:00
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extern int coex_bt_request(uint32_t event, uint32_t latency, uint32_t duration);
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extern int coex_bt_release(uint32_t event);
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extern int coex_register_bt_cb(coex_func_cb_t cb);
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extern uint32_t coex_bb_reset_lock(void);
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extern void coex_bb_reset_unlock(uint32_t restore);
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2021-03-23 04:55:30 -04:00
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extern int coex_schm_register_btdm_callback(void *callback);
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extern void coex_schm_status_bit_clear(uint32_t type, uint32_t status);
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extern void coex_schm_status_bit_set(uint32_t type, uint32_t status);
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extern uint32_t coex_schm_interval_get(void);
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extern uint8_t coex_schm_curr_period_get(void);
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extern void * coex_schm_curr_phase_get(void);
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extern int coex_wifi_channel_get(uint8_t *primary, uint8_t *secondary);
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extern int coex_register_wifi_channel_change_callback(void *cb);
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2021-11-01 08:39:37 -04:00
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|
/* Shutdown */
|
|
|
|
extern void esp_bt_controller_shutdown(void);
|
2018-06-15 09:40:51 -04:00
|
|
|
|
|
|
|
extern char _bss_start_btdm;
|
|
|
|
extern char _bss_end_btdm;
|
|
|
|
extern char _data_start_btdm;
|
|
|
|
extern char _data_end_btdm;
|
|
|
|
extern uint32_t _data_start_btdm_rom;
|
|
|
|
extern uint32_t _data_end_btdm_rom;
|
|
|
|
|
|
|
|
extern uint32_t _bt_bss_start;
|
|
|
|
extern uint32_t _bt_bss_end;
|
2019-06-24 21:03:58 -04:00
|
|
|
extern uint32_t _nimble_bss_start;
|
|
|
|
extern uint32_t _nimble_bss_end;
|
2018-06-15 09:40:51 -04:00
|
|
|
extern uint32_t _btdm_bss_start;
|
|
|
|
extern uint32_t _btdm_bss_end;
|
|
|
|
extern uint32_t _bt_data_start;
|
|
|
|
extern uint32_t _bt_data_end;
|
2019-06-24 21:03:58 -04:00
|
|
|
extern uint32_t _nimble_data_start;
|
|
|
|
extern uint32_t _nimble_data_end;
|
2018-06-15 09:40:51 -04:00
|
|
|
extern uint32_t _btdm_data_start;
|
|
|
|
extern uint32_t _btdm_data_end;
|
|
|
|
|
|
|
|
/* Local Function Declare
|
|
|
|
*********************************************************************
|
|
|
|
*/
|
2021-09-03 04:51:09 -04:00
|
|
|
#if CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
static bool btdm_queue_generic_register(const btdm_queue_item_t *queue);
|
|
|
|
static bool btdm_queue_generic_deregister(btdm_queue_item_t *queue);
|
|
|
|
#endif /* CONFIG_SPIRAM_USE_MALLOC */
|
|
|
|
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
static xt_handler set_isr_hlevel_wrapper(int n, xt_handler f, void *arg);
|
|
|
|
static void IRAM_ATTR interrupt_hlevel_disable(void);
|
|
|
|
static void IRAM_ATTR interrupt_hlevel_restore(void);
|
2021-09-02 09:49:30 -04:00
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2021-09-01 09:55:50 -04:00
|
|
|
static void IRAM_ATTR task_yield(void);
|
2018-06-15 09:40:51 -04:00
|
|
|
static void IRAM_ATTR task_yield_from_isr(void);
|
2018-10-29 04:54:32 -04:00
|
|
|
static void *semphr_create_wrapper(uint32_t max, uint32_t init);
|
|
|
|
static void semphr_delete_wrapper(void *semphr);
|
2018-06-15 09:40:51 -04:00
|
|
|
static int32_t IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw);
|
|
|
|
static int32_t IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw);
|
2018-10-29 04:54:32 -04:00
|
|
|
static int32_t semphr_take_wrapper(void *semphr, uint32_t block_time_ms);
|
|
|
|
static int32_t semphr_give_wrapper(void *semphr);
|
|
|
|
static void *mutex_create_wrapper(void);
|
|
|
|
static void mutex_delete_wrapper(void *mutex);
|
|
|
|
static int32_t mutex_lock_wrapper(void *mutex);
|
|
|
|
static int32_t mutex_unlock_wrapper(void *mutex);
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
static void *queue_create_hlevel_wrapper(uint32_t queue_len, uint32_t item_size);
|
|
|
|
static void queue_delete_hlevel_wrapper(void *queue);
|
|
|
|
static int32_t IRAM_ATTR queue_send_hlevel_wrapper(void *queue, void *item, uint32_t block_time_ms);
|
|
|
|
static int32_t IRAM_ATTR queue_send_from_isr_hlevel_wrapper(void *queue, void *item, void *hptw);
|
|
|
|
static int32_t IRAM_ATTR queue_recv_hlevel_wrapper(void *queue, void *item, uint32_t block_time_ms);
|
|
|
|
static int32_t IRAM_ATTR queue_recv_from_isr_hlevel_wrapper(void *queue, void *item, void *hptw);
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size);
|
|
|
|
static void queue_delete_wrapper(void *queue);
|
|
|
|
static int32_t IRAM_ATTR queue_send_wrapper(void *queue, void *item, uint32_t block_time_ms);
|
|
|
|
static int32_t IRAM_ATTR queue_send_from_isr_wrapper(void *queue, void *item, void *hptw);
|
|
|
|
static int32_t IRAM_ATTR queue_recv_wrapper(void *queue, void *item, uint32_t block_time_ms);
|
|
|
|
static int32_t IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, void *item, void *hptw);
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2018-10-29 04:54:32 -04:00
|
|
|
static int32_t task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id);
|
|
|
|
static void task_delete_wrapper(void *task_handle);
|
2018-06-15 09:40:51 -04:00
|
|
|
static bool IRAM_ATTR is_in_isr_wrapper(void);
|
|
|
|
static void IRAM_ATTR cause_sw_intr(void *arg);
|
|
|
|
static int IRAM_ATTR cause_sw_intr_to_core_wrapper(int core_id, int intr_no);
|
2018-10-29 04:54:32 -04:00
|
|
|
static void *malloc_internal_wrapper(size_t size);
|
2018-06-15 09:40:51 -04:00
|
|
|
static int32_t IRAM_ATTR read_mac_wrapper(uint8_t mac[6]);
|
|
|
|
static void IRAM_ATTR srand_wrapper(unsigned int seed);
|
|
|
|
static int IRAM_ATTR rand_wrapper(void);
|
|
|
|
static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles);
|
|
|
|
static uint32_t IRAM_ATTR btdm_us_2_lpcycles(uint32_t us);
|
|
|
|
static bool IRAM_ATTR btdm_sleep_check_duration(uint32_t *slot_cnt);
|
2018-12-11 03:49:01 -05:00
|
|
|
static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles);
|
|
|
|
static void btdm_sleep_enter_phase2_wrapper(void);
|
|
|
|
static void btdm_sleep_exit_phase3_wrapper(void);
|
2020-03-20 05:58:05 -04:00
|
|
|
static bool coex_bt_wakeup_request(void);
|
|
|
|
static void coex_bt_wakeup_request_end(void);
|
2020-08-26 05:51:13 -04:00
|
|
|
static int coex_bt_request_wrapper(uint32_t event, uint32_t latency, uint32_t duration);
|
|
|
|
static int coex_bt_release_wrapper(uint32_t event);
|
|
|
|
static int coex_register_bt_cb_wrapper(coex_func_cb_t cb);
|
|
|
|
static uint32_t coex_bb_reset_lock_wrapper(void);
|
|
|
|
static void coex_bb_reset_unlock_wrapper(uint32_t restore);
|
2021-03-23 04:55:30 -04:00
|
|
|
static int coex_schm_register_btdm_callback_wrapper(void *callback);
|
|
|
|
static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
|
|
|
|
static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status);
|
|
|
|
static uint32_t coex_schm_interval_get_wrapper(void);
|
|
|
|
static uint8_t coex_schm_curr_period_get_wrapper(void);
|
|
|
|
static void * coex_schm_curr_phase_get_wrapper(void);
|
|
|
|
static int coex_wifi_channel_get_wrapper(uint8_t *primary, uint8_t *secondary);
|
|
|
|
static int coex_register_wifi_channel_change_callback_wrapper(void *cb);
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
static void *customer_queue_create_hlevel_wrapper(uint32_t queue_len, uint32_t item_size);
|
2021-09-02 09:49:30 -04:00
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2021-09-01 09:55:50 -04:00
|
|
|
static void IRAM_ATTR interrupt_l3_disable(void);
|
|
|
|
static void IRAM_ATTR interrupt_l3_restore(void);
|
|
|
|
|
2018-06-15 09:40:51 -04:00
|
|
|
/* Local variable definition
|
|
|
|
***************************************************************************
|
|
|
|
*/
|
|
|
|
/* OSI funcs */
|
|
|
|
static const struct osi_funcs_t osi_funcs_ro = {
|
|
|
|
._version = OSI_VERSION,
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
._set_isr = set_isr_hlevel_wrapper,
|
2018-06-15 09:40:51 -04:00
|
|
|
._ints_on = xt_ints_on,
|
2021-09-01 09:55:50 -04:00
|
|
|
._interrupt_disable = interrupt_hlevel_disable,
|
|
|
|
._interrupt_restore = interrupt_hlevel_restore,
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
._set_isr = xt_set_interrupt_handler,
|
|
|
|
._ints_on = xt_ints_on,
|
|
|
|
._interrupt_disable = interrupt_l3_disable,
|
|
|
|
._interrupt_restore = interrupt_l3_restore,
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2021-09-01 09:55:50 -04:00
|
|
|
._task_yield = task_yield,
|
2018-06-15 09:40:51 -04:00
|
|
|
._task_yield_from_isr = task_yield_from_isr,
|
|
|
|
._semphr_create = semphr_create_wrapper,
|
|
|
|
._semphr_delete = semphr_delete_wrapper,
|
|
|
|
._semphr_take_from_isr = semphr_take_from_isr_wrapper,
|
|
|
|
._semphr_give_from_isr = semphr_give_from_isr_wrapper,
|
|
|
|
._semphr_take = semphr_take_wrapper,
|
|
|
|
._semphr_give = semphr_give_wrapper,
|
|
|
|
._mutex_create = mutex_create_wrapper,
|
|
|
|
._mutex_delete = mutex_delete_wrapper,
|
|
|
|
._mutex_lock = mutex_lock_wrapper,
|
|
|
|
._mutex_unlock = mutex_unlock_wrapper,
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
._queue_create = queue_create_hlevel_wrapper,
|
|
|
|
._queue_delete = queue_delete_hlevel_wrapper,
|
|
|
|
._queue_send = queue_send_hlevel_wrapper,
|
|
|
|
._queue_send_from_isr = queue_send_from_isr_hlevel_wrapper,
|
|
|
|
._queue_recv = queue_recv_hlevel_wrapper,
|
|
|
|
._queue_recv_from_isr = queue_recv_from_isr_hlevel_wrapper,
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
._queue_create = queue_create_wrapper,
|
|
|
|
._queue_delete = queue_delete_wrapper,
|
|
|
|
._queue_send = queue_send_wrapper,
|
|
|
|
._queue_send_from_isr = queue_send_from_isr_wrapper,
|
|
|
|
._queue_recv = queue_recv_wrapper,
|
|
|
|
._queue_recv_from_isr = queue_recv_from_isr_wrapper,
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2018-06-15 09:40:51 -04:00
|
|
|
._task_create = task_create_wrapper,
|
|
|
|
._task_delete = task_delete_wrapper,
|
|
|
|
._is_in_isr = is_in_isr_wrapper,
|
|
|
|
._cause_sw_intr_to_core = cause_sw_intr_to_core_wrapper,
|
|
|
|
._malloc = malloc,
|
|
|
|
._malloc_internal = malloc_internal_wrapper,
|
|
|
|
._free = free,
|
|
|
|
._read_efuse_mac = read_mac_wrapper,
|
|
|
|
._srand = srand_wrapper,
|
|
|
|
._rand = rand_wrapper,
|
|
|
|
._btdm_lpcycles_2_us = btdm_lpcycles_2_us,
|
|
|
|
._btdm_us_2_lpcycles = btdm_us_2_lpcycles,
|
|
|
|
._btdm_sleep_check_duration = btdm_sleep_check_duration,
|
2018-12-11 03:49:01 -05:00
|
|
|
._btdm_sleep_enter_phase1 = btdm_sleep_enter_phase1_wrapper,
|
|
|
|
._btdm_sleep_enter_phase2 = btdm_sleep_enter_phase2_wrapper,
|
2020-09-03 08:51:19 -04:00
|
|
|
._btdm_sleep_exit_phase1 = NULL,
|
2018-12-11 03:49:01 -05:00
|
|
|
._btdm_sleep_exit_phase2 = NULL,
|
|
|
|
._btdm_sleep_exit_phase3 = btdm_sleep_exit_phase3_wrapper,
|
2020-03-20 05:58:05 -04:00
|
|
|
._coex_bt_wakeup_request = coex_bt_wakeup_request,
|
|
|
|
._coex_bt_wakeup_request_end = coex_bt_wakeup_request_end,
|
2019-02-20 08:01:27 -05:00
|
|
|
._coex_bt_request = coex_bt_request_wrapper,
|
|
|
|
._coex_bt_release = coex_bt_release_wrapper,
|
|
|
|
._coex_register_bt_cb = coex_register_bt_cb_wrapper,
|
|
|
|
._coex_bb_reset_lock = coex_bb_reset_lock_wrapper,
|
|
|
|
._coex_bb_reset_unlock = coex_bb_reset_unlock_wrapper,
|
2021-03-23 04:55:30 -04:00
|
|
|
._coex_schm_register_btdm_callback = coex_schm_register_btdm_callback_wrapper,
|
|
|
|
._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper,
|
|
|
|
._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper,
|
|
|
|
._coex_schm_interval_get = coex_schm_interval_get_wrapper,
|
|
|
|
._coex_schm_curr_period_get = coex_schm_curr_period_get_wrapper,
|
|
|
|
._coex_schm_curr_phase_get = coex_schm_curr_phase_get_wrapper,
|
|
|
|
._coex_wifi_channel_get = coex_wifi_channel_get_wrapper,
|
|
|
|
._coex_register_wifi_channel_change_callback = coex_register_wifi_channel_change_callback_wrapper,
|
2021-09-01 09:55:50 -04:00
|
|
|
._set_isr_l3 = xt_set_interrupt_handler,
|
|
|
|
._interrupt_l3_disable = interrupt_l3_disable,
|
|
|
|
._interrupt_l3_restore = interrupt_l3_restore,
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
._customer_queue_create = customer_queue_create_hlevel_wrapper,
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
._customer_queue_create = NULL,
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2018-06-15 09:40:51 -04:00
|
|
|
._magic = OSI_MAGIC_VALUE,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* the mode column will be modified by release function to indicate the available region */
|
|
|
|
static btdm_dram_available_region_t btdm_dram_available_region[] = {
|
|
|
|
//following is .data
|
|
|
|
{ESP_BT_MODE_BTDM, SOC_MEM_BT_DATA_START, SOC_MEM_BT_DATA_END },
|
|
|
|
//following is memory which HW will use
|
|
|
|
{ESP_BT_MODE_BTDM, SOC_MEM_BT_EM_BTDM0_START, SOC_MEM_BT_EM_BTDM0_END },
|
|
|
|
{ESP_BT_MODE_BLE, SOC_MEM_BT_EM_BLE_START, SOC_MEM_BT_EM_BLE_END },
|
|
|
|
{ESP_BT_MODE_BTDM, SOC_MEM_BT_EM_BTDM1_START, SOC_MEM_BT_EM_BTDM1_END },
|
|
|
|
{ESP_BT_MODE_CLASSIC_BT, SOC_MEM_BT_EM_BREDR_START, SOC_MEM_BT_EM_BREDR_REAL_END},
|
|
|
|
//following is .bss
|
|
|
|
{ESP_BT_MODE_BTDM, SOC_MEM_BT_BSS_START, SOC_MEM_BT_BSS_END },
|
|
|
|
{ESP_BT_MODE_BTDM, SOC_MEM_BT_MISC_START, SOC_MEM_BT_MISC_END },
|
2016-10-18 09:49:00 -04:00
|
|
|
};
|
|
|
|
|
2018-06-15 09:40:51 -04:00
|
|
|
/* Reserve the full memory region used by Bluetooth Controller,
|
|
|
|
* some may be released later at runtime. */
|
|
|
|
SOC_RESERVE_MEMORY_REGION(SOC_MEM_BT_EM_START, SOC_MEM_BT_EM_BREDR_REAL_END, rom_bt_em);
|
|
|
|
SOC_RESERVE_MEMORY_REGION(SOC_MEM_BT_BSS_START, SOC_MEM_BT_BSS_END, rom_bt_bss);
|
|
|
|
SOC_RESERVE_MEMORY_REGION(SOC_MEM_BT_MISC_START, SOC_MEM_BT_MISC_END, rom_bt_misc);
|
|
|
|
SOC_RESERVE_MEMORY_REGION(SOC_MEM_BT_DATA_START, SOC_MEM_BT_DATA_END, rom_bt_data);
|
|
|
|
|
2018-12-13 22:29:00 -05:00
|
|
|
static DRAM_ATTR struct osi_funcs_t *osi_funcs_p;
|
2018-06-15 09:40:51 -04:00
|
|
|
|
2021-09-03 04:51:09 -04:00
|
|
|
#if CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
static DRAM_ATTR btdm_queue_item_t btdm_queue_table[BTDM_MAX_QUEUE_NUM];
|
|
|
|
static DRAM_ATTR SemaphoreHandle_t btdm_queue_table_mux = NULL;
|
|
|
|
#endif /* #if CONFIG_SPIRAM_USE_MALLOC */
|
|
|
|
|
2017-02-17 06:24:58 -05:00
|
|
|
/* Static variable declare */
|
2018-12-11 03:49:01 -05:00
|
|
|
// timestamp when PHY/RF was switched on
|
2018-12-13 22:29:00 -05:00
|
|
|
static DRAM_ATTR int64_t s_time_phy_rf_just_enabled = 0;
|
|
|
|
static DRAM_ATTR esp_bt_controller_status_t btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
2017-02-17 06:24:58 -05:00
|
|
|
|
2018-12-13 22:29:00 -05:00
|
|
|
static DRAM_ATTR portMUX_TYPE global_int_mux = portMUX_INITIALIZER_UNLOCKED;
|
2016-10-18 09:49:00 -04:00
|
|
|
|
2018-04-08 07:19:47 -04:00
|
|
|
// measured average low power clock period in micro seconds
|
2018-12-13 22:29:00 -05:00
|
|
|
static DRAM_ATTR uint32_t btdm_lpcycle_us = 0;
|
|
|
|
static DRAM_ATTR uint8_t btdm_lpcycle_us_frac = 0; // number of fractional bit for btdm_lpcycle_us
|
2018-04-08 07:19:47 -04:00
|
|
|
|
2020-07-09 08:58:13 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG
|
2020-02-20 01:34:28 -05:00
|
|
|
// used low power clock
|
|
|
|
static DRAM_ATTR uint8_t btdm_lpclk_sel;
|
2020-07-09 08:58:13 -04:00
|
|
|
#endif /* #ifdef CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG */
|
2020-02-20 01:34:28 -05:00
|
|
|
|
2020-09-03 08:51:19 -04:00
|
|
|
static DRAM_ATTR QueueHandle_t s_wakeup_req_sem = NULL;
|
2017-10-09 03:34:31 -04:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2018-12-13 22:29:00 -05:00
|
|
|
static DRAM_ATTR esp_timer_handle_t s_btdm_slp_tmr;
|
|
|
|
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock;
|
2020-09-03 08:51:19 -04:00
|
|
|
static bool s_pm_lock_acquired = true;
|
2020-02-20 01:34:28 -05:00
|
|
|
static DRAM_ATTR bool s_btdm_allow_light_sleep;
|
2019-04-09 07:48:13 -04:00
|
|
|
// pm_lock to prevent light sleep when using main crystal as Bluetooth low power clock
|
|
|
|
static DRAM_ATTR esp_pm_lock_handle_t s_light_sleep_pm_lock;
|
2018-12-11 03:49:01 -05:00
|
|
|
static void btdm_slp_tmr_callback(void *arg);
|
2020-02-20 01:34:28 -05:00
|
|
|
#endif /* #ifdef CONFIG_PM_ENABLE */
|
|
|
|
|
2017-10-09 03:34:31 -04:00
|
|
|
|
2021-09-14 05:47:09 -04:00
|
|
|
static inline void esp_bt_power_domain_on(void)
|
|
|
|
{
|
|
|
|
// Bluetooth module power up
|
|
|
|
esp_wifi_bt_power_domain_on();
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void esp_bt_power_domain_off(void)
|
|
|
|
{
|
|
|
|
// Bluetooth module power down
|
|
|
|
esp_wifi_bt_power_domain_off();
|
|
|
|
}
|
|
|
|
|
2018-12-11 03:49:01 -05:00
|
|
|
static inline void btdm_check_and_init_bb(void)
|
|
|
|
{
|
|
|
|
/* init BT-BB if PHY/RF has been switched off since last BT-BB init */
|
|
|
|
int64_t latest_ts = esp_phy_rf_get_on_ts();
|
|
|
|
if (latest_ts != s_time_phy_rf_just_enabled ||
|
|
|
|
s_time_phy_rf_just_enabled == 0) {
|
|
|
|
btdm_rf_bb_init_phase2();
|
|
|
|
s_time_phy_rf_just_enabled = latest_ts;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-09-03 04:51:09 -04:00
|
|
|
#if CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
static bool btdm_queue_generic_register(const btdm_queue_item_t *queue)
|
|
|
|
{
|
|
|
|
if (!btdm_queue_table_mux || !queue) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ret = false;
|
|
|
|
btdm_queue_item_t *item;
|
|
|
|
xSemaphoreTake(btdm_queue_table_mux, portMAX_DELAY);
|
|
|
|
for (int i = 0; i < BTDM_MAX_QUEUE_NUM; ++i) {
|
|
|
|
item = &btdm_queue_table[i];
|
|
|
|
if (item->handle == NULL) {
|
|
|
|
memcpy(item, queue, sizeof(btdm_queue_item_t));
|
|
|
|
ret = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
xSemaphoreGive(btdm_queue_table_mux);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool btdm_queue_generic_deregister(btdm_queue_item_t *queue)
|
|
|
|
{
|
|
|
|
if (!btdm_queue_table_mux || !queue) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ret = false;
|
|
|
|
btdm_queue_item_t *item;
|
|
|
|
xSemaphoreTake(btdm_queue_table_mux, portMAX_DELAY);
|
|
|
|
for (int i = 0; i < BTDM_MAX_QUEUE_NUM; ++i) {
|
|
|
|
item = &btdm_queue_table[i];
|
|
|
|
if (item->handle == queue->handle) {
|
|
|
|
memcpy(queue, item, sizeof(btdm_queue_item_t));
|
|
|
|
memset(item, 0, sizeof(btdm_queue_item_t));
|
|
|
|
ret = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
xSemaphoreGive(btdm_queue_table_mux);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_SPIRAM_USE_MALLOC */
|
|
|
|
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
struct interrupt_hlevel_cb{
|
|
|
|
uint32_t status;
|
|
|
|
uint8_t nested;
|
|
|
|
};
|
|
|
|
|
|
|
|
static DRAM_ATTR struct interrupt_hlevel_cb hli_cb = {
|
|
|
|
.status = 0,
|
|
|
|
.nested = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static xt_handler set_isr_hlevel_wrapper(int mask, xt_handler f, void *arg)
|
2018-03-29 23:39:42 -04:00
|
|
|
{
|
2021-09-01 09:55:50 -04:00
|
|
|
esp_err_t err = hli_intr_register((intr_handler_t) f, arg, DPORT_PRO_INTR_STATUS_0_REG, mask);
|
|
|
|
if (err == ESP_OK) {
|
|
|
|
return f;
|
|
|
|
} else {
|
|
|
|
return 0;
|
2018-03-29 23:39:42 -04:00
|
|
|
}
|
2021-09-01 09:55:50 -04:00
|
|
|
}
|
2018-03-29 23:39:42 -04:00
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static void IRAM_ATTR interrupt_hlevel_disable(void)
|
|
|
|
{
|
|
|
|
assert(xPortGetCoreID() == CONFIG_BTDM_CTRL_PINNED_TO_CORE);
|
2020-12-24 08:30:36 -05:00
|
|
|
assert(hli_cb.nested != ~0);
|
2021-09-01 09:55:50 -04:00
|
|
|
uint32_t status = hli_intr_disable();
|
|
|
|
if (hli_cb.nested++ == 0) {
|
|
|
|
hli_cb.status = status;
|
2018-03-29 23:39:42 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static void IRAM_ATTR interrupt_hlevel_restore(void)
|
2018-03-29 23:39:42 -04:00
|
|
|
{
|
2021-09-01 09:55:50 -04:00
|
|
|
assert(xPortGetCoreID() == CONFIG_BTDM_CTRL_PINNED_TO_CORE);
|
|
|
|
assert(hli_cb.nested > 0);
|
|
|
|
if (--hli_cb.nested == 0) {
|
|
|
|
hli_intr_restore(hli_cb.status);
|
2018-03-29 23:39:42 -04:00
|
|
|
}
|
|
|
|
}
|
2021-09-02 09:49:30 -04:00
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2018-03-29 23:39:42 -04:00
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static void IRAM_ATTR interrupt_l3_disable(void)
|
2016-10-18 09:49:00 -04:00
|
|
|
{
|
2018-07-01 09:35:00 -04:00
|
|
|
if (xPortInIsrContext()) {
|
|
|
|
portENTER_CRITICAL_ISR(&global_int_mux);
|
|
|
|
} else {
|
|
|
|
portENTER_CRITICAL(&global_int_mux);
|
|
|
|
}
|
2016-10-18 09:49:00 -04:00
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static void IRAM_ATTR interrupt_l3_restore(void)
|
2016-10-18 09:49:00 -04:00
|
|
|
{
|
2018-07-01 09:35:00 -04:00
|
|
|
if (xPortInIsrContext()) {
|
|
|
|
portEXIT_CRITICAL_ISR(&global_int_mux);
|
|
|
|
} else {
|
|
|
|
portEXIT_CRITICAL(&global_int_mux);
|
|
|
|
}
|
2016-10-18 09:49:00 -04:00
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static void IRAM_ATTR task_yield(void)
|
|
|
|
{
|
|
|
|
vPortYield();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2017-06-07 02:58:17 -04:00
|
|
|
static void IRAM_ATTR task_yield_from_isr(void)
|
|
|
|
{
|
|
|
|
portYIELD_FROM_ISR();
|
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static void *semphr_create_wrapper(uint32_t max, uint32_t init)
|
2016-10-18 09:49:00 -04:00
|
|
|
{
|
2021-09-03 04:51:09 -04:00
|
|
|
void *handle = NULL;
|
|
|
|
|
|
|
|
#if !CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
handle = (void *)xSemaphoreCreateCounting(max, init);
|
|
|
|
#else
|
|
|
|
StaticQueue_t *queue_buffer = NULL;
|
|
|
|
|
|
|
|
queue_buffer = heap_caps_malloc(sizeof(StaticQueue_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
|
|
|
|
if (!queue_buffer) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
handle = (void *)xSemaphoreCreateCountingStatic(max, init, queue_buffer);
|
|
|
|
if (!handle) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
btdm_queue_item_t item = {
|
|
|
|
.handle = handle,
|
|
|
|
.storage = NULL,
|
|
|
|
.buffer = queue_buffer,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (!btdm_queue_generic_register(&item)) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-03 04:51:09 -04:00
|
|
|
SemaphoreHandle_t downstream_semaphore = handle;
|
2021-09-01 09:55:50 -04:00
|
|
|
assert(downstream_semaphore);
|
|
|
|
hli_queue_handle_t s_semaphore = hli_semaphore_create(max, downstream_semaphore);
|
|
|
|
assert(downstream_semaphore);
|
|
|
|
return s_semaphore;
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
2021-09-03 04:51:09 -04:00
|
|
|
return handle;
|
2021-09-02 09:49:30 -04:00
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2021-09-03 04:51:09 -04:00
|
|
|
|
|
|
|
#if CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
error:
|
|
|
|
if (handle) {
|
|
|
|
vSemaphoreDelete(handle);
|
|
|
|
}
|
|
|
|
if (queue_buffer) {
|
|
|
|
free(queue_buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
#endif
|
2016-10-18 09:49:00 -04:00
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static void semphr_delete_wrapper(void *semphr)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
2021-09-03 04:51:09 -04:00
|
|
|
void *handle = NULL;
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
if (((hli_queue_handle_t)semphr)->downstream != NULL) {
|
2021-09-03 04:51:09 -04:00
|
|
|
handle = ((hli_queue_handle_t)semphr)->downstream;
|
2021-09-01 09:55:50 -04:00
|
|
|
}
|
2018-03-29 23:39:42 -04:00
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
hli_queue_delete(semphr);
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
2021-09-03 04:51:09 -04:00
|
|
|
handle = semphr;
|
2021-09-02 09:49:30 -04:00
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2021-09-03 04:51:09 -04:00
|
|
|
|
|
|
|
#if !CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
vSemaphoreDelete(handle);
|
|
|
|
#else
|
|
|
|
btdm_queue_item_t item = {
|
|
|
|
.handle = handle,
|
|
|
|
.storage = NULL,
|
|
|
|
.buffer = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (btdm_queue_generic_deregister(&item)) {
|
|
|
|
vSemaphoreDelete(item.handle);
|
|
|
|
free(item.buffer);
|
|
|
|
}
|
|
|
|
#endif
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
static int32_t IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw)
|
|
|
|
{
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
return (int32_t)xSemaphoreTakeFromISR(((hli_queue_handle_t)semphr)->downstream, hptw);
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
return (int32_t)xSemaphoreTakeFromISR(semphr, hptw);
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
2016-10-18 09:49:00 -04:00
|
|
|
static int32_t IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw)
|
|
|
|
{
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
UNUSED(hptw);
|
|
|
|
assert(xPortGetCoreID() == CONFIG_BTDM_CTRL_PINNED_TO_CORE);
|
|
|
|
return hli_semaphore_give(semphr);
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2016-10-18 09:49:00 -04:00
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static int32_t semphr_take_wrapper(void *semphr, uint32_t block_time_ms)
|
2016-10-18 09:49:00 -04:00
|
|
|
{
|
2021-09-01 09:55:50 -04:00
|
|
|
bool ret;
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2017-07-11 09:46:17 -04:00
|
|
|
if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) {
|
2021-09-01 09:55:50 -04:00
|
|
|
ret = xSemaphoreTake(((hli_queue_handle_t)semphr)->downstream, portMAX_DELAY);
|
2017-07-11 09:46:17 -04:00
|
|
|
} else {
|
2021-09-01 09:55:50 -04:00
|
|
|
ret = xSemaphoreTake(((hli_queue_handle_t)semphr)->downstream, block_time_ms / portTICK_PERIOD_MS);
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) {
|
|
|
|
ret = xSemaphoreTake(semphr, portMAX_DELAY);
|
|
|
|
} else {
|
|
|
|
ret = xSemaphoreTake(semphr, block_time_ms / portTICK_PERIOD_MS);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2021-09-01 09:55:50 -04:00
|
|
|
return (int32_t)ret;
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static int32_t semphr_give_wrapper(void *semphr)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
return (int32_t)xSemaphoreGive(((hli_queue_handle_t)semphr)->downstream);
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
return (int32_t)xSemaphoreGive(semphr);
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2016-10-18 09:49:00 -04:00
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static void *mutex_create_wrapper(void)
|
2016-10-18 09:49:00 -04:00
|
|
|
{
|
2021-09-03 04:51:09 -04:00
|
|
|
#if CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
StaticQueue_t *queue_buffer = NULL;
|
|
|
|
QueueHandle_t handle = NULL;
|
|
|
|
|
|
|
|
queue_buffer = heap_caps_malloc(sizeof(StaticQueue_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
|
|
|
|
if (!queue_buffer) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
handle = xSemaphoreCreateMutexStatic(queue_buffer);
|
|
|
|
if (!handle) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
btdm_queue_item_t item = {
|
|
|
|
.handle = handle,
|
|
|
|
.storage = NULL,
|
|
|
|
.buffer = queue_buffer,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (!btdm_queue_generic_register(&item)) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
return handle;
|
|
|
|
|
|
|
|
error:
|
|
|
|
if (handle) {
|
|
|
|
vSemaphoreDelete(handle);
|
|
|
|
}
|
|
|
|
if (queue_buffer) {
|
|
|
|
free(queue_buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
#else
|
2016-10-18 09:49:00 -04:00
|
|
|
return (void *)xSemaphoreCreateMutex();
|
2021-09-03 04:51:09 -04:00
|
|
|
#endif
|
2016-10-18 09:49:00 -04:00
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static void mutex_delete_wrapper(void *mutex)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
2021-09-03 04:51:09 -04:00
|
|
|
#if !CONFIG_SPIRAM_USE_MALLOC
|
2017-07-11 09:46:17 -04:00
|
|
|
vSemaphoreDelete(mutex);
|
2021-09-03 04:51:09 -04:00
|
|
|
#else
|
|
|
|
btdm_queue_item_t item = {
|
|
|
|
.handle = mutex,
|
|
|
|
.storage = NULL,
|
|
|
|
.buffer = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (btdm_queue_generic_deregister(&item)) {
|
|
|
|
vSemaphoreDelete(item.handle);
|
|
|
|
free(item.buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
#endif
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static int32_t mutex_lock_wrapper(void *mutex)
|
2016-10-18 09:49:00 -04:00
|
|
|
{
|
|
|
|
return (int32_t)xSemaphoreTake(mutex, portMAX_DELAY);
|
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static int32_t mutex_unlock_wrapper(void *mutex)
|
2016-10-18 09:49:00 -04:00
|
|
|
{
|
|
|
|
return (int32_t)xSemaphoreGive(mutex);
|
|
|
|
}
|
|
|
|
|
2021-09-03 04:51:09 -04:00
|
|
|
static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size)
|
|
|
|
{
|
|
|
|
#if CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
StaticQueue_t *queue_buffer = NULL;
|
|
|
|
uint8_t *queue_storage = NULL;
|
|
|
|
QueueHandle_t handle = NULL;
|
|
|
|
|
|
|
|
queue_buffer = heap_caps_malloc(sizeof(StaticQueue_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
|
|
|
|
if (!queue_buffer) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
queue_storage = heap_caps_malloc((queue_len*item_size), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
|
|
|
|
if (!queue_storage ) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
handle = xQueueCreateStatic(queue_len, item_size, queue_storage, queue_buffer);
|
|
|
|
if (!handle) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
btdm_queue_item_t item = {
|
|
|
|
.handle = handle,
|
|
|
|
.storage = queue_storage,
|
|
|
|
.buffer = queue_buffer,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (!btdm_queue_generic_register(&item)) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
return handle;
|
|
|
|
|
|
|
|
error:
|
|
|
|
if (handle) {
|
|
|
|
vQueueDelete(handle);
|
|
|
|
}
|
|
|
|
if (queue_storage) {
|
|
|
|
free(queue_storage);
|
|
|
|
}
|
|
|
|
if (queue_buffer) {
|
|
|
|
free(queue_buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
#else
|
|
|
|
return (void *)xQueueCreate(queue_len, item_size);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void queue_delete_wrapper(void *queue)
|
|
|
|
{
|
|
|
|
#if !CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
vQueueDelete(queue);
|
|
|
|
#else
|
|
|
|
btdm_queue_item_t item = {
|
|
|
|
.handle = queue,
|
|
|
|
.storage = NULL,
|
|
|
|
.buffer = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (btdm_queue_generic_deregister(&item)) {
|
|
|
|
vQueueDelete(item.handle);
|
|
|
|
free(item.storage);
|
|
|
|
free(item.buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
static void *queue_create_hlevel_wrapper(uint32_t queue_len, uint32_t item_size)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
2021-09-03 04:51:09 -04:00
|
|
|
QueueHandle_t downstream_queue = queue_create_wrapper(queue_len, item_size);
|
2021-09-01 09:55:50 -04:00
|
|
|
assert(downstream_queue);
|
|
|
|
hli_queue_handle_t queue = hli_queue_create(queue_len, item_size, downstream_queue);
|
|
|
|
assert(queue);
|
|
|
|
return queue;
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static void *customer_queue_create_hlevel_wrapper(uint32_t queue_len, uint32_t item_size)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
2021-09-03 04:51:09 -04:00
|
|
|
QueueHandle_t downstream_queue = queue_create_wrapper(queue_len, item_size);
|
2021-09-01 09:55:50 -04:00
|
|
|
assert(downstream_queue);
|
|
|
|
hli_queue_handle_t queue = hli_customer_queue_create(queue_len, item_size, downstream_queue);
|
|
|
|
assert(queue);
|
|
|
|
return queue;
|
|
|
|
}
|
2018-03-29 23:39:42 -04:00
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static void queue_delete_hlevel_wrapper(void *queue)
|
|
|
|
{
|
|
|
|
if (((hli_queue_handle_t)queue)->downstream != NULL) {
|
2021-09-03 04:51:09 -04:00
|
|
|
queue_delete_wrapper(((hli_queue_handle_t)queue)->downstream);
|
2018-03-29 23:39:42 -04:00
|
|
|
}
|
2021-09-01 09:55:50 -04:00
|
|
|
hli_queue_delete(queue);
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static int32_t queue_send_hlevel_wrapper(void *queue, void *item, uint32_t block_time_ms)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
|
|
|
if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) {
|
2021-09-01 09:55:50 -04:00
|
|
|
return (int32_t)xQueueSend(((hli_queue_handle_t)queue)->downstream, item, portMAX_DELAY);
|
2017-07-11 09:46:17 -04:00
|
|
|
} else {
|
2021-09-01 09:55:50 -04:00
|
|
|
return (int32_t)xQueueSend(((hli_queue_handle_t)queue)->downstream, item, block_time_ms / portTICK_PERIOD_MS);
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
/**
|
|
|
|
* Queue send from isr
|
|
|
|
* @param queue The queue which will send to
|
|
|
|
* @param item The message which will be send
|
|
|
|
* @param hptw need do task yield or not
|
|
|
|
* @return send success or not
|
|
|
|
* There is an issue here: When the queue is full, it may reture true but it send fail to the queue, sometimes.
|
|
|
|
* But in Bluetooth controller's isr, We don't care about the return value.
|
|
|
|
* It only required tp send success when the queue is empty all the time.
|
|
|
|
* So, this function meets the requirement.
|
|
|
|
*/
|
|
|
|
static int32_t IRAM_ATTR queue_send_from_isr_hlevel_wrapper(void *queue, void *item, void *hptw)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
2021-09-01 09:55:50 -04:00
|
|
|
UNUSED(hptw);
|
|
|
|
assert(xPortGetCoreID() == CONFIG_BTDM_CTRL_PINNED_TO_CORE);
|
|
|
|
return hli_queue_put(queue, item);
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static int32_t queue_recv_hlevel_wrapper(void *queue, void *item, uint32_t block_time_ms)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
2021-09-01 09:55:50 -04:00
|
|
|
bool ret;
|
2017-07-11 09:46:17 -04:00
|
|
|
if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) {
|
2021-09-02 09:49:30 -04:00
|
|
|
ret = xQueueReceive(((hli_queue_handle_t)queue)->downstream, item, portMAX_DELAY);
|
2017-07-11 09:46:17 -04:00
|
|
|
} else {
|
2020-12-24 08:30:36 -05:00
|
|
|
ret = xQueueReceive(((hli_queue_handle_t)queue)->downstream, item, block_time_ms / portTICK_PERIOD_MS);
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
2021-09-01 09:55:50 -04:00
|
|
|
|
2021-09-02 09:49:30 -04:00
|
|
|
return (int32_t)ret;
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
static int32_t IRAM_ATTR queue_recv_from_isr_hlevel_wrapper(void *queue, void *item, void *hptw)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
2021-09-01 09:55:50 -04:00
|
|
|
return (int32_t)xQueueReceiveFromISR(((hli_queue_handle_t)queue)->downstream, item, hptw);
|
2017-07-11 09:46:17 -04:00
|
|
|
}
|
|
|
|
|
2021-09-02 09:49:30 -04:00
|
|
|
#else
|
|
|
|
|
|
|
|
static int32_t queue_send_wrapper(void *queue, void *item, uint32_t block_time_ms)
|
|
|
|
{
|
|
|
|
if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) {
|
|
|
|
return (int32_t)xQueueSend(queue, item, portMAX_DELAY);
|
|
|
|
} else {
|
|
|
|
return (int32_t)xQueueSend(queue, item, block_time_ms / portTICK_PERIOD_MS);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int32_t IRAM_ATTR queue_send_from_isr_wrapper(void *queue, void *item, void *hptw)
|
|
|
|
{
|
|
|
|
return (int32_t)xQueueSendFromISR(queue, item, hptw);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int32_t queue_recv_wrapper(void *queue, void *item, uint32_t block_time_ms)
|
|
|
|
{
|
|
|
|
bool ret;
|
|
|
|
if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) {
|
|
|
|
ret = xQueueReceive(queue, item, portMAX_DELAY);
|
|
|
|
} else {
|
|
|
|
ret = xQueueReceive(queue, item, block_time_ms / portTICK_PERIOD_MS);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (int32_t)ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int32_t IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, void *item, void *hptw)
|
|
|
|
{
|
|
|
|
return (int32_t)xQueueReceiveFromISR(queue, item, hptw);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
|
|
|
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static int32_t task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
|
|
|
return (uint32_t)xTaskCreatePinnedToCore(task_func, name, stack_depth, param, prio, task_handle, (core_id < portNUM_PROCESSORS ? core_id : tskNO_AFFINITY));
|
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static void task_delete_wrapper(void *task_handle)
|
2017-07-11 09:46:17 -04:00
|
|
|
{
|
|
|
|
vTaskDelete(task_handle);
|
|
|
|
}
|
|
|
|
|
2017-07-25 07:58:39 -04:00
|
|
|
static bool IRAM_ATTR is_in_isr_wrapper(void)
|
|
|
|
{
|
2019-10-28 06:43:35 -04:00
|
|
|
return !xPortCanYield();
|
2017-07-25 07:58:39 -04:00
|
|
|
}
|
|
|
|
|
2017-10-20 05:09:03 -04:00
|
|
|
static void IRAM_ATTR cause_sw_intr(void *arg)
|
|
|
|
{
|
|
|
|
/* just convert void * to int, because the width is the same */
|
|
|
|
uint32_t intr_no = (uint32_t)arg;
|
|
|
|
XTHAL_SET_INTSET((1<<intr_no));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int IRAM_ATTR cause_sw_intr_to_core_wrapper(int core_id, int intr_no)
|
|
|
|
{
|
|
|
|
esp_err_t err = ESP_OK;
|
|
|
|
|
2019-08-15 03:05:59 -04:00
|
|
|
#if CONFIG_FREERTOS_UNICORE
|
|
|
|
cause_sw_intr((void *)intr_no);
|
|
|
|
#else /* CONFIG_FREERTOS_UNICORE */
|
2017-10-20 05:09:03 -04:00
|
|
|
if (xPortGetCoreID() == core_id) {
|
|
|
|
cause_sw_intr((void *)intr_no);
|
|
|
|
} else {
|
|
|
|
err = esp_ipc_call(core_id, cause_sw_intr, (void *)intr_no);
|
|
|
|
}
|
2019-08-15 03:05:59 -04:00
|
|
|
#endif /* !CONFIG_FREERTOS_UNICORE */
|
2017-10-20 05:09:03 -04:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2018-10-29 04:54:32 -04:00
|
|
|
static void *malloc_internal_wrapper(size_t size)
|
2018-06-15 09:40:51 -04:00
|
|
|
{
|
2019-10-31 00:19:17 -04:00
|
|
|
return heap_caps_malloc(size, MALLOC_CAP_8BIT|MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
|
2018-06-15 09:40:51 -04:00
|
|
|
}
|
|
|
|
|
2017-03-01 08:04:12 -05:00
|
|
|
static int32_t IRAM_ATTR read_mac_wrapper(uint8_t mac[6])
|
|
|
|
{
|
|
|
|
return esp_read_mac(mac, ESP_MAC_BT);
|
|
|
|
}
|
|
|
|
|
2017-03-24 02:57:07 -04:00
|
|
|
static void IRAM_ATTR srand_wrapper(unsigned int seed)
|
|
|
|
{
|
|
|
|
/* empty function */
|
|
|
|
}
|
|
|
|
|
|
|
|
static int IRAM_ATTR rand_wrapper(void)
|
|
|
|
{
|
|
|
|
return (int)esp_random();
|
|
|
|
}
|
|
|
|
|
2018-04-08 07:19:47 -04:00
|
|
|
static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles)
|
|
|
|
{
|
2018-12-11 03:49:01 -05:00
|
|
|
// The number of lp cycles should not lead to overflow. Thrs: 100s
|
2018-04-08 07:19:47 -04:00
|
|
|
// clock measurement is conducted
|
|
|
|
uint64_t us = (uint64_t)btdm_lpcycle_us * cycles;
|
|
|
|
us = (us + (1 << (btdm_lpcycle_us_frac - 1))) >> btdm_lpcycle_us_frac;
|
|
|
|
return (uint32_t)us;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* @brief Converts a duration in slots into a number of low power clock cycles.
|
|
|
|
*/
|
|
|
|
static uint32_t IRAM_ATTR btdm_us_2_lpcycles(uint32_t us)
|
|
|
|
{
|
2018-06-27 05:23:23 -04:00
|
|
|
// The number of sleep duration(us) should not lead to overflow. Thrs: 100s
|
2018-04-08 07:19:47 -04:00
|
|
|
// Compute the sleep duration in us to low power clock cycles, with calibration result applied
|
|
|
|
// clock measurement is conducted
|
|
|
|
uint64_t cycles = ((uint64_t)(us) << btdm_lpcycle_us_frac) / btdm_lpcycle_us;
|
|
|
|
|
|
|
|
return (uint32_t)cycles;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool IRAM_ATTR btdm_sleep_check_duration(uint32_t *slot_cnt)
|
|
|
|
{
|
|
|
|
if (*slot_cnt < BTDM_MIN_SLEEP_DURATION) {
|
|
|
|
return false;
|
|
|
|
}
|
2018-12-11 03:49:01 -05:00
|
|
|
/* wake up in advance considering the delay in enabling PHY/RF */
|
|
|
|
*slot_cnt -= BTDM_MODEM_WAKE_UP_DELAY;
|
2018-04-08 07:19:47 -04:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-12-11 03:49:01 -05:00
|
|
|
static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
// start a timer to wake up and acquire the pm_lock before modem_sleep awakes
|
|
|
|
uint32_t us_to_sleep = btdm_lpcycles_2_us(lpcycles);
|
|
|
|
|
2019-04-09 05:06:16 -04:00
|
|
|
#define BTDM_MIN_TIMER_UNCERTAINTY_US (500)
|
2018-12-11 03:49:01 -05:00
|
|
|
assert(us_to_sleep > BTDM_MIN_TIMER_UNCERTAINTY_US);
|
|
|
|
// allow a maximum time uncertainty to be about 488ppm(1/2048) at least as clock drift
|
|
|
|
// and set the timer in advance
|
|
|
|
uint32_t uncertainty = (us_to_sleep >> 11);
|
|
|
|
if (uncertainty < BTDM_MIN_TIMER_UNCERTAINTY_US) {
|
|
|
|
uncertainty = BTDM_MIN_TIMER_UNCERTAINTY_US;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (esp_timer_start_once(s_btdm_slp_tmr, us_to_sleep - uncertainty) != ESP_OK) {
|
|
|
|
ESP_LOGW(BTDM_LOG_TAG, "timer start failed");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void btdm_sleep_enter_phase2_wrapper(void)
|
2018-04-08 07:19:47 -04:00
|
|
|
{
|
|
|
|
if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG) {
|
2020-05-22 05:15:28 -04:00
|
|
|
esp_phy_disable();
|
2018-12-11 03:49:01 -05:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-09-03 08:51:19 -04:00
|
|
|
if (s_pm_lock_acquired) {
|
|
|
|
esp_pm_lock_release(s_pm_lock);
|
|
|
|
s_pm_lock_acquired = false;
|
|
|
|
}
|
2018-12-11 03:49:01 -05:00
|
|
|
#endif
|
2018-04-08 07:19:47 -04:00
|
|
|
} else if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_EVED) {
|
2020-05-22 05:15:28 -04:00
|
|
|
esp_phy_disable();
|
2018-04-08 07:19:47 -04:00
|
|
|
// pause bluetooth baseband
|
|
|
|
periph_module_disable(PERIPH_BT_BASEBAND_MODULE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-09-03 08:51:19 -04:00
|
|
|
static void btdm_sleep_exit_phase3_wrapper(void)
|
2018-12-11 03:49:01 -05:00
|
|
|
{
|
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-09-03 08:51:19 -04:00
|
|
|
if (!s_pm_lock_acquired) {
|
|
|
|
s_pm_lock_acquired = true;
|
2018-12-11 03:49:01 -05:00
|
|
|
esp_pm_lock_acquire(s_pm_lock);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-04-08 07:19:47 -04:00
|
|
|
if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG) {
|
2020-05-22 05:15:28 -04:00
|
|
|
esp_phy_enable();
|
2018-12-11 03:49:01 -05:00
|
|
|
btdm_check_and_init_bb();
|
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
esp_timer_stop(s_btdm_slp_tmr);
|
|
|
|
#endif
|
2018-04-08 07:19:47 -04:00
|
|
|
} else if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_EVED) {
|
|
|
|
// resume bluetooth baseband
|
|
|
|
periph_module_enable(PERIPH_BT_BASEBAND_MODULE);
|
2020-05-22 05:15:28 -04:00
|
|
|
esp_phy_enable();
|
2018-04-08 07:19:47 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-11 03:49:01 -05:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-09-03 08:51:19 -04:00
|
|
|
static void btdm_slp_tmr_customer_callback(void * arg)
|
2018-12-11 03:49:01 -05:00
|
|
|
{
|
2020-09-03 08:51:19 -04:00
|
|
|
(void)(arg);
|
|
|
|
|
|
|
|
if (!s_pm_lock_acquired) {
|
|
|
|
s_pm_lock_acquired = true;
|
2018-12-11 03:49:01 -05:00
|
|
|
esp_pm_lock_acquire(s_pm_lock);
|
|
|
|
}
|
|
|
|
}
|
2020-09-03 08:51:19 -04:00
|
|
|
|
|
|
|
static void IRAM_ATTR btdm_slp_tmr_callback(void *arg)
|
|
|
|
{
|
|
|
|
(void)(arg);
|
|
|
|
btdm_dispatch_work_to_controller(btdm_slp_tmr_customer_callback, NULL, true);
|
|
|
|
}
|
2018-12-11 03:49:01 -05:00
|
|
|
#endif
|
|
|
|
|
2020-09-03 08:51:19 -04:00
|
|
|
#define BTDM_ASYNC_WAKEUP_REQ_HCI 0
|
|
|
|
#define BTDM_ASYNC_WAKEUP_REQ_COEX 1
|
|
|
|
#define BTDM_ASYNC_WAKEUP_REQ_CTRL_DISA 2
|
|
|
|
#define BTDM_ASYNC_WAKEUP_REQMAX 3
|
|
|
|
|
|
|
|
static void btdm_wakeup_request_callback(void * arg)
|
|
|
|
{
|
|
|
|
(void)(arg);
|
|
|
|
|
|
|
|
#if CONFIG_PM_ENABLE
|
|
|
|
if (!s_pm_lock_acquired) {
|
|
|
|
s_pm_lock_acquired = true;
|
|
|
|
esp_pm_lock_acquire(s_pm_lock);
|
|
|
|
}
|
|
|
|
esp_timer_stop(s_btdm_slp_tmr);
|
|
|
|
#endif
|
|
|
|
btdm_wakeup_request();
|
|
|
|
|
|
|
|
semphr_give_wrapper(s_wakeup_req_sem);
|
|
|
|
}
|
2017-01-03 02:53:06 -05:00
|
|
|
|
2020-03-20 05:58:05 -04:00
|
|
|
static bool async_wakeup_request(int event)
|
2017-01-03 02:53:06 -05:00
|
|
|
{
|
2020-09-03 08:51:19 -04:00
|
|
|
bool do_wakeup_request = false;
|
|
|
|
|
2020-03-20 05:58:05 -04:00
|
|
|
switch (event) {
|
|
|
|
case BTDM_ASYNC_WAKEUP_REQ_HCI:
|
2020-10-14 08:20:57 -04:00
|
|
|
btdm_in_wakeup_requesting_set(true);
|
2020-09-03 08:51:19 -04:00
|
|
|
// NO break
|
|
|
|
case BTDM_ASYNC_WAKEUP_REQ_CTRL_DISA:
|
|
|
|
if (!btdm_power_state_active()) {
|
|
|
|
do_wakeup_request = true;
|
|
|
|
|
|
|
|
btdm_dispatch_work_to_controller(btdm_wakeup_request_callback, NULL, true);
|
|
|
|
semphr_take_wrapper(s_wakeup_req_sem, OSI_FUNCS_TIME_BLOCKING);
|
|
|
|
}
|
2020-03-20 05:58:05 -04:00
|
|
|
break;
|
|
|
|
case BTDM_ASYNC_WAKEUP_REQ_COEX:
|
2020-09-03 08:51:19 -04:00
|
|
|
if (!btdm_power_state_active()) {
|
|
|
|
do_wakeup_request = true;
|
|
|
|
#if CONFIG_PM_ENABLE
|
|
|
|
if (!s_pm_lock_acquired) {
|
|
|
|
s_pm_lock_acquired = true;
|
|
|
|
esp_pm_lock_acquire(s_pm_lock);
|
|
|
|
}
|
|
|
|
esp_timer_stop(s_btdm_slp_tmr);
|
|
|
|
#endif
|
|
|
|
btdm_wakeup_request();
|
|
|
|
}
|
2020-03-20 05:58:05 -04:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return do_wakeup_request;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void async_wakeup_request_end(int event)
|
|
|
|
{
|
|
|
|
bool request_lock = false;
|
|
|
|
switch (event) {
|
|
|
|
case BTDM_ASYNC_WAKEUP_REQ_HCI:
|
|
|
|
request_lock = true;
|
|
|
|
break;
|
|
|
|
case BTDM_ASYNC_WAKEUP_REQ_COEX:
|
2020-09-03 08:51:19 -04:00
|
|
|
case BTDM_ASYNC_WAKEUP_REQ_CTRL_DISA:
|
2020-03-20 05:58:05 -04:00
|
|
|
request_lock = false;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (request_lock) {
|
2020-09-03 08:51:19 -04:00
|
|
|
btdm_in_wakeup_requesting_set(false);
|
2018-04-08 07:19:47 -04:00
|
|
|
}
|
2019-07-27 05:47:33 -04:00
|
|
|
|
2020-03-20 05:58:05 -04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool coex_bt_wakeup_request(void)
|
|
|
|
{
|
|
|
|
return async_wakeup_request(BTDM_ASYNC_WAKEUP_REQ_COEX);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void coex_bt_wakeup_request_end(void)
|
|
|
|
{
|
|
|
|
async_wakeup_request_end(BTDM_ASYNC_WAKEUP_REQ_COEX);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2021-03-23 04:55:30 -04:00
|
|
|
static int IRAM_ATTR coex_bt_request_wrapper(uint32_t event, uint32_t latency, uint32_t duration)
|
2020-08-26 05:51:13 -04:00
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_bt_request(event, latency, duration);
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-03-23 04:55:30 -04:00
|
|
|
static int IRAM_ATTR coex_bt_release_wrapper(uint32_t event)
|
2020-08-26 05:51:13 -04:00
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_bt_release(event);
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-03-23 04:55:30 -04:00
|
|
|
static int coex_register_bt_cb_wrapper(coex_func_cb_t cb)
|
2020-08-26 05:51:13 -04:00
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_register_bt_cb(cb);
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-03-23 04:55:30 -04:00
|
|
|
static uint32_t IRAM_ATTR coex_bb_reset_lock_wrapper(void)
|
2020-08-26 05:51:13 -04:00
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_bb_reset_lock();
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-03-23 04:55:30 -04:00
|
|
|
static void IRAM_ATTR coex_bb_reset_unlock_wrapper(uint32_t restore)
|
2020-08-26 05:51:13 -04:00
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
coex_bb_reset_unlock(restore);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-03-23 04:55:30 -04:00
|
|
|
static int coex_schm_register_btdm_callback_wrapper(void *callback)
|
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_schm_register_btdm_callback(callback);
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
|
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
coex_schm_status_bit_clear(type, status);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status)
|
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
coex_schm_status_bit_set(type, status);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t coex_schm_interval_get_wrapper(void)
|
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_schm_interval_get();
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint8_t coex_schm_curr_period_get_wrapper(void)
|
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_schm_curr_period_get();
|
|
|
|
#else
|
2021-03-23 09:11:12 -04:00
|
|
|
return 1;
|
2021-03-23 04:55:30 -04:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void * coex_schm_curr_phase_get_wrapper(void)
|
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_schm_curr_phase_get();
|
|
|
|
#else
|
|
|
|
return NULL;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static int coex_wifi_channel_get_wrapper(uint8_t *primary, uint8_t *secondary)
|
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_wifi_channel_get(primary, secondary);
|
|
|
|
#else
|
2021-03-23 09:11:12 -04:00
|
|
|
return -1;
|
2021-03-23 04:55:30 -04:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static int coex_register_wifi_channel_change_callback_wrapper(void *cb)
|
|
|
|
{
|
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
return coex_register_wifi_channel_change_callback(cb);
|
|
|
|
#else
|
2021-03-23 09:11:12 -04:00
|
|
|
return -1;
|
2021-03-23 04:55:30 -04:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2020-03-20 05:58:05 -04:00
|
|
|
bool esp_vhci_host_check_send_available(void)
|
|
|
|
{
|
|
|
|
return API_vhci_host_check_send_available();
|
|
|
|
}
|
|
|
|
|
|
|
|
void esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
|
|
|
|
{
|
2020-10-14 08:20:57 -04:00
|
|
|
async_wakeup_request(BTDM_ASYNC_WAKEUP_REQ_HCI);
|
2020-03-20 05:58:05 -04:00
|
|
|
|
2017-01-03 02:53:06 -05:00
|
|
|
API_vhci_host_send_packet(data, len);
|
2019-07-27 05:47:33 -04:00
|
|
|
|
2020-10-14 08:20:57 -04:00
|
|
|
async_wakeup_request_end(BTDM_ASYNC_WAKEUP_REQ_HCI);
|
2017-01-03 02:53:06 -05:00
|
|
|
}
|
|
|
|
|
2018-06-15 09:40:51 -04:00
|
|
|
esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
|
2017-01-03 02:53:06 -05:00
|
|
|
{
|
2018-06-15 09:40:51 -04:00
|
|
|
return API_vhci_host_register_callback((const vhci_host_callback_t *)callback) == 0 ? ESP_OK : ESP_FAIL;
|
2017-01-03 02:53:06 -05:00
|
|
|
}
|
|
|
|
|
2017-02-21 04:46:59 -05:00
|
|
|
static uint32_t btdm_config_mask_load(void)
|
|
|
|
{
|
|
|
|
uint32_t mask = 0x0;
|
|
|
|
|
2019-05-02 09:36:06 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HCI_MODE_UART_H4
|
2017-03-16 05:14:20 -04:00
|
|
|
mask |= BTDM_CFG_HCI_UART;
|
|
|
|
#endif
|
2019-05-02 09:36:06 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_PINNED_TO_CORE == 1
|
2017-03-16 05:14:20 -04:00
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mask |= BTDM_CFG_CONTROLLER_RUN_APP_CPU;
|
2017-02-21 04:46:59 -05:00
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|
#endif
|
2019-05-02 09:36:06 -04:00
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|
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#if CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED
|
2018-11-28 07:00:40 -05:00
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mask |= BTDM_CFG_BLE_FULL_SCAN_SUPPORTED;
|
2019-05-02 09:36:06 -04:00
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|
|
#endif /* CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED */
|
2018-05-03 08:22:08 -04:00
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mask |= BTDM_CFG_SCAN_DUPLICATE_OPTIONS;
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mask |= BTDM_CFG_SEND_ADV_RESERVED_SIZE;
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|
2017-02-21 04:46:59 -05:00
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|
|
return mask;
|
|
|
|
}
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|
|
|
|
2017-09-19 08:10:35 -04:00
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|
|
static void btdm_controller_mem_init(void)
|
2017-09-12 10:36:17 -04:00
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|
|
{
|
2018-06-15 09:40:51 -04:00
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|
|
/* initialise .data section */
|
2017-09-19 08:10:35 -04:00
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|
memcpy(&_data_start_btdm, (void *)_data_start_btdm_rom, &_data_end_btdm - &_data_start_btdm);
|
2018-08-28 04:01:07 -04:00
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|
ESP_LOGD(BTDM_LOG_TAG, ".data initialise [0x%08x] <== [0x%08x]", (uint32_t)&_data_start_btdm, _data_start_btdm_rom);
|
2017-09-19 08:10:35 -04:00
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|
|
2018-06-15 09:40:51 -04:00
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|
|
//initial em, .bss section
|
2017-09-19 08:10:35 -04:00
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for (int i = 1; i < sizeof(btdm_dram_available_region)/sizeof(btdm_dram_available_region_t); i++) {
|
|
|
|
if (btdm_dram_available_region[i].mode != ESP_BT_MODE_IDLE) {
|
|
|
|
memset((void *)btdm_dram_available_region[i].start, 0x0, btdm_dram_available_region[i].end - btdm_dram_available_region[i].start);
|
2018-08-28 04:01:07 -04:00
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|
|
ESP_LOGD(BTDM_LOG_TAG, ".bss initialise [0x%08x] - [0x%08x]", btdm_dram_available_region[i].start, btdm_dram_available_region[i].end);
|
2017-09-19 08:10:35 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-08-28 04:01:07 -04:00
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|
|
static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end)
|
|
|
|
{
|
|
|
|
int ret = heap_caps_add_region(start, end);
|
|
|
|
/* heap_caps_add_region() returns ESP_ERR_INVALID_SIZE if the memory region is
|
|
|
|
* is too small to fit a heap. This cannot be termed as a fatal error and hence
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|
|
|
* we replace it by ESP_OK
|
|
|
|
*/
|
|
|
|
if (ret == ESP_ERR_INVALID_SIZE) {
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-09-19 08:10:35 -04:00
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|
|
esp_err_t esp_bt_controller_mem_release(esp_bt_mode_t mode)
|
|
|
|
{
|
|
|
|
bool update = true;
|
2020-03-12 03:07:03 -04:00
|
|
|
intptr_t mem_start=(intptr_t) NULL, mem_end=(intptr_t) NULL;
|
2017-09-19 08:10:35 -04:00
|
|
|
|
2017-12-12 02:24:43 -05:00
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
2017-09-19 08:10:35 -04:00
|
|
|
}
|
|
|
|
|
2018-02-13 01:55:18 -05:00
|
|
|
//already released
|
2017-09-19 08:10:35 -04:00
|
|
|
if (!(mode & btdm_dram_available_region[0].mode)) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int i = 0; i < sizeof(btdm_dram_available_region)/sizeof(btdm_dram_available_region_t); i++) {
|
|
|
|
//skip the share mode, idle mode and other mode
|
|
|
|
if (btdm_dram_available_region[i].mode == ESP_BT_MODE_IDLE
|
|
|
|
|| (mode & btdm_dram_available_region[i].mode) != btdm_dram_available_region[i].mode) {
|
|
|
|
//clear the bit of the mode which will be released
|
|
|
|
btdm_dram_available_region[i].mode &= ~mode;
|
|
|
|
continue;
|
|
|
|
} else {
|
|
|
|
//clear the bit of the mode which will be released
|
|
|
|
btdm_dram_available_region[i].mode &= ~mode;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (update) {
|
|
|
|
mem_start = btdm_dram_available_region[i].start;
|
|
|
|
mem_end = btdm_dram_available_region[i].end;
|
|
|
|
update = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i < sizeof(btdm_dram_available_region)/sizeof(btdm_dram_available_region_t) - 1) {
|
|
|
|
mem_end = btdm_dram_available_region[i].end;
|
|
|
|
if (btdm_dram_available_region[i+1].mode != ESP_BT_MODE_IDLE
|
|
|
|
&& (mode & btdm_dram_available_region[i+1].mode) == btdm_dram_available_region[i+1].mode
|
|
|
|
&& mem_end == btdm_dram_available_region[i+1].start) {
|
|
|
|
continue;
|
|
|
|
} else {
|
2018-08-28 04:01:07 -04:00
|
|
|
ESP_LOGD(BTDM_LOG_TAG, "Release DRAM [0x%08x] - [0x%08x]", mem_start, mem_end);
|
|
|
|
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
|
2017-09-19 08:10:35 -04:00
|
|
|
update = true;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
mem_end = btdm_dram_available_region[i].end;
|
2018-08-28 04:01:07 -04:00
|
|
|
ESP_LOGD(BTDM_LOG_TAG, "Release DRAM [0x%08x] - [0x%08x]", mem_start, mem_end);
|
|
|
|
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
|
2017-09-19 08:10:35 -04:00
|
|
|
update = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-07-11 02:22:32 -04:00
|
|
|
if (mode == ESP_BT_MODE_BTDM) {
|
|
|
|
mem_start = (intptr_t)&_btdm_bss_start;
|
|
|
|
mem_end = (intptr_t)&_btdm_bss_end;
|
2018-08-17 02:49:48 -04:00
|
|
|
if (mem_start != mem_end) {
|
2018-08-28 04:01:07 -04:00
|
|
|
ESP_LOGD(BTDM_LOG_TAG, "Release BTDM BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
|
|
|
|
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
|
2018-08-17 02:49:48 -04:00
|
|
|
}
|
2018-07-11 02:22:32 -04:00
|
|
|
mem_start = (intptr_t)&_btdm_data_start;
|
|
|
|
mem_end = (intptr_t)&_btdm_data_end;
|
2018-08-17 02:49:48 -04:00
|
|
|
if (mem_start != mem_end) {
|
2018-08-28 04:01:07 -04:00
|
|
|
ESP_LOGD(BTDM_LOG_TAG, "Release BTDM Data [0x%08x] - [0x%08x]", mem_start, mem_end);
|
|
|
|
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
|
2018-08-17 02:49:48 -04:00
|
|
|
}
|
2018-07-11 02:22:32 -04:00
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
intptr_t mem_start, mem_end;
|
|
|
|
|
|
|
|
ret = esp_bt_controller_mem_release(mode);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mode == ESP_BT_MODE_BTDM) {
|
|
|
|
mem_start = (intptr_t)&_bt_bss_start;
|
|
|
|
mem_end = (intptr_t)&_bt_bss_end;
|
2018-08-17 02:49:48 -04:00
|
|
|
if (mem_start != mem_end) {
|
2018-08-28 04:01:07 -04:00
|
|
|
ESP_LOGD(BTDM_LOG_TAG, "Release BT BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
|
|
|
|
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
|
2018-08-17 02:49:48 -04:00
|
|
|
}
|
2018-07-11 02:22:32 -04:00
|
|
|
mem_start = (intptr_t)&_bt_data_start;
|
|
|
|
mem_end = (intptr_t)&_bt_data_end;
|
2018-08-17 02:49:48 -04:00
|
|
|
if (mem_start != mem_end) {
|
2018-08-28 04:01:07 -04:00
|
|
|
ESP_LOGD(BTDM_LOG_TAG, "Release BT Data [0x%08x] - [0x%08x]", mem_start, mem_end);
|
2019-06-24 21:03:58 -04:00
|
|
|
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
|
|
|
|
}
|
|
|
|
|
|
|
|
mem_start = (intptr_t)&_nimble_bss_start;
|
|
|
|
mem_end = (intptr_t)&_nimble_bss_end;
|
|
|
|
if (mem_start != mem_end) {
|
|
|
|
ESP_LOGD(BTDM_LOG_TAG, "Release NimBLE BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
|
|
|
|
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
|
|
|
|
}
|
|
|
|
mem_start = (intptr_t)&_nimble_data_start;
|
|
|
|
mem_end = (intptr_t)&_nimble_data_end;
|
|
|
|
if (mem_start != mem_end) {
|
|
|
|
ESP_LOGD(BTDM_LOG_TAG, "Release NimBLE Data [0x%08x] - [0x%08x]", mem_start, mem_end);
|
2018-08-28 04:01:07 -04:00
|
|
|
ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
|
2018-08-17 02:49:48 -04:00
|
|
|
}
|
2018-07-11 02:22:32 -04:00
|
|
|
}
|
2017-09-19 08:10:35 -04:00
|
|
|
return ESP_OK;
|
2017-09-12 10:36:17 -04:00
|
|
|
}
|
|
|
|
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
static void hli_queue_setup_cb(void* arg)
|
|
|
|
{
|
|
|
|
hli_queue_setup();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hli_queue_setup_pinned_to_core(int core_id)
|
|
|
|
{
|
|
|
|
#if CONFIG_FREERTOS_UNICORE
|
|
|
|
hli_queue_setup_cb(NULL);
|
|
|
|
#else /* CONFIG_FREERTOS_UNICORE */
|
|
|
|
if (xPortGetCoreID() == core_id) {
|
|
|
|
hli_queue_setup_cb(NULL);
|
|
|
|
} else {
|
|
|
|
esp_ipc_call(core_id, hli_queue_setup_cb, NULL);
|
|
|
|
}
|
|
|
|
#endif /* !CONFIG_FREERTOS_UNICORE */
|
|
|
|
}
|
2021-09-02 09:49:30 -04:00
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2021-09-01 09:55:50 -04:00
|
|
|
|
2017-04-05 09:19:15 -04:00
|
|
|
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
|
2016-10-18 09:49:00 -04:00
|
|
|
{
|
2018-12-11 03:49:01 -05:00
|
|
|
esp_err_t err;
|
2017-07-11 09:46:17 -04:00
|
|
|
uint32_t btdm_cfg_mask = 0;
|
2017-04-05 09:19:15 -04:00
|
|
|
|
2021-09-02 09:49:30 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_HLI
|
2021-09-01 09:55:50 -04:00
|
|
|
hli_queue_setup_pinned_to_core(CONFIG_BTDM_CTRL_PINNED_TO_CORE);
|
2021-09-02 09:49:30 -04:00
|
|
|
#endif /* CONFIG_BTDM_CTRL_HLI */
|
2021-09-01 09:55:50 -04:00
|
|
|
|
2020-10-26 03:56:55 -04:00
|
|
|
//if all the bt available memory was already released, cannot initialize bluetooth controller
|
|
|
|
if (btdm_dram_available_region[0].mode == ESP_BT_MODE_IDLE) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2020-11-10 02:40:01 -05:00
|
|
|
|
2018-06-15 09:40:51 -04:00
|
|
|
osi_funcs_p = (struct osi_funcs_t *)malloc_internal_wrapper(sizeof(struct osi_funcs_t));
|
|
|
|
if (osi_funcs_p == NULL) {
|
|
|
|
return ESP_ERR_NO_MEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(osi_funcs_p, &osi_funcs_ro, sizeof(struct osi_funcs_t));
|
|
|
|
if (btdm_osi_funcs_register(osi_funcs_p) != 0) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
|
2017-02-20 12:05:37 -05:00
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
|
2017-04-05 09:19:15 -04:00
|
|
|
return ESP_ERR_INVALID_STATE;
|
2017-02-20 12:05:37 -05:00
|
|
|
}
|
|
|
|
|
2017-04-05 09:19:15 -04:00
|
|
|
if (cfg == NULL) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
|
2017-07-11 09:46:17 -04:00
|
|
|
if (cfg->controller_task_prio != ESP_TASK_BT_CONTROLLER_PRIO
|
|
|
|
|| cfg->controller_task_stack_size < ESP_TASK_BT_CONTROLLER_STACK) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
2017-06-13 05:14:50 -04:00
|
|
|
}
|
|
|
|
|
2018-06-15 09:40:51 -04:00
|
|
|
//overwrite some parameters
|
2019-05-02 09:36:06 -04:00
|
|
|
cfg->bt_max_sync_conn = CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF;
|
2018-06-15 09:40:51 -04:00
|
|
|
cfg->magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL;
|
|
|
|
|
|
|
|
if (((cfg->mode & ESP_BT_MODE_BLE) && (cfg->ble_max_conn <= 0 || cfg->ble_max_conn > BTDM_CONTROLLER_BLE_MAX_CONN_LIMIT))
|
|
|
|
|| ((cfg->mode & ESP_BT_MODE_CLASSIC_BT) && (cfg->bt_max_acl_conn <= 0 || cfg->bt_max_acl_conn > BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_LIMIT))
|
|
|
|
|| ((cfg->mode & ESP_BT_MODE_CLASSIC_BT) && (cfg->bt_max_sync_conn > BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_LIMIT))) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
|
2018-08-28 04:01:07 -04:00
|
|
|
ESP_LOGI(BTDM_LOG_TAG, "BT controller compile version [%s]", btdm_controller_get_compile_version());
|
2018-03-27 04:35:00 -04:00
|
|
|
|
2021-09-03 04:51:09 -04:00
|
|
|
#if CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
btdm_queue_table_mux = xSemaphoreCreateMutex();
|
|
|
|
if (btdm_queue_table_mux == NULL) {
|
|
|
|
return ESP_ERR_NO_MEM;
|
|
|
|
}
|
|
|
|
memset(btdm_queue_table, 0, sizeof(btdm_queue_item_t) * BTDM_MAX_QUEUE_NUM);
|
|
|
|
#endif
|
|
|
|
|
2020-09-03 08:51:19 -04:00
|
|
|
s_wakeup_req_sem = semphr_create_wrapper(1, 0);
|
|
|
|
if (s_wakeup_req_sem == NULL) {
|
|
|
|
err = ESP_ERR_NO_MEM;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2021-09-14 05:47:09 -04:00
|
|
|
esp_bt_power_domain_on();
|
|
|
|
|
2020-02-20 01:34:28 -05:00
|
|
|
btdm_controller_mem_init();
|
|
|
|
|
|
|
|
periph_module_enable(PERIPH_BT_MODULE);
|
|
|
|
|
2018-12-11 03:49:01 -05:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-02-20 01:34:28 -05:00
|
|
|
s_btdm_allow_light_sleep = false;
|
|
|
|
#endif
|
|
|
|
|
2020-02-26 02:58:44 -05:00
|
|
|
// set default sleep clock cycle and its fractional bits
|
|
|
|
btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT;
|
|
|
|
btdm_lpcycle_us = 2 << (btdm_lpcycle_us_frac);
|
|
|
|
|
2020-07-09 08:58:13 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG
|
2020-02-20 01:34:28 -05:00
|
|
|
|
|
|
|
btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL; // set default value
|
2020-07-09 08:58:13 -04:00
|
|
|
#if CONFIG_BTDM_CTRL_LPCLK_SEL_EXT_32K_XTAL
|
2020-02-20 01:34:28 -05:00
|
|
|
// check whether or not EXT_CRYS is working
|
|
|
|
if (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_32K_XTAL) {
|
2021-08-10 03:51:09 -04:00
|
|
|
btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL32K; // External 32kHz XTAL
|
2020-02-20 01:34:28 -05:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
s_btdm_allow_light_sleep = true;
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
ESP_LOGW(BTDM_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock\n"
|
|
|
|
"light sleep mode will not be able to apply when bluetooth is enabled");
|
|
|
|
btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL; // set default value
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL; // set default value
|
|
|
|
#endif
|
|
|
|
|
2021-02-12 00:01:05 -05:00
|
|
|
bool select_src_ret __attribute__((unused));
|
|
|
|
bool set_div_ret __attribute__((unused));
|
2020-02-20 01:34:28 -05:00
|
|
|
if (btdm_lpclk_sel == BTDM_LPCLK_SEL_XTAL) {
|
|
|
|
select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL);
|
|
|
|
set_div_ret = btdm_lpclk_set_div(rtc_clk_xtal_freq_get() * 2 - 1);
|
|
|
|
assert(select_src_ret && set_div_ret);
|
|
|
|
btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT;
|
|
|
|
btdm_lpcycle_us = 2 << (btdm_lpcycle_us_frac);
|
|
|
|
} else { // btdm_lpclk_sel == BTDM_LPCLK_SEL_XTAL32K
|
|
|
|
select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL32K);
|
|
|
|
set_div_ret = btdm_lpclk_set_div(0);
|
|
|
|
assert(select_src_ret && set_div_ret);
|
|
|
|
btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT;
|
|
|
|
btdm_lpcycle_us = (RTC_CLK_CAL_FRACT > 15) ? (1000000 << (RTC_CLK_CAL_FRACT - 15)) :
|
|
|
|
(1000000 >> (15 - RTC_CLK_CAL_FRACT));
|
|
|
|
assert(btdm_lpcycle_us != 0);
|
|
|
|
}
|
|
|
|
btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_ORIG);
|
|
|
|
|
2020-07-09 08:58:13 -04:00
|
|
|
#elif CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_EVED
|
2020-02-20 01:34:28 -05:00
|
|
|
btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_EVED);
|
|
|
|
#else
|
|
|
|
btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_NONE);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
if (!s_btdm_allow_light_sleep) {
|
|
|
|
if ((err = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "btLS", &s_light_sleep_pm_lock)) != ESP_OK) {
|
|
|
|
goto error;
|
|
|
|
}
|
2018-12-17 06:54:57 -05:00
|
|
|
}
|
2018-12-11 03:49:01 -05:00
|
|
|
if ((err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "bt", &s_pm_lock)) != ESP_OK) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
esp_timer_create_args_t create_args = {
|
|
|
|
.callback = btdm_slp_tmr_callback,
|
|
|
|
.arg = NULL,
|
|
|
|
.name = "btSlp"
|
|
|
|
};
|
|
|
|
if ((err = esp_timer_create(&create_args, &s_btdm_slp_tmr)) != ESP_OK) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2020-09-03 08:51:19 -04:00
|
|
|
s_pm_lock_acquired = true;
|
2018-12-11 03:49:01 -05:00
|
|
|
#endif
|
|
|
|
|
2020-08-26 05:51:13 -04:00
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
coex_init();
|
|
|
|
#endif
|
|
|
|
|
2017-07-11 09:46:17 -04:00
|
|
|
btdm_cfg_mask = btdm_config_mask_load();
|
2017-04-05 09:19:15 -04:00
|
|
|
|
2018-12-11 03:49:01 -05:00
|
|
|
if (btdm_controller_init(btdm_cfg_mask, cfg) != 0) {
|
|
|
|
err = ESP_ERR_NO_MEM;
|
|
|
|
goto error;
|
2017-04-05 09:19:15 -04:00
|
|
|
}
|
|
|
|
|
2017-07-11 09:46:17 -04:00
|
|
|
btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
|
2018-12-11 03:49:01 -05:00
|
|
|
|
2017-04-05 09:19:15 -04:00
|
|
|
return ESP_OK;
|
2018-12-11 03:49:01 -05:00
|
|
|
|
|
|
|
error:
|
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-02-20 01:34:28 -05:00
|
|
|
if (!s_btdm_allow_light_sleep) {
|
|
|
|
if (s_light_sleep_pm_lock != NULL) {
|
|
|
|
esp_pm_lock_delete(s_light_sleep_pm_lock);
|
|
|
|
s_light_sleep_pm_lock = NULL;
|
|
|
|
}
|
2018-12-17 06:54:57 -05:00
|
|
|
}
|
2018-12-11 03:49:01 -05:00
|
|
|
if (s_pm_lock != NULL) {
|
|
|
|
esp_pm_lock_delete(s_pm_lock);
|
|
|
|
s_pm_lock = NULL;
|
|
|
|
}
|
|
|
|
if (s_btdm_slp_tmr != NULL) {
|
|
|
|
esp_timer_delete(s_btdm_slp_tmr);
|
|
|
|
s_btdm_slp_tmr = NULL;
|
|
|
|
}
|
|
|
|
#endif
|
2020-09-03 08:51:19 -04:00
|
|
|
if (s_wakeup_req_sem) {
|
|
|
|
semphr_delete_wrapper(s_wakeup_req_sem);
|
|
|
|
s_wakeup_req_sem = NULL;
|
|
|
|
}
|
2018-12-11 03:49:01 -05:00
|
|
|
return err;
|
2017-02-17 06:24:58 -05:00
|
|
|
}
|
|
|
|
|
2017-07-11 09:46:17 -04:00
|
|
|
esp_err_t esp_bt_controller_deinit(void)
|
2017-02-17 06:24:58 -05:00
|
|
|
{
|
2017-07-11 09:46:17 -04:00
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
|
2018-07-17 03:46:56 -04:00
|
|
|
btdm_controller_deinit();
|
2017-07-11 09:46:17 -04:00
|
|
|
|
2017-11-01 05:05:38 -04:00
|
|
|
periph_module_disable(PERIPH_BT_MODULE);
|
|
|
|
|
2018-12-11 03:49:01 -05:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-02-20 01:34:28 -05:00
|
|
|
if (!s_btdm_allow_light_sleep) {
|
|
|
|
esp_pm_lock_delete(s_light_sleep_pm_lock);
|
|
|
|
s_light_sleep_pm_lock = NULL;
|
|
|
|
}
|
2021-10-08 05:04:47 -04:00
|
|
|
|
|
|
|
if (s_pm_lock != NULL) {
|
|
|
|
esp_pm_lock_delete(s_pm_lock);
|
|
|
|
s_pm_lock = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s_btdm_slp_tmr != NULL) {
|
|
|
|
esp_timer_stop(s_btdm_slp_tmr);
|
|
|
|
esp_timer_delete(s_btdm_slp_tmr);
|
|
|
|
s_btdm_slp_tmr = NULL;
|
|
|
|
}
|
|
|
|
|
2020-09-03 08:51:19 -04:00
|
|
|
s_pm_lock_acquired = false;
|
2018-12-11 03:49:01 -05:00
|
|
|
#endif
|
2020-09-03 08:51:19 -04:00
|
|
|
semphr_delete_wrapper(s_wakeup_req_sem);
|
|
|
|
s_wakeup_req_sem = NULL;
|
2018-12-11 03:49:01 -05:00
|
|
|
|
2021-09-03 04:51:09 -04:00
|
|
|
#if CONFIG_SPIRAM_USE_MALLOC
|
|
|
|
vSemaphoreDelete(btdm_queue_table_mux);
|
|
|
|
btdm_queue_table_mux = NULL;
|
|
|
|
memset(btdm_queue_table, 0, sizeof(btdm_queue_item_t) * BTDM_MAX_QUEUE_NUM);
|
|
|
|
#endif
|
|
|
|
|
2018-06-15 09:40:51 -04:00
|
|
|
free(osi_funcs_p);
|
|
|
|
osi_funcs_p = NULL;
|
|
|
|
|
2017-10-10 03:35:17 -04:00
|
|
|
btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
|
2017-10-09 03:34:31 -04:00
|
|
|
|
2018-04-08 07:19:47 -04:00
|
|
|
btdm_lpcycle_us = 0;
|
|
|
|
btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_NONE);
|
2017-10-09 03:34:31 -04:00
|
|
|
|
2021-09-14 05:47:09 -04:00
|
|
|
esp_bt_power_domain_off();
|
|
|
|
|
2017-07-11 09:46:17 -04:00
|
|
|
return ESP_OK;
|
2017-02-17 06:24:58 -05:00
|
|
|
}
|
|
|
|
|
2021-11-23 06:47:00 -05:00
|
|
|
static void bt_controller_shutdown(void* arg)
|
|
|
|
{
|
|
|
|
esp_bt_controller_shutdown();
|
|
|
|
}
|
|
|
|
|
2020-12-21 07:08:10 -05:00
|
|
|
static void bt_shutdown(void)
|
|
|
|
{
|
2021-11-01 08:39:37 -04:00
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
|
|
|
return;
|
2020-12-21 07:08:10 -05:00
|
|
|
}
|
2021-11-23 06:47:00 -05:00
|
|
|
#if !CONFIG_FREERTOS_UNICORE
|
|
|
|
esp_ipc_call_blocking(CONFIG_BTDM_CTRL_PINNED_TO_CORE, bt_controller_shutdown, NULL);
|
|
|
|
#else
|
|
|
|
bt_controller_shutdown(NULL);
|
|
|
|
#endif
|
2021-11-01 08:39:37 -04:00
|
|
|
esp_phy_disable();
|
|
|
|
|
2020-12-21 07:08:10 -05:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2017-02-17 06:24:58 -05:00
|
|
|
esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2017-02-20 12:05:37 -05:00
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2017-09-19 08:10:35 -04:00
|
|
|
|
2018-06-15 09:40:51 -04:00
|
|
|
//As the history reason, mode should be equal to the mode which set in esp_bt_controller_init()
|
|
|
|
if (mode != btdm_controller_get_mode()) {
|
2017-02-17 06:24:58 -05:00
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
|
2017-10-09 03:34:31 -04:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-02-20 01:34:28 -05:00
|
|
|
if (!s_btdm_allow_light_sleep) {
|
|
|
|
esp_pm_lock_acquire(s_light_sleep_pm_lock);
|
|
|
|
}
|
2017-10-09 03:34:31 -04:00
|
|
|
esp_pm_lock_acquire(s_pm_lock);
|
|
|
|
#endif
|
|
|
|
|
2020-05-22 05:15:28 -04:00
|
|
|
esp_phy_enable();
|
|
|
|
|
2020-08-26 05:51:13 -04:00
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
coex_enable();
|
2020-05-22 05:15:28 -04:00
|
|
|
#endif
|
2017-11-09 21:54:50 -05:00
|
|
|
|
2018-04-08 07:19:47 -04:00
|
|
|
if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG) {
|
|
|
|
btdm_controller_enable_sleep(true);
|
|
|
|
}
|
2017-02-17 06:24:58 -05:00
|
|
|
|
2018-12-11 03:49:01 -05:00
|
|
|
// inititalize bluetooth baseband
|
|
|
|
btdm_check_and_init_bb();
|
2017-02-17 06:24:58 -05:00
|
|
|
|
|
|
|
ret = btdm_controller_enable(mode);
|
2020-05-22 05:15:28 -04:00
|
|
|
if (ret != 0) {
|
2020-08-26 05:51:13 -04:00
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
coex_disable();
|
2020-05-22 05:15:28 -04:00
|
|
|
#endif
|
|
|
|
esp_phy_disable();
|
2018-07-17 03:46:56 -04:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-02-20 01:34:28 -05:00
|
|
|
if (!s_btdm_allow_light_sleep) {
|
|
|
|
esp_pm_lock_release(s_light_sleep_pm_lock);
|
|
|
|
}
|
2018-07-17 03:46:56 -04:00
|
|
|
esp_pm_lock_release(s_pm_lock);
|
|
|
|
#endif
|
2017-02-17 06:24:58 -05:00
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
|
2017-02-20 12:05:37 -05:00
|
|
|
btdm_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED;
|
2020-12-21 07:08:10 -05:00
|
|
|
ret = esp_register_shutdown_handler(bt_shutdown);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
ESP_LOGW(BTDM_LOG_TAG, "Register shutdown handler failed, ret = 0x%x", ret);
|
|
|
|
}
|
2017-02-20 12:05:37 -05:00
|
|
|
|
2017-02-17 06:24:58 -05:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2017-09-19 08:10:35 -04:00
|
|
|
esp_err_t esp_bt_controller_disable(void)
|
2017-02-17 06:24:58 -05:00
|
|
|
{
|
2017-02-20 12:05:37 -05:00
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
|
2018-04-08 07:19:47 -04:00
|
|
|
// disable modem sleep and wake up from sleep mode
|
|
|
|
if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG) {
|
|
|
|
btdm_controller_enable_sleep(false);
|
2020-09-03 08:51:19 -04:00
|
|
|
async_wakeup_request(BTDM_ASYNC_WAKEUP_REQ_CTRL_DISA);
|
2018-04-08 07:19:47 -04:00
|
|
|
while (!btdm_power_state_active()) {
|
2020-07-21 01:07:34 -04:00
|
|
|
esp_rom_delay_us(1000);
|
2018-04-08 07:19:47 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-07-17 03:46:56 -04:00
|
|
|
btdm_controller_disable();
|
2017-02-17 06:24:58 -05:00
|
|
|
|
2020-08-26 05:51:13 -04:00
|
|
|
#if CONFIG_SW_COEXIST_ENABLE
|
|
|
|
coex_disable();
|
2020-05-22 05:15:28 -04:00
|
|
|
#endif
|
|
|
|
|
|
|
|
esp_phy_disable();
|
2018-07-17 03:46:56 -04:00
|
|
|
btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
|
2020-12-21 07:08:10 -05:00
|
|
|
esp_unregister_shutdown_handler(bt_shutdown);
|
2017-02-20 12:05:37 -05:00
|
|
|
|
2017-10-09 03:34:31 -04:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
2020-02-20 01:34:28 -05:00
|
|
|
if (!s_btdm_allow_light_sleep) {
|
|
|
|
esp_pm_lock_release(s_light_sleep_pm_lock);
|
|
|
|
}
|
2017-10-09 03:34:31 -04:00
|
|
|
esp_pm_lock_release(s_pm_lock);
|
|
|
|
#endif
|
|
|
|
|
2017-02-17 06:24:58 -05:00
|
|
|
return ESP_OK;
|
2016-10-18 09:49:00 -04:00
|
|
|
}
|
|
|
|
|
2017-02-20 12:05:37 -05:00
|
|
|
esp_bt_controller_status_t esp_bt_controller_get_status(void)
|
|
|
|
{
|
|
|
|
return btdm_controller_status;
|
|
|
|
}
|
|
|
|
|
2017-07-11 09:46:17 -04:00
|
|
|
/* extra functions */
|
|
|
|
esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level)
|
|
|
|
{
|
|
|
|
if (ble_txpwr_set(power_type, power_level) != 0) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type)
|
|
|
|
{
|
|
|
|
return (esp_power_level_t)ble_txpwr_get(power_type);
|
|
|
|
}
|
|
|
|
|
2018-04-19 05:22:49 -04:00
|
|
|
esp_err_t esp_bredr_tx_power_set(esp_power_level_t min_power_level, esp_power_level_t max_power_level)
|
|
|
|
{
|
|
|
|
esp_err_t err;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = bredr_txpwr_set(min_power_level, max_power_level);
|
|
|
|
|
|
|
|
if (ret == 0) {
|
|
|
|
err = ESP_OK;
|
|
|
|
} else if (ret == -1) {
|
|
|
|
err = ESP_ERR_INVALID_ARG;
|
|
|
|
} else {
|
|
|
|
err = ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t esp_bredr_tx_power_get(esp_power_level_t *min_power_level, esp_power_level_t *max_power_level)
|
|
|
|
{
|
|
|
|
if (bredr_txpwr_get((int *)min_power_level, (int *)max_power_level) != 0) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2018-04-08 07:19:47 -04:00
|
|
|
esp_err_t esp_bt_sleep_enable (void)
|
|
|
|
{
|
|
|
|
esp_err_t status;
|
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2020-05-22 05:15:28 -04:00
|
|
|
if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG ||
|
|
|
|
btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_EVED) {
|
2018-04-08 07:19:47 -04:00
|
|
|
btdm_controller_enable_sleep (true);
|
|
|
|
status = ESP_OK;
|
|
|
|
} else {
|
|
|
|
status = ESP_ERR_NOT_SUPPORTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t esp_bt_sleep_disable (void)
|
|
|
|
{
|
|
|
|
esp_err_t status;
|
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2020-05-22 05:15:28 -04:00
|
|
|
if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG ||
|
|
|
|
btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_EVED) {
|
2018-04-08 07:19:47 -04:00
|
|
|
btdm_controller_enable_sleep (false);
|
|
|
|
status = ESP_OK;
|
|
|
|
} else {
|
|
|
|
status = ESP_ERR_NOT_SUPPORTED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2018-05-20 23:33:30 -04:00
|
|
|
esp_err_t esp_bredr_sco_datapath_set(esp_sco_data_path_t data_path)
|
|
|
|
{
|
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
bredr_sco_datapath_set(data_path);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2018-08-20 03:04:37 -04:00
|
|
|
esp_err_t esp_ble_scan_dupilcate_list_flush(void)
|
|
|
|
{
|
|
|
|
if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
btdm_controller_scan_duplicate_list_clear();
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2021-09-01 09:55:50 -04:00
|
|
|
/**
|
|
|
|
* This function re-write controller's function,
|
|
|
|
* As coredump can not show paramerters in function which is in a .a file.
|
|
|
|
*
|
|
|
|
* After coredump fixing this issue, just delete this function.
|
|
|
|
*/
|
|
|
|
void IRAM_ATTR r_assert(const char *condition, int param0, int param1, const char *file, int line)
|
|
|
|
{
|
|
|
|
__asm__ __volatile__("ill\n");
|
|
|
|
}
|
|
|
|
|
2017-09-12 10:36:17 -04:00
|
|
|
#endif /* CONFIG_BT_ENABLED */
|