2021-08-03 02:35:29 -04:00
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/*
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2023-09-06 07:33:39 -04:00
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* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
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2021-08-03 02:35:29 -04:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/portmacro.h"
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2021-12-21 06:17:11 -05:00
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#include "esp_private/esp_ipc_isr.h"
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2023-09-06 07:33:39 -04:00
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#include "esp_private/esp_ipc_isr_port.h"
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2021-08-03 02:35:29 -04:00
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#include "esp_ipc_isr.h"
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#include "sdkconfig.h"
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static portMUX_TYPE s_ipc_isr_mux = portMUX_INITIALIZER_UNLOCKED;
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uint32_t volatile esp_ipc_isr_start_fl; // the flag shows that it is about to run esp_ipc_func()
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uint32_t volatile esp_ipc_isr_end_fl = 1; // the flag shows that esp_ipc_func() is done
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esp_ipc_isr_func_t volatile esp_ipc_func; // the function which will be run in the ipc_isr context
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void * volatile esp_ipc_func_arg; // the argument of esp_ipc_func()
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typedef enum {
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STALL_STATE_IDLE = 0,
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STALL_STATE_RUNNING = 1,
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} stall_state_t;
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static stall_state_t volatile s_stall_state = STALL_STATE_IDLE;
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static int32_t volatile s_count_of_nested_calls[portNUM_PROCESSORS] = { 0 };
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static BaseType_t s_stored_interrupt_level;
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static uint32_t volatile esp_ipc_isr_finish_cmd;
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/**
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* @brief Type of calling
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*/
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typedef enum {
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IPC_ISR_WAIT_FOR_START = 0, /*!< The caller is waiting for the start */
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IPC_ISR_WAIT_FOR_END = 1, /*!< The caller is waiting for the end */
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} esp_ipc_isr_wait_t;
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#define IPC_ISR_ENTER_CRITICAL() portENTER_CRITICAL_SAFE(&s_ipc_isr_mux)
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#define IPC_ISR_EXIT_CRITICAL() portEXIT_CRITICAL_SAFE(&s_ipc_isr_mux)
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static void esp_ipc_isr_call_and_wait(esp_ipc_isr_func_t func, void* arg, esp_ipc_isr_wait_t wait_for);
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/* Initializing IPC_ISR */
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2021-12-21 06:17:11 -05:00
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void esp_ipc_isr_init(void)
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{
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const uint32_t cpuid = xPortGetCoreID();
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esp_ipc_isr_port_init(cpuid);
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2021-08-03 02:35:29 -04:00
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if (cpuid != 0) {
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s_stall_state = STALL_STATE_RUNNING;
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}
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}
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/* End initializing IPC_ISR */
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/* Public API functions */
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2023-09-06 07:33:39 -04:00
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void IRAM_ATTR esp_ipc_isr_call(esp_ipc_isr_func_t func, void* arg)
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{
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IPC_ISR_ENTER_CRITICAL();
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esp_ipc_isr_call_and_wait(func, arg, IPC_ISR_WAIT_FOR_START);
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IPC_ISR_EXIT_CRITICAL();
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}
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2023-09-06 07:33:39 -04:00
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void IRAM_ATTR esp_ipc_isr_call_blocking(esp_ipc_isr_func_t func, void* arg)
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{
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IPC_ISR_ENTER_CRITICAL();
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esp_ipc_isr_call_and_wait(func, arg, IPC_ISR_WAIT_FOR_END);
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IPC_ISR_EXIT_CRITICAL();
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}
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// This asm function is from esp_ipc_isr_routines.S.
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// It is waiting for the finish_cmd command in a loop.
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void esp_ipc_isr_waiting_for_finish_cmd(void* finish_cmd);
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/*
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* esp_ipc_isr_stall_other_cpu is used for:
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* - stall other CPU,
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* - do protection when dual core access DPORT internal register and APB register via DPORT simultaneously.
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* This function will be initialize after FreeRTOS startup.
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* When cpu0 wants to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute.
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* When cpu1 already in high-priority interrupt, cpu0 can access DPORT register.
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* Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
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*/
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void IRAM_ATTR esp_ipc_isr_stall_other_cpu(void)
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{
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2022-06-17 03:37:07 -04:00
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#if CONFIG_FREERTOS_SMP
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/*
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Temporary workaround to prevent deadlocking on the SMP FreeRTOS kernel lock after stalling the other CPU.
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See IDF-5257
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*/
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taskENTER_CRITICAL();
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#endif
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if (s_stall_state == STALL_STATE_RUNNING) {
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2022-05-29 18:11:24 -04:00
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#if CONFIG_FREERTOS_SMP
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BaseType_t intLvl = portDISABLE_INTERRUPTS();
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#else
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2021-10-15 12:14:27 -04:00
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BaseType_t intLvl = portSET_INTERRUPT_MASK_FROM_ISR();
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#endif
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const uint32_t cpu_id = xPortGetCoreID();
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if (s_count_of_nested_calls[cpu_id]++ == 0) {
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IPC_ISR_ENTER_CRITICAL();
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s_stored_interrupt_level = intLvl;
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esp_ipc_isr_finish_cmd = 0;
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esp_ipc_isr_call_and_wait(&esp_ipc_isr_waiting_for_finish_cmd, (void*)&esp_ipc_isr_finish_cmd, IPC_ISR_WAIT_FOR_START);
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return;
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}
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/* Interrupts are already disabled by the parent, we're nested here. */
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2022-05-29 18:11:24 -04:00
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#if CONFIG_FREERTOS_SMP
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portRESTORE_INTERRUPTS(intLvl);
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#else
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portCLEAR_INTERRUPT_MASK_FROM_ISR(intLvl);
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#endif
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}
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}
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void IRAM_ATTR esp_ipc_isr_release_other_cpu(void)
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{
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if (s_stall_state == STALL_STATE_RUNNING) {
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const uint32_t cpu_id = xPortGetCoreID();
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if (--s_count_of_nested_calls[cpu_id] == 0) {
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esp_ipc_isr_finish_cmd = 1;
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2023-05-19 13:01:41 -04:00
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// Make sure end flag is cleared and esp_ipc_isr_waiting_for_finish_cmd is done.
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while (!esp_ipc_isr_end_fl) {};
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IPC_ISR_EXIT_CRITICAL();
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#if CONFIG_FREERTOS_SMP
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portRESTORE_INTERRUPTS(s_stored_interrupt_level);
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#else
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portCLEAR_INTERRUPT_MASK_FROM_ISR(s_stored_interrupt_level);
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#endif
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} else if (s_count_of_nested_calls[cpu_id] < 0) {
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assert(0);
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}
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}
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2022-06-17 03:37:07 -04:00
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#if CONFIG_FREERTOS_SMP
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/*
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Temporary workaround to prevent deadlocking on the SMP FreeRTOS kernel lock after stalling the other CPU.
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See IDF-5257
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*/
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taskEXIT_CRITICAL();
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#endif
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}
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void IRAM_ATTR esp_ipc_isr_stall_pause(void)
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{
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IPC_ISR_ENTER_CRITICAL();
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s_stall_state = STALL_STATE_IDLE;
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IPC_ISR_EXIT_CRITICAL();
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}
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void IRAM_ATTR esp_ipc_isr_stall_abort(void)
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{
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2021-10-26 09:12:26 -04:00
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//Note: We don't enter a critical section here as we are calling this from a panic.
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s_stall_state = STALL_STATE_IDLE;
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}
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void IRAM_ATTR esp_ipc_isr_stall_resume(void)
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{
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IPC_ISR_ENTER_CRITICAL();
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s_stall_state = STALL_STATE_RUNNING;
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IPC_ISR_EXIT_CRITICAL();
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}
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/* End public API functions */
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/* Private functions*/
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static void IRAM_ATTR esp_ipc_isr_call_and_wait(esp_ipc_isr_func_t func, void* arg, esp_ipc_isr_wait_t wait_for)
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{
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const uint32_t cpu_id = xPortGetCoreID();
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// waiting for the end of the previous call
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while (!esp_ipc_isr_end_fl) {};
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esp_ipc_func = func;
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esp_ipc_func_arg = arg;
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esp_ipc_isr_start_fl = 0;
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esp_ipc_isr_end_fl = 0;
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2023-09-06 07:33:39 -04:00
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// Trigger an interrupt on the opposite core.
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esp_ipc_isr_port_int_trigger(!cpu_id);
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2021-08-03 02:35:29 -04:00
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// IPC_ISR handler will be called and `...isr_start` and `...isr_end` will be updated there
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if (wait_for == IPC_ISR_WAIT_FOR_START) {
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while (!esp_ipc_isr_start_fl) {};
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} else {
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// IPC_ISR_WAIT_FOR_END
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while (!esp_ipc_isr_end_fl) {};
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}
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}
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/* End private functions*/
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