2021-01-26 00:03:14 -05:00
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2020-02-02 10:23:16 -05:00
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menu "ESP System Settings"
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choice ESP_SYSTEM_PANIC
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prompt "Panic handler behaviour"
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default ESP_SYSTEM_PANIC_PRINT_REBOOT
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help
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If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
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invoked. Configure the panic handler's action here.
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config ESP_SYSTEM_PANIC_PRINT_HALT
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bool "Print registers and halt"
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help
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Outputs the relevant registers over the serial port and halt the
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processor. Needs a manual reset to restart.
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config ESP_SYSTEM_PANIC_PRINT_REBOOT
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bool "Print registers and reboot"
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help
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Outputs the relevant registers over the serial port and immediately
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reset the processor.
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config ESP_SYSTEM_PANIC_SILENT_REBOOT
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bool "Silent reboot"
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help
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Just resets the processor without outputting anything
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config ESP_SYSTEM_PANIC_GDBSTUB
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2021-04-15 03:52:09 -04:00
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bool "GDBStub on panic"
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2020-02-02 10:23:16 -05:00
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select ESP_GDBSTUB_ENABLED
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help
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Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
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of the crash.
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2021-04-15 03:52:09 -04:00
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config ESP_SYSTEM_GDBSTUB_RUNTIME
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bool "GDBStub at runtime"
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select FREERTOS_UNICORE
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select ESP_GDBSTUB_ENABLED
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help
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Invoke gdbstub on the serial port, allowing for gdb to attach to it and to do a debug on runtime.
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This feature will switch system to single core mode.
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2020-02-02 10:23:16 -05:00
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endchoice
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2020-02-13 07:43:23 -05:00
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config ESP_SYSTEM_SINGLE_CORE_MODE
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bool
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default n
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help
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Only initialize and use the main core.
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2020-07-14 08:39:30 -04:00
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config ESP_SYSTEM_RTC_EXT_XTAL
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# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
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# e.g. It will be selected on when ESP32_RTC_CLK_SRC_EXT_CRYS is on
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bool
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default n
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2021-08-29 23:30:12 -04:00
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config ESP_SYSTEM_RTC_EXT_OSC
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# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
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# e.g. It will be selected on when ESPX_RTC_CLK_SRC_EXT_OSC is on
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bool
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default n
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2020-07-14 08:39:30 -04:00
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config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
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int "Bootstrap cycles for external 32kHz crystal"
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depends on ESP_SYSTEM_RTC_EXT_XTAL
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default 5 if IDF_TARGET_ESP32
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default 0
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range 0 32768
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help
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To reduce the startup time of an external RTC crystal,
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we bootstrap it with a 32kHz square wave for a fixed number of cycles.
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Setting 0 will disable bootstrapping (if disabled, the crystal may take
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longer to start up or fail to oscillate under some conditions).
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If this value is too high, a faulty crystal may initially start and then fail.
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If this value is too low, an otherwise good crystal may not start.
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To accurately determine if the crystal has started,
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set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
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2020-12-21 00:26:00 -05:00
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config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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bool
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default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE
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default y if IDF_TARGET_ESP32S2
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default y if IDF_TARGET_ESP32C3
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default y if IDF_TARGET_ESP32S3
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2021-06-10 03:22:43 -04:00
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default y if IDF_TARGET_ESP32H2
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2021-11-06 05:24:45 -04:00
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depends on !IDF_TARGET_ESP8684
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2020-12-21 00:26:00 -05:00
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config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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bool "Enable RTC fast memory for dynamic allocations"
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2021-08-12 22:28:58 -04:00
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default y
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2020-12-21 00:26:00 -05:00
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depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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help
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This config option allows to add RTC fast memory region to system heap with capability
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similar to that of DRAM region but without DMA. This memory will be consumed first per
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heap initialization order by early startup services and scheduler related code. Speed
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wise RTC fast memory operates on APB clock and hence does not have much performance impact.
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2021-01-13 23:09:40 -05:00
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config ESP_SYSTEM_USE_EH_FRAME
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bool "Generate and use eh_frame for backtracing"
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default n
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depends on IDF_TARGET_ARCH_RISCV
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help
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2021-02-07 02:03:51 -05:00
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Generate DWARF information for each function of the project. These information will parsed and used to
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perform backtracing when panics occur. Activating this option will activate asynchronous frame unwinding
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and generation of both .eh_frame and .eh_frame_hdr sections, resulting in a bigger binary size (20% to
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100% larger). The main purpose of this option is to be able to have a backtrace parsed and printed by
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the program itself, regardless of the serial monitor used.
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This option shall NOT be used for production.
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2021-01-13 23:09:40 -05:00
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2021-01-04 13:38:10 -05:00
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menu "Memory protection"
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2021-08-06 11:18:19 -04:00
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config ESP_SYSTEM_MEMPROT_DEPCHECK
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bool
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default y if IDF_TARGET_ESP32S2
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default y if IDF_TARGET_ESP32C3
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default y if IDF_TARGET_ESP32H2
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2021-01-04 13:38:10 -05:00
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config ESP_SYSTEM_MEMPROT_FEATURE
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bool "Enable memory protection"
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2021-08-06 11:18:19 -04:00
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depends on ESP_SYSTEM_MEMPROT_DEPCHECK
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2021-01-04 13:38:10 -05:00
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default "y"
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help
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If enabled, the permission control module watches all the memory access and fires the panic handler
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if a permission violation is detected. This feature automatically splits
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the SRAM memory into data and instruction segments and sets Read/Execute permissions
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for the instruction part (below given splitting address) and Read/Write permissions
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for the data part (above the splitting address). The memory protection is effective
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on all access through the IRAM0 and DRAM0 buses.
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config ESP_SYSTEM_MEMPROT_FEATURE_LOCK
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depends on ESP_SYSTEM_MEMPROT_FEATURE
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bool "Lock memory protection settings"
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default "y"
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help
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Once locked, memory protection settings cannot be changed anymore.
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The lock is reset only on the chip startup.
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2021-08-06 11:18:19 -04:00
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config ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE
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# Hidden option for linker script usage
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int
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depends on ESP_SYSTEM_MEMPROT_DEPCHECK
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default 16
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config ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE
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# Hidden option for linker script usage
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int
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depends on ESP_SYSTEM_MEMPROT_DEPCHECK
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default 4 if IDF_TARGET_ESP32S2
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default 256 if IDF_TARGET_ESP32S3
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default 512
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2021-01-04 13:38:10 -05:00
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endmenu # Memory protection
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2021-02-20 04:52:30 -05:00
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2021-01-26 00:03:14 -05:00
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config ESP_SYSTEM_EVENT_QUEUE_SIZE
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int "System event queue size"
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default 32
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help
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Config system event queue size in different application.
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config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
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int "Event loop task stack size"
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default 2304
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help
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Config system event task stack size in different application.
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config ESP_MAIN_TASK_STACK_SIZE
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int "Main task stack size"
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default 3584
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help
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Configure the "main task" stack size. This is the stack of the task
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which calls app_main(). If app_main() returns then this task is deleted
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and its stack memory is freed.
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2021-02-27 14:13:01 -05:00
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choice ESP_MAIN_TASK_AFFINITY
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prompt "Main task core affinity"
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default ESP_MAIN_TASK_AFFINITY_CPU0
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help
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Configure the "main task" core affinity. This is the used core of the task
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which calls app_main(). If app_main() returns then this task is deleted.
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config ESP_MAIN_TASK_AFFINITY_CPU0
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bool "CPU0"
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config ESP_MAIN_TASK_AFFINITY_CPU1
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bool "CPU1"
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depends on !FREERTOS_UNICORE
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config ESP_MAIN_TASK_AFFINITY_NO_AFFINITY
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bool "No affinity"
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endchoice
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config ESP_MAIN_TASK_AFFINITY
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hex
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default 0x0 if ESP_MAIN_TASK_AFFINITY_CPU0
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default 0x1 if ESP_MAIN_TASK_AFFINITY_CPU1
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default FREERTOS_NO_AFFINITY if ESP_MAIN_TASK_AFFINITY_NO_AFFINITY
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2021-01-26 00:03:14 -05:00
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config ESP_MINIMAL_SHARED_STACK_SIZE
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int "Minimal allowed size for shared stack"
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default 2048
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help
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Minimal value of size, in bytes, accepted to execute a expression
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with shared stack.
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choice ESP_CONSOLE_UART
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prompt "Channel for console output"
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default ESP_CONSOLE_UART_DEFAULT
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help
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Select where to send console output (through stdout and stderr).
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- Default is to use UART0 on pre-defined GPIOs.
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- If "Custom" is selected, UART0 or UART1 can be chosen,
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and any pins can be selected.
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- If "None" is selected, there will be no console output on any UART, except
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for initial output from ROM bootloader. This ROM output can be suppressed by
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GPIO strapping or EFUSE, refer to chip datasheet for details.
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2021-04-28 04:38:24 -04:00
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- On chips with USB OTG peripheral, "USB CDC" option redirects output to the
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2021-01-26 00:03:14 -05:00
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CDC port. This option uses the CDC driver in the chip ROM.
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This option is incompatible with TinyUSB stack.
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2021-04-28 04:38:24 -04:00
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- On chips with an USB serial/JTAG debug controller, selecting the option
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for that redirects output to the CDC/ACM (serial port emulation) component
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of that device.
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2021-01-26 00:03:14 -05:00
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config ESP_CONSOLE_UART_DEFAULT
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bool "Default: UART0"
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config ESP_CONSOLE_USB_CDC
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bool "USB CDC"
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2021-07-08 23:15:26 -04:00
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# && !TINY_USB is because the ROM CDC driver is currently incompatible with TinyUSB.
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depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !TINY_USB
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2021-04-28 04:38:24 -04:00
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config ESP_CONSOLE_USB_SERIAL_JTAG
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bool "USB Serial/JTAG Controller"
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2021-06-04 02:48:20 -04:00
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select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32S3 #ESPTOOL-251
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select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32C3 #ESPTOOL-252
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depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
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2021-01-26 00:03:14 -05:00
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config ESP_CONSOLE_UART_CUSTOM
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bool "Custom UART"
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config ESP_CONSOLE_NONE
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bool "None"
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endchoice
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2021-10-21 00:46:24 -04:00
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choice ESP_CONSOLE_SECONDARY
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depends on IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3
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prompt "Channel for console secondary output"
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default ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
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help
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This secondary option supports output through other specific port like USB_SERIAL_JTAG
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when UART0 port as a primary is selected but not connected. This secondary output currently only supports
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non-blocking mode without using REPL. If you want to output in blocking mode with REPL or
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input through this secondary port, please change the primary config to this port
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in `Channel for console output` menu.
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config ESP_CONSOLE_SECONDARY_NONE
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bool "No secondary console"
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config ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
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bool "USB_SERIAL_JTAG PORT"
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depends on !ESP_CONSOLE_USB_SERIAL_JTAG
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help
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This option supports output through USB_SERIAL_JTAG port when the UART0 port is not connected.
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The output currently only supports non-blocking mode without using the console.
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If you want to output in blocking mode with REPL or input through USB_SERIAL_JTAG port,
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please change the primary config to ESP_CONSOLE_USB_SERIAL_JTAG above.
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endchoice
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|
2021-01-26 00:03:14 -05:00
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config ESP_CONSOLE_UART
|
2021-10-21 00:46:24 -04:00
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# Internal option, indicates that console UART is used (and not USB, for example)
|
2021-01-26 00:03:14 -05:00
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bool
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default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM
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config ESP_CONSOLE_MULTIPLE_UART
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bool
|
2021-11-06 05:24:45 -04:00
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default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP8684
|
2021-01-26 00:03:14 -05:00
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choice ESP_CONSOLE_UART_NUM
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prompt "UART peripheral to use for console output (0-1)"
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depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART
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default ESP_CONSOLE_UART_CUSTOM_NUM_0
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help
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This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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Due to an ESP32 ROM bug, UART2 is not supported for console output
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via esp_rom_printf.
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config ESP_CONSOLE_UART_CUSTOM_NUM_0
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bool "UART0"
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config ESP_CONSOLE_UART_CUSTOM_NUM_1
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bool "UART1"
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endchoice
|
|
|
|
|
|
|
|
|
|
config ESP_CONSOLE_UART_NUM
|
|
|
|
|
int
|
|
|
|
|
default 0 if ESP_CONSOLE_UART_DEFAULT
|
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|
|
default 0 if !ESP_CONSOLE_MULTIPLE_UART
|
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|
|
|
default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
|
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|
|
default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
|
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|
|
default -1 if !ESP_CONSOLE_UART
|
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|
|
config ESP_CONSOLE_UART_TX_GPIO
|
|
|
|
|
int "UART TX on GPIO#"
|
|
|
|
|
depends on ESP_CONSOLE_UART_CUSTOM
|
|
|
|
|
range 0 46
|
|
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|
|
default 1 if IDF_TARGET_ESP32
|
|
|
|
|
default 21 if IDF_TARGET_ESP32C3
|
|
|
|
|
default 43
|
|
|
|
|
help
|
|
|
|
|
This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including
|
|
|
|
|
boot log output and default standard output and standard error of the app).
|
|
|
|
|
|
|
|
|
|
If the configuration is different in the Bootloader binary compared to the app binary, UART
|
|
|
|
|
is reconfigured after the bootloader exits and the app starts.
|
|
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|
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|
|
config ESP_CONSOLE_UART_RX_GPIO
|
|
|
|
|
int "UART RX on GPIO#"
|
|
|
|
|
depends on ESP_CONSOLE_UART_CUSTOM
|
|
|
|
|
range 0 46
|
|
|
|
|
default 3 if IDF_TARGET_ESP32
|
|
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|
|
default 20 if IDF_TARGET_ESP32C3
|
|
|
|
|
default 44
|
|
|
|
|
help
|
|
|
|
|
This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including
|
|
|
|
|
default default standard input of the app).
|
|
|
|
|
|
|
|
|
|
Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.
|
|
|
|
|
|
|
|
|
|
If the configuration is different in the Bootloader binary compared to the app binary, UART
|
|
|
|
|
is reconfigured after the bootloader exits and the app starts.
|
|
|
|
|
|
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|
|
config ESP_CONSOLE_UART_BAUDRATE
|
|
|
|
|
int
|
|
|
|
|
prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
|
|
|
|
|
depends on ESP_CONSOLE_UART
|
|
|
|
|
default 115200
|
|
|
|
|
range 1200 4000000 if !PM_ENABLE
|
|
|
|
|
range 1200 1000000 if PM_ENABLE
|
|
|
|
|
help
|
|
|
|
|
This baud rate is used by both the ESP-IDF Bootloader and the app (including
|
|
|
|
|
boot log output and default standard input/output/error of the app).
|
|
|
|
|
|
|
|
|
|
The app's maximum baud rate depends on the UART clock source. If Power Management is disabled,
|
|
|
|
|
the UART clock source is the APB clock and all baud rates in the available range will be sufficiently
|
|
|
|
|
accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided
|
|
|
|
|
from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be
|
|
|
|
|
accurate.
|
|
|
|
|
|
|
|
|
|
If the configuration is different in the Bootloader binary compared to the app binary, UART
|
|
|
|
|
is reconfigured after the bootloader exits and the app starts.
|
|
|
|
|
|
|
|
|
|
config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE
|
|
|
|
|
int "Size of USB CDC RX buffer"
|
|
|
|
|
depends on ESP_CONSOLE_USB_CDC
|
|
|
|
|
default 64
|
|
|
|
|
range 4 16384
|
|
|
|
|
help
|
|
|
|
|
Set the size of USB CDC RX buffer. Increase the buffer size if your application
|
|
|
|
|
is often receiving data over USB CDC.
|
|
|
|
|
|
|
|
|
|
config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
|
|
|
|
|
bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC"
|
|
|
|
|
depends on ESP_CONSOLE_USB_CDC
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
|
|
|
|
|
Disabling this option saves about 1kB or RAM.
|
|
|
|
|
|
2021-02-20 04:52:30 -05:00
|
|
|
config ESP_INT_WDT
|
|
|
|
|
bool "Interrupt watchdog"
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
|
|
|
|
|
either because a task turned off interrupts and did not turn them on for a long time, or because an
|
|
|
|
|
interrupt handler did not return. It will try to invoke the panic handler first and failing that
|
|
|
|
|
reset the SoC.
|
|
|
|
|
|
|
|
|
|
config ESP_INT_WDT_TIMEOUT_MS
|
|
|
|
|
int "Interrupt watchdog timeout (ms)"
|
|
|
|
|
depends on ESP_INT_WDT
|
|
|
|
|
default 300 if !ESP32_SPIRAM_SUPPORT
|
|
|
|
|
default 800 if ESP32_SPIRAM_SUPPORT
|
|
|
|
|
range 10 10000
|
|
|
|
|
help
|
|
|
|
|
The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
|
|
|
|
|
|
|
|
|
|
config ESP_INT_WDT_CHECK_CPU1
|
|
|
|
|
bool "Also watch CPU1 tick interrupt"
|
|
|
|
|
depends on ESP_INT_WDT && !FREERTOS_UNICORE
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Also detect if interrupts on CPU 1 are disabled for too long.
|
|
|
|
|
|
|
|
|
|
config ESP_TASK_WDT
|
|
|
|
|
bool "Initialize Task Watchdog Timer on startup"
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
The Task Watchdog Timer can be used to make sure individual tasks are still
|
|
|
|
|
running. Enabling this option will cause the Task Watchdog Timer to be
|
|
|
|
|
initialized automatically at startup. The Task Watchdog timer can be
|
|
|
|
|
initialized after startup as well (see Task Watchdog Timer API Reference)
|
|
|
|
|
|
|
|
|
|
config ESP_TASK_WDT_PANIC
|
|
|
|
|
bool "Invoke panic handler on Task Watchdog timeout"
|
|
|
|
|
depends on ESP_TASK_WDT
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
If this option is enabled, the Task Watchdog Timer will be configured to
|
|
|
|
|
trigger the panic handler when it times out. This can also be configured
|
|
|
|
|
at run time (see Task Watchdog Timer API Reference)
|
|
|
|
|
|
|
|
|
|
config ESP_TASK_WDT_TIMEOUT_S
|
|
|
|
|
int "Task Watchdog timeout period (seconds)"
|
|
|
|
|
depends on ESP_TASK_WDT
|
|
|
|
|
range 1 60
|
|
|
|
|
default 5
|
|
|
|
|
help
|
|
|
|
|
Timeout period configuration for the Task Watchdog Timer in seconds.
|
|
|
|
|
This is also configurable at run time (see Task Watchdog Timer API Reference)
|
|
|
|
|
|
|
|
|
|
config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
|
|
|
|
|
bool "Watch CPU0 Idle Task"
|
|
|
|
|
depends on ESP_TASK_WDT
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
If this option is enabled, the Task Watchdog Timer will watch the CPU0
|
|
|
|
|
Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
|
|
|
|
|
of CPU starvation as the Idle Task not being called is usually a symptom of
|
|
|
|
|
CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
|
|
|
|
|
tasks depend on the Idle Task getting some runtime every now and then.
|
|
|
|
|
|
|
|
|
|
config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
|
|
|
|
|
bool "Watch CPU1 Idle Task"
|
|
|
|
|
depends on ESP_TASK_WDT && !FREERTOS_UNICORE
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
If this option is enabled, the Task Wtachdog Timer will wach the CPU1
|
|
|
|
|
Idle Task.
|
2021-01-26 00:03:14 -05:00
|
|
|
|
2021-08-29 23:30:12 -04:00
|
|
|
config ESP_XT_WDT
|
|
|
|
|
bool "Initialize XTAL32K watchdog timer on startup"
|
|
|
|
|
depends on !IDF_TARGET_ESP32 && (ESP_SYSTEM_RTC_EXT_OSC || ESP_SYSTEM_RTC_EXT_XTAL)
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This watchdog timer can detect oscillation failure of the XTAL32K_CLK. When such a failure
|
|
|
|
|
is detected the hardware can be set up to automatically switch to BACKUP32K_CLK and generate
|
|
|
|
|
an interrupt.
|
|
|
|
|
|
|
|
|
|
config ESP_XT_WDT_TIMEOUT
|
|
|
|
|
int "XTAL32K watchdog timeout period"
|
|
|
|
|
depends on ESP_XT_WDT
|
|
|
|
|
range 1 255
|
|
|
|
|
default 200
|
|
|
|
|
help
|
|
|
|
|
Timeout period configuration for the XTAL32K watchdog timer based on RTC_CLK.
|
|
|
|
|
|
|
|
|
|
config ESP_XT_WDT_BACKUP_CLK_ENABLE
|
|
|
|
|
bool "Automatically switch to BACKUP32K_CLK when timer expires"
|
|
|
|
|
depends on ESP_XT_WDT
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Enable this to automatically switch to BACKUP32K_CLK as the source of RTC_SLOW_CLK when
|
|
|
|
|
the watchdog timer expires.
|
|
|
|
|
|
2021-01-26 00:03:14 -05:00
|
|
|
config ESP_PANIC_HANDLER_IRAM
|
|
|
|
|
bool "Place panic handler code in IRAM"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
If this option is disabled (default), the panic handler code is placed in flash not IRAM.
|
|
|
|
|
This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
|
|
|
|
|
automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
|
|
|
|
|
risk, if the flash cache status is also corrupted during the crash.
|
|
|
|
|
|
2021-03-24 00:11:07 -04:00
|
|
|
If this option is enabled, the panic handler code (including required UART functions) is placed
|
|
|
|
|
in IRAM. This may be necessary to debug some complex issues with crashes while flash cache is
|
|
|
|
|
disabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception
|
|
|
|
|
is triggered.
|
2021-01-26 00:03:14 -05:00
|
|
|
|
2021-01-25 21:48:12 -05:00
|
|
|
config ESP_DEBUG_STUBS_ENABLE
|
2021-09-15 17:06:10 -04:00
|
|
|
bool "OpenOCD debug stubs"
|
2021-01-25 21:48:12 -05:00
|
|
|
default COMPILER_OPTIMIZATION_LEVEL_DEBUG
|
2021-10-22 16:32:36 -04:00
|
|
|
depends on !ESP32_TRAX && !ESP32S2_TRAX && !ESP32S3_TRAX
|
2021-01-25 21:48:12 -05:00
|
|
|
help
|
|
|
|
|
Debug stubs are used by OpenOCD to execute pre-compiled onboard code
|
|
|
|
|
which does some useful debugging stuff, e.g. GCOV data dump.
|
|
|
|
|
|
2021-09-02 09:10:29 -04:00
|
|
|
choice ESP_SYSTEM_CHECK_INT_LEVEL
|
|
|
|
|
prompt "Interrupt level to use for Interrupt Watchdog and other system checks"
|
2020-12-24 08:30:36 -05:00
|
|
|
default ESP_SYSTEM_CHECK_INT_LEVEL_4
|
2021-09-02 09:10:29 -04:00
|
|
|
help
|
|
|
|
|
Interrupt level to use for Interrupt Watchdog and other system checks.
|
|
|
|
|
|
|
|
|
|
config ESP_SYSTEM_CHECK_INT_LEVEL_5
|
|
|
|
|
bool "Level 5 interrupt"
|
2020-12-24 08:30:36 -05:00
|
|
|
depends on IDF_TARGET_ESP32
|
2021-09-02 09:10:29 -04:00
|
|
|
help
|
|
|
|
|
Using level 5 interrupt for Interrupt Watchdog and other system checks.
|
|
|
|
|
|
|
|
|
|
config ESP_SYSTEM_CHECK_INT_LEVEL_4
|
|
|
|
|
bool "Level 4 interrupt"
|
2021-09-02 09:49:30 -04:00
|
|
|
depends on !BTDM_CTRL_HLI
|
2021-09-02 09:10:29 -04:00
|
|
|
help
|
|
|
|
|
Using level 4 interrupt for Interrupt Watchdog and other system checks.
|
|
|
|
|
endchoice
|
2021-01-04 13:38:10 -05:00
|
|
|
|
2020-02-02 10:23:16 -05:00
|
|
|
endmenu # ESP System Settings
|
2021-09-16 23:14:32 -04:00
|
|
|
|
|
|
|
|
menu "IPC (Inter-Processor Call)"
|
|
|
|
|
|
|
|
|
|
config ESP_IPC_TASK_STACK_SIZE
|
|
|
|
|
int "Inter-Processor Call (IPC) task stack size"
|
|
|
|
|
range 512 65536 if !APPTRACE_ENABLE
|
|
|
|
|
range 2048 65536 if APPTRACE_ENABLE
|
|
|
|
|
default 2048 if APPTRACE_ENABLE
|
|
|
|
|
default 1024
|
|
|
|
|
help
|
2021-10-26 09:12:26 -04:00
|
|
|
Configure the IPC tasks stack size. An IPC task runs on each core (in dual core mode), and allows for
|
|
|
|
|
cross-core function calls. See IPC documentation for more details. The default IPC stack size should be
|
|
|
|
|
enough for most common simple use cases. However, users can increase/decrease the stack size to their
|
|
|
|
|
needs.
|
2021-09-16 23:14:32 -04:00
|
|
|
|
|
|
|
|
config ESP_IPC_USES_CALLERS_PRIORITY
|
|
|
|
|
bool "IPC runs at caller's priority"
|
|
|
|
|
default y
|
|
|
|
|
depends on !FREERTOS_UNICORE
|
|
|
|
|
help
|
2021-10-26 09:12:26 -04:00
|
|
|
If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0,
|
|
|
|
|
hence IPC task will run at (configMAX_PRIORITIES - 1) priority.
|
2021-09-16 23:14:32 -04:00
|
|
|
|
|
|
|
|
config ESP_IPC_ISR_ENABLE
|
|
|
|
|
bool
|
|
|
|
|
default y if !FREERTOS_UNICORE
|
|
|
|
|
help
|
2021-10-26 09:12:26 -04:00
|
|
|
The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the
|
|
|
|
|
context of a High Priority Interrupt. The IPC ISR feature is itended for low latency execution of simple
|
|
|
|
|
callbacks written in assembly on another CPU. Due to being run in a High Priority Interrupt, the assembly
|
|
|
|
|
callbacks must be written with particular restrictions (see "IPC" and "High-Level Interrupt" docs for more
|
|
|
|
|
details).
|
2021-09-16 23:14:32 -04:00
|
|
|
|
|
|
|
|
endmenu # "IPC (Inter-Processor Call)
|
