2022-12-23 06:47:00 -05:00
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/*
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2023-01-11 00:49:47 -05:00
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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2022-12-23 06:47:00 -05:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <esp_types.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "soc/soc.h"
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2023-03-22 09:50:04 -04:00
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#include "soc/soc_caps.h"
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2022-12-23 06:47:00 -05:00
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#include "freertos/FreeRTOS.h"
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#include "hal/clk_gate_ll.h"
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#include "esp_private/esp_modem_clock.h"
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2023-01-11 00:49:47 -05:00
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#include "esp_private/esp_pmu.h"
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2022-12-23 06:47:00 -05:00
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#include "esp_sleep.h"
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2023-06-26 00:11:04 -04:00
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#include "hal/efuse_hal.h"
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2022-12-23 06:47:00 -05:00
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// Please define the frequently called modules in the low bit,
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// which will improve the execution efficiency
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typedef enum {
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2023-09-24 23:29:15 -04:00
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MODEM_CLOCK_MODEM_ADC_COMMON_FE,
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MODEM_CLOCK_MODEM_PRIVATE_FE,
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2023-03-22 09:52:09 -04:00
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MODEM_CLOCK_COEXIST,
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MODEM_CLOCK_I2C_MASTER,
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#if SOC_WIFI_SUPPORTED
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MODEM_CLOCK_WIFI_MAC,
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MODEM_CLOCK_WIFI_BB,
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#endif
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MODEM_CLOCK_ETM,
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#if SOC_BT_SUPPORTED
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MODEM_CLOCK_BLE_MAC,
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MODEM_CLOCK_BLE_BB,
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#endif
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#if SOC_IEEE802154_SUPPORTED
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MODEM_CLOCK_802154_MAC,
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#endif
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MODEM_CLOCK_DATADUMP,
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MODEM_CLOCK_DEVICE_MAX
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2022-12-23 06:47:00 -05:00
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} modem_clock_device_t;
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typedef struct modem_clock_context {
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modem_clock_hal_context_t *hal;
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portMUX_TYPE lock;
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struct {
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int16_t refs;
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uint16_t reserved; /* reserved for 4 bytes aligned */
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void (*configure)(struct modem_clock_context *, bool);
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} dev[MODEM_CLOCK_DEVICE_MAX];
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/* the low-power clock source for each module */
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modem_clock_lpclk_src_t lpclk_src[PERIPH_MODEM_MODULE_NUM];
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} modem_clock_context_t;
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2023-03-22 09:50:04 -04:00
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#if SOC_WIFI_SUPPORTED
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2022-12-23 06:47:00 -05:00
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static void IRAM_ATTR modem_clock_wifi_mac_configure(modem_clock_context_t *ctx, bool enable)
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{
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2023-03-07 01:45:30 -05:00
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if (enable) {
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modem_syscon_ll_enable_wifi_apb_clock(ctx->hal->syscon_dev, enable);
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modem_syscon_ll_enable_wifi_mac_clock(ctx->hal->syscon_dev, enable);
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}
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2022-12-23 06:47:00 -05:00
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}
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static void IRAM_ATTR modem_clock_wifi_bb_configure(modem_clock_context_t *ctx, bool enable)
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{
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2023-03-07 01:45:30 -05:00
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if (enable) {
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modem_syscon_ll_clk_wifibb_configure(ctx->hal->syscon_dev, enable);
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}
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2022-12-23 06:47:00 -05:00
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}
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2023-03-22 09:50:04 -04:00
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#endif // SOC_WIFI_SUPPORTED
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2022-12-23 06:47:00 -05:00
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2023-03-22 09:50:04 -04:00
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#if SOC_BT_SUPPORTED
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2022-12-23 06:47:00 -05:00
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static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx, bool enable)
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{
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2023-03-13 07:57:39 -04:00
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modem_syscon_ll_enable_modem_sec_clock(ctx->hal->syscon_dev, enable);
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2022-12-23 06:47:00 -05:00
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modem_syscon_ll_enable_ble_timer_clock(ctx->hal->syscon_dev, enable);
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}
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static void IRAM_ATTR modem_clock_ble_bb_configure(modem_clock_context_t *ctx, bool enable)
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{
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modem_syscon_ll_enable_bt_apb_clock(ctx->hal->syscon_dev, enable);
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modem_syscon_ll_enable_bt_clock(ctx->hal->syscon_dev, enable);
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}
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2023-03-22 09:50:04 -04:00
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#endif // SOC_BT_SUPPORTED
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#if SOC_IEEE802154_SUPPORTED
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2022-12-23 06:47:00 -05:00
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static void IRAM_ATTR modem_clock_ieee802154_mac_configure(modem_clock_context_t *ctx, bool enable)
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{
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modem_syscon_ll_enable_ieee802154_apb_clock(ctx->hal->syscon_dev, enable);
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modem_syscon_ll_enable_ieee802154_mac_clock(ctx->hal->syscon_dev, enable);
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}
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2023-03-22 09:50:04 -04:00
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#endif // SOC_IEEE802154_SUPPORTED
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2022-12-23 06:47:00 -05:00
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static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, bool enable)
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{
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modem_lpcon_ll_enable_coex_clock(ctx->hal->lpcon_dev, enable);
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}
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2023-09-24 23:29:15 -04:00
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static void IRAM_ATTR modem_clock_modem_adc_common_fe_configure(modem_clock_context_t *ctx, bool enable)
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2022-12-23 06:47:00 -05:00
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{
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2023-09-24 23:29:15 -04:00
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modem_clock_hal_enable_modem_adc_common_fe_clock(ctx->hal, enable);
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2023-09-19 23:05:02 -04:00
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}
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2023-09-24 23:29:15 -04:00
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static void IRAM_ATTR modem_clock_modem_private_fe_configure(modem_clock_context_t *ctx, bool enable)
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2023-09-19 23:05:02 -04:00
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{
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2023-09-24 23:29:15 -04:00
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modem_clock_hal_enable_modem_private_fe_clock(ctx->hal, enable);
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2022-12-23 06:47:00 -05:00
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}
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static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable)
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{
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modem_lpcon_ll_enable_i2c_master_clock(ctx->hal->lpcon_dev, enable);
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}
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static void IRAM_ATTR modem_clock_etm_configure(modem_clock_context_t *ctx, bool enable)
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{
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modem_syscon_ll_enable_etm_clock(ctx->hal->syscon_dev, enable);
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}
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static void IRAM_ATTR modem_clock_data_dump_configure(modem_clock_context_t *ctx, bool enable)
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{
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modem_syscon_ll_enable_data_dump_clock(ctx->hal->syscon_dev, enable);
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modem_syscon_ll_enable_data_dump_mux_clock(ctx->hal->syscon_dev, enable);
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}
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modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(void)
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{
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/* It should be explicitly defined in the internal RAM */
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static DRAM_ATTR modem_clock_hal_context_t modem_clock_hal = { .syscon_dev = &MODEM_SYSCON, .lpcon_dev = &MODEM_LPCON };
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static DRAM_ATTR modem_clock_context_t modem_clock_context = {
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.hal = &modem_clock_hal, .lock = portMUX_INITIALIZER_UNLOCKED,
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.dev = {
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2023-09-24 23:29:15 -04:00
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[MODEM_CLOCK_MODEM_ADC_COMMON_FE] = { .refs = 0, .configure = modem_clock_modem_adc_common_fe_configure },
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[MODEM_CLOCK_MODEM_PRIVATE_FE] = { .refs = 0, .configure = modem_clock_modem_private_fe_configure },
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[MODEM_CLOCK_COEXIST] = { .refs = 0, .configure = modem_clock_coex_configure },
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[MODEM_CLOCK_I2C_MASTER] = { .refs = 0, .configure = modem_clock_i2c_master_configure },
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2023-03-22 09:50:04 -04:00
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#if SOC_WIFI_SUPPORTED
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2023-09-24 23:29:15 -04:00
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[MODEM_CLOCK_WIFI_MAC] = { .refs = 0, .configure = modem_clock_wifi_mac_configure },
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[MODEM_CLOCK_WIFI_BB] = { .refs = 0, .configure = modem_clock_wifi_bb_configure },
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2023-03-22 09:52:09 -04:00
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#endif
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2023-09-24 23:29:15 -04:00
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[MODEM_CLOCK_ETM] = { .refs = 0, .configure = modem_clock_etm_configure },
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2023-03-22 09:50:04 -04:00
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#if SOC_BT_SUPPORTED
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2023-09-24 23:29:15 -04:00
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[MODEM_CLOCK_BLE_MAC] = { .refs = 0, .configure = modem_clock_ble_mac_configure },
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[MODEM_CLOCK_BLE_BB] = { .refs = 0, .configure = modem_clock_ble_bb_configure },
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2023-03-22 09:52:09 -04:00
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#endif
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2023-03-22 09:50:04 -04:00
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#if SOC_IEEE802154_SUPPORTED
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2023-09-24 23:29:15 -04:00
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[MODEM_CLOCK_802154_MAC] = { .refs = 0, .configure = modem_clock_ieee802154_mac_configure },
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2023-03-22 09:52:09 -04:00
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#endif
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2023-09-24 23:29:15 -04:00
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[MODEM_CLOCK_DATADUMP] = { .refs = 0, .configure = modem_clock_data_dump_configure }
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2022-12-23 06:47:00 -05:00
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},
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.lpclk_src = { [0 ... PERIPH_MODEM_MODULE_NUM - 1] = MODEM_CLOCK_LPCLK_SRC_INVALID }
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};
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return &modem_clock_context;
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}
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2023-03-22 09:50:04 -04:00
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#if SOC_PM_SUPPORT_PMU_MODEM_STATE
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2023-06-14 02:56:44 -04:00
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esp_err_t modem_clock_domain_clk_gate_enable(modem_clock_domain_t domain, pmu_hp_icg_modem_mode_t mode)
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{
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if (domain >= MODEM_CLOCK_DOMAIN_MAX || domain < MODEM_CLOCK_DOMAIN_MODEM_APB) {
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return ESP_ERR_INVALID_ARG;
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}
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if (mode > PMU_HP_ICG_MODEM_CODE_ACTIVE || mode < PMU_HP_ICG_MODEM_CODE_SLEEP) {
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return ESP_ERR_INVALID_ARG;
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}
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portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
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uint32_t code = modem_clock_hal_get_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain);
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modem_clock_hal_set_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain, (code & ~BIT(mode)));
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portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
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return ESP_OK;
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}
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esp_err_t modem_clock_domain_clk_gate_disable(modem_clock_domain_t domain, pmu_hp_icg_modem_mode_t mode)
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{
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if (domain >= MODEM_CLOCK_DOMAIN_MAX || domain < MODEM_CLOCK_DOMAIN_MODEM_APB) {
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return ESP_ERR_INVALID_ARG;
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}
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if (mode > PMU_HP_ICG_MODEM_CODE_ACTIVE || mode < PMU_HP_ICG_MODEM_CODE_SLEEP) {
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return ESP_ERR_INVALID_ARG;
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}
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portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
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uint32_t code = modem_clock_hal_get_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain);
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modem_clock_hal_set_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain, (code | BIT(mode)));
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portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
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return ESP_OK;
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}
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2023-03-22 09:50:04 -04:00
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#endif // #if SOC_PM_SUPPORT_PMU_MODEM_STATE
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2022-12-23 06:47:00 -05:00
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static void IRAM_ATTR modem_clock_device_enable(modem_clock_context_t *ctx, uint32_t dev_map)
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{
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int16_t refs = 0;
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portENTER_CRITICAL_SAFE(&ctx->lock);
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for (int i = 0; dev_map; dev_map >>= 1, i++) {
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if (dev_map & BIT(0)) {
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refs = ctx->dev[i].refs++;
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if (refs == 0) {
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(*ctx->dev[i].configure)(ctx, true);
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}
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}
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}
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portEXIT_CRITICAL_SAFE(&ctx->lock);
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assert(refs >= 0);
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}
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static void IRAM_ATTR modem_clock_device_disable(modem_clock_context_t *ctx, uint32_t dev_map)
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{
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int16_t refs = 0;
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portENTER_CRITICAL_SAFE(&ctx->lock);
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for (int i = 0; dev_map; dev_map >>= 1, i++) {
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if (dev_map & BIT(0)) {
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refs = --ctx->dev[i].refs;
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if (refs == 0) {
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(*ctx->dev[i].configure)(ctx, false);
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}
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}
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}
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portEXIT_CRITICAL_SAFE(&ctx->lock);
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assert(refs >= 0);
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}
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2023-06-04 22:31:00 -04:00
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void IRAM_ATTR modem_clock_module_mac_reset(periph_module_t module)
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2023-05-26 03:11:47 -04:00
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{
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modem_clock_context_t *ctx = MODEM_CLOCK_instance();
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portENTER_CRITICAL_SAFE(&ctx->lock);
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2023-06-04 22:31:00 -04:00
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switch (module)
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{
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#if SOC_WIFI_SUPPORTED
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case PERIPH_WIFI_MODULE:
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modem_syscon_ll_reset_wifimac(ctx->hal->syscon_dev);
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break;
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#endif
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#if SOC_BT_SUPPORTED
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case PERIPH_BT_MODULE:
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modem_syscon_ll_reset_btmac(ctx->hal->syscon_dev);
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modem_syscon_ll_reset_btmac_apb(ctx->hal->syscon_dev);
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modem_syscon_ll_reset_ble_timer(ctx->hal->syscon_dev);
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modem_syscon_ll_reset_modem_sec(ctx->hal->syscon_dev);
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break;
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2023-05-26 03:11:47 -04:00
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#endif
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2023-06-04 22:31:00 -04:00
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#if SOC_IEEE802154_SUPPORTED
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case PERIPH_IEEE802154_MODULE:
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modem_syscon_ll_reset_zbmac(ctx->hal->syscon_dev);
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break;
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default:
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#endif
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assert(0);
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}
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portEXIT_CRITICAL_SAFE(&ctx->lock);
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2023-05-26 03:11:47 -04:00
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}
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2023-08-02 02:06:07 -04:00
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#define WIFI_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_WIFI_BB) | BIT(MODEM_CLOCK_COEXIST))
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#define BLE_CLOCK_DEPS (BIT(MODEM_CLOCK_BLE_MAC) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST))
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#define IEEE802154_CLOCK_DEPS (BIT(MODEM_CLOCK_802154_MAC) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST))
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#define COEXIST_CLOCK_DEPS (BIT(MODEM_CLOCK_COEXIST))
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2023-09-24 23:29:15 -04:00
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#define PHY_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER) | BIT(MODEM_CLOCK_MODEM_ADC_COMMON_FE) | BIT(MODEM_CLOCK_MODEM_PRIVATE_FE))
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2023-08-02 02:06:07 -04:00
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#define I2C_ANA_MST_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER))
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2023-08-09 03:10:55 -04:00
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#define MODEM_ETM_CLOCK_DEPS (BIT(MODEM_CLOCK_ETM))
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2023-09-24 23:29:15 -04:00
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#define MODEM_ADC_COMMON_FE_CLOCK_DEPS (BIT(MODEM_CLOCK_MODEM_ADC_COMMON_FE))
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2022-12-23 06:47:00 -05:00
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2023-06-25 05:12:43 -04:00
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static IRAM_ATTR uint32_t modem_clock_get_module_deps(periph_module_t module)
|
2023-03-22 09:50:04 -04:00
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{
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uint32_t deps = 0;
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2023-08-09 03:10:55 -04:00
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switch (module) {
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2023-09-24 23:29:15 -04:00
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case PERIPH_ANA_I2C_MASTER_MODULE: deps = I2C_ANA_MST_CLOCK_DEPS; break;
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case PERIPH_PHY_MODULE: deps = PHY_CLOCK_DEPS; break;
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case PERIPH_MODEM_ADC_COMMON_FE_MODULE: deps = MODEM_ADC_COMMON_FE_CLOCK_DEPS; break;
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2023-08-09 03:10:55 -04:00
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#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
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2023-09-24 23:29:15 -04:00
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case PERIPH_COEX_MODULE: deps = COEXIST_CLOCK_DEPS; break;
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2023-08-09 03:10:55 -04:00
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#endif
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2023-03-22 09:50:04 -04:00
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#if SOC_WIFI_SUPPORTED
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2023-09-24 23:29:15 -04:00
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case PERIPH_WIFI_MODULE: deps = WIFI_CLOCK_DEPS; break;
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2023-03-22 09:50:04 -04:00
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#endif
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#if SOC_BT_SUPPORTED
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2023-09-24 23:29:15 -04:00
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case PERIPH_BT_MODULE: deps = BLE_CLOCK_DEPS; break;
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2023-03-22 09:50:04 -04:00
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#endif
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#if SOC_IEEE802154_SUPPORTED
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2023-09-24 23:29:15 -04:00
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case PERIPH_IEEE802154_MODULE: deps = IEEE802154_CLOCK_DEPS; break;
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2023-08-09 03:10:55 -04:00
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#endif
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#if SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
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2023-09-24 23:29:15 -04:00
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case PERIPH_MODEM_ETM_MODULE: deps = MODEM_ETM_CLOCK_DEPS; break;
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2023-03-22 09:50:04 -04:00
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#endif
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2023-08-09 03:10:55 -04:00
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default:
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assert(0);
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}
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2023-03-22 09:50:04 -04:00
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return deps;
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}
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2023-11-15 02:51:40 -05:00
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#if SOC_PM_SUPPORT_PMU_MODEM_STATE
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/* the ICG code's bit 0, 1 and 2 indicates the ICG state
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* of pmu SLEEP, MODEM and ACTIVE mode respectively */
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#define ICG_NOGATING_SLEEP (BIT(PMU_HP_ICG_MODEM_CODE_SLEEP))
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#define ICG_NOGATING_MODEM (BIT(PMU_HP_ICG_MODEM_CODE_MODEM))
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#define ICG_NOGATING_ACTIVE (BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE))
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|
2023-11-27 02:01:00 -05:00
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static const DRAM_ATTR uint32_t initial_gating_mode[MODEM_CLOCK_DOMAIN_MAX] = {
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[MODEM_CLOCK_DOMAIN_MODEM_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
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[MODEM_CLOCK_DOMAIN_MODEM_PERIPH] = ICG_NOGATING_ACTIVE,
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[MODEM_CLOCK_DOMAIN_WIFI] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
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[MODEM_CLOCK_DOMAIN_BT] = ICG_NOGATING_ACTIVE,
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[MODEM_CLOCK_DOMAIN_MODEM_FE] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
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[MODEM_CLOCK_DOMAIN_IEEE802154] = ICG_NOGATING_ACTIVE,
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[MODEM_CLOCK_DOMAIN_LP_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
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[MODEM_CLOCK_DOMAIN_I2C_MASTER] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
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[MODEM_CLOCK_DOMAIN_COEX] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
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[MODEM_CLOCK_DOMAIN_WIFIPWR] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
|
2023-11-15 02:51:40 -05:00
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};
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|
2023-11-27 02:01:00 -05:00
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static IRAM_ATTR void modem_clock_module_icg_map_init_all(void)
|
2023-11-15 02:51:40 -05:00
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{
|
2023-11-27 02:01:00 -05:00
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portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
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for (int domain = 0; domain < MODEM_CLOCK_DOMAIN_MAX; domain++) {
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uint32_t code = modem_clock_hal_get_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain);
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modem_clock_hal_set_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain, initial_gating_mode[domain] | code);
|
2023-11-15 02:51:40 -05:00
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}
|
2023-11-27 02:01:00 -05:00
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portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
|
2023-11-15 02:51:40 -05:00
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}
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#endif // SOC_PM_SUPPORT_PMU_MODEM_STATE
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|
2022-12-23 06:47:00 -05:00
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void IRAM_ATTR modem_clock_module_enable(periph_module_t module)
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{
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assert(IS_MODEM_MODULE(module));
|
2023-11-15 02:51:40 -05:00
|
|
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#if SOC_PM_SUPPORT_PMU_MODEM_STATE
|
2023-11-27 02:01:00 -05:00
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modem_clock_module_icg_map_init_all();
|
2023-11-15 02:51:40 -05:00
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#endif
|
2023-03-22 09:50:04 -04:00
|
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uint32_t deps = modem_clock_get_module_deps(module);
|
2022-12-23 06:47:00 -05:00
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modem_clock_device_enable(MODEM_CLOCK_instance(), deps);
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}
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void IRAM_ATTR modem_clock_module_disable(periph_module_t module)
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{
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assert(IS_MODEM_MODULE(module));
|
2023-03-22 09:50:04 -04:00
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uint32_t deps = modem_clock_get_module_deps(module);
|
2022-12-23 06:47:00 -05:00
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modem_clock_device_disable(MODEM_CLOCK_instance(), deps);
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}
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void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpclk_src_t src, uint32_t divider)
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{
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assert(IS_MODEM_MODULE(module));
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portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
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switch (module)
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{
|
2023-03-22 09:50:04 -04:00
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#if SOC_WIFI_SUPPORTED
|
2022-12-23 06:47:00 -05:00
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case PERIPH_WIFI_MODULE:
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modem_clock_hal_deselect_all_wifi_lpclk_source(MODEM_CLOCK_instance()->hal);
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modem_clock_hal_select_wifi_lpclk_source(MODEM_CLOCK_instance()->hal, src);
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modem_lpcon_ll_set_wifi_lpclk_divisor_value(MODEM_CLOCK_instance()->hal->lpcon_dev, divider);
|
2023-06-16 05:36:18 -04:00
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modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, true);
|
2022-12-23 06:47:00 -05:00
|
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|
break;
|
2023-03-22 09:50:04 -04:00
|
|
|
#endif // SOC_WIFI_SUPPORTED
|
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|
|
|
|
|
|
#if SOC_BT_SUPPORTED
|
2022-12-23 06:47:00 -05:00
|
|
|
case PERIPH_BT_MODULE:
|
2023-03-22 09:50:04 -04:00
|
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|
modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(MODEM_CLOCK_instance()->hal);
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|
modem_clock_hal_select_ble_rtc_timer_lpclk_source(MODEM_CLOCK_instance()->hal, src);
|
|
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modem_clock_hal_set_ble_rtc_timer_divisor_value(MODEM_CLOCK_instance()->hal, divider);
|
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|
modem_clock_hal_enable_ble_rtc_timer_clock(MODEM_CLOCK_instance()->hal, true);
|
2023-06-26 00:11:04 -04:00
|
|
|
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
|
|
|
|
if (efuse_hal_chip_revision() != 0) {
|
|
|
|
if (src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
|
|
|
pmu_sleep_enable_hp_sleep_sysclk(true);
|
|
|
|
}
|
|
|
|
modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, true);
|
|
|
|
modem_clock_domain_clk_gate_disable(MODEM_CLOCK_DOMAIN_WIFIPWR, PMU_HP_ICG_MODEM_CODE_SLEEP);
|
2023-06-25 23:26:27 -04:00
|
|
|
}
|
2023-06-26 00:11:04 -04:00
|
|
|
#endif
|
2022-12-23 06:47:00 -05:00
|
|
|
break;
|
2023-03-22 09:50:04 -04:00
|
|
|
#endif // SOC_BT_SUPPORTED
|
|
|
|
|
2022-12-23 06:47:00 -05:00
|
|
|
case PERIPH_COEX_MODULE:
|
|
|
|
modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal);
|
|
|
|
modem_clock_hal_select_coex_lpclk_source(MODEM_CLOCK_instance()->hal, src);
|
|
|
|
modem_lpcon_ll_set_coex_lpclk_divisor_value(MODEM_CLOCK_instance()->hal->lpcon_dev, divider);
|
|
|
|
// modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, true); // TODO: IDF-5727
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
modem_clock_lpclk_src_t last_src = MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN];
|
|
|
|
MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = src;
|
|
|
|
portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
|
|
|
|
|
|
|
|
/* The power domain of the low-power clock source required by the modem
|
|
|
|
* module remains powered on during sleep */
|
|
|
|
esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \
|
|
|
|
(last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \
|
|
|
|
: (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \
|
|
|
|
: (last_src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \
|
|
|
|
: (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \
|
|
|
|
: ESP_PD_DOMAIN_MAX);
|
|
|
|
esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t) ( \
|
|
|
|
(src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \
|
|
|
|
: (src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \
|
|
|
|
: (src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \
|
|
|
|
: (src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \
|
|
|
|
: ESP_PD_DOMAIN_MAX);
|
|
|
|
esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF);
|
|
|
|
esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON);
|
|
|
|
}
|
|
|
|
|
|
|
|
void modem_clock_deselect_lp_clock_source(periph_module_t module)
|
|
|
|
{
|
|
|
|
assert(IS_MODEM_MODULE(module));
|
|
|
|
portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
|
2023-06-25 23:26:27 -04:00
|
|
|
modem_clock_lpclk_src_t last_src = MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN];
|
|
|
|
MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = MODEM_CLOCK_LPCLK_SRC_INVALID;
|
2022-12-23 06:47:00 -05:00
|
|
|
switch (module)
|
|
|
|
{
|
2023-03-22 09:50:04 -04:00
|
|
|
#if SOC_WIFI_SUPPORTED
|
2022-12-23 06:47:00 -05:00
|
|
|
case PERIPH_WIFI_MODULE:
|
|
|
|
modem_clock_hal_deselect_all_wifi_lpclk_source(MODEM_CLOCK_instance()->hal);
|
2023-06-16 05:36:18 -04:00
|
|
|
modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, false);
|
2022-12-23 06:47:00 -05:00
|
|
|
break;
|
2023-03-22 09:50:04 -04:00
|
|
|
#endif // SOC_WIFI_SUPPORTED
|
|
|
|
|
|
|
|
#if SOC_BT_SUPPORTED
|
2022-12-23 06:47:00 -05:00
|
|
|
case PERIPH_BT_MODULE:
|
2023-03-22 09:50:04 -04:00
|
|
|
modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(MODEM_CLOCK_instance()->hal);
|
|
|
|
modem_clock_hal_enable_ble_rtc_timer_clock(MODEM_CLOCK_instance()->hal, false);
|
2023-06-26 00:11:04 -04:00
|
|
|
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
|
|
|
|
if (efuse_hal_chip_revision() != 0) {
|
|
|
|
if (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
|
|
|
|
pmu_sleep_enable_hp_sleep_sysclk(false);
|
|
|
|
}
|
|
|
|
modem_clock_hal_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal, false);
|
|
|
|
modem_clock_domain_clk_gate_enable(MODEM_CLOCK_DOMAIN_WIFI, PMU_HP_ICG_MODEM_CODE_SLEEP);
|
2023-06-25 23:26:27 -04:00
|
|
|
}
|
2023-06-26 00:11:04 -04:00
|
|
|
#endif
|
2022-12-23 06:47:00 -05:00
|
|
|
break;
|
2023-03-22 09:50:04 -04:00
|
|
|
#endif // SOC_BT_SUPPORTED
|
2022-12-23 06:47:00 -05:00
|
|
|
case PERIPH_COEX_MODULE:
|
|
|
|
modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal);
|
|
|
|
// modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); // TODO: IDF-5727
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
|
|
|
|
|
|
|
|
esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \
|
|
|
|
(last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \
|
|
|
|
: (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \
|
|
|
|
: (last_src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K \
|
|
|
|
: (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \
|
|
|
|
: ESP_PD_DOMAIN_MAX);
|
|
|
|
esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF);
|
|
|
|
}
|