2021-11-06 05:24:45 -04:00
|
|
|
/*
|
|
|
|
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
|
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*/
|
2021-01-26 00:12:54 -05:00
|
|
|
#include "sdkconfig.h"
|
|
|
|
#include "soc/soc.h"
|
2020-08-27 05:12:00 -04:00
|
|
|
#ifndef CONFIG_IDF_TARGET_ESP32
|
|
|
|
#include "soc/system_reg.h"
|
|
|
|
#endif // not CONFIG_IDF_TARGET_ESP32
|
2021-01-26 00:12:54 -05:00
|
|
|
#include "soc/rtc.h"
|
2022-07-12 08:42:28 -04:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
|
|
#include "esp32/rom/rtc.h"
|
|
|
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
|
|
|
#include "esp32s2/rom/rtc.h"
|
|
|
|
#elif CONFIG_IDF_TARGET_ESP32S3
|
|
|
|
#include "esp32s3/rom/rtc.h"
|
|
|
|
#elif CONFIG_IDF_TARGET_ESP32C3
|
|
|
|
#include "esp32c3/rom/rtc.h"
|
|
|
|
#elif CONFIG_IDF_TARGET_ESP32C2
|
|
|
|
#include "esp32c2/rom/rtc.h"
|
|
|
|
#elif CONFIG_IDF_TARGET_ESP32C6
|
|
|
|
#include "esp32c6/rom/rtc.h"
|
2023-01-30 03:37:20 -05:00
|
|
|
#include "esp_private/esp_pmu.h"
|
2022-12-06 00:46:03 -05:00
|
|
|
#elif CONFIG_IDF_TARGET_ESP32H2
|
|
|
|
#include "esp32h2/rom/rtc.h"
|
2022-07-12 08:42:28 -04:00
|
|
|
#endif
|
2021-01-26 00:12:54 -05:00
|
|
|
#include "esp_log.h"
|
|
|
|
#include "esp_rom_sys.h"
|
|
|
|
#include "esp_rom_uart.h"
|
|
|
|
#include "esp_attr.h"
|
|
|
|
|
|
|
|
static const char *TAG = "fpga";
|
|
|
|
|
|
|
|
extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
|
|
|
|
|
|
|
|
static void s_warn(void)
|
|
|
|
{
|
|
|
|
ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work");
|
|
|
|
}
|
|
|
|
|
|
|
|
void bootloader_clock_configure(void)
|
|
|
|
{
|
|
|
|
s_warn();
|
|
|
|
esp_rom_uart_tx_wait_idle(0);
|
|
|
|
|
|
|
|
uint32_t xtal_freq_mhz = 40;
|
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32S2
|
|
|
|
uint32_t apb_freq_hz = 20000000;
|
|
|
|
#else
|
2022-07-12 08:42:28 -04:00
|
|
|
uint32_t apb_freq_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000;
|
2021-01-26 00:12:54 -05:00
|
|
|
#endif // CONFIG_IDF_TARGET_ESP32S2
|
|
|
|
ets_update_cpu_frequency(apb_freq_hz / 1000000);
|
2020-11-05 18:21:25 -05:00
|
|
|
#ifdef RTC_APB_FREQ_REG
|
|
|
|
REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
|
|
|
|
#endif
|
2022-07-12 08:42:28 -04:00
|
|
|
REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
|
2021-01-26 00:12:54 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Placed in IRAM since test_apps expects it to be */
|
|
|
|
void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
|
|
|
|
{
|
|
|
|
uint8_t *buffer_bytes = (uint8_t *)buffer;
|
|
|
|
for (int i = 0; i < length; i++) {
|
|
|
|
buffer_bytes[i] = 0x5A;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void esp_clk_init(void)
|
|
|
|
{
|
|
|
|
s_warn();
|
2023-01-30 03:37:20 -05:00
|
|
|
#if SOC_PMU_SUPPORTED
|
|
|
|
pmu_init();
|
|
|
|
#endif
|
2021-01-26 00:12:54 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
void esp_perip_clk_init(void)
|
|
|
|
{
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief No-op function, used to force linking this file
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
void esp_common_include_fpga_overrides(void)
|
|
|
|
{
|
|
|
|
}
|