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https://github.com/espressif/esp-idf.git
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esp_common: other movements
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@ -4,6 +4,3 @@
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COMPONENT_ADD_INCLUDEDIRS := include
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COMPONENT_SRCDIRS := src
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ifndef CONFIG_IDF_ENV_FPGA
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COMPONENT_OBJEXCLUDE += src/fpga_overrides.o
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endif
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@ -10,8 +10,6 @@ if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs "clk_ctrl_os.c" "mac_addr.c")
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endif()
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endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS include
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REQUIRES ${requires}
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@ -1,10 +1,5 @@
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menu "Hardware Settings"
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menu "MAC Config"
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config ESP_UNIVERSAL_MAC_ADDRESSES
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int
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default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
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default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
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config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
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bool
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@ -6,5 +6,4 @@ port/$(IDF_TARGET)/rtc_clk.o: CFLAGS += -fno-jump-tables -fno-tree-switch-conver
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ifdef IS_BOOTLOADER_BUILD
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COMPONENT_OBJEXCLUDE += clk_ctrl_os.o mac_addr.o
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endif
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@ -1,5 +1,5 @@
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if(IDF_TARGET STREQUAL "esp32")
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idf_component_register(SRC_DIRS "."
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PRIV_INCLUDE_DIRS "."
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PRIV_REQUIRES cmock test_utils)
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PRIV_REQUIRES cmock test_utils esp_ipc)
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endif()
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@ -6,30 +6,36 @@ endif()
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idf_build_get_property(target IDF_TARGET)
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set(srcs "intr_alloc.c"
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"esp_async_memcpy.c"
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"panic.c"
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"system_api.c"
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"startup.c"
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"system_time.c"
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"sleep_modes.c"
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"task_wdt.c"
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"int_wdt.c"
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"stack_check.c"
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"freertos_hooks.c"
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"esp_err.c")
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# Remove when sleep is brought up on master for C3 TODO ESP32-C3 IDF-2571
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set(srcs "esp_err.c"
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"freertos_hooks.c"
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"intr_alloc.c"
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"int_wdt.c"
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"esp_async_memcpy.c"
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"panic.c"
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"system_api.c"
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"startup.c"
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"system_time.c"
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"stack_check.c"
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"sleep_modes.c"
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"task_wdt.c")
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if(NOT (${target} STREQUAL "esp32c3") )
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list(APPEND srcs "dbg_stubs.c")
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endif()
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if(CONFIG_IDF_ENV_FPGA)
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list(APPEND srcs "fpga_overrides.c")
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endif()
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idf_component_register(SRCS "${srcs}"
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INCLUDE_DIRS include
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PRIV_REQUIRES spi_flash
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# [refactor-todo] requirements due to init code,
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# should be removable once using component init functions
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# link-time registration is used.
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esp_pm app_update nvs_flash pthread app_trace esp_gdbstub
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esp_pm app_update nvs_flash pthread app_trace esp_gdbstub esp_ipc
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espcoredump
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LDFRAGMENTS "linker.lf")
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add_subdirectory(port)
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@ -54,3 +60,8 @@ if(NOT CMAKE_BUILD_EARLY_EXPANSION)
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set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/sleep_modes.c" PROPERTIES
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COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
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endif()
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if(CONFIG_IDF_ENV_FPGA)
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# Forces the linker to include fpga stubs from this component
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target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_common_include_fpga_overrides")
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endif()
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@ -1,11 +1,15 @@
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ifdef IS_BOOTLOADER_BUILD
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COMPONENT_CONFIG_ONLY := 1
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else
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SOC_NAME := $(IDF_TARGET)
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COMPONENT_SRCDIRS := .
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COMPONENT_ADD_INCLUDEDIRS := include
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COMPONENT_PRIV_INCLUDEDIRS := private_include port/include
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COMPONENT_PRIV_INCLUDEDIRS := port/include port
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COMPONENT_ADD_LDFRAGMENTS += linker.lf
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include $(COMPONENT_PATH)/port/soc/$(SOC_NAME)/component.mk
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# disable stack protection in files which are involved in initialization of that feature
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startup.o stack_check.o: CFLAGS := $(filter-out -fstack-protector%, $(CFLAGS))
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endif
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73
components/esp_system/fpga_overrides.c
Normal file
73
components/esp_system/fpga_overrides.c
Normal file
@ -0,0 +1,73 @@
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// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "esp_log.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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#include "esp_attr.h"
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static const char *TAG = "fpga";
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extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
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static void s_warn(void)
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{
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ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work");
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}
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void bootloader_clock_configure(void)
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{
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s_warn();
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esp_rom_uart_tx_wait_idle(0);
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uint32_t xtal_freq_mhz = 40;
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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uint32_t apb_freq_hz = 20000000;
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#else
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uint32_t apb_freq_hz = 40000000;
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#endif // CONFIG_IDF_TARGET_ESP32S2
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ets_update_cpu_frequency(apb_freq_hz / 1000000);
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REG_WRITE(RTC_CNTL_STORE5_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
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REG_WRITE(RTC_CNTL_STORE4_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
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}
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/* Placed in IRAM since test_apps expects it to be */
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void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
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{
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uint8_t *buffer_bytes = (uint8_t *)buffer;
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for (int i = 0; i < length; i++) {
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buffer_bytes[i] = 0x5A;
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}
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}
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void esp_clk_init(void)
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{
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s_warn();
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}
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void esp_perip_clk_init(void)
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{
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}
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/**
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* @brief No-op function, used to force linking this file
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*
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*/
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void esp_common_include_fpga_overrides(void)
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{
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}
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