2017-04-21 00:32:50 -04:00
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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2016-12-08 09:22:10 -05:00
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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2016-09-12 03:23:15 -04:00
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#include <stddef.h>
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2020-11-26 03:56:13 -05:00
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#include <string.h>
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2016-09-12 03:23:15 -04:00
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#include <sys/lock.h>
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2017-04-21 00:32:50 -04:00
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#include <sys/param.h>
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2020-04-23 00:39:07 -04:00
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2016-12-13 00:23:04 -05:00
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#include "esp_attr.h"
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2017-04-21 00:32:50 -04:00
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#include "esp_sleep.h"
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2020-02-06 01:00:18 -05:00
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#include "esp_private/esp_timer_private.h"
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2020-09-03 06:17:24 -04:00
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#include "esp_private/system_internal.h"
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2016-12-13 00:23:04 -05:00
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#include "esp_log.h"
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2017-04-21 00:32:50 -04:00
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#include "esp_newlib.h"
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2020-05-04 06:17:06 -04:00
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#include "esp_timer.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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2020-11-26 03:56:13 -05:00
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#include "soc/soc_caps.h"
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2020-05-04 06:17:06 -04:00
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#include "driver/rtc_io.h"
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2020-11-26 03:56:13 -05:00
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#include "hal/rtc_io_hal.h"
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2020-05-04 06:17:06 -04:00
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#include "driver/uart.h"
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2016-12-13 00:23:04 -05:00
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#include "soc/cpu.h"
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2017-04-11 03:44:43 -04:00
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#include "soc/rtc.h"
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2020-09-09 22:37:58 -04:00
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#include "soc/soc_caps.h"
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2020-05-04 06:17:06 -04:00
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#include "hal/wdt_hal.h"
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#include "hal/rtc_hal.h"
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#include "hal/uart_hal.h"
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2020-11-26 03:56:13 -05:00
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#if SOC_TOUCH_SENSOR_NUM > 0
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#include "hal/touch_sensor_hal.h"
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2020-12-29 00:20:24 -05:00
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#include "driver/touch_sensor.h"
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#include "driver/touch_sensor_common.h"
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#endif
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#include "hal/clk_gate_ll.h"
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2020-05-04 06:17:06 -04:00
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2016-12-12 10:20:15 -05:00
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#include "sdkconfig.h"
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2020-04-23 00:39:07 -04:00
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#include "esp_rom_uart.h"
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#ifdef CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/cache.h"
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#include "esp32/clk.h"
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2020-05-04 06:17:06 -04:00
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#include "esp32/rom/rtc.h"
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2020-11-12 07:39:55 -05:00
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#include "driver/gpio.h"
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2020-04-23 00:39:07 -04:00
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/clk.h"
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#include "esp32s2/rom/cache.h"
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#include "esp32s2/rom/rtc.h"
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2021-02-09 06:30:43 -05:00
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#include "esp32s2/brownout.h"
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#include "soc/extmem_reg.h"
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2020-11-12 07:39:55 -05:00
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#include "driver/gpio.h"
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2020-07-29 01:13:51 -04:00
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/clk.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32s3/rom/rtc.h"
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#include "soc/extmem_reg.h"
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2020-11-26 03:56:13 -05:00
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/clk.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32c3/rom/rtc.h"
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#include "soc/extmem_reg.h"
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2020-12-24 08:02:32 -05:00
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#include "esp_heap_caps.h"
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2020-04-23 00:39:07 -04:00
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#endif
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2016-09-12 03:23:15 -04:00
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2017-04-21 00:32:50 -04:00
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// If light sleep time is less than that, don't power down flash
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#define FLASH_PD_MIN_SLEEP_TIME_US 2000
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// Time from VDD_SDIO power up to first flash read in ROM code
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#define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700
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2020-11-06 04:28:57 -05:00
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// Cycles for RTC Timer clock source (internal oscillator) calibrate
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#define RTC_CLK_SRC_CAL_CYCLES (10)
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2020-04-23 00:39:07 -04:00
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#ifdef CONFIG_IDF_TARGET_ESP32
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2020-12-03 22:09:21 -05:00
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#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (212)
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#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (60)
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2020-04-23 00:39:07 -04:00
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#elif CONFIG_IDF_TARGET_ESP32S2
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2020-12-03 22:09:21 -05:00
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#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (147)
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#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (28)
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#elif CONFIG_IDF_TARGET_ESP32S3
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2020-12-03 22:09:21 -05:00
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#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (0)
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#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (0)
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2020-11-26 03:56:13 -05:00
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#elif CONFIG_IDF_TARGET_ESP32C3
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2020-12-03 22:09:21 -05:00
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#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ
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#define DEFAULT_SLEEP_OUT_OVERHEAD_US (105)
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#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37)
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2020-04-23 00:39:07 -04:00
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#endif
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2020-12-03 22:09:21 -05:00
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#define LIGHT_SLEEP_TIME_OVERHEAD_US DEFAULT_HARDWARE_OUT_OVERHEAD_US
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#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) || \
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defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS) || \
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defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS) || \
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defined(CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS)
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#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
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2020-11-06 04:28:57 -05:00
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#else
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2020-12-03 22:09:21 -05:00
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#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
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#endif
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2020-04-23 00:39:07 -04:00
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#if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY)
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#define DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY
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#else
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#define DEEP_SLEEP_WAKEUP_DELAY 0
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#endif
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2018-04-04 03:05:50 -04:00
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2020-12-30 03:42:39 -05:00
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extern void periph_inform_out_light_sleep_overhead(uint32_t out_light_sleep_time);
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2018-04-04 03:05:50 -04:00
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// Minimal amount of time we can sleep for
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#define LIGHT_SLEEP_MIN_TIME_US 200
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#define RTC_MODULE_SLEEP_PREPARE_CYCLES (6)
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2018-04-04 03:05:50 -04:00
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2018-03-16 02:57:35 -04:00
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#define CHECK_SOURCE(source, value, mask) ((s_config.wakeup_triggers & mask) && \
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(source == value))
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2016-12-16 01:26:05 -05:00
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/**
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* Internal structure which holds all requested deep sleep parameters
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*/
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typedef struct {
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2017-04-21 00:32:50 -04:00
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esp_sleep_pd_option_t pd_options[ESP_PD_DOMAIN_MAX];
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2016-12-16 01:26:05 -05:00
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uint64_t sleep_duration;
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2020-11-03 21:47:40 -05:00
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uint32_t wakeup_triggers : 15;
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2016-12-16 01:26:05 -05:00
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uint32_t ext1_trigger_mode : 1;
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uint32_t ext1_rtc_gpio_mask : 18;
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uint32_t ext0_trigger_level : 1;
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uint32_t ext0_rtc_gpio_num : 5;
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2021-02-05 04:10:44 -05:00
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uint32_t gpio_wakeup_mask : 6;
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uint32_t gpio_trigger_mode :6;
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2018-04-04 03:05:50 -04:00
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uint32_t sleep_time_adjustment;
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2020-11-06 04:28:57 -05:00
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uint32_t ccount_ticks_record;
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uint32_t sleep_time_overhead_out;
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uint32_t rtc_clk_cal_period;
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2018-04-04 03:05:50 -04:00
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uint64_t rtc_ticks_at_sleep_start;
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2020-12-24 08:02:32 -05:00
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#if SOC_PM_SUPPORT_CPU_PD
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void *cpu_pd_mem;
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#endif
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2018-04-04 03:05:50 -04:00
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} sleep_config_t;
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2016-12-16 01:26:05 -05:00
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2018-04-04 03:05:50 -04:00
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static sleep_config_t s_config = {
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2020-12-24 08:02:32 -05:00
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.pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO },
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2020-11-06 04:28:57 -05:00
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.ccount_ticks_record = 0,
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.sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US,
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2016-12-16 01:26:05 -05:00
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.wakeup_triggers = 0
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};
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2018-12-04 23:22:55 -05:00
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/* Internal variable used to track if light sleep wakeup sources are to be
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expected when determining wakeup cause. */
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static bool s_light_sleep_wakeup = false;
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2018-09-04 00:56:47 -04:00
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2016-09-12 03:23:15 -04:00
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/* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc()
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2020-10-07 03:34:33 -04:00
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is not thread-safe, so we need to disable interrupts before going to deep sleep. */
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static portMUX_TYPE spinlock_rtc_deep_sleep = portMUX_INITIALIZER_UNLOCKED;
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2016-09-12 03:23:15 -04:00
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2017-04-21 00:32:50 -04:00
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static const char* TAG = "sleep";
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2016-12-14 01:20:01 -05:00
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2019-07-16 05:33:30 -04:00
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static uint32_t get_power_down_flags(void);
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2021-01-12 06:10:21 -05:00
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#if SOC_PM_SUPPORT_EXT_WAKEUP
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2019-07-16 05:33:30 -04:00
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static void ext0_wakeup_prepare(void);
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static void ext1_wakeup_prepare(void);
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2021-01-12 06:10:21 -05:00
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#endif
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2019-07-16 05:33:30 -04:00
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static void timer_wakeup_prepare(void);
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2020-10-26 04:10:37 -04:00
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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2020-04-23 00:39:07 -04:00
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static void touch_wakeup_prepare(void);
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#endif
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2021-02-05 04:10:44 -05:00
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#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
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static void esp_deep_sleep_wakeup_prepare(void);
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#endif
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2020-04-23 00:39:07 -04:00
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2021-01-28 09:28:04 -05:00
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#if CONFIG_MAC_BB_PD
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#define MAC_BB_POWER_DOWN_CB_NO 2
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#define MAC_BB_POWER_UP_CB_NO 2
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static DRAM_ATTR mac_bb_power_down_cb_t s_mac_bb_power_down_cb[MAC_BB_POWER_DOWN_CB_NO];
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static DRAM_ATTR mac_bb_power_up_cb_t s_mac_bb_power_up_cb[MAC_BB_POWER_UP_CB_NO];
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esp_err_t esp_register_mac_bb_pd_callback(mac_bb_power_down_cb_t cb)
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{
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int index = MAC_BB_POWER_DOWN_CB_NO;
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for (int i = MAC_BB_POWER_DOWN_CB_NO -1; i >= 0; i--) {
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if (s_mac_bb_power_down_cb[i] == cb) {
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return ESP_ERR_INVALID_STATE;
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}
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if (s_mac_bb_power_down_cb[i] == NULL) {
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index = i;
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}
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}
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if (index < MAC_BB_POWER_DOWN_CB_NO) {
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s_mac_bb_power_down_cb[index] = cb;
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return ESP_OK;
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}
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return ESP_ERR_NO_MEM;
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}
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esp_err_t esp_unregister_mac_bb_pd_callback(mac_bb_power_down_cb_t cb)
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{
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for (int i = MAC_BB_POWER_DOWN_CB_NO -1; i >= 0; i--) {
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if (s_mac_bb_power_down_cb[i] == cb) {
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s_mac_bb_power_down_cb[i] = NULL;
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return ESP_OK;
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}
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}
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return ESP_ERR_INVALID_STATE;
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}
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static IRAM_ATTR void mac_bb_power_down_cb_execute(void)
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{
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for (int i = 0; i < MAC_BB_POWER_DOWN_CB_NO; i++) {
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if (s_mac_bb_power_down_cb[i]) {
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s_mac_bb_power_down_cb[i]();
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}
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}
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}
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esp_err_t esp_register_mac_bb_pu_callback(mac_bb_power_up_cb_t cb)
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{
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int index = MAC_BB_POWER_UP_CB_NO;
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for (int i = MAC_BB_POWER_UP_CB_NO -1; i >= 0; i--) {
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if (s_mac_bb_power_up_cb[i] == cb) {
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return ESP_ERR_INVALID_STATE;
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}
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if (s_mac_bb_power_up_cb[i] == NULL) {
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index = i;
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}
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}
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if (index < MAC_BB_POWER_UP_CB_NO) {
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s_mac_bb_power_up_cb[index] = cb;
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return ESP_OK;
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}
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return ESP_ERR_NO_MEM;
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}
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esp_err_t esp_unregister_mac_bb_pu_callback(mac_bb_power_up_cb_t cb)
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{
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for (int i = MAC_BB_POWER_UP_CB_NO -1; i >= 0; i--) {
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if (s_mac_bb_power_up_cb[i] == cb) {
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s_mac_bb_power_up_cb[i] = NULL;
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return ESP_OK;
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}
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}
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return ESP_ERR_INVALID_STATE;
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}
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static IRAM_ATTR void mac_bb_power_up_cb_execute(void)
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{
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for (int i = 0; i < MAC_BB_POWER_UP_CB_NO; i++) {
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if (s_mac_bb_power_up_cb[i]) {
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s_mac_bb_power_up_cb[i]();
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}
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}
|
|
|
|
}
|
|
|
|
#endif ///CONFIG_MAC_BB_PD
|
|
|
|
|
2016-12-08 09:22:10 -05:00
|
|
|
/* Wake from deep sleep stub
|
|
|
|
See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
|
|
|
|
*/
|
2016-09-12 03:23:15 -04:00
|
|
|
esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
|
|
|
|
{
|
2018-08-26 20:12:28 -04:00
|
|
|
esp_deep_sleep_wake_stub_fn_t stub_ptr = (esp_deep_sleep_wake_stub_fn_t) REG_READ(RTC_ENTRY_ADDR_REG);
|
|
|
|
if (!esp_ptr_executable(stub_ptr)) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
return stub_ptr;
|
2016-09-12 03:23:15 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
|
|
|
|
{
|
|
|
|
REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
|
|
|
|
}
|
|
|
|
|
|
|
|
void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) {
|
2016-10-12 20:46:51 -04:00
|
|
|
/* Clear MMU for CPU 0 */
|
2020-04-23 00:39:07 -04:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2017-09-01 06:35:42 -04:00
|
|
|
_DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG,
|
|
|
|
_DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR);
|
|
|
|
_DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG,
|
|
|
|
_DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR));
|
2020-04-23 00:39:07 -04:00
|
|
|
#if DEEP_SLEEP_WAKEUP_DELAY > 0
|
2016-12-12 10:20:15 -05:00
|
|
|
// ROM code has not started yet, so we need to set delay factor
|
2020-07-21 01:07:34 -04:00
|
|
|
// used by esp_rom_delay_us first.
|
2017-01-11 04:17:13 -05:00
|
|
|
ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000);
|
2016-12-16 01:26:05 -05:00
|
|
|
// This delay is configured in menuconfig, it can be used to give
|
|
|
|
// the flash chip some time to become ready.
|
2020-04-23 00:39:07 -04:00
|
|
|
esp_rom_delay_us(DEEP_SLEEP_WAKEUP_DELAY);
|
|
|
|
#endif
|
|
|
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
|
|
|
REG_SET_BIT(EXTMEM_CACHE_DBG_INT_ENA_REG, EXTMEM_CACHE_DBG_EN);
|
2016-12-12 10:20:15 -05:00
|
|
|
#endif
|
2016-09-12 03:23:15 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
|
2016-11-21 10:05:23 -05:00
|
|
|
|
|
|
|
void esp_deep_sleep(uint64_t time_in_us)
|
|
|
|
{
|
2017-04-21 00:32:50 -04:00
|
|
|
esp_sleep_enable_timer_wakeup(time_in_us);
|
2016-12-08 09:22:10 -05:00
|
|
|
esp_deep_sleep_start();
|
|
|
|
}
|
|
|
|
|
2020-04-23 00:39:07 -04:00
|
|
|
// [refactor-todo] provide target logic for body of uart functions below
|
2019-07-16 05:33:30 -04:00
|
|
|
static void IRAM_ATTR flush_uarts(void)
|
2018-07-04 00:11:07 -04:00
|
|
|
{
|
2020-04-23 00:39:07 -04:00
|
|
|
for (int i = 0; i < SOC_UART_NUM; ++i) {
|
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
2020-07-13 09:33:23 -04:00
|
|
|
esp_rom_uart_tx_wait_idle(i);
|
2021-01-16 00:58:55 -05:00
|
|
|
#else
|
2020-04-23 00:39:07 -04:00
|
|
|
if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
|
|
|
|
esp_rom_uart_tx_wait_idle(i);
|
|
|
|
}
|
|
|
|
#endif
|
2018-07-04 00:11:07 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
static void IRAM_ATTR suspend_uarts(void)
|
2018-04-04 03:05:50 -04:00
|
|
|
{
|
2020-04-23 00:39:07 -04:00
|
|
|
for (int i = 0; i < SOC_UART_NUM; ++i) {
|
2020-12-03 22:20:07 -05:00
|
|
|
#ifndef CONFIG_IDF_TARGET_ESP32
|
|
|
|
if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) continue;
|
|
|
|
#endif
|
|
|
|
uart_ll_force_xoff(i);
|
|
|
|
#if SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
|
|
|
|
uint32_t uart_fsm = 0;
|
|
|
|
do {
|
|
|
|
uart_fsm = uart_ll_get_fsm_status(i);
|
|
|
|
} while (!(uart_fsm == UART_FSM_IDLE || uart_fsm == UART_FSM_TX_WAIT_SEND));
|
|
|
|
#else
|
|
|
|
while (uart_ll_get_fsm_status(i) != 0) {}
|
2020-04-23 00:39:07 -04:00
|
|
|
#endif
|
2018-04-04 03:05:50 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
static void IRAM_ATTR resume_uarts(void)
|
2018-04-04 03:05:50 -04:00
|
|
|
{
|
2020-04-23 00:39:07 -04:00
|
|
|
for (int i = 0; i < SOC_UART_NUM; ++i) {
|
2020-12-03 22:20:07 -05:00
|
|
|
#ifndef CONFIG_IDF_TARGET_ESP32
|
|
|
|
if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) continue;
|
2020-04-23 00:39:07 -04:00
|
|
|
#endif
|
2020-12-03 22:20:07 -05:00
|
|
|
uart_ll_force_xon(i);
|
2018-04-04 03:05:50 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-07 03:34:33 -04:00
|
|
|
inline static uint32_t IRAM_ATTR call_rtc_sleep_start(uint32_t reject_triggers);
|
|
|
|
|
2020-12-24 08:02:32 -05:00
|
|
|
#if SOC_PM_SUPPORT_CPU_PD
|
|
|
|
esp_err_t esp_sleep_cpu_pd_low_init(bool enable)
|
|
|
|
{
|
|
|
|
if (enable) {
|
|
|
|
if (s_config.cpu_pd_mem == NULL) {
|
|
|
|
void *buf = heap_caps_aligned_alloc(RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN,
|
|
|
|
RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE,
|
|
|
|
MALLOC_CAP_RETENTION|MALLOC_CAP_DEFAULT);
|
|
|
|
if (buf) {
|
|
|
|
memset(buf, 0, RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE);
|
|
|
|
s_config.cpu_pd_mem = rtc_cntl_hal_dma_link_init(buf,
|
|
|
|
buf+RTC_HAL_DMA_LINK_NODE_SIZE, RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE, NULL);
|
|
|
|
} else {
|
|
|
|
return ESP_ERR_NO_MEM;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (s_config.cpu_pd_mem) {
|
|
|
|
heap_caps_free(s_config.cpu_pd_mem);
|
|
|
|
s_config.cpu_pd_mem = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
#endif // SOC_PM_SUPPORT_CPU_PD
|
|
|
|
|
2020-11-12 07:39:55 -05:00
|
|
|
#if SOC_GPIO_SUPPORT_SLP_SWITCH
|
|
|
|
#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
|
|
|
|
static inline void gpio_sleep_mode_config_apply(void)
|
|
|
|
{
|
|
|
|
for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
|
|
|
|
if (GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
gpio_sleep_pupd_config_apply(gpio_num);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void gpio_sleep_mode_config_unapply(void)
|
|
|
|
{
|
|
|
|
for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
|
|
|
|
if (GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
gpio_sleep_pupd_config_unapply(gpio_num);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void esp_sleep_gpio_status_init(void)
|
|
|
|
{
|
|
|
|
ESP_LOGI(TAG, "Init to disable all pins at light sleep");
|
|
|
|
for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
|
|
|
|
if (GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
gpio_sleep_set_direction(gpio_num, GPIO_MODE_DISABLE);
|
|
|
|
gpio_sleep_set_pull_mode(gpio_num, GPIO_FLOATING);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void esp_sleep_gpio_status_switch_configure(bool enable)
|
|
|
|
{
|
|
|
|
if (enable) {
|
|
|
|
ESP_LOGI(TAG, "Light sleep enabled, start GPIO status switching");
|
|
|
|
} else {
|
|
|
|
ESP_LOGI(TAG, "Light sleep disabled, stop GPIO status switching");
|
|
|
|
}
|
|
|
|
for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
|
|
|
|
if (GPIO_IS_VALID_GPIO(gpio_num)) {
|
|
|
|
if (enable) {
|
|
|
|
gpio_sleep_sel_en(gpio_num);
|
|
|
|
} else {
|
|
|
|
gpio_sleep_sel_dis(gpio_num);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif // SOC_GPIO_SUPPORT_SLP_SWITCH
|
2020-11-12 07:39:55 -05:00
|
|
|
|
2021-01-28 09:28:04 -05:00
|
|
|
|
2017-04-21 00:32:50 -04:00
|
|
|
static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
|
2016-12-08 09:22:10 -05:00
|
|
|
{
|
2018-07-04 00:11:07 -04:00
|
|
|
// Stop UART output so that output is not lost due to APB frequency change.
|
|
|
|
// For light sleep, suspend UART output — it will resume after wakeup.
|
|
|
|
// For deep sleep, wait for the contents of UART FIFO to be sent.
|
2020-10-07 03:34:33 -04:00
|
|
|
bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG;
|
|
|
|
|
2020-12-21 00:26:00 -05:00
|
|
|
#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
2020-10-07 03:34:33 -04:00
|
|
|
/* Currently only safe to use deep sleep wake stub & RTC memory as heap in single core mode.
|
|
|
|
|
2020-12-21 00:26:00 -05:00
|
|
|
For ESP32-S3, either disable ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP in config or find a way to set the
|
2020-10-07 03:34:33 -04:00
|
|
|
deep sleep wake stub to NULL.
|
|
|
|
*/
|
|
|
|
assert(!deep_sleep || esp_get_deep_sleep_wake_stub() == NULL);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (deep_sleep) {
|
2018-07-04 00:11:07 -04:00
|
|
|
flush_uarts();
|
|
|
|
} else {
|
|
|
|
suspend_uarts();
|
|
|
|
}
|
2018-04-04 03:05:50 -04:00
|
|
|
|
|
|
|
// Save current frequency and switch to XTAL
|
2018-07-29 03:50:49 -04:00
|
|
|
rtc_cpu_freq_config_t cpu_freq_config;
|
|
|
|
rtc_clk_cpu_freq_get_config(&cpu_freq_config);
|
|
|
|
rtc_clk_cpu_freq_set_xtal();
|
2016-12-14 01:20:01 -05:00
|
|
|
|
2021-03-09 00:49:59 -05:00
|
|
|
#if CONFIG_MAC_BB_PD
|
|
|
|
mac_bb_power_down_cb_execute();
|
|
|
|
#endif
|
|
|
|
|
2021-01-12 06:10:21 -05:00
|
|
|
#if SOC_PM_SUPPORT_EXT_WAKEUP
|
2017-04-11 03:44:43 -04:00
|
|
|
// Configure pins for external wakeup
|
|
|
|
if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
|
|
|
|
ext0_wakeup_prepare();
|
2016-12-08 09:22:10 -05:00
|
|
|
}
|
2017-04-11 03:44:43 -04:00
|
|
|
if (s_config.wakeup_triggers & RTC_EXT1_TRIG_EN) {
|
|
|
|
ext1_wakeup_prepare();
|
|
|
|
}
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif
|
2020-04-23 00:39:07 -04:00
|
|
|
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
|
|
|
|
if (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN) {
|
|
|
|
esp_deep_sleep_wakeup_prepare();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2020-04-23 00:39:07 -04:00
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
2017-04-11 03:44:43 -04:00
|
|
|
// Enable ULP wakeup
|
|
|
|
if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) {
|
2020-04-27 02:01:30 -04:00
|
|
|
rtc_hal_ulp_wakeup_enable();
|
2017-04-11 03:44:43 -04:00
|
|
|
}
|
2020-11-12 07:39:55 -05:00
|
|
|
#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
|
|
|
|
gpio_sleep_mode_config_apply();
|
|
|
|
#endif
|
2020-04-23 00:39:07 -04:00
|
|
|
#endif
|
|
|
|
|
2020-10-26 04:10:37 -04:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
|
|
|
if (deep_sleep) {
|
|
|
|
if (s_config.wakeup_triggers & RTC_TOUCH_TRIG_EN) {
|
|
|
|
touch_wakeup_prepare();
|
|
|
|
/* Workaround: In deep sleep, for ESP32S2, Power down the RTC_PERIPH will change the slope configuration of Touch sensor sleep pad.
|
|
|
|
* The configuration change will change the reading of the sleep pad, which will cause the touch wake-up sensor to trigger falsely.
|
|
|
|
*/
|
|
|
|
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* In light sleep, the RTC_PERIPH power domain should be in the power-on state (Power on the touch circuit in light sleep),
|
|
|
|
* otherwise the touch sensor FSM will be cleared, causing touch sensor false triggering.
|
|
|
|
*/
|
|
|
|
if (touch_ll_get_fsm_state()) { // Check if the touch sensor is working properly.
|
|
|
|
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
|
|
|
|
}
|
2020-04-23 00:39:07 -04:00
|
|
|
}
|
|
|
|
#endif
|
2020-06-18 08:01:25 -04:00
|
|
|
uint32_t reject_triggers = 0;
|
|
|
|
if ((pd_flags & RTC_SLEEP_PD_DIG) == 0 && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) {
|
|
|
|
/* Light sleep, enable sleep reject for faster return from this function,
|
|
|
|
* in case the wakeup is already triggerred.
|
|
|
|
*/
|
2020-04-23 00:39:07 -04:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2020-06-18 08:01:25 -04:00
|
|
|
reject_triggers = RTC_CNTL_LIGHT_SLP_REJECT_EN_M | RTC_CNTL_GPIO_REJECT_EN_M;
|
2021-02-05 04:10:44 -05:00
|
|
|
#else
|
2020-04-23 00:39:07 -04:00
|
|
|
reject_triggers = s_config.wakeup_triggers;
|
|
|
|
#endif
|
2020-06-18 08:01:25 -04:00
|
|
|
}
|
|
|
|
|
2018-04-04 03:05:50 -04:00
|
|
|
// Enter sleep
|
|
|
|
rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags);
|
|
|
|
rtc_sleep_init(config);
|
2021-01-12 06:10:21 -05:00
|
|
|
rtc_sleep_low_init(s_config.rtc_clk_cal_period);
|
2018-04-04 03:05:50 -04:00
|
|
|
|
2020-11-06 04:28:57 -05:00
|
|
|
// Set state machine time for light sleep
|
|
|
|
if(!deep_sleep) {
|
|
|
|
rtc_sleep_low_init(s_config.rtc_clk_cal_period);
|
|
|
|
}
|
|
|
|
|
2017-04-11 03:44:43 -04:00
|
|
|
// Configure timer wakeup
|
|
|
|
if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) &&
|
|
|
|
s_config.sleep_duration > 0) {
|
|
|
|
timer_wakeup_prepare();
|
|
|
|
}
|
2020-04-23 00:39:07 -04:00
|
|
|
|
2020-10-07 03:34:33 -04:00
|
|
|
uint32_t result;
|
|
|
|
if (deep_sleep) {
|
|
|
|
/* Disable interrupts in case another task writes to RTC memory while we
|
|
|
|
* calculate RTC memory CRC
|
|
|
|
*
|
|
|
|
* Note: for ESP32-S3 running in dual core mode this is currently not enough,
|
|
|
|
* see the assert at top of this function.
|
|
|
|
*/
|
|
|
|
portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
|
|
|
|
|
2020-12-21 00:26:00 -05:00
|
|
|
#if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
2020-10-07 03:34:33 -04:00
|
|
|
/* If not possible stack is in RTC FAST memory, use the ROM function to calculate the CRC and save ~140 bytes IRAM */
|
|
|
|
set_rtc_memory_crc();
|
|
|
|
result = call_rtc_sleep_start(reject_triggers);
|
|
|
|
#else
|
|
|
|
/* Otherwise, need to call the dedicated soc function for this */
|
|
|
|
result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
|
2020-04-23 00:39:07 -04:00
|
|
|
#endif
|
2017-04-11 03:44:43 -04:00
|
|
|
|
2020-10-07 03:34:33 -04:00
|
|
|
portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
|
|
|
|
} else {
|
|
|
|
result = call_rtc_sleep_start(reject_triggers);
|
|
|
|
}
|
|
|
|
|
2018-04-04 03:05:50 -04:00
|
|
|
// Restore CPU frequency
|
2018-07-29 03:50:49 -04:00
|
|
|
rtc_clk_cpu_freq_set_config(&cpu_freq_config);
|
2018-04-04 03:05:50 -04:00
|
|
|
|
2020-11-06 04:28:57 -05:00
|
|
|
if (!deep_sleep) {
|
|
|
|
s_config.ccount_ticks_record = cpu_ll_get_cycle_count();
|
|
|
|
}
|
|
|
|
|
2020-12-24 08:02:32 -05:00
|
|
|
#if SOC_PM_SUPPORT_CPU_PD
|
|
|
|
rtc_cntl_hal_disable_cpu_retention();
|
|
|
|
#endif
|
|
|
|
|
2020-11-12 07:39:55 -05:00
|
|
|
#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
|
|
|
|
gpio_sleep_mode_config_unapply();
|
|
|
|
#endif
|
2020-12-03 22:09:21 -05:00
|
|
|
|
2021-01-28 09:28:04 -05:00
|
|
|
#if CONFIG_MAC_BB_PD
|
|
|
|
mac_bb_power_up_cb_execute();
|
|
|
|
#endif
|
2018-04-04 03:05:50 -04:00
|
|
|
// re-enable UART output
|
|
|
|
resume_uarts();
|
|
|
|
|
|
|
|
return result;
|
2017-04-21 00:32:50 -04:00
|
|
|
}
|
|
|
|
|
2020-10-07 03:34:33 -04:00
|
|
|
inline static uint32_t IRAM_ATTR call_rtc_sleep_start(uint32_t reject_triggers)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
|
|
|
return rtc_sleep_start(s_config.wakeup_triggers, reject_triggers);
|
|
|
|
#else
|
|
|
|
return rtc_sleep_start(s_config.wakeup_triggers, reject_triggers, 1);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
void IRAM_ATTR esp_deep_sleep_start(void)
|
2017-04-21 00:32:50 -04:00
|
|
|
{
|
2021-02-09 06:30:43 -05:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
|
|
|
/* Due to hardware limitations, on S2 the brownout detector sometimes trigger during deep sleep
|
|
|
|
to circumvent this we disable the brownout detector before sleeping */
|
|
|
|
esp_brownout_disable();
|
|
|
|
#endif //CONFIG_IDF_TARGET_ESP32S2
|
|
|
|
|
2018-04-04 03:05:50 -04:00
|
|
|
// record current RTC time
|
|
|
|
s_config.rtc_ticks_at_sleep_start = rtc_time_get();
|
2020-05-04 06:17:06 -04:00
|
|
|
|
|
|
|
// record current RTC time
|
2018-06-04 03:39:18 -04:00
|
|
|
esp_sync_counters_rtc_and_frc();
|
2017-04-21 00:32:50 -04:00
|
|
|
// Configure wake stub
|
|
|
|
if (esp_get_deep_sleep_wake_stub() == NULL) {
|
|
|
|
esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Decide which power domains can be powered down
|
|
|
|
uint32_t pd_flags = get_power_down_flags();
|
|
|
|
|
2020-11-06 04:28:57 -05:00
|
|
|
s_config.rtc_clk_cal_period = esp_clk_slowclk_cal_get();
|
|
|
|
|
2018-04-04 03:05:50 -04:00
|
|
|
// Correct the sleep time
|
|
|
|
s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US;
|
|
|
|
|
2021-03-09 04:04:13 -05:00
|
|
|
uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO;
|
|
|
|
|
|
|
|
#if SOC_PM_SUPPORT_WIFI_PD
|
|
|
|
force_pd_flags |= RTC_SLEEP_PD_WIFI;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if SOC_PM_SUPPORT_BT_PD
|
|
|
|
force_pd_flags |= RTC_SLEEP_PD_BT;
|
|
|
|
#endif
|
|
|
|
|
2017-04-21 00:32:50 -04:00
|
|
|
// Enter sleep
|
2021-03-09 04:04:13 -05:00
|
|
|
esp_sleep_start(force_pd_flags | pd_flags);
|
2017-04-21 00:32:50 -04:00
|
|
|
|
2016-12-16 01:26:05 -05:00
|
|
|
// Because RTC is in a slower clock domain than the CPU, it
|
|
|
|
// can take several CPU cycles for the sleep mode to start.
|
2016-11-21 10:05:23 -05:00
|
|
|
while (1) {
|
|
|
|
;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-04-21 00:32:50 -04:00
|
|
|
/**
|
|
|
|
* Helper function which handles entry to and exit from light sleep
|
|
|
|
* Placed into IRAM as flash may need some time to be powered on.
|
|
|
|
*/
|
2017-09-21 23:41:30 -04:00
|
|
|
static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
|
2018-04-04 03:05:50 -04:00
|
|
|
uint32_t flash_enable_time_us,
|
2017-11-01 03:16:32 -04:00
|
|
|
rtc_vddsdio_config_t vddsdio_config) IRAM_ATTR __attribute__((noinline));
|
2017-09-21 23:41:30 -04:00
|
|
|
|
|
|
|
static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
|
2018-04-04 03:05:50 -04:00
|
|
|
uint32_t flash_enable_time_us,
|
2017-11-01 03:16:32 -04:00
|
|
|
rtc_vddsdio_config_t vddsdio_config)
|
2017-04-21 00:32:50 -04:00
|
|
|
{
|
|
|
|
// Enter sleep
|
|
|
|
esp_err_t err = esp_sleep_start(pd_flags);
|
|
|
|
|
2017-11-01 03:16:32 -04:00
|
|
|
// If VDDSDIO regulator was controlled by RTC registers before sleep,
|
|
|
|
// restore the configuration.
|
|
|
|
if (vddsdio_config.force) {
|
|
|
|
rtc_vddsdio_set_config(vddsdio_config);
|
|
|
|
}
|
|
|
|
|
2017-04-21 00:32:50 -04:00
|
|
|
// If SPI flash was powered down, wait for it to become ready
|
|
|
|
if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
|
|
|
|
// Wait for the flash chip to start up
|
2020-07-21 01:07:34 -04:00
|
|
|
esp_rom_delay_us(flash_enable_time_us);
|
2017-04-21 00:32:50 -04:00
|
|
|
}
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
esp_err_t esp_light_sleep_start(void)
|
2017-04-21 00:32:50 -04:00
|
|
|
{
|
2021-01-08 05:29:54 -05:00
|
|
|
s_config.ccount_ticks_record = cpu_ll_get_cycle_count();
|
2017-04-21 00:32:50 -04:00
|
|
|
static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED;
|
|
|
|
portENTER_CRITICAL(&light_sleep_lock);
|
2020-02-06 01:00:18 -05:00
|
|
|
/* We will be calling esp_timer_private_advance inside DPORT access critical
|
2018-05-04 00:50:39 -04:00
|
|
|
* section. Make sure the code on the other CPU is not holding esp_timer
|
|
|
|
* lock, otherwise there will be deadlock.
|
|
|
|
*/
|
2020-02-06 01:00:18 -05:00
|
|
|
esp_timer_private_lock();
|
2020-11-06 04:28:57 -05:00
|
|
|
|
2018-04-04 03:05:50 -04:00
|
|
|
s_config.rtc_ticks_at_sleep_start = rtc_time_get();
|
2020-11-06 04:28:57 -05:00
|
|
|
uint32_t ccount_at_sleep_start = cpu_ll_get_cycle_count();
|
2020-09-03 06:17:24 -04:00
|
|
|
uint64_t frc_time_at_start = esp_system_get_time();
|
2020-11-06 04:28:57 -05:00
|
|
|
uint32_t sleep_time_overhead_in = (ccount_at_sleep_start-s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL);
|
|
|
|
|
2018-04-04 03:05:50 -04:00
|
|
|
DPORT_STALL_OTHER_CPU_START();
|
2017-04-21 00:32:50 -04:00
|
|
|
|
|
|
|
// Decide which power domains can be powered down
|
|
|
|
uint32_t pd_flags = get_power_down_flags();
|
|
|
|
|
2020-11-06 04:28:57 -05:00
|
|
|
// Re-calibrate the RTC Timer clock
|
2020-12-03 22:09:21 -05:00
|
|
|
#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) || defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS) || defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS)
|
2020-11-06 04:28:57 -05:00
|
|
|
uint64_t time_per_us = 1000000ULL;
|
|
|
|
s_config.rtc_clk_cal_period = (time_per_us << RTC_CLK_CAL_FRACT) / rtc_clk_slow_freq_get_hz();
|
|
|
|
#elif defined(CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC)
|
|
|
|
s_config.rtc_clk_cal_period = rtc_clk_cal_cycling(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES);
|
2021-01-09 05:03:18 -05:00
|
|
|
esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
|
2020-11-06 04:28:57 -05:00
|
|
|
#else
|
|
|
|
s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Adjustment time consists of parts below:
|
|
|
|
* 1. Hardware time waiting for internal 8M oscilate clock and XTAL;
|
|
|
|
* 2. Hardware state swithing time of the rtc main state machine;
|
|
|
|
* 3. Code execution time when clock is not stable;
|
|
|
|
* 4. Code execution time which can be measured;
|
|
|
|
*/
|
|
|
|
|
|
|
|
uint32_t rtc_cntl_xtl_buf_wait_slp_cycles = rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, s_config.rtc_clk_cal_period);
|
|
|
|
s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out
|
|
|
|
+ rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_slp_cycles + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, s_config.rtc_clk_cal_period);
|
2018-04-04 03:05:50 -04:00
|
|
|
|
2017-10-18 08:04:40 -04:00
|
|
|
// Decide if VDD_SDIO needs to be powered down;
|
|
|
|
// If it needs to be powered down, adjust sleep time.
|
2020-04-23 00:39:07 -04:00
|
|
|
const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US + DEEP_SLEEP_WAKEUP_DELAY;
|
2017-04-21 00:32:50 -04:00
|
|
|
|
2020-11-06 04:28:57 -05:00
|
|
|
#if CONFIG_ESP_SYSTEM_PD_FLASH
|
|
|
|
/*
|
|
|
|
* When SPIRAM is disabled in menuconfig, the minimum sleep time of the
|
|
|
|
* system needs to meet the sum below:
|
|
|
|
* 1. Wait time for the flash power-on after waking up;
|
|
|
|
* 2. The execution time of codes between RTC Timer get start time
|
|
|
|
* with hardware starts to switch state to sleep;
|
|
|
|
* 3. The hardware state switching time of the rtc state machine during
|
|
|
|
* sleep and wake-up. This process requires 6 cycles to complete.
|
|
|
|
* The specific hardware state switching process and the cycles
|
|
|
|
* consumed are rtc_cpu_run_stall(1), cut_pll_rtl(2), cut_8m(1),
|
|
|
|
* min_protect(2);
|
|
|
|
* 4. All the adjustment time which is s_config.sleep_time_adjustment below.
|
|
|
|
*/
|
2018-04-04 03:05:50 -04:00
|
|
|
const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
|
2020-11-06 04:28:57 -05:00
|
|
|
flash_enable_time_us + LIGHT_SLEEP_MIN_TIME_US + s_config.sleep_time_adjustment
|
|
|
|
+ rtc_time_slowclk_to_us(RTC_MODULE_SLEEP_PREPARE_CYCLES, s_config.rtc_clk_cal_period));
|
2018-04-04 03:05:50 -04:00
|
|
|
|
|
|
|
if (s_config.sleep_duration > vddsdio_pd_sleep_duration) {
|
2017-04-21 00:32:50 -04:00
|
|
|
pd_flags |= RTC_SLEEP_PD_VDDSDIO;
|
2020-11-06 04:28:57 -05:00
|
|
|
if (s_config.sleep_time_overhead_out < flash_enable_time_us) {
|
|
|
|
s_config.sleep_time_adjustment += flash_enable_time_us;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (s_config.sleep_time_overhead_out > flash_enable_time_us) {
|
|
|
|
s_config.sleep_time_adjustment -= flash_enable_time_us;
|
|
|
|
}
|
2017-04-21 00:32:50 -04:00
|
|
|
}
|
2020-11-06 04:28:57 -05:00
|
|
|
#endif //CONFIG_ESP_SYSTEM_PD_FLASH
|
2018-04-04 03:05:50 -04:00
|
|
|
|
2020-12-30 03:42:39 -05:00
|
|
|
periph_inform_out_light_sleep_overhead(s_config.sleep_time_adjustment - sleep_time_overhead_in);
|
|
|
|
|
2020-12-24 08:02:32 -05:00
|
|
|
#if SOC_PM_SUPPORT_CPU_PD
|
|
|
|
rtc_cntl_hal_enable_cpu_retention(s_config.cpu_pd_mem);
|
|
|
|
#endif
|
|
|
|
|
2017-11-01 03:16:32 -04:00
|
|
|
rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
|
2017-04-21 00:32:50 -04:00
|
|
|
|
|
|
|
// Safety net: enable WDT in case exit from light sleep fails
|
2019-12-26 03:30:03 -05:00
|
|
|
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
|
|
|
bool wdt_was_enabled = wdt_hal_is_enabled(&rtc_wdt_ctx); // If WDT was enabled in the user code, then do not change it here.
|
2018-07-23 06:59:37 -04:00
|
|
|
if (!wdt_was_enabled) {
|
2019-12-26 03:30:03 -05:00
|
|
|
wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
|
|
|
|
uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
|
|
|
|
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
|
|
|
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
|
|
|
|
wdt_hal_enable(&rtc_wdt_ctx);
|
|
|
|
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
2018-07-23 06:59:37 -04:00
|
|
|
}
|
2017-04-21 00:32:50 -04:00
|
|
|
|
|
|
|
// Enter sleep, then wait for flash to be ready on wakeup
|
2018-04-04 03:05:50 -04:00
|
|
|
esp_err_t err = esp_light_sleep_inner(pd_flags,
|
2017-11-01 03:16:32 -04:00
|
|
|
flash_enable_time_us, vddsdio_config);
|
2017-04-21 00:32:50 -04:00
|
|
|
|
2018-09-04 00:56:47 -04:00
|
|
|
s_light_sleep_wakeup = true;
|
|
|
|
|
2018-04-04 03:05:50 -04:00
|
|
|
// FRC1 has been clock gated for the duration of the sleep, correct for that.
|
2020-12-03 22:09:21 -05:00
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32C3
|
|
|
|
/**
|
|
|
|
* On esp32c3, rtc_time_get() is non-blocking, esp_system_get_time() is
|
|
|
|
* blocking, and the measurement data shows that this order is better.
|
|
|
|
*/
|
|
|
|
uint64_t frc_time_at_end = esp_system_get_time();
|
|
|
|
uint64_t rtc_ticks_at_end = rtc_time_get();
|
|
|
|
#else
|
2018-04-04 03:05:50 -04:00
|
|
|
uint64_t rtc_ticks_at_end = rtc_time_get();
|
2020-09-03 06:17:24 -04:00
|
|
|
uint64_t frc_time_at_end = esp_system_get_time();
|
2020-12-03 22:09:21 -05:00
|
|
|
#endif
|
2017-04-21 00:32:50 -04:00
|
|
|
|
2020-11-06 04:28:57 -05:00
|
|
|
uint64_t rtc_time_diff = rtc_time_slowclk_to_us(rtc_ticks_at_end - s_config.rtc_ticks_at_sleep_start, s_config.rtc_clk_cal_period);
|
2018-04-04 03:05:50 -04:00
|
|
|
uint64_t frc_time_diff = frc_time_at_end - frc_time_at_start;
|
|
|
|
|
|
|
|
int64_t time_diff = rtc_time_diff - frc_time_diff;
|
|
|
|
/* Small negative values (up to 1 RTC_SLOW clock period) are possible,
|
|
|
|
* for very small values of sleep_duration. Ignore those to keep esp_timer
|
|
|
|
* monotonic.
|
|
|
|
*/
|
|
|
|
if (time_diff > 0) {
|
2020-02-06 01:00:18 -05:00
|
|
|
esp_timer_private_advance(time_diff);
|
2018-04-04 03:05:50 -04:00
|
|
|
}
|
|
|
|
esp_set_time_from_rtc();
|
2017-04-21 00:32:50 -04:00
|
|
|
|
2020-02-06 01:00:18 -05:00
|
|
|
esp_timer_private_unlock();
|
2018-04-04 03:05:50 -04:00
|
|
|
DPORT_STALL_OTHER_CPU_END();
|
2018-07-23 06:59:37 -04:00
|
|
|
if (!wdt_was_enabled) {
|
2019-12-26 03:30:03 -05:00
|
|
|
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
|
|
|
wdt_hal_disable(&rtc_wdt_ctx);
|
|
|
|
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
2018-07-23 06:59:37 -04:00
|
|
|
}
|
2017-04-21 00:32:50 -04:00
|
|
|
portEXIT_CRITICAL(&light_sleep_lock);
|
2020-11-06 04:28:57 -05:00
|
|
|
s_config.sleep_time_overhead_out = (cpu_ll_get_cycle_count() - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL);
|
2017-04-21 00:32:50 -04:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2018-03-16 02:57:35 -04:00
|
|
|
esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
|
|
|
|
{
|
|
|
|
// For most of sources it is enough to set trigger mask in local
|
|
|
|
// configuration structure. The actual RTC wake up options
|
|
|
|
// will be updated by esp_sleep_start().
|
2018-08-13 20:43:35 -04:00
|
|
|
if (source == ESP_SLEEP_WAKEUP_ALL) {
|
|
|
|
s_config.wakeup_triggers = 0;
|
|
|
|
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TIMER, RTC_TIMER_TRIG_EN)) {
|
2018-03-16 02:57:35 -04:00
|
|
|
s_config.wakeup_triggers &= ~RTC_TIMER_TRIG_EN;
|
|
|
|
s_config.sleep_duration = 0;
|
2021-01-12 06:10:21 -05:00
|
|
|
#if SOC_PM_SUPPORT_EXT_WAKEUP
|
2018-08-13 20:42:03 -04:00
|
|
|
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT0, RTC_EXT0_TRIG_EN)) {
|
2018-03-16 02:57:35 -04:00
|
|
|
s_config.ext0_rtc_gpio_num = 0;
|
|
|
|
s_config.ext0_trigger_level = 0;
|
|
|
|
s_config.wakeup_triggers &= ~RTC_EXT0_TRIG_EN;
|
2018-08-13 20:42:03 -04:00
|
|
|
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT1, RTC_EXT1_TRIG_EN)) {
|
2018-03-16 02:57:35 -04:00
|
|
|
s_config.ext1_rtc_gpio_mask = 0;
|
|
|
|
s_config.ext1_trigger_mode = 0;
|
|
|
|
s_config.wakeup_triggers &= ~RTC_EXT1_TRIG_EN;
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif
|
|
|
|
#if SOC_TOUCH_PAD_WAKE_SUPPORTED
|
2018-08-13 20:42:03 -04:00
|
|
|
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TOUCHPAD, RTC_TOUCH_TRIG_EN)) {
|
2018-03-16 02:57:35 -04:00
|
|
|
s_config.wakeup_triggers &= ~RTC_TOUCH_TRIG_EN;
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif
|
2018-08-13 20:42:03 -04:00
|
|
|
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_GPIO, RTC_GPIO_TRIG_EN)) {
|
|
|
|
s_config.wakeup_triggers &= ~RTC_GPIO_TRIG_EN;
|
|
|
|
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
|
|
|
|
s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
|
2018-03-16 02:57:35 -04:00
|
|
|
}
|
2020-04-23 00:39:07 -04:00
|
|
|
#if defined(CONFIG_ESP32_ULP_COPROC_ENABLED) || defined(CONFIG_ESP32S2_ULP_COPROC_ENABLED)
|
2018-03-20 02:43:48 -04:00
|
|
|
else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
|
2018-03-16 02:57:35 -04:00
|
|
|
s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
else {
|
|
|
|
ESP_LOGE(TAG, "Incorrect wakeup source (%d) to disable.", (int) source);
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
esp_err_t esp_sleep_enable_ulp_wakeup(void)
|
2016-12-08 09:22:10 -05:00
|
|
|
{
|
2020-04-27 02:01:30 -04:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2020-09-18 05:23:28 -04:00
|
|
|
#if ((defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2))
|
|
|
|
ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal");
|
2018-12-22 01:19:46 -05:00
|
|
|
return ESP_ERR_NOT_SUPPORTED;
|
2020-09-18 05:23:28 -04:00
|
|
|
#endif
|
2019-04-30 06:51:55 -04:00
|
|
|
#ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
|
2017-04-11 03:44:43 -04:00
|
|
|
if(s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
|
2017-01-27 10:36:52 -05:00
|
|
|
ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
|
2017-01-24 02:53:59 -05:00
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2017-04-11 03:44:43 -04:00
|
|
|
s_config.wakeup_triggers |= RTC_ULP_TRIG_EN;
|
2016-12-08 09:22:10 -05:00
|
|
|
return ESP_OK;
|
2020-04-23 00:39:07 -04:00
|
|
|
#else // CONFIG_ESP32_ULP_COPROC_ENABLED
|
2016-12-08 09:22:10 -05:00
|
|
|
return ESP_ERR_INVALID_STATE;
|
2020-04-23 00:39:07 -04:00
|
|
|
#endif // CONFIG_ESP32_ULP_COPROC_ENABLED
|
2020-07-29 01:13:51 -04:00
|
|
|
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
2020-04-27 02:01:30 -04:00
|
|
|
s_config.wakeup_triggers |= (RTC_ULP_TRIG_EN | RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN);
|
|
|
|
return ESP_OK;
|
2021-01-12 06:10:21 -05:00
|
|
|
#else
|
|
|
|
return ESP_ERR_NOT_SUPPORTED;
|
2016-12-08 09:22:10 -05:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-04-21 00:32:50 -04:00
|
|
|
esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
|
2016-12-08 09:22:10 -05:00
|
|
|
{
|
2017-04-11 03:44:43 -04:00
|
|
|
s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN;
|
2016-12-16 01:26:05 -05:00
|
|
|
s_config.sleep_duration = time_in_us;
|
2016-12-08 09:22:10 -05:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
static void timer_wakeup_prepare(void)
|
2017-04-11 03:44:43 -04:00
|
|
|
{
|
2018-04-04 03:05:50 -04:00
|
|
|
int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment;
|
|
|
|
if (sleep_duration < 0) {
|
|
|
|
sleep_duration = 0;
|
|
|
|
}
|
2020-04-23 00:39:07 -04:00
|
|
|
|
2020-11-06 04:28:57 -05:00
|
|
|
int64_t ticks = rtc_time_us_to_slowclk(sleep_duration, s_config.rtc_clk_cal_period);
|
2020-05-04 06:17:06 -04:00
|
|
|
rtc_hal_set_wakeup_timer(s_config.rtc_ticks_at_sleep_start + ticks);
|
2020-04-23 00:39:07 -04:00
|
|
|
}
|
|
|
|
|
2020-10-26 04:10:37 -04:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
2020-04-23 00:39:07 -04:00
|
|
|
/* In deep sleep mode, only the sleep channel is supported, and other touch channels should be turned off. */
|
|
|
|
static void touch_wakeup_prepare(void)
|
|
|
|
{
|
2020-10-26 04:10:37 -04:00
|
|
|
touch_pad_t touch_num = TOUCH_PAD_NUM0;
|
|
|
|
touch_ll_sleep_get_channel_num(&touch_num); // Check if the sleep pad is enabled.
|
|
|
|
if ((touch_num > TOUCH_PAD_NUM0) && (touch_num < TOUCH_PAD_MAX) && touch_ll_get_fsm_state()) {
|
|
|
|
touch_ll_stop_fsm();
|
|
|
|
touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
|
|
|
|
touch_ll_set_channel_mask(BIT(touch_num));
|
|
|
|
touch_ll_start_fsm();
|
|
|
|
}
|
2017-04-11 03:44:43 -04:00
|
|
|
}
|
2020-04-23 00:39:07 -04:00
|
|
|
#endif
|
2017-04-11 03:44:43 -04:00
|
|
|
|
2021-01-12 06:10:21 -05:00
|
|
|
#if SOC_TOUCH_SENSOR_NUM > 0
|
2021-01-16 01:08:34 -05:00
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
esp_err_t esp_sleep_enable_touchpad_wakeup(void)
|
2017-01-23 23:32:30 -05:00
|
|
|
{
|
2020-09-18 05:23:28 -04:00
|
|
|
#if ((defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2))
|
|
|
|
ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal");
|
2018-12-22 01:19:46 -05:00
|
|
|
return ESP_ERR_NOT_SUPPORTED;
|
|
|
|
#endif
|
2017-04-11 03:44:43 -04:00
|
|
|
if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
|
2017-01-27 10:36:52 -05:00
|
|
|
ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
|
2017-01-24 02:53:59 -05:00
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
s_config.wakeup_triggers |= RTC_TOUCH_TRIG_EN;
|
2017-01-23 23:32:30 -05:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
|
2017-01-27 10:48:00 -05:00
|
|
|
{
|
2017-04-21 00:32:50 -04:00
|
|
|
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
|
2017-01-27 10:48:00 -05:00
|
|
|
return TOUCH_PAD_MAX;
|
|
|
|
}
|
2018-07-05 02:37:37 -04:00
|
|
|
touch_pad_t pad_num;
|
2020-04-23 00:39:07 -04:00
|
|
|
esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); //TODO 723diff commit id:fda9ada1b
|
2018-07-05 02:37:37 -04:00
|
|
|
assert(ret == ESP_OK && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero");
|
|
|
|
return pad_num;
|
2017-01-27 10:48:00 -05:00
|
|
|
}
|
2021-01-16 01:08:34 -05:00
|
|
|
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif // SOC_TOUCH_SENSOR_NUM > 0
|
2017-01-27 10:48:00 -05:00
|
|
|
|
2020-11-23 01:09:16 -05:00
|
|
|
bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
|
|
|
return RTC_GPIO_IS_VALID_GPIO(gpio_num);
|
|
|
|
#else
|
2021-02-05 04:10:44 -05:00
|
|
|
return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);
|
2021-01-16 01:08:34 -05:00
|
|
|
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
2020-11-23 01:09:16 -05:00
|
|
|
}
|
|
|
|
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_PM_SUPPORT_EXT_WAKEUP
|
|
|
|
|
2017-04-21 00:32:50 -04:00
|
|
|
esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
|
2016-12-08 09:22:10 -05:00
|
|
|
{
|
|
|
|
if (level < 0 || level > 1) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2020-11-23 01:09:16 -05:00
|
|
|
if (!esp_sleep_is_valid_wakeup_gpio(gpio_num)) {
|
2016-12-08 09:22:10 -05:00
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2017-04-11 03:44:43 -04:00
|
|
|
if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
|
2017-01-27 10:36:52 -05:00
|
|
|
ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
|
2017-01-24 02:53:59 -05:00
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2019-07-25 11:11:31 -04:00
|
|
|
s_config.ext0_rtc_gpio_num = rtc_io_number_get(gpio_num);
|
2016-12-16 01:26:05 -05:00
|
|
|
s_config.ext0_trigger_level = level;
|
2017-04-11 03:44:43 -04:00
|
|
|
s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN;
|
2016-12-08 09:22:10 -05:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
static void ext0_wakeup_prepare(void)
|
2016-12-16 01:26:05 -05:00
|
|
|
{
|
|
|
|
int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
|
2020-04-27 02:01:30 -04:00
|
|
|
rtcio_hal_ext0_set_wakeup_pin(rtc_gpio_num, s_config.ext0_trigger_level);
|
|
|
|
rtcio_hal_function_select(rtc_gpio_num, RTCIO_FUNC_RTC);
|
|
|
|
rtcio_hal_input_enable(rtc_gpio_num);
|
2016-12-16 01:26:05 -05:00
|
|
|
}
|
|
|
|
|
2017-04-21 00:32:50 -04:00
|
|
|
esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode)
|
2016-12-08 09:22:10 -05:00
|
|
|
{
|
2016-12-14 01:20:01 -05:00
|
|
|
if (mode > ESP_EXT1_WAKEUP_ANY_HIGH) {
|
2016-12-08 09:22:10 -05:00
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
// Translate bit map of GPIO numbers into the bit map of RTC IO numbers
|
|
|
|
uint32_t rtc_gpio_mask = 0;
|
|
|
|
for (int gpio = 0; mask; ++gpio, mask >>= 1) {
|
|
|
|
if ((mask & 1) == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
2020-11-23 01:09:16 -05:00
|
|
|
if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
|
2016-12-08 09:22:10 -05:00
|
|
|
ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio);
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2019-07-25 11:11:31 -04:00
|
|
|
rtc_gpio_mask |= BIT(rtc_io_number_get(gpio));
|
2016-12-16 01:26:05 -05:00
|
|
|
}
|
|
|
|
s_config.ext1_rtc_gpio_mask = rtc_gpio_mask;
|
|
|
|
s_config.ext1_trigger_mode = mode;
|
2017-04-11 03:44:43 -04:00
|
|
|
s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN;
|
2016-12-16 01:26:05 -05:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
static void ext1_wakeup_prepare(void)
|
2016-12-16 01:26:05 -05:00
|
|
|
{
|
|
|
|
// Configure all RTC IOs selected as ext1 wakeup inputs
|
|
|
|
uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
|
|
|
|
for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
|
2019-07-25 11:11:31 -04:00
|
|
|
int rtc_pin = rtc_io_number_get(gpio);
|
2016-12-16 01:26:05 -05:00
|
|
|
if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
2020-11-26 03:56:13 -05:00
|
|
|
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
2016-12-16 01:26:05 -05:00
|
|
|
// Route pad to RTC
|
2020-04-27 02:01:30 -04:00
|
|
|
rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_RTC);
|
sleep: make sure input enable is set for EXT0/EXT1 wakeup
Since commit 94250e4, EXT0 wakeup mechanism, when wakeup level was set
to 0, started waking up chip immediately after entering deep sleep.
This failure was triggered in that commit by a change of
RTC_CNTL_MIN_SLP_VAL (i.e. minimum time in sleep mode until wakeup
can happen) from 128 cycles to 2 cycles.
The reason for this behaviour is related to the way input enable (IE)
signal going into an RTC pad is obtained:
PAD_IE = (SLP_SEL) ? SLP_IE & CHIP_SLEEP : IE,
where SLP_IE, SLP_SEL, and IE are bits of an RTC_IO register related
to the given pad. CHIP_SLEEP is the signal indicating that chip has
entered sleep mode.
The code in prepare_ext{0,1}_wakeup did not enable IE, but did enable
SLP_SEL and SLP_IE. This meant that until CHIP_SLEEP went high, PAD_IE
was 0, hence the input from the pad read 0 even if external signal
was 1. CHIP_SLEEP went high on the 2nd cycle of sleep. So when
RTC_CNTL_MIN_SLP_VAL was set to 2, the input signal from the pad was
latched as 0 at the moment when CHIP_SLEEP went high, causing EXT0
wakeup with level 0 to trigger.
This commit changes the way PAD_IE is enabled: SLP_SEL and SLP_IE are
no longer used, and IE is set to 1. If EXT0 wakeup is used, RTC_IO is
not powered down, so IE signal stays 1 both before CHIP_SLEEP goes
high and after. If EXT1 wakeup is used, RTC_IO may be powered down.
However prepare_ext1_wakeup enables Hold on the pad, locking states
of all the control signals, including IE.
Closes https://github.com/espressif/esp-idf/issues/1931
Closes https://github.com/espressif/esp-idf/issues/2043
2018-06-12 08:23:26 -04:00
|
|
|
// set input enable in sleep mode
|
2020-04-27 02:01:30 -04:00
|
|
|
rtcio_hal_input_enable(rtc_pin);
|
2020-11-26 03:56:13 -05:00
|
|
|
#endif
|
2020-04-27 02:01:30 -04:00
|
|
|
|
2016-12-16 01:26:05 -05:00
|
|
|
// Pad configuration depends on RTC_PERIPH state in sleep mode
|
sleep: make sure input enable is set for EXT0/EXT1 wakeup
Since commit 94250e4, EXT0 wakeup mechanism, when wakeup level was set
to 0, started waking up chip immediately after entering deep sleep.
This failure was triggered in that commit by a change of
RTC_CNTL_MIN_SLP_VAL (i.e. minimum time in sleep mode until wakeup
can happen) from 128 cycles to 2 cycles.
The reason for this behaviour is related to the way input enable (IE)
signal going into an RTC pad is obtained:
PAD_IE = (SLP_SEL) ? SLP_IE & CHIP_SLEEP : IE,
where SLP_IE, SLP_SEL, and IE are bits of an RTC_IO register related
to the given pad. CHIP_SLEEP is the signal indicating that chip has
entered sleep mode.
The code in prepare_ext{0,1}_wakeup did not enable IE, but did enable
SLP_SEL and SLP_IE. This meant that until CHIP_SLEEP went high, PAD_IE
was 0, hence the input from the pad read 0 even if external signal
was 1. CHIP_SLEEP went high on the 2nd cycle of sleep. So when
RTC_CNTL_MIN_SLP_VAL was set to 2, the input signal from the pad was
latched as 0 at the moment when CHIP_SLEEP went high, causing EXT0
wakeup with level 0 to trigger.
This commit changes the way PAD_IE is enabled: SLP_SEL and SLP_IE are
no longer used, and IE is set to 1. If EXT0 wakeup is used, RTC_IO is
not powered down, so IE signal stays 1 both before CHIP_SLEEP goes
high and after. If EXT1 wakeup is used, RTC_IO may be powered down.
However prepare_ext1_wakeup enables Hold on the pad, locking states
of all the control signals, including IE.
Closes https://github.com/espressif/esp-idf/issues/1931
Closes https://github.com/espressif/esp-idf/issues/2043
2018-06-12 08:23:26 -04:00
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
|
2020-11-26 03:56:13 -05:00
|
|
|
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
sleep: make sure input enable is set for EXT0/EXT1 wakeup
Since commit 94250e4, EXT0 wakeup mechanism, when wakeup level was set
to 0, started waking up chip immediately after entering deep sleep.
This failure was triggered in that commit by a change of
RTC_CNTL_MIN_SLP_VAL (i.e. minimum time in sleep mode until wakeup
can happen) from 128 cycles to 2 cycles.
The reason for this behaviour is related to the way input enable (IE)
signal going into an RTC pad is obtained:
PAD_IE = (SLP_SEL) ? SLP_IE & CHIP_SLEEP : IE,
where SLP_IE, SLP_SEL, and IE are bits of an RTC_IO register related
to the given pad. CHIP_SLEEP is the signal indicating that chip has
entered sleep mode.
The code in prepare_ext{0,1}_wakeup did not enable IE, but did enable
SLP_SEL and SLP_IE. This meant that until CHIP_SLEEP went high, PAD_IE
was 0, hence the input from the pad read 0 even if external signal
was 1. CHIP_SLEEP went high on the 2nd cycle of sleep. So when
RTC_CNTL_MIN_SLP_VAL was set to 2, the input signal from the pad was
latched as 0 at the moment when CHIP_SLEEP went high, causing EXT0
wakeup with level 0 to trigger.
This commit changes the way PAD_IE is enabled: SLP_SEL and SLP_IE are
no longer used, and IE is set to 1. If EXT0 wakeup is used, RTC_IO is
not powered down, so IE signal stays 1 both before CHIP_SLEEP goes
high and after. If EXT1 wakeup is used, RTC_IO may be powered down.
However prepare_ext1_wakeup enables Hold on the pad, locking states
of all the control signals, including IE.
Closes https://github.com/espressif/esp-idf/issues/1931
Closes https://github.com/espressif/esp-idf/issues/2043
2018-06-12 08:23:26 -04:00
|
|
|
// RTC_PERIPH will be powered down, so RTC_IO_ registers will
|
|
|
|
// loose their state. Lock pad configuration.
|
|
|
|
// Pullups/pulldowns also need to be disabled.
|
2020-04-27 02:01:30 -04:00
|
|
|
rtcio_hal_pullup_disable(rtc_pin);
|
|
|
|
rtcio_hal_pulldown_disable(rtc_pin);
|
2020-11-26 03:56:13 -05:00
|
|
|
#endif
|
2020-04-27 02:01:30 -04:00
|
|
|
rtcio_hal_hold_enable(rtc_pin);
|
2016-12-16 01:26:05 -05:00
|
|
|
}
|
|
|
|
// Keep track of pins which are processed to bail out early
|
|
|
|
rtc_gpio_mask &= ~BIT(rtc_pin);
|
2016-12-08 09:22:10 -05:00
|
|
|
}
|
2020-04-27 02:01:30 -04:00
|
|
|
|
2016-12-16 01:26:05 -05:00
|
|
|
// Clear state from previous wakeup
|
2020-04-27 02:01:30 -04:00
|
|
|
rtc_hal_ext1_clear_wakeup_pins();
|
|
|
|
// Set RTC IO pins and mode (any high, all low) to be used for wakeup
|
|
|
|
rtc_hal_ext1_set_wakeup_pins(s_config.ext1_rtc_gpio_mask, s_config.ext1_trigger_mode);
|
2016-12-08 09:22:10 -05:00
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
uint64_t esp_sleep_get_ext1_wakeup_status(void)
|
2016-12-08 09:22:10 -05:00
|
|
|
{
|
2017-04-21 00:32:50 -04:00
|
|
|
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
|
2016-12-08 09:22:10 -05:00
|
|
|
return 0;
|
|
|
|
}
|
2020-04-27 02:01:30 -04:00
|
|
|
uint32_t status = rtc_hal_ext1_get_wakeup_pins();
|
2016-12-08 09:22:10 -05:00
|
|
|
// Translate bit map of RTC IO numbers into the bit map of GPIO numbers
|
|
|
|
uint64_t gpio_mask = 0;
|
2016-12-16 01:26:05 -05:00
|
|
|
for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
|
2020-11-23 01:09:16 -05:00
|
|
|
if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
|
2016-12-08 09:22:10 -05:00
|
|
|
continue;
|
|
|
|
}
|
2019-07-25 11:11:31 -04:00
|
|
|
int rtc_pin = rtc_io_number_get(gpio);
|
2016-12-08 09:22:10 -05:00
|
|
|
if ((status & BIT(rtc_pin)) == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
2017-08-18 03:27:54 -04:00
|
|
|
gpio_mask |= 1ULL << gpio;
|
2016-12-08 09:22:10 -05:00
|
|
|
}
|
|
|
|
return gpio_mask;
|
|
|
|
}
|
2021-01-16 01:08:34 -05:00
|
|
|
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif // SOC_PM_SUPPORT_EXT_WAKEUP
|
2016-12-14 01:20:01 -05:00
|
|
|
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
|
|
|
|
uint64_t esp_sleep_get_gpio_wakeup_status(void)
|
|
|
|
{
|
|
|
|
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_GPIO) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rtc_hal_gpio_get_wakeup_pins();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void esp_deep_sleep_wakeup_prepare(void)
|
|
|
|
{
|
|
|
|
for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++) {
|
|
|
|
if (((1ULL << gpio_idx) & s_config.gpio_wakeup_mask) == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (s_config.gpio_trigger_mode & BIT(gpio_idx)) {
|
|
|
|
ESP_ERROR_CHECK(gpio_pullup_dis(gpio_idx));
|
|
|
|
ESP_ERROR_CHECK(gpio_pulldown_en(gpio_idx));
|
|
|
|
} else {
|
|
|
|
ESP_ERROR_CHECK(gpio_pullup_en(gpio_idx));
|
|
|
|
ESP_ERROR_CHECK(gpio_pulldown_dis(gpio_idx));
|
|
|
|
}
|
|
|
|
rtc_hal_gpio_set_wakeup_pins();
|
|
|
|
ESP_ERROR_CHECK(gpio_hold_en(gpio_idx));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepsleep_gpio_wake_up_mode_t mode)
|
|
|
|
{
|
|
|
|
if (mode > ESP_GPIO_WAKEUP_GPIO_HIGH) {
|
|
|
|
ESP_LOGE(TAG, "invalid mode");
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
gpio_int_type_t intr_type = ((mode == ESP_GPIO_WAKEUP_GPIO_LOW) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL);
|
|
|
|
esp_err_t err = ESP_OK;
|
|
|
|
for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++, gpio_pin_mask >>= 1) {
|
|
|
|
if ((gpio_pin_mask & 1) == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (!esp_sleep_is_valid_wakeup_gpio(gpio_idx)) {
|
|
|
|
ESP_LOGE(TAG, "invalid mask, please ensure gpio number is no more than 5");
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
err = gpio_deep_sleep_wakeup_enable(gpio_idx, intr_type);
|
|
|
|
|
|
|
|
s_config.gpio_wakeup_mask |= BIT(gpio_idx);
|
|
|
|
if (mode == ESP_GPIO_WAKEUP_GPIO_HIGH) {
|
|
|
|
s_config.gpio_trigger_mode |= (mode << gpio_idx);
|
|
|
|
} else {
|
|
|
|
s_config.gpio_trigger_mode &= ~(mode << gpio_idx);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
|
|
|
|
rtc_hal_gpio_clear_wakeup_pins();
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
esp_err_t esp_sleep_enable_gpio_wakeup(void)
|
2018-08-13 20:42:03 -04:00
|
|
|
{
|
2020-11-26 03:56:13 -05:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2018-08-13 20:42:03 -04:00
|
|
|
if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
|
|
|
|
ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2020-11-26 03:56:13 -05:00
|
|
|
#endif
|
2018-08-13 20:42:03 -04:00
|
|
|
s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t esp_sleep_enable_uart_wakeup(int uart_num)
|
|
|
|
{
|
|
|
|
if (uart_num == UART_NUM_0) {
|
|
|
|
s_config.wakeup_triggers |= RTC_UART0_TRIG_EN;
|
|
|
|
} else if (uart_num == UART_NUM_1) {
|
|
|
|
s_config.wakeup_triggers |= RTC_UART1_TRIG_EN;
|
|
|
|
} else {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2020-04-23 00:39:07 -04:00
|
|
|
esp_err_t esp_sleep_enable_wifi_wakeup(void)
|
|
|
|
{
|
2021-01-12 06:10:21 -05:00
|
|
|
#if SOC_PM_SUPPORT_WIFI_WAKEUP
|
2020-04-23 00:39:07 -04:00
|
|
|
s_config.wakeup_triggers |= RTC_WIFI_TRIG_EN;
|
|
|
|
return ESP_OK;
|
2021-01-12 06:10:21 -05:00
|
|
|
#else
|
|
|
|
return ESP_ERR_NOT_SUPPORTED;
|
2020-04-23 00:39:07 -04:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
|
2017-01-27 10:48:00 -05:00
|
|
|
{
|
2018-09-04 00:56:47 -04:00
|
|
|
if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET && !s_light_sleep_wakeup) {
|
2017-04-21 00:32:50 -04:00
|
|
|
return ESP_SLEEP_WAKEUP_UNDEFINED;
|
2017-01-27 10:48:00 -05:00
|
|
|
}
|
|
|
|
|
2020-04-23 00:39:07 -04:00
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
2017-01-27 10:48:00 -05:00
|
|
|
uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
2021-01-12 06:10:21 -05:00
|
|
|
#else
|
2020-04-23 00:39:07 -04:00
|
|
|
uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
|
|
|
#endif
|
|
|
|
|
2021-01-12 06:10:21 -05:00
|
|
|
if (wakeup_cause & RTC_TIMER_TRIG_EN) {
|
|
|
|
return ESP_SLEEP_WAKEUP_TIMER;
|
|
|
|
} else if (wakeup_cause & RTC_GPIO_TRIG_EN) {
|
|
|
|
return ESP_SLEEP_WAKEUP_GPIO;
|
|
|
|
} else if (wakeup_cause & (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN)) {
|
|
|
|
return ESP_SLEEP_WAKEUP_UART;
|
|
|
|
#if SOC_PM_SUPPORT_EXT_WAKEUP
|
|
|
|
} else if (wakeup_cause & RTC_EXT0_TRIG_EN) {
|
2017-04-21 00:32:50 -04:00
|
|
|
return ESP_SLEEP_WAKEUP_EXT0;
|
2017-04-11 03:44:43 -04:00
|
|
|
} else if (wakeup_cause & RTC_EXT1_TRIG_EN) {
|
2017-04-21 00:32:50 -04:00
|
|
|
return ESP_SLEEP_WAKEUP_EXT1;
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif
|
|
|
|
#if SOC_TOUCH_PAD_WAKE_SUPPORTED
|
2017-04-11 03:44:43 -04:00
|
|
|
} else if (wakeup_cause & RTC_TOUCH_TRIG_EN) {
|
2017-04-21 00:32:50 -04:00
|
|
|
return ESP_SLEEP_WAKEUP_TOUCHPAD;
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif
|
2020-11-26 03:56:13 -05:00
|
|
|
#if SOC_ULP_SUPPORTED
|
2017-04-11 03:44:43 -04:00
|
|
|
} else if (wakeup_cause & RTC_ULP_TRIG_EN) {
|
2017-04-21 00:32:50 -04:00
|
|
|
return ESP_SLEEP_WAKEUP_ULP;
|
2020-11-26 03:56:13 -05:00
|
|
|
#endif
|
2021-01-12 06:10:21 -05:00
|
|
|
#if SOC_PM_SUPPORT_WIFI_WAKEUP
|
2020-04-23 00:39:07 -04:00
|
|
|
} else if (wakeup_cause & RTC_WIFI_TRIG_EN) {
|
|
|
|
return ESP_SLEEP_WAKEUP_WIFI;
|
2021-01-12 06:10:21 -05:00
|
|
|
#endif
|
|
|
|
#if SOC_PM_SUPPORT_BT_WAKEUP
|
|
|
|
} else if (wakeup_cause & RTC_BT_TRIG_EN) {
|
|
|
|
return ESP_SLEEP_WAKEUP_BT;
|
|
|
|
#endif
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
2020-04-23 00:39:07 -04:00
|
|
|
} else if (wakeup_cause & RTC_COCPU_TRIG_EN) {
|
|
|
|
return ESP_SLEEP_WAKEUP_ULP;
|
|
|
|
} else if (wakeup_cause & RTC_COCPU_TRAP_TRIG_EN) {
|
|
|
|
return ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG;
|
|
|
|
#endif
|
2017-01-27 10:48:00 -05:00
|
|
|
} else {
|
2017-04-21 00:32:50 -04:00
|
|
|
return ESP_SLEEP_WAKEUP_UNDEFINED;
|
2017-01-27 10:48:00 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-04-21 00:32:50 -04:00
|
|
|
esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
|
|
|
|
esp_sleep_pd_option_t option)
|
2016-12-14 01:20:01 -05:00
|
|
|
{
|
|
|
|
if (domain >= ESP_PD_DOMAIN_MAX || option > ESP_PD_OPTION_AUTO) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2016-12-16 01:26:05 -05:00
|
|
|
s_config.pd_options[domain] = option;
|
2016-12-14 01:20:01 -05:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
static uint32_t get_power_down_flags(void)
|
2016-12-14 01:20:01 -05:00
|
|
|
{
|
|
|
|
// Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.
|
|
|
|
|
2017-01-11 04:23:23 -05:00
|
|
|
// RTC_SLOW_MEM is needed for the ULP, so keep RTC_SLOW_MEM powered up if ULP
|
|
|
|
// is used and RTC_SLOW_MEM is Auto.
|
|
|
|
// If there is any data placed into .rtc.data or .rtc.bss segments, and
|
|
|
|
// RTC_SLOW_MEM is Auto, keep it powered up as well.
|
|
|
|
|
2020-11-26 03:56:13 -05:00
|
|
|
#if SOC_RTC_SLOW_MEM_SUPPORTED && SOC_ULP_SUPPORTED
|
2020-04-23 00:39:07 -04:00
|
|
|
// Labels are defined in the linker script
|
2018-09-29 02:01:35 -04:00
|
|
|
extern int _rtc_slow_length;
|
2017-01-11 04:23:23 -05:00
|
|
|
|
2018-06-06 07:50:28 -04:00
|
|
|
if ((s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] == ESP_PD_OPTION_AUTO) &&
|
2018-09-29 02:01:35 -04:00
|
|
|
((size_t) &_rtc_slow_length > 0 ||
|
2018-09-06 06:31:17 -04:00
|
|
|
(s_config.wakeup_triggers & RTC_ULP_TRIG_EN))) {
|
2017-01-11 04:23:23 -05:00
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] = ESP_PD_OPTION_ON;
|
2016-12-14 01:20:01 -05:00
|
|
|
}
|
2020-11-26 03:56:13 -05:00
|
|
|
#endif
|
2016-12-14 01:20:01 -05:00
|
|
|
|
2020-12-21 00:26:00 -05:00
|
|
|
#if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
2020-12-10 01:45:41 -05:00
|
|
|
/* RTC_FAST_MEM is needed for deep sleep stub.
|
|
|
|
If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub can run.
|
|
|
|
In the new chip revision, deep sleep stub will be optional, and this can be changed. */
|
2016-12-16 01:26:05 -05:00
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO) {
|
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
|
2016-12-14 01:20:01 -05:00
|
|
|
}
|
2020-12-10 01:45:41 -05:00
|
|
|
#else
|
|
|
|
/* If RTC_FAST_MEM is used for heap, force RTC_FAST_MEM to be powered on. */
|
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
|
|
|
|
#endif
|
2016-12-14 01:20:01 -05:00
|
|
|
|
2018-08-13 20:42:03 -04:00
|
|
|
// RTC_PERIPH is needed for EXT0 wakeup and GPIO wakeup.
|
|
|
|
// If RTC_PERIPH is auto, and EXT0/GPIO aren't enabled, power down RTC_PERIPH.
|
2016-12-16 01:26:05 -05:00
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) {
|
2020-12-29 02:39:52 -05:00
|
|
|
#if SOC_TOUCH_PAD_WAKE_SUPPORTED
|
2020-11-26 03:56:13 -05:00
|
|
|
uint32_t wakeup_source = RTC_TOUCH_TRIG_EN;
|
|
|
|
#if SOC_ULP_SUPPORTED
|
|
|
|
wakeup_source |= RTC_ULP_TRIG_EN;
|
|
|
|
#endif
|
2018-08-13 20:42:03 -04:00
|
|
|
if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN)) {
|
2016-12-16 01:26:05 -05:00
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
|
2020-11-26 03:56:13 -05:00
|
|
|
} else if (s_config.wakeup_triggers & wakeup_source) {
|
2017-01-27 10:36:52 -05:00
|
|
|
// In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH
|
|
|
|
// prevents ULP timer and touch FSMs from working correctly.
|
2017-01-24 02:53:59 -05:00
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
|
2016-12-14 01:20:01 -05:00
|
|
|
}
|
2020-12-29 02:39:52 -05:00
|
|
|
#else
|
|
|
|
if (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN) {
|
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
|
|
|
|
} else {
|
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
|
|
|
|
}
|
|
|
|
#endif // SOC_TOUCH_PAD_WAKE_SUPPORTED
|
2016-12-14 01:20:01 -05:00
|
|
|
}
|
|
|
|
|
2021-01-20 09:21:51 -05:00
|
|
|
#if SOC_PM_SUPPORT_CPU_PD
|
|
|
|
if (s_config.cpu_pd_mem == NULL) {
|
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_CPU] != ESP_PD_OPTION_ON) {
|
2020-12-24 08:02:32 -05:00
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-04-04 03:05:50 -04:00
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) {
|
|
|
|
s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF;
|
|
|
|
}
|
|
|
|
|
2016-12-16 01:26:05 -05:00
|
|
|
const char* option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
|
2020-11-26 03:56:13 -05:00
|
|
|
ESP_LOGD(TAG, "RTC_PERIPH: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]]);
|
|
|
|
#if SOC_RTC_SLOW_MEM_SUPPORTED
|
|
|
|
ESP_LOGD(TAG, "RTC_SLOW_MEM: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]]);
|
|
|
|
#endif
|
|
|
|
ESP_LOGD(TAG, "RTC_FAST_MEM: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]);
|
2016-12-14 01:20:01 -05:00
|
|
|
|
|
|
|
// Prepare flags based on the selected options
|
2017-04-21 00:32:50 -04:00
|
|
|
uint32_t pd_flags = 0;
|
2016-12-16 01:26:05 -05:00
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) {
|
2017-04-11 03:44:43 -04:00
|
|
|
pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM;
|
2016-12-14 01:20:01 -05:00
|
|
|
}
|
2020-11-26 03:56:13 -05:00
|
|
|
#if SOC_RTC_SLOW_MEM_SUPPORTED
|
2016-12-16 01:26:05 -05:00
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) {
|
2017-04-11 03:44:43 -04:00
|
|
|
pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM;
|
2016-12-14 01:20:01 -05:00
|
|
|
}
|
2020-11-26 03:56:13 -05:00
|
|
|
#endif
|
2016-12-16 01:26:05 -05:00
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
|
2017-04-11 03:44:43 -04:00
|
|
|
pd_flags |= RTC_SLEEP_PD_RTC_PERIPH;
|
2016-12-14 01:20:01 -05:00
|
|
|
}
|
2020-04-23 00:39:07 -04:00
|
|
|
|
2020-12-24 08:02:32 -05:00
|
|
|
#if SOC_PM_SUPPORT_CPU_PD
|
|
|
|
if (s_config.pd_options[ESP_PD_DOMAIN_CPU] != ESP_PD_OPTION_ON) {
|
|
|
|
pd_flags |= RTC_SLEEP_PD_CPU;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2020-04-23 00:39:07 -04:00
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
2020-05-10 04:18:50 -04:00
|
|
|
pd_flags |= RTC_SLEEP_PD_XTAL;
|
|
|
|
#endif
|
2018-12-22 01:19:46 -05:00
|
|
|
|
2020-05-10 04:18:50 -04:00
|
|
|
#if ((defined CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) && (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT))
|
2018-12-22 01:19:46 -05:00
|
|
|
if ((s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) == 0) {
|
|
|
|
// If enabled EXT1 only and enable the additional current by touch, should be keep RTC_PERIPH power on.
|
2020-05-10 04:18:50 -04:00
|
|
|
pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
|
2018-12-22 01:19:46 -05:00
|
|
|
}
|
2020-04-23 00:39:07 -04:00
|
|
|
#endif
|
|
|
|
|
2016-12-14 01:20:01 -05:00
|
|
|
return pd_flags;
|
|
|
|
}
|
2018-09-04 04:03:18 -04:00
|
|
|
|
|
|
|
void esp_deep_sleep_disable_rom_logging(void)
|
|
|
|
{
|
2020-04-15 04:46:10 -04:00
|
|
|
esp_rom_disable_logging();
|
2018-09-04 04:03:18 -04:00
|
|
|
}
|