2021-08-05 10:30:10 -04:00
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2020-01-21 17:20:34 -05:00
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2020-11-05 23:00:07 -05:00
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#pragma once
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2020-01-21 17:20:34 -05:00
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#include <stdint.h>
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#include <stdbool.h>
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2021-12-13 23:38:15 -05:00
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#include "esp_cpu.h"
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2021-06-18 02:51:11 -04:00
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#include "soc/soc_memory_types.h"
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2020-11-05 23:00:07 -05:00
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#if __XTENSA__
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2020-01-21 17:20:34 -05:00
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#include "xtensa/xtruntime.h"
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2020-11-05 23:00:07 -05:00
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#endif
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2020-01-21 17:20:34 -05:00
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2020-09-30 03:24:04 -04:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2020-01-21 17:20:34 -05:00
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static inline void __attribute__((always_inline)) compare_and_set_native(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
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{
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2020-11-10 02:40:01 -05:00
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#if (XCHAL_HAVE_S32C1I > 0)
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2020-01-21 17:20:34 -05:00
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__asm__ __volatile__ (
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"WSR %2,SCOMPARE1 \n"
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"S32C1I %0, %1, 0 \n"
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:"=r"(*set)
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:"r"(addr), "r"(compare), "0"(*set)
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);
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#else
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2020-11-05 23:00:07 -05:00
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uint32_t old_value;
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#ifdef __XTENSA__
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2020-01-21 17:20:34 -05:00
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// No S32C1I, so do this by disabling and re-enabling interrupts (slower)
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2020-11-05 23:00:07 -05:00
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uint32_t intlevel;
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2020-01-21 17:20:34 -05:00
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__asm__ __volatile__ ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) "\n"
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: "=r"(intlevel));
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2020-11-05 23:00:07 -05:00
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#else
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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#endif
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2020-01-21 17:20:34 -05:00
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old_value = *addr;
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if (old_value == compare) {
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*addr = *set;
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}
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2020-11-05 23:00:07 -05:00
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#ifdef __XTENSA__
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2020-01-21 17:20:34 -05:00
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__asm__ __volatile__ ("memw \n"
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"wsr %0, ps\n"
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:: "r"(intlevel));
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2020-11-05 23:00:07 -05:00
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#else
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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#endif
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2020-01-21 17:20:34 -05:00
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*set = old_value;
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#endif
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}
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void compare_and_set_extram(volatile uint32_t *addr, uint32_t compare, uint32_t *set);
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2020-09-30 03:24:04 -04:00
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#ifdef __cplusplus
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}
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#endif
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