2021-09-30 03:12:55 -04:00
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/*
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* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2018-04-03 03:37:28 -04:00
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#include "esp_coexist.h"
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2019-02-20 08:01:27 -05:00
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#include "esp_coexist_internal.h"
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2018-04-03 03:37:28 -04:00
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2021-01-18 02:55:14 -05:00
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#if CONFIG_EXTERNAL_COEX_ENABLE
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2022-03-14 23:55:37 -04:00
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#include "esp_log.h"
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2021-01-18 02:55:14 -05:00
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#include "driver/gpio.h"
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#include "esp_rom_gpio.h"
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#include "hal/gpio_hal.h"
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#include "hal/gpio_types.h"
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#include "soc/gpio_periph.h"
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2022-03-14 23:55:37 -04:00
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#include "soc/gpio_struct.h"
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2021-01-18 02:55:14 -05:00
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#endif
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2018-04-03 03:37:28 -04:00
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const char *esp_coex_version_get(void)
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{
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return coex_version_get();
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}
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esp_err_t esp_coex_preference_set(esp_coex_prefer_t prefer)
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{
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return coex_preference_set((coex_prefer_t)prefer);
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}
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2021-01-18 02:55:14 -05:00
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#if CONFIG_EXTERNAL_COEX_ENABLE
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#define GPIO_PIN_REG(a) (GPIO_PIN0_REG + a * 0x04)
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2022-03-14 23:55:37 -04:00
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#if SOC_EXTERNAL_COEX_ADVANCE
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static const char *TAG = "external_coex";
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external_coex_classification s_external_coex_partner[EXTERNAL_COEX_UNKNOWN_ROLE][EXTERN_COEX_WIRE_NUM] = {
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{ wire_1_leader_mode, wire_2_leader_mode, wire_3_leader_mode },
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{},
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{ wire_1_follower_mode, wire_2_follower_mode, wire_3_follower_mode },
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};
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static esp_external_coex_advance_t g_external_coex_params = { EXTERNAL_COEX_LEADER_ROLE, 0, true };
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esp_external_coex_follower_pti_t g_external_coex_follower_pti_val = { 0, 0 };
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esp_err_t esp_external_coex_set_work_mode(esp_extern_coex_work_mode_t work_mode)
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{
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g_external_coex_params.work_mode = work_mode;
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if(EXTERNAL_COEX_FOLLOWER_ROLE == work_mode) {
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g_external_coex_follower_pti_val.pti_val1 = 8;
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g_external_coex_follower_pti_val.pti_val2 = 13;
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}
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return ESP_OK;
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}
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esp_err_t esp_external_coex_set_grant_delay(uint8_t delay_us)
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{
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g_external_coex_params.delay_us = delay_us;
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return ESP_OK;
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}
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esp_err_t esp_external_coex_set_validate_high(bool is_high_valid)
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{
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g_external_coex_params.is_high_valid = is_high_valid;
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return ESP_OK;
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}
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bool is_legal_external_coex_gpio(external_coex_wire_t wire_type, esp_external_coex_gpio_set_t gpio_pin)
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{
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external_coex_classification external_coex_configure = s_external_coex_partner[g_external_coex_params.work_mode][wire_type];
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switch (external_coex_configure)
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{
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case wire_3_leader_mode:
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{
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if(gpio_pin.in_pin0 == gpio_pin.in_pin1) {
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return false;
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}
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if(gpio_pin.in_pin0 == gpio_pin.out_pin0) {
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return false;
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}
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if(gpio_pin.in_pin1 == gpio_pin.out_pin0) {
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return false;
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}
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if(gpio_pin.in_pin0 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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if(gpio_pin.in_pin1 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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if(gpio_pin.out_pin0 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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return true;
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}
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case wire_3_follower_mode:
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{
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if(gpio_pin.in_pin0 == gpio_pin.out_pin0) {
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return false;
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}
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if(gpio_pin.in_pin0 == gpio_pin.out_pin1) {
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return false;
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}
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if(gpio_pin.out_pin0 == gpio_pin.out_pin1) {
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return false;
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}
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if(gpio_pin.in_pin0 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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if(gpio_pin.out_pin1 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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if(gpio_pin.out_pin0 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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return true;
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}
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case wire_2_leader_mode:
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case wire_2_follower_mode:
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{
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if(gpio_pin.in_pin0 == gpio_pin.out_pin0) {
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return false;
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}
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if(gpio_pin.in_pin0 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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if(gpio_pin.out_pin0 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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return true;
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}
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case wire_1_leader_mode:
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{
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if(gpio_pin.in_pin0 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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return true;
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}
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case wire_1_follower_mode:
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{
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if(gpio_pin.out_pin0 >= SOC_GPIO_PIN_COUNT) {
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return false;
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}
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return true;
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}
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default:
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return false;
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}
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}
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esp_err_t esp_external_coex_leader_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t in_pin0, uint32_t in_pin1, uint32_t out_pin0)
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{
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esp_external_coex_set_work_mode(EXTERNAL_COEX_LEADER_ROLE);
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esp_external_coex_gpio_set_t gpio_pin;
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switch (wire_type) {
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case EXTERN_COEX_WIRE_3:
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{
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gpio_pin.in_pin0 = in_pin0;
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gpio_pin.in_pin1 = in_pin1;
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gpio_pin.out_pin0 = out_pin0;
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break;
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}
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case EXTERN_COEX_WIRE_2:
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{
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gpio_pin.in_pin0 = in_pin0;
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gpio_pin.out_pin0 = out_pin0;
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break;
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}
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case EXTERN_COEX_WIRE_1:
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{
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gpio_pin.in_pin0 = in_pin0;
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break;
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}
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default:
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{
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gpio_pin.in_pin0 = in_pin0;
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gpio_pin.in_pin1 = in_pin1;
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gpio_pin.out_pin0 = out_pin0;
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break;
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}
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}
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return esp_enable_extern_coex_gpio_pin(wire_type, gpio_pin);
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}
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esp_err_t esp_external_coex_follower_role_set_gpio_pin(external_coex_wire_t wire_type, uint32_t in_pin0, uint32_t out_pin0, uint32_t out_pin1)
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{
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esp_external_coex_set_work_mode(EXTERNAL_COEX_FOLLOWER_ROLE);
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esp_external_coex_gpio_set_t gpio_pin;
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switch (wire_type) {
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case EXTERN_COEX_WIRE_3:
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{
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gpio_pin.in_pin0 = in_pin0;
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gpio_pin.out_pin0 = out_pin0;
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gpio_pin.out_pin1 = out_pin1;
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break;
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}
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case EXTERN_COEX_WIRE_2:
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{
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gpio_pin.in_pin0 = in_pin0;
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gpio_pin.out_pin0 = out_pin0;
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break;
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}
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case EXTERN_COEX_WIRE_1:
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{
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gpio_pin.out_pin0 = out_pin0;
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break;
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}
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default:
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{
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gpio_pin.in_pin0 = in_pin0;
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gpio_pin.out_pin0 = out_pin0;
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gpio_pin.out_pin1 = out_pin1;
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break;
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}
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}
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return esp_enable_extern_coex_gpio_pin(wire_type, gpio_pin);
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}
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#endif
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2021-01-18 02:55:14 -05:00
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esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_external_coex_gpio_set_t gpio_pin)
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{
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2022-03-14 23:55:37 -04:00
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#if SOC_EXTERNAL_COEX_ADVANCE
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if(false == is_legal_external_coex_gpio(wire_type, gpio_pin))
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{
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ESP_LOGE(TAG, "Configure external coex with unexpected gpio pin!!!\n");
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return ESP_ERR_INVALID_ARG;
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}
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phy_coex_force_rx_ant();
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esp_coex_external_params(g_external_coex_params, g_external_coex_follower_pti_val.pti_val1,
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g_external_coex_follower_pti_val.pti_val2);
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#endif
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2021-01-18 02:55:14 -05:00
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switch (wire_type)
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{
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case EXTERN_COEX_WIRE_3:
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{
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2022-03-14 23:55:37 -04:00
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#if SOC_EXTERNAL_COEX_ADVANCE
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if(EXTERNAL_COEX_LEADER_ROLE == g_external_coex_params.work_mode) {
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#endif
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2021-01-18 02:55:14 -05:00
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/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX:GPIO_BT_ACTIVE_IDX*/
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
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2022-03-14 23:55:37 -04:00
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#if SOC_EXTERNAL_COEX_ADVANCE
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esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
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#else
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2021-01-18 02:55:14 -05:00
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esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
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2022-03-14 23:55:37 -04:00
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#endif
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2021-01-18 02:55:14 -05:00
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin1], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_pin.in_pin1, GPIO_MODE_INPUT);
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2022-03-14 23:55:37 -04:00
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#if SOC_EXTERNAL_COEX_ADVANCE
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esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, EXTERN_PRIORITY_I_IDX, false);
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#else
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2021-01-18 02:55:14 -05:00
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esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, GPIO_BT_PRIORITY_IDX, false);
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2022-03-14 23:55:37 -04:00
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#endif
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2021-01-18 02:55:14 -05:00
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/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
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REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
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2022-03-14 23:55:37 -04:00
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#if SOC_EXTERNAL_COEX_ADVANCE
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esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
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#else
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2021-01-18 02:55:14 -05:00
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esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, GPIO_WLAN_ACTIVE_IDX, false, false);
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#endif
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2021-01-18 02:55:14 -05:00
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REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
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REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
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REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC1_BYPASS, 2);
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REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC2_BYPASS, 2);
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2022-03-14 23:55:37 -04:00
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#if SOC_EXTERNAL_COEX_ADVANCE
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}
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else if(EXTERNAL_COEX_FOLLOWER_ROLE == g_external_coex_params.work_mode) {
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/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX:GPIO_BT_ACTIVE_IDX*/
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
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2021-01-18 02:55:14 -05:00
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2022-03-14 23:55:37 -04:00
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esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
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/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
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REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
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esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin1], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_pin.out_pin1, GPIO_MODE_OUTPUT);
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REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin1));
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esp_rom_gpio_connect_out_signal(gpio_pin.out_pin1, EXTERN_PRIORITY_O_IDX, false, false);
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REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
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REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
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}
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#else
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#endif
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2021-01-18 02:55:14 -05:00
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int ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
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if (ESP_OK != ret) {
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return ESP_FAIL;
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}
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break;
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}
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case EXTERN_COEX_WIRE_2:
|
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{
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/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX:GPIO_BT_ACTIVE_IDX*/
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
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gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
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2022-03-14 23:55:37 -04:00
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|
#if SOC_EXTERNAL_COEX_ADVANCE
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esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
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#else
|
2021-01-18 02:55:14 -05:00
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esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
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2022-03-14 23:55:37 -04:00
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#endif
|
2021-01-18 02:55:14 -05:00
|
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|
|
|
|
/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
|
|
|
|
|
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
|
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|
|
|
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
|
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|
|
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
|
2022-03-14 23:55:37 -04:00
|
|
|
|
|
|
|
|
|
#if SOC_EXTERNAL_COEX_ADVANCE
|
|
|
|
|
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
|
|
|
|
|
#else
|
2021-01-18 02:55:14 -05:00
|
|
|
|
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, GPIO_WLAN_ACTIVE_IDX, false, false);
|
2022-03-14 23:55:37 -04:00
|
|
|
|
#endif
|
2021-01-18 02:55:14 -05:00
|
|
|
|
|
|
|
|
|
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
|
|
|
|
|
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
|
|
|
|
|
|
|
|
|
|
int ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID);
|
|
|
|
|
if (ESP_OK != ret) {
|
|
|
|
|
return ESP_FAIL;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case EXTERN_COEX_WIRE_1:
|
|
|
|
|
{
|
2022-03-14 23:55:37 -04:00
|
|
|
|
#if SOC_EXTERNAL_COEX_ADVANCE
|
|
|
|
|
if(EXTERNAL_COEX_LEADER_ROLE == g_external_coex_params.work_mode) {
|
|
|
|
|
#endif
|
2021-01-18 02:55:14 -05:00
|
|
|
|
/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX:GPIO_BT_ACTIVE_IDX*/
|
|
|
|
|
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
|
|
|
|
|
gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
|
2022-03-14 23:55:37 -04:00
|
|
|
|
|
|
|
|
|
#if SOC_EXTERNAL_COEX_ADVANCE
|
|
|
|
|
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, EXTERN_ACTIVE_I_IDX, false);
|
|
|
|
|
#else
|
2021-01-18 02:55:14 -05:00
|
|
|
|
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
|
2022-03-14 23:55:37 -04:00
|
|
|
|
#endif
|
2021-01-18 02:55:14 -05:00
|
|
|
|
|
|
|
|
|
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
|
|
|
|
|
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
|
2022-03-14 23:55:37 -04:00
|
|
|
|
#if SOC_EXTERNAL_COEX_ADVANCE
|
|
|
|
|
}
|
|
|
|
|
else if(EXTERNAL_COEX_FOLLOWER_ROLE == g_external_coex_params.work_mode) {
|
|
|
|
|
/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
|
|
|
|
|
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
|
|
|
|
|
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
|
|
|
|
|
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
|
|
|
|
|
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, EXTERN_ACTIVE_O_IDX, false, false);
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
#endif
|
2021-01-18 02:55:14 -05:00
|
|
|
|
|
|
|
|
|
int ret = esp_coex_external_set(EXTERN_COEX_PTI_HIGH, EXTERN_COEX_PTI_HIGH, EXTERN_COEX_PTI_HIGH);
|
|
|
|
|
if (ESP_OK != ret) {
|
|
|
|
|
return ESP_FAIL;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default:
|
|
|
|
|
{
|
|
|
|
|
return ESP_FAIL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return ESP_OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
esp_err_t esp_disable_extern_coex_gpio_pin()
|
|
|
|
|
{
|
2022-03-14 23:55:37 -04:00
|
|
|
|
#if SOC_EXTERNAL_COEX_ADVANCE
|
|
|
|
|
phy_coex_dismiss_rx_ant();
|
|
|
|
|
#endif
|
2021-01-18 02:55:14 -05:00
|
|
|
|
esp_coex_external_stop();
|
|
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
|
}
|
|
|
|
|
#endif/*External Coex*/
|