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56 lines
1.7 KiB
Markdown
56 lines
1.7 KiB
Markdown
# Change Log AD9833
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All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/)
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and this project adheres to [Semantic Versioning](http://semver.org/).
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## [0.3.0] - 2023-11-26
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- fix #10, explicit write control register fixes glitch.
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- rename **writeFreqRegister()** to **writeFrequencyRegister()**
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- refactor **writeFrequencyRegister()**
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- rename parameters reg => channel
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- catch define conflict __SPI_CLASS__
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- update readme.md
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- add experimental support for HLB write mode
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- **void writeFrequencyRegisterLSB(uint8_t reg, uint16_t LSB)**
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- **void writeFrequencyRegisterMSB(uint8_t reg, uint16_t MSB)**
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- update keywords.txt
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----
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## [0.2.0] - 2023-11-26
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- refactor constructor/begin interface - breaking changes.
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- minimize conditional code. -- create SPI_CLASS macro to solve it.
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- reordered parameters software SPI constructor.
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- update readme.md
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- update examples
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----
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## [0.1.2] - 2023-10-16
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- release for #5 set DIV2 flag
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- add examples switching phase and frequency channel
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- add example for multi device
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- minor edits
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## [0.1.1] - 2023-08-25
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- fix #2 - external FSYNC control
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- add **setPowerMode(uint8_t mode = 0)** // mode = 0..3
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- add **void hardwareReset()**
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- redefined **reset()** - see readme.md
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- first tests with hardware.
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- improved performance **setFrequency()**
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- fixed software SPI
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- made low level register access public for "expert users"
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- **void writeControlRegister(uint16_t value)**
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- **void writeFreqRegister(uint8_t reg, uint32_t freq)**
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- **void writePhaseRegister(uint8_t reg, uint16_t value)**
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- update readme.md
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- minor edits
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## [0.1.0] - 2023-08-25
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- initial version
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