mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
ea06b047c2
It will free libble.a & libbt all txt, data and bss segment memory. This memory is combined into one large memory and put into the heap pool.
339 lines
10 KiB
Plaintext
339 lines
10 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Default entry point */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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.iram0.text :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to start of IRAM */
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ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
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KEEP(*(.exception_vectors.text));
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. = ALIGN(4);
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_invalid_pc_placeholder = ABSOLUTE(.);
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/* Code marked as running out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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mapping[iram0_text]
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} > iram0_0_seg
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/**
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* This section is required to skip .iram0.text area because iram0_0_seg and
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* dram0_0_seg reflect the same address space on different buses.
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*/
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.dram0.dummy (NOLOAD):
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{
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. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
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} > dram0_0_seg
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/**
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* This section MUST be placed at the beginning of the DRAM0,
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* which will be released along with iram0_bt.text when Bluetooth is no longer in use
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*/
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.dram0.bt.data :
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{
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_data_start = ABSOLUTE(.);
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mapping[dram0_bt_data]
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. = ALIGN(8);
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} > dram0_0_seg
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.dram0.bt.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_bss_bt_start = ABSOLUTE(.);
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mapping[dram0_bt_bss]
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_bss_bt_end = ABSOLUTE(.);
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} > dram0_0_seg
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.dram0.data :
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{
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*(.gnu.linkonce.d.*)
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*(.data1)
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__global_pointer$ = . + 0x800;
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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mapping[dram0_data]
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_data_end = ABSOLUTE(.);
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. = ALIGN(4);
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} > dram0_0_seg
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/**
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* This section holds data that should not be initialized at power up.
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* The section located in Internal SRAM memory region. The macro _NOINIT
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* can be used as attribute to place data into this section.
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* See the "esp_attr.h" file for more information.
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*/
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.noinit (NOLOAD):
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{
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. = ALIGN(4);
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_noinit_start = ABSOLUTE(.);
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*(.noinit .noinit.*)
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. = ALIGN(4) ;
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_noinit_end = ABSOLUTE(.);
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} > dram0_0_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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mapping[dram0_bss]
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.share.mem)
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*(.gnu.linkonce.b.*)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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} > dram0_0_seg
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ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
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.flash.text :
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{
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_stext = .;
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_instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */
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_text_start = ABSOLUTE(.);
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mapping[flash_text]
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*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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/** CPU will try to prefetch up to 16 bytes of
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* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += _esp_flash_mmap_prefetch_pad_size;
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_text_end = ABSOLUTE(.);
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_instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */
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_etext = .;
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/**
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* Similar to _iram_start, this symbol goes here so it is
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* resolved by addr2line in preference to the first symbol in
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* the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} > default_code_seg
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/**
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* This dummy section represents the .flash.text section but in default_rodata_seg.
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* Thus, it must have its alignment and (at least) its size.
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*/
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.flash_rodata_dummy (NOLOAD):
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{
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_flash_rodata_dummy_start = .;
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/* Start at the same alignment constraint than .flash.text */
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. = ALIGN(ALIGNOF(.flash.text));
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/* Create an empty gap as big as .flash.text section */
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. = . + SIZEOF(.flash.text);
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/* Prepare the alignment of the section above. Few bytes (0x20) must be
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* added for the mapping header. */
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. = ALIGN(_esp_mmu_block_size) + 0x20;
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} > default_rodata_seg
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.flash.appdesc : ALIGN(0x10)
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{
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_rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */
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_rodata_start = ABSOLUTE(.);
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*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
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*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
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/* Create an empty gap within this section. Thanks to this, the end of this
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* section will match .flash.rodata's begin address. Thus, both sections
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* will be merged when creating the final bin image. */
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. = ALIGN(ALIGNOF(.flash.rodata));
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} >default_rodata_seg
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.flash.rodata : ALIGN(0x10)
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{
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_flash_rodata_start = ABSOLUTE(.);
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mapping[flash_rodata]
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table .gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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. = (. + 7) & ~ 3;
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/*
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* C++ constructor and destructor tables
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* Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.
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*
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* RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.
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* But the init_priority sections will be sorted for iteration in ascending order during startup.
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* The rest of the init_array sections is sorted for iteration in descending order during startup, however.
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* Hence a different section is generated for the init_priority functions which is iterated in
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* ascending order during startup. The corresponding code can be found in startup.c.
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*/
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__init_priority_array_start = ABSOLUTE(.);
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
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__init_priority_array_end = ABSOLUTE(.);
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__init_array_start = ABSOLUTE(.);
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
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__init_array_end = ABSOLUTE(.);
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KEEP (*crtbegin.*(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
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soc_reserved_memory_region_start = ABSOLUTE(.);
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KEEP (*(.reserved_memory_address))
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soc_reserved_memory_region_end = ABSOLUTE(.);
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/* System init functions registered via ESP_SYSTEM_INIT_FN */
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_esp_system_init_fn_array_start = ABSOLUTE(.);
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KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
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_esp_system_init_fn_array_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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. = ALIGN(4);
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_thread_local_start = ABSOLUTE(.);
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*(.tdata)
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*(.tdata.*)
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*(.tbss)
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*(.tbss.*)
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_thread_local_end = ABSOLUTE(.);
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. = ALIGN(ALIGNOF(.eh_frame));
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} > default_rodata_seg
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/* Keep this section shall be at least aligned on 4 */
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.eh_frame : ALIGN(8)
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{
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__eh_frame = ABSOLUTE(.);
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KEEP (*(.eh_frame))
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__eh_frame_end = ABSOLUTE(.);
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/* Guarantee that this section and the next one will be merged by making
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* them adjacent. */
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. = ALIGN(ALIGNOF(.eh_frame_hdr));
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} > default_rodata_seg
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/* To avoid any exception in C++ exception frame unwinding code, this section
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* shall be aligned on 8. */
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.eh_frame_hdr : ALIGN(8)
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{
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__eh_frame_hdr = ABSOLUTE(.);
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KEEP (*(.eh_frame_hdr))
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__eh_frame_hdr_end = ABSOLUTE(.);
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} > default_rodata_seg
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/*
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This section is a place where we dump all the rodata which aren't used at runtime,
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so as to avoid binary size increase
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*/
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.flash.rodata_noload (NOLOAD) :
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{
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/*
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This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address
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We don't need to include the noload rodata in this section
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*/
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_rodata_reserved_end = ABSOLUTE(.);
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. = ALIGN (4);
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mapping[rodata_noload]
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} > default_rodata_seg
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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/* ESP32-C2 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */
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. += _esp_memprot_prefetch_pad_size;
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. = ALIGN(_esp_memprot_align_size);
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/* iram_end_test section exists for use by memprot unit tests only */
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*(.iram_end_test)
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_iram_text_end = ABSOLUTE(.);
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} > iram0_0_seg
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.iram0.data :
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{
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. = ALIGN(16);
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_iram_data_start = ABSOLUTE(.);
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mapping[iram0_data]
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_iram_data_end = ABSOLUTE(.);
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} > iram0_0_seg
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.iram0.bss (NOLOAD) :
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{
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. = ALIGN(16);
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_iram_bss_start = ABSOLUTE(.);
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mapping[iram0_bss]
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_iram_bss_end = ABSOLUTE(.);
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} > iram0_0_seg
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/**
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* This section needs to be placed at the end of the IRAM0,
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* which will be released along with dram0_bt_data and dram0_bt_bss when Bluetooth is no longer in use
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*/
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.iram0.bt.text :
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{
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. = ALIGN(16);
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_iram_bt_text_start = ABSOLUTE(.);
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mapping[iram0_bt_text]
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. = ALIGN(16);
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_iram_end = ABSOLUTE(.);
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} > iram0_0_seg
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/* Marks the end of data, bss and possibly rodata */
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.dram0.heap_start (NOLOAD) :
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{
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. = ALIGN (16);
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_heap_start = ABSOLUTE(.);
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} > dram0_0_seg
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}
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ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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"IRAM0 segment data does not fit.")
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ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
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"DRAM segment data does not fit.")
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