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b72f987c5c
This commit adds support for ULP RISC-V for esp32s3. Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
6 lines
152 B
Plaintext
6 lines
152 B
Plaintext
CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240=y
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CONFIG_ESP32S3_ULP_COPROC_ENABLED=y
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CONFIG_ESP32S3_ULP_COPROC_RISCV=y
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CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=4096
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