mirror of
https://github.com/espressif/esp-idf.git
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264 lines
8.0 KiB
C
264 lines
8.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/pcr_reg.h"
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#include "soc/tee_reg.h"
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#include "soc/hp_apm_reg.h"
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#include "soc/hp_apm_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
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#define APM_LL_REGION_ADDR_START_REG(regn_num) (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num))
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#define APM_LL_REGION_ADDR_END_REG(regn_num) (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num))
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#define APM_LL_REGION_ADDR_ATTR_REG(regn_num) (HP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num))
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#define APM_LL_TEE_EXCP_STATUS_REG(sec_mode) (HP_APM_M0_STATUS_REG + 0x10 * (sec_mode))
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#define APM_LL_TEE_EXCP_CLR_REG(sec_mode) (HP_APM_M0_STATUS_CLR_REG + 0x10 * (sec_mode))
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#define APM_LL_TEE_EXCP_INFO0_REG(sec_mode) (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (sec_mode))
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#define APM_LL_HP_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1)))
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#define APM_LL_HP_SEC_MODE_REGION_ATTR_V 0x00000003U
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#define APM_LL_HP_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_HP_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
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#define APM_LL_HP_MAX_REGION_NUM 15
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#define APM_LL_MASTER_MAX 32
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/**
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* @brief APM Master ID
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*/
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typedef enum {
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APM_LL_MASTER_HPCORE = 0,
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APM_LL_MASTER_LPCORE = 1,
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APM_LL_MASTER_REGDMA = 2,
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APM_LL_MASTER_SDIOSLV = 3,
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APM_LL_MASTER_MODEM = 4,
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APM_LL_MASTER_MEM_MONITOR = 5,
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APM_LL_MASTER_TRACE = 6,
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APM_LL_MASTER_GDMA = 16, // The beginning of GDMA master ID
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APM_LL_MASTER_GDMA_SPI2 = 16,
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APM_LL_MASTER_GDMA_UHCI0 = 18,
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APM_LL_MASTER_GDMA_I2S0 = 19,
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APM_LL_MASTER_GDMA_AES = 22,
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APM_LL_MASTER_GDMA_SHA = 23,
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APM_LL_MASTER_GDMA_ADC = 24,
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APM_LL_MASTER_GDMA_PARLIO = 25,
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} apm_ll_master_id_t;
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/**
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* @brief APM Secure Mode
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*/
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typedef enum {
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APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */
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APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 (need to configure APM strategy for this mode) */
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APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 (need to configure APM strategy for this mode) */
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APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 (need to configure APM strategy for this mode) */
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} apm_ll_secure_mode_t;
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/**
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* @brief APM HP access path
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*/
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typedef enum {
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APM_LL_HP_ACCESS_PATH_M0 = 0x0,
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APM_LL_HP_ACCESS_PATH_M1 = 0x1,
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APM_LL_HP_ACCESS_PATH_M2 = 0x2,
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APM_LL_HP_ACCESS_PATH_M3 = 0x3,
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} apm_ll_hp_access_path_t;
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/**
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* @brief APM exception information
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*/
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typedef struct {
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uint8_t excp_id;
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apm_ll_secure_mode_t sec_mode;
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uint8_t excp_regn;
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uint8_t excp_mode;
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uint32_t excp_addr;
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} apm_hp_m_exception_info_t;
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/**
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* @brief Set secure mode
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*
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* @param master_id APM master ID
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* @param mode Secure mode
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*/
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static inline void apm_tee_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode)
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{
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REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode);
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}
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/**
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* @brief TEE controller clock auto gating enable
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*
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* @param enable Flag for HP clock auto gating enable/disable
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*/
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static inline void apm_tee_ll_clk_gating_enable(bool enable)
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{
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if (enable) {
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REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
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} else {
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REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
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}
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}
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/**
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* @brief enable/disable HP Region access permission filter
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*
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* @param regn_num Memory Region number
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* @param enable Flag for Region access filter enable/disable
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*/
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static inline void apm_hp_ll_region_filter_enable(uint32_t regn_num, bool enable)
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{
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if (enable) {
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REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num));
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} else {
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REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num));
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}
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}
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/**
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* @brief enable/disable HP access path(M[0:3])
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*
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* @param hp_m_path HP access path
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* @param enable Flag for HP M path filter enable/disable
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*/
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static inline void apm_hp_ll_m_filter_enable(apm_ll_hp_access_path_t hp_m_path, bool enable)
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{
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if (enable) {
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REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path));
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} else {
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REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path));
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}
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}
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/**
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* @brief HP Region start address configuration
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*
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* @param regn_num HP Region number to be configured
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* @param addr Region start address
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*/
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static inline void apm_hp_ll_set_region_start_address(uint32_t regn_num, uint32_t addr)
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{
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REG_WRITE(APM_LL_REGION_ADDR_START_REG(regn_num), addr);
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}
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/**
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* @brief HP Region end address configuration
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*
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* @param regn_num HP Region number to be configured
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* @param addr Region end address
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*/
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static inline void apm_hp_ll_set_region_end_address(uint32_t regn_num, uint32_t addr)
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{
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REG_WRITE(APM_LL_REGION_ADDR_END_REG(regn_num), addr);
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}
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/**
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* @brief HP Region pms attributes configuration
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*
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* @param regn_num Region number to be configured
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* @param sec_mode Secure mode of the Master
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* @param regn_pms XWR permissions for the given secure mode and Region number
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*/
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static inline void apm_hp_ll_sec_mode_region_attr_config(uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms)
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{
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uint32_t val = 0;
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val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(regn_num));
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val &= ~APM_LL_HP_SEC_MODE_REGION_ATTR_M(sec_mode);
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val |= APM_LL_HP_SEC_MODE_REGION_ATTR(sec_mode, regn_pms);
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REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(regn_num), val);
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}
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/**
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* @brief Get HP access path(M[0:3]) exception status
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*
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* @param hp_m_path HP access path
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*/
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static inline uint8_t apm_hp_ll_m_exception_status(apm_ll_hp_access_path_t hp_m_path)
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{
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return REG_READ(APM_LL_TEE_EXCP_STATUS_REG(hp_m_path));
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}
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/**
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* @brief Clear HP access path(M[0:3]) exception
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*
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* @param hp_m_path HP access path
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*/
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static inline void apm_hp_ll_m_exception_clear(apm_ll_hp_access_path_t hp_m_path)
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{
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REG_SET_BIT(APM_LL_TEE_EXCP_CLR_REG(hp_m_path), HP_APM_M0_REGION_STATUS_CLR);
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}
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/**
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* @brief Get HP access path(M[0:3]) exception information
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*
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* @param excp_info Exception related information like addr,
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* region, sec_mode and master id
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*/
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static inline void apm_hp_ll_get_m_exception_info(apm_hp_m_exception_info_t *excp_info)
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{
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excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_ID);
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excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_MODE);
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excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_REGION);
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excp_info->excp_addr = REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG);
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}
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/**
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* @brief Interrupt enable for access path(M[0:3])
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*
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* @param hp_m_path HP access path
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* @param enable Flag for access path interrupt enable/disable
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*/
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static inline void apm_hp_ll_m_interrupt_enable(apm_ll_hp_access_path_t hp_m_path, bool enable)
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{
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if (enable) {
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REG_SET_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path));
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} else {
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REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path));
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}
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}
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/**
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* @brief HP clock auto gating enable
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*
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* @param enable Flag for HP clock auto gating enable/disable
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*/
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static inline void apm_hp_ll_clk_gating_enable(bool enable)
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{
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if (enable) {
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REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN);
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} else {
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REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN);
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}
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}
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/**
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* @brief APM/TEE/HP System Reg reset event bypass enable
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*
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* Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset,
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* but also some reset events.
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* Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset.
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* Some reset events will be bypassed.
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*
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* @param enable Flag for event bypass enable/disable
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*/
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static inline void apm_hp_ll_reset_event_enable(bool enable)
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{
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if (enable) {
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REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
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} else {
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REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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