mirror of
https://github.com/espressif/esp-idf.git
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223 lines
8.0 KiB
C
223 lines
8.0 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** HUK_CLK_REG register
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* HUK Generator clock gate control register
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*/
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#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
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/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
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* Write 1 to force on register clock gate.
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*/
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#define HUK_CLK_EN (BIT(0))
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#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
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#define HUK_CLK_EN_V 0x00000001U
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#define HUK_CLK_EN_S 0
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/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
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* Write 1 to force on memory clock gate.
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*/
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#define HUK_MEM_CG_FORCE_ON (BIT(1))
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#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
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#define HUK_MEM_CG_FORCE_ON_V 0x00000001U
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#define HUK_MEM_CG_FORCE_ON_S 1
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/** HUK_INT_RAW_REG register
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* HUK Generator interrupt raw register, valid in level.
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*/
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#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
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/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the huk_prep_done_int interrupt
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*/
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#define HUK_PREP_DONE_INT_RAW (BIT(0))
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#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
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#define HUK_PREP_DONE_INT_RAW_V 0x00000001U
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#define HUK_PREP_DONE_INT_RAW_S 0
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/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status bit for the huk_proc_done_int interrupt
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*/
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#define HUK_PROC_DONE_INT_RAW (BIT(1))
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#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
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#define HUK_PROC_DONE_INT_RAW_V 0x00000001U
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#define HUK_PROC_DONE_INT_RAW_S 1
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/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status bit for the huk_post_done_int interrupt
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*/
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#define HUK_POST_DONE_INT_RAW (BIT(2))
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#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
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#define HUK_POST_DONE_INT_RAW_V 0x00000001U
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#define HUK_POST_DONE_INT_RAW_S 2
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/** HUK_INT_ST_REG register
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* HUK Generator interrupt status register.
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*/
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#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
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/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the huk_prep_done_int interrupt
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*/
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#define HUK_PREP_DONE_INT_ST (BIT(0))
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#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
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#define HUK_PREP_DONE_INT_ST_V 0x00000001U
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#define HUK_PREP_DONE_INT_ST_S 0
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/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
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* The masked interrupt status bit for the huk_proc_done_int interrupt
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*/
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#define HUK_PROC_DONE_INT_ST (BIT(1))
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#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
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#define HUK_PROC_DONE_INT_ST_V 0x00000001U
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#define HUK_PROC_DONE_INT_ST_S 1
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/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
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* The masked interrupt status bit for the huk_post_done_int interrupt
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*/
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#define HUK_POST_DONE_INT_ST (BIT(2))
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#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
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#define HUK_POST_DONE_INT_ST_V 0x00000001U
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#define HUK_POST_DONE_INT_ST_S 2
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/** HUK_INT_ENA_REG register
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* HUK Generator interrupt enable register.
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*/
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#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
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/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the huk_prep_done_int interrupt
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*/
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#define HUK_PREP_DONE_INT_ENA (BIT(0))
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#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
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#define HUK_PREP_DONE_INT_ENA_V 0x00000001U
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#define HUK_PREP_DONE_INT_ENA_S 0
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/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
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* The interrupt enable bit for the huk_proc_done_int interrupt
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*/
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#define HUK_PROC_DONE_INT_ENA (BIT(1))
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#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
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#define HUK_PROC_DONE_INT_ENA_V 0x00000001U
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#define HUK_PROC_DONE_INT_ENA_S 1
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/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
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* The interrupt enable bit for the huk_post_done_int interrupt
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*/
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#define HUK_POST_DONE_INT_ENA (BIT(2))
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#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
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#define HUK_POST_DONE_INT_ENA_V 0x00000001U
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#define HUK_POST_DONE_INT_ENA_S 2
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/** HUK_INT_CLR_REG register
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* HUK Generator interrupt clear register.
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*/
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#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
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/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the huk_prep_done_int interrupt
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*/
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#define HUK_PREP_DONE_INT_CLR (BIT(0))
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#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
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#define HUK_PREP_DONE_INT_CLR_V 0x00000001U
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#define HUK_PREP_DONE_INT_CLR_S 0
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/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
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* Set this bit to clear the huk_proc_done_int interrupt
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*/
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#define HUK_PROC_DONE_INT_CLR (BIT(1))
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#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
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#define HUK_PROC_DONE_INT_CLR_V 0x00000001U
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#define HUK_PROC_DONE_INT_CLR_S 1
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/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
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* Set this bit to clear the huk_post_done_int interrupt
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*/
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#define HUK_POST_DONE_INT_CLR (BIT(2))
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#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
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#define HUK_POST_DONE_INT_CLR_V 0x00000001U
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#define HUK_POST_DONE_INT_CLR_S 2
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/** HUK_CONF_REG register
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* HUK Generator configuration register
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*/
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#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
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/** HUK_MODE : R/W; bitpos: [0]; default: 0;
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* Set this field to choose the huk process. 1: process huk generate mode. 0: process
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* huk recovery mode.
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*/
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#define HUK_MODE (BIT(0))
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#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S)
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#define HUK_MODE_V 0x00000001U
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#define HUK_MODE_S 0
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/** HUK_START_REG register
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* HUK Generator control register
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*/
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#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
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/** HUK_START : WT; bitpos: [0]; default: 0;
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* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
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*/
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#define HUK_START (BIT(0))
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#define HUK_START_M (HUK_START_V << HUK_START_S)
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#define HUK_START_V 0x00000001U
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#define HUK_START_S 0
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/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
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* Write 1 to start HUK Generator at IDLE state.
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*/
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#define HUK_CONTINUE (BIT(1))
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#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S)
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#define HUK_CONTINUE_V 0x00000001U
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#define HUK_CONTINUE_S 1
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/** HUK_STATE_REG register
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* HUK Generator state register
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*/
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#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
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/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
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* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
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*/
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#define HUK_STATE 0x00000003U
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#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S)
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#define HUK_STATE_V 0x00000003U
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#define HUK_STATE_S 0
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/** HUK_STATUS_REG register
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* HUK Generator HUK status register
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*/
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#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
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/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
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* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
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* 2: HUK is generated but invalid. 3: reserved.
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*/
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#define HUK_STATUS 0x00000003U
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#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S)
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#define HUK_STATUS_V 0x00000003U
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#define HUK_STATUS_S 0
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/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
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* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
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* are in the PUF SRAM. 7: Error Level, HUK is invalid.
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*/
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#define HUK_RISK_LEVEL 0x00000007U
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#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
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#define HUK_RISK_LEVEL_V 0x00000007U
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#define HUK_RISK_LEVEL_S 2
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/** HUK_DATE_REG register
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* Version control register
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*/
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#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
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/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704;
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* HUK Generator version control register.
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*/
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#define HUK_DATE 0x0FFFFFFFU
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#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S)
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#define HUK_DATE_V 0x0FFFFFFFU
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#define HUK_DATE_S 0
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/** HUK_INFO_MEM register
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* The memory that stores HUK info.
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*/
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#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
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#define HUK_INFO_MEM_SIZE_BYTES 384
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#ifdef __cplusplus
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}
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#endif
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