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509 lines
15 KiB
C
509 lines
15 KiB
C
/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: PARL_IO RX Mode Configuration */
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/** Type of rx_mode_cfg register
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* Parallel RX Sampling mode configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:21;
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/** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
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* Configures rx external enable signal selection from IO PAD.
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*/
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uint32_t rx_ext_en_sel:4;
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/** rx_sw_en : R/W; bitpos: [25]; default: 0;
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* Set this bit to enable data sampling by software.
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*/
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uint32_t rx_sw_en:1;
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/** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
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* Set this bit to invert the external enable signal.
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*/
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uint32_t rx_ext_en_inv:1;
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/** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
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* Configures the rxd pulse sampling submode.
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* 4'd0: positive pulse start(data bit included) && positive pulse end(data bit
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* included)
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* 4'd1: positive pulse start(data bit included) && positive pulse end (data bit
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* excluded)
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* 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
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* included)
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* 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
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* excluded)
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* 4'd4: positive pulse start(data bit included) && length end
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* 4'd5: positive pulse start(data bit excluded) && length end
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*/
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uint32_t rx_pulse_submode_sel:3;
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/** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
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* Configures the rxd sampling mode.
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* 2'b00: external level enable mode
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* 2'b01: external pulse enable mode
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* 2'b10: internal software enable mode
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*/
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uint32_t rx_smp_mode_sel:2;
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};
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uint32_t val;
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} parl_io_rx_mode_cfg_reg_t;
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/** Group: PARL_IO RX Data Configuration */
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/** Type of rx_data_cfg register
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* Parallel RX data configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:9;
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/** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
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* Configures expected byte number of received data.
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*/
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uint32_t rx_bitlen:19;
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/** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
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* Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
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*/
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uint32_t rx_data_order_inv:1;
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/** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
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* Configures the rxd bus width.
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* 3'd0: bus width is 1.
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* 3'd1: bus width is 2.
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* 3'd2: bus width is 4.
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* 3'd3: bus width is 8.
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*/
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uint32_t rx_bus_wid_sel:3;
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};
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uint32_t val;
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} parl_io_rx_data_cfg_reg_t;
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/** Group: PARL_IO RX General Configuration */
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/** Type of rx_genrl_cfg register
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* Parallel RX general configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:12;
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/** rx_gating_en : R/W; bitpos: [12]; default: 0;
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* Set this bit to enable the clock gating of output rx clock.
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*/
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uint32_t rx_gating_en:1;
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/** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
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* Configures threshold of timeout counter.
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*/
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uint32_t rx_timeout_thres:16;
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/** rx_timeout_en : R/W; bitpos: [29]; default: 1;
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* Set this bit to enable timeout function to generate error eof.
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*/
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uint32_t rx_timeout_en:1;
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/** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
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* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
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* 1'b1: eof generated by external enable signal.
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*/
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uint32_t rx_eof_gen_sel:1;
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uint32_t reserved_31:1;
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};
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uint32_t val;
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} parl_io_rx_genrl_cfg_reg_t;
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/** Group: PARL_IO RX Start Configuration */
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/** Type of rx_start_cfg register
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* Parallel RX Start configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** rx_start : R/W; bitpos: [31]; default: 0;
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* Set this bit to start rx data sampling.
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*/
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uint32_t rx_start:1;
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};
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uint32_t val;
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} parl_io_rx_start_cfg_reg_t;
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/** Group: PARL_IO TX Data Configuration */
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/** Type of tx_data_cfg register
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* Parallel TX data configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:9;
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/** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
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* Configures expected byte number of sent data.
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*/
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uint32_t tx_bitlen:19;
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/** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
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* Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
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*/
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uint32_t tx_data_order_inv:1;
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/** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
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* Configures the txd bus width.
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* 3'd0: bus width is 1.
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* 3'd1: bus width is 2.
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* 3'd2: bus width is 4.
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* 3'd3: bus width is 8.
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*/
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uint32_t tx_bus_wid_sel:3;
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};
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uint32_t val;
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} parl_io_tx_data_cfg_reg_t;
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/** Group: PARL_IO TX Start Configuration */
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/** Type of tx_start_cfg register
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* Parallel TX Start configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** tx_start : R/W; bitpos: [31]; default: 0;
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* Set this bit to start tx data transmit.
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*/
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uint32_t tx_start:1;
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};
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uint32_t val;
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} parl_io_tx_start_cfg_reg_t;
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/** Group: PARL_IO TX General Configuration */
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/** Type of tx_genrl_cfg register
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* Parallel TX general configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:13;
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/** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
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* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
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* 1'b1: eof generated by DMA eof.
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*/
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uint32_t tx_eof_gen_sel:1;
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/** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
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* Configures bus value of transmitter in IDLE state.
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*/
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uint32_t tx_idle_value:16;
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/** tx_gating_en : R/W; bitpos: [30]; default: 0;
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* Set this bit to enable the clock gating of output tx clock.
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*/
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uint32_t tx_gating_en:1;
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/** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
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* Set this bit to enable the output of tx data valid signal.
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*/
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uint32_t tx_valid_output_en:1;
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};
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uint32_t val;
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} parl_io_tx_genrl_cfg_reg_t;
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/** Group: PARL_IO FIFO Configuration */
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/** Type of fifo_cfg register
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* Parallel IO FIFO configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:30;
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/** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
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* Set this bit to reset async fifo in tx module.
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*/
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uint32_t tx_fifo_srst:1;
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/** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
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* Set this bit to reset async fifo in rx module.
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*/
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uint32_t rx_fifo_srst:1;
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};
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uint32_t val;
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} parl_io_fifo_cfg_reg_t;
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/** Group: PARL_IO Register Update Configuration */
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/** Type of reg_update register
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* Parallel IO FIFO configuration register.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** rx_reg_update : WT; bitpos: [31]; default: 0;
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* Set this bit to update rx register configuration.
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*/
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uint32_t rx_reg_update:1;
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};
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uint32_t val;
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} parl_io_reg_update_reg_t;
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/** Group: PARL_IO Status */
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/** Type of st register
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* Parallel IO module status register0.
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** tx_ready : RO; bitpos: [31]; default: 0;
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* Represents the status that tx is ready to transmit.
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*/
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uint32_t tx_ready:1;
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};
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uint32_t val;
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} parl_io_st_reg_t;
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/** Group: PARL_IO Interrupt Configuration and Status */
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/** Type of int_ena register
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* Parallel IO interrupt enable singal configuration register.
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*/
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typedef union {
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struct {
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/** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
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* Set this bit to enable TX_FIFO_REMPTY_INT.
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*/
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uint32_t tx_fifo_rempty_int_ena:1;
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/** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
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* Set this bit to enable RX_FIFO_WOVF_INT.
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*/
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uint32_t rx_fifo_wovf_int_ena:1;
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/** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
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* Set this bit to enable TX_EOF_INT.
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*/
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uint32_t tx_eof_int_ena:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} parl_io_int_ena_reg_t;
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/** Type of int_raw register
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* Parallel IO interrupt raw singal status register.
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*/
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typedef union {
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struct {
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/** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status of TX_FIFO_REMPTY_INT.
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*/
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uint32_t tx_fifo_rempty_int_raw:1;
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/** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status of RX_FIFO_WOVF_INT.
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*/
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uint32_t rx_fifo_wovf_int_raw:1;
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/** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status of TX_EOF_INT.
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*/
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uint32_t tx_eof_int_raw:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} parl_io_int_raw_reg_t;
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/** Type of int_st register
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* Parallel IO interrupt singal status register.
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*/
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typedef union {
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struct {
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/** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
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* The masked interrupt status of TX_FIFO_REMPTY_INT.
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*/
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uint32_t tx_fifo_rempty_int_st:1;
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/** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
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* The masked interrupt status of RX_FIFO_WOVF_INT.
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*/
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uint32_t rx_fifo_wovf_int_st:1;
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/** tx_eof_int_st : RO; bitpos: [2]; default: 0;
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* The masked interrupt status of TX_EOF_INT.
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*/
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uint32_t tx_eof_int_st:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} parl_io_int_st_reg_t;
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/** Type of int_clr register
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* Parallel IO interrupt clear singal configuration register.
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*/
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typedef union {
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struct {
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/** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
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* Set this bit to clear TX_FIFO_REMPTY_INT.
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*/
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uint32_t tx_fifo_rempty_int_clr:1;
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/** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
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* Set this bit to clear RX_FIFO_WOVF_INT.
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*/
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uint32_t rx_fifo_wovf_int_clr:1;
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/** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
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* Set this bit to clear TX_EOF_INT.
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*/
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uint32_t tx_eof_int_clr:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} parl_io_int_clr_reg_t;
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/** Group: PARL_IO Rx Status0 */
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/** Type of rx_st0 register
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* Parallel IO RX status register0
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*/
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typedef union {
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struct {
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uint32_t reserved_0:8;
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/** rx_cnt : RO; bitpos: [12:8]; default: 0;
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* Indicates the cycle number of reading Rx FIFO.
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*/
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uint32_t rx_cnt:5;
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/** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
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* Indicates the current written bit number into Rx FIFO.
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*/
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uint32_t rx_fifo_wr_bit_cnt:19;
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};
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uint32_t val;
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} parl_io_rx_st0_reg_t;
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/** Group: PARL_IO Rx Status1 */
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/** Type of rx_st1 register
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* Parallel IO RX status register1
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*/
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typedef union {
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struct {
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uint32_t reserved_0:13;
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/** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
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* Indicates the current read bit number from Rx FIFO.
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*/
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uint32_t rx_fifo_rd_bit_cnt:19;
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};
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uint32_t val;
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} parl_io_rx_st1_reg_t;
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/** Group: PARL_IO Tx Status0 */
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/** Type of tx_st0 register
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* Parallel IO TX status register0
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*/
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typedef union {
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struct {
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uint32_t reserved_0:6;
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/** tx_cnt : RO; bitpos: [12:6]; default: 0;
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* Indicates the cycle number of reading Tx FIFO.
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*/
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uint32_t tx_cnt:7;
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/** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
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* Indicates the current read bit number from Tx FIFO.
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*/
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uint32_t tx_fifo_rd_bit_cnt:19;
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};
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uint32_t val;
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} parl_io_tx_st0_reg_t;
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/** Group: PARL_IO Rx Clock Configuration */
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/** Type of rx_clk_cfg register
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* Parallel IO RX clk configuration register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:30;
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/** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
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* Set this bit to invert the input Rx core clock.
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*/
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uint32_t rx_clk_i_inv:1;
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/** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
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* Set this bit to invert the output Rx core clock.
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*/
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uint32_t rx_clk_o_inv:1;
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};
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uint32_t val;
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} parl_io_rx_clk_cfg_reg_t;
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/** Group: PARL_IO Tx Clock Configuration */
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/** Type of tx_clk_cfg register
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* Parallel IO TX clk configuration register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:30;
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/** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
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* Set this bit to invert the input Tx core clock.
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*/
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uint32_t tx_clk_i_inv:1;
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/** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
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* Set this bit to invert the output Tx core clock.
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*/
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uint32_t tx_clk_o_inv:1;
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};
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uint32_t val;
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} parl_io_tx_clk_cfg_reg_t;
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/** Group: PARL_IO Clock Configuration */
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/** Type of clk register
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* Parallel IO clk configuration register
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*/
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typedef union {
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struct {
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uint32_t reserved_0:31;
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/** clk_en : R/W; bitpos: [31]; default: 0;
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* Force clock on for this register file
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*/
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uint32_t clk_en:1;
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};
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uint32_t val;
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} parl_io_clk_reg_t;
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/** Group: PARL_IO Version Register */
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/** Type of version register
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* Version register.
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 35725920;
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* Version of this register file
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} parl_io_version_reg_t;
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typedef struct parl_io_dev_t {
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volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
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volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
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volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
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volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
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volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
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volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
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volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
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volatile parl_io_fifo_cfg_reg_t fifo_cfg;
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volatile parl_io_reg_update_reg_t reg_update;
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volatile parl_io_st_reg_t st;
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volatile parl_io_int_ena_reg_t int_ena;
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volatile parl_io_int_raw_reg_t int_raw;
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volatile parl_io_int_st_reg_t int_st;
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volatile parl_io_int_clr_reg_t int_clr;
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volatile parl_io_rx_st0_reg_t rx_st0;
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volatile parl_io_rx_st1_reg_t rx_st1;
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volatile parl_io_tx_st0_reg_t tx_st0;
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volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
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volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
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uint32_t reserved_04c[53];
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volatile parl_io_clk_reg_t clk;
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uint32_t reserved_124[182];
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volatile parl_io_version_reg_t version;
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} parl_io_dev_t;
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#ifndef __cplusplus
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_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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