mirror of
https://github.com/espressif/esp-idf.git
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954 lines
32 KiB
C
954 lines
32 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include <assert.h>
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#include <string.h>
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#include <stdio.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#if CONFIG_IDF_TARGET_ESP32
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#include "soc/dport_reg.h"
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#include <esp32/rom/cache.h>
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#elif CONFIG_IDF_TARGET_ESP32P4
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#include "esp32p4/rom/cache.h"
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#endif
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#include "esp_rom_spiflash.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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#include <soc/soc.h>
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#include "sdkconfig.h"
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#ifndef CONFIG_FREERTOS_UNICORE
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#include "esp_private/esp_ipc.h"
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#endif
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#include "esp_attr.h"
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#include "esp_memory_utils.h"
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#include "esp_intr_alloc.h"
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#include "spi_flash_override.h"
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/freertos_idf_additions_priv.h"
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#include "esp_log.h"
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#include "esp_cpu.h"
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static __attribute__((unused)) const char *TAG = "cache";
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/**
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* These two shouldn't be declared as static otherwise if `CONFIG_SPI_FLASH_ROM_IMPL` is enabled,
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* they won't get replaced by the rom version
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*/
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void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state);
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void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
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// Used only on ROM impl. in idf, this param unused, cache status hold by hal
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static uint32_t s_flash_op_cache_state[2];
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#ifndef CONFIG_FREERTOS_UNICORE
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static SemaphoreHandle_t s_flash_op_mutex;
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static volatile bool s_flash_op_can_start = false;
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static volatile bool s_flash_op_complete = false;
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#ifndef NDEBUG
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static volatile int s_flash_op_cpu = -1;
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#endif
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static inline bool esp_task_stack_is_sane_cache_disabled(void)
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{
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const void *sp = (const void *)esp_cpu_get_sp();
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return esp_ptr_in_dram(sp)
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#if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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|| esp_ptr_in_rtc_dram_fast(sp)
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#endif
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;
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}
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void spi_flash_init_lock(void)
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{
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s_flash_op_mutex = xSemaphoreCreateRecursiveMutex();
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assert(s_flash_op_mutex != NULL);
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}
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void spi_flash_op_lock(void)
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{
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xSemaphoreTakeRecursive(s_flash_op_mutex, portMAX_DELAY);
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}
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void spi_flash_op_unlock(void)
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{
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xSemaphoreGiveRecursive(s_flash_op_mutex);
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}
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/*
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If you're going to modify this, keep in mind that while the flash caches of the pro and app
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cpu are separate, the psram cache is *not*. If one of the CPUs returns from a flash routine
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with its cache enabled but the other CPUs cache is not enabled yet, you will have problems
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when accessing psram from the former CPU.
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*/
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void IRAM_ATTR spi_flash_op_block_func(void *arg)
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{
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// Disable scheduler on this CPU
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#if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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/*
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Note: FreeRTOS SMP has changed the behavior of scheduler suspension. But the vTaskPreemptionDisable() function should
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achieve the same affect as before (i.e., prevent the current task from being preempted).
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*/
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vTaskPreemptionDisable(NULL);
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#else
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vTaskSuspendAll();
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#endif // #if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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// Restore interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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uint32_t cpuid = (uint32_t) arg;
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// s_flash_op_complete flag is cleared on *this* CPU, otherwise the other
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// CPU may reset the flag back to false before IPC task has a chance to check it
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// (if it is preempted by an ISR taking non-trivial amount of time)
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s_flash_op_complete = false;
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s_flash_op_can_start = true;
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while (!s_flash_op_complete) {
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// busy loop here and wait for the other CPU to finish flash operation
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}
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// Flash operation is complete, re-enable cache
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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// Restore interrupts that aren't located in IRAM
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esp_intr_noniram_enable();
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#if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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//Note: Scheduler suspension behavior changed in FreeRTOS SMP
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vTaskPreemptionEnable(NULL);
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#else
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// Re-enable scheduler
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xTaskResumeAll();
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#endif // #if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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}
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void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
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{
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assert(esp_task_stack_is_sane_cache_disabled());
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spi_flash_op_lock();
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int cpuid = xPortGetCoreID();
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uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
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#ifndef NDEBUG
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// For sanity check later: record the CPU which has started doing flash operation
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assert(s_flash_op_cpu == -1);
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s_flash_op_cpu = cpuid;
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#endif
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if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) {
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// Scheduler hasn't been started yet, it means that spi_flash API is being
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// called from the 2nd stage bootloader or from user_start_cpu0, i.e. from
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// PRO CPU. APP CPU is either in reset or spinning inside user_start_cpu1,
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// which is in IRAM. So it is safe to disable cache for the other_cpuid after
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// esp_intr_noniram_disable.
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assert(other_cpuid == 1);
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} else {
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bool ipc_call_was_send_to_other_cpu;
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do {
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#if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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//Note: Scheduler suspension behavior changed in FreeRTOS SMP
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vTaskPreemptionDisable(NULL);
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#else
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// Disable scheduler on the current CPU
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vTaskSuspendAll();
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#endif
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cpuid = xPortGetCoreID();
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other_cpuid = (cpuid == 0) ? 1 : 0;
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#ifndef NDEBUG
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s_flash_op_cpu = cpuid;
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#endif
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s_flash_op_can_start = false;
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ipc_call_was_send_to_other_cpu = esp_ipc_call_nonblocking(other_cpuid, &spi_flash_op_block_func, (void *) other_cpuid) == ESP_OK;
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if (!ipc_call_was_send_to_other_cpu) {
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// IPC call was not send to other cpu because another nonblocking API is running now.
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// Enable the Scheduler again will not help the IPC to speed it up
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// but there is a benefit to schedule to a higher priority task before the nonblocking running IPC call is done.
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#if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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//Note: Scheduler suspension behavior changed in FreeRTOS SMP
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vTaskPreemptionEnable(NULL);
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#else
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xTaskResumeAll();
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#endif
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}
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} while (!ipc_call_was_send_to_other_cpu);
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while (!s_flash_op_can_start) {
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// Busy loop and wait for spi_flash_op_block_func to disable cache
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// on the other CPU
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}
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}
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// Kill interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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// This CPU executes this routine, with non-IRAM interrupts and the scheduler
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// disabled. The other CPU is spinning in the spi_flash_op_block_func task, also
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// with non-iram interrupts and the scheduler disabled. None of these CPUs will
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// touch external RAM or flash this way, so we can safely disable caches.
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spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
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#if SOC_IDCACHE_PER_CORE
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//only needed if cache(s) is per core
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spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
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#endif
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
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{
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const int cpuid = xPortGetCoreID();
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#ifndef NDEBUG
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// Sanity check: flash operation ends on the same CPU as it has started
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assert(cpuid == s_flash_op_cpu);
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// More sanity check: if scheduler isn't started, only CPU0 can call this.
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assert(!(xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED && cpuid != 0));
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s_flash_op_cpu = -1;
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#endif
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// Re-enable cache. After this, cache (flash and external RAM) should work again.
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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#if SOC_IDCACHE_PER_CORE
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//only needed if cache(s) is per core
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const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
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spi_flash_restore_cache(other_cpuid, s_flash_op_cache_state[other_cpuid]);
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#endif
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if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
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// Signal to spi_flash_op_block_task that flash operation is complete
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s_flash_op_complete = true;
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}
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// Re-enable non-iram interrupts
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esp_intr_noniram_enable();
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// Resume tasks on the current CPU, if the scheduler has started.
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// NOTE: enabling non-IRAM interrupts has to happen before this,
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// because once the scheduler has started, due to preemption the
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// current task can end up being moved to the other CPU.
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// But esp_intr_noniram_enable has to be called on the same CPU which
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// called esp_intr_noniram_disable
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if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
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#if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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//Note: Scheduler suspension behavior changed in FreeRTOS SMP
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vTaskPreemptionEnable(NULL);
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#else
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xTaskResumeAll();
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#endif // #if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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}
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// Release API lock
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spi_flash_op_unlock();
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}
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void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void)
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{
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const uint32_t cpuid = xPortGetCoreID();
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const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
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// do not care about other CPU, it was halted upon entering panic handler
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spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
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// Kill interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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// Disable cache on this CPU as well
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spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void)
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{
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const uint32_t cpuid = xPortGetCoreID();
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// Re-enable cache on this CPU
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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// Re-enable non-iram interrupts
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esp_intr_noniram_enable();
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}
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#else // CONFIG_FREERTOS_UNICORE
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void spi_flash_init_lock(void)
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{
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}
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void spi_flash_op_lock(void)
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{
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#if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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if (xTaskGetSchedulerState() == taskSCHEDULER_RUNNING) {
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//Note: Scheduler suspension behavior changed in FreeRTOS SMP
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vTaskPreemptionDisable(NULL);
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}
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#else
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vTaskSuspendAll();
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#endif // #if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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}
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void spi_flash_op_unlock(void)
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{
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#if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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if (xTaskGetSchedulerState() == taskSCHEDULER_RUNNING) {
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//Note: Scheduler suspension behavior changed in FreeRTOS SMP
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vTaskPreemptionEnable(NULL);
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}
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#else
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xTaskResumeAll();
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#endif // #if ( ( CONFIG_FREERTOS_SMP ) && ( !CONFIG_FREERTOS_UNICORE ) )
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}
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void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
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{
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spi_flash_op_lock();
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esp_intr_noniram_disable();
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spi_flash_disable_cache(0, &s_flash_op_cache_state[0]);
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
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{
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spi_flash_restore_cache(0, s_flash_op_cache_state[0]);
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esp_intr_noniram_enable();
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spi_flash_op_unlock();
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}
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void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void)
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{
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// Kill interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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// Disable cache on this CPU as well
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spi_flash_disable_cache(0, &s_flash_op_cache_state[0]);
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void)
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{
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// Re-enable cache on this CPU
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spi_flash_restore_cache(0, s_flash_op_cache_state[0]);
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// Re-enable non-iram interrupts
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esp_intr_noniram_enable();
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}
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#endif // CONFIG_FREERTOS_UNICORE
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void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
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{
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#if CONFIG_IDF_TARGET_ESP32
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uint32_t cache_value = cache_ll_l1_get_enabled_bus(cpuid);
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// Re-enable cache on this CPU
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spi_flash_restore_cache(cpuid, cache_value);
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#else
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spi_flash_restore_cache(0, 0); // TODO cache_value should be non-zero
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#endif
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}
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void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)
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{
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cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
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}
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void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
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{
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cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
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}
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bool IRAM_ATTR spi_flash_cache_enabled(void)
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{
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return cache_hal_is_cache_enabled(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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IRAM_ATTR void esp_config_instruction_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_16KB;
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#endif
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cache_ways = CACHE_4WAYS_ASSOC;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#else
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cache_line_size = CACHE_LINE_SIZE_32B;
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#endif
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ESP_EARLY_LOGI(TAG, "Instruction cache \t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32);
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Cache_Suspend_ICache();
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Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
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Cache_Invalidate_ICache_All();
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Cache_Resume_ICache(0);
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}
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IRAM_ATTR void esp_config_data_cache_mode(void)
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{
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#define CACHE_SIZE_0KB 99 //If Cache set to 0 KB, cache is bypassed, the cache size doesn't take into effect. Set this macro to a unique value for log
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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#if CONFIG_ESP32S2_DATA_CACHE_0KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_0KB;
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#elif CONFIG_ESP32S2_DATA_CACHE_8KB
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_8KB;
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#else
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Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_16KB;
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#endif
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#else
|
|
#if CONFIG_ESP32S2_DATA_CACHE_0KB
|
|
Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
|
|
cache_size = CACHE_SIZE_0KB;
|
|
#elif CONFIG_ESP32S2_DATA_CACHE_8KB
|
|
Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
|
|
cache_size = CACHE_SIZE_8KB;
|
|
#else
|
|
Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
|
|
cache_size = CACHE_SIZE_16KB;
|
|
#endif
|
|
#endif
|
|
|
|
cache_ways = CACHE_4WAYS_ASSOC;
|
|
#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B
|
|
cache_line_size = CACHE_LINE_SIZE_16B;
|
|
#else
|
|
cache_line_size = CACHE_LINE_SIZE_32B;
|
|
#endif
|
|
ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", (cache_size == CACHE_SIZE_0KB) ? 0 : ((cache_size == CACHE_SIZE_8KB) ? 8 : 16), 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32);
|
|
Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
|
|
Cache_Invalidate_DCache_All();
|
|
}
|
|
|
|
static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache)
|
|
{
|
|
uint32_t i_autoload, d_autoload;
|
|
if (icache) {
|
|
i_autoload = Cache_Suspend_ICache();
|
|
}
|
|
if (dcache) {
|
|
d_autoload = Cache_Suspend_DCache();
|
|
}
|
|
REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND);
|
|
if (icache) {
|
|
Cache_Resume_ICache(i_autoload);
|
|
}
|
|
if (dcache) {
|
|
Cache_Resume_DCache(d_autoload);
|
|
}
|
|
}
|
|
|
|
#if (CONFIG_IDF_TARGET_ESP32S2 && CONFIG_SPIRAM)
|
|
static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache)
|
|
{
|
|
uint32_t i_autoload, d_autoload;
|
|
if (icache) {
|
|
i_autoload = Cache_Suspend_ICache();
|
|
}
|
|
if (dcache) {
|
|
d_autoload = Cache_Suspend_DCache();
|
|
}
|
|
REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND);
|
|
if (icache) {
|
|
Cache_Resume_ICache(i_autoload);
|
|
}
|
|
if (dcache) {
|
|
Cache_Resume_DCache(d_autoload);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable)
|
|
{
|
|
int icache_wrap_size = 0, dcache_wrap_size = 0;
|
|
int flash_wrap_sizes[2] = {-1, -1}, spiram_wrap_sizes[2] = {-1, -1};
|
|
int flash_wrap_size = 0, spiram_wrap_size = 0;
|
|
int flash_count = 0, spiram_count = 0;
|
|
int i;
|
|
bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
|
|
uint32_t drom0_in_icache = 1;//always 1 in esp32s2
|
|
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4
|
|
drom0_in_icache = 0;
|
|
#endif
|
|
|
|
if (icache_wrap_enable) {
|
|
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B || CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B
|
|
icache_wrap_size = FLASH_WRAP_SIZE_16B;
|
|
#else
|
|
icache_wrap_size = FLASH_WRAP_SIZE_32B;
|
|
#endif
|
|
}
|
|
if (dcache_wrap_enable) {
|
|
#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B || CONFIG_ESP32S3_DATA_CACHE_LINE_16B
|
|
dcache_wrap_size = FLASH_WRAP_SIZE_16B;
|
|
#else
|
|
dcache_wrap_size = FLASH_WRAP_SIZE_32B;
|
|
#endif
|
|
}
|
|
|
|
uint32_t instruction_use_spiram = 0;
|
|
uint32_t rodata_use_spiram = 0;
|
|
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
|
|
extern uint32_t esp_spiram_instruction_access_enabled(void);
|
|
instruction_use_spiram = esp_spiram_instruction_access_enabled();
|
|
#endif
|
|
#if CONFIG_SPIRAM_RODATA
|
|
extern uint32_t esp_spiram_rodata_access_enabled(void);
|
|
rodata_use_spiram = esp_spiram_rodata_access_enabled();
|
|
#endif
|
|
|
|
if (instruction_use_spiram) {
|
|
spiram_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
flash_wrap_sizes[0] = icache_wrap_size;
|
|
}
|
|
if (rodata_use_spiram) {
|
|
if (drom0_in_icache) {
|
|
spiram_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
spiram_wrap_sizes[1] = dcache_wrap_size;
|
|
flash_wrap_sizes[1] = dcache_wrap_size;
|
|
}
|
|
} else {
|
|
if (drom0_in_icache) {
|
|
flash_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
flash_wrap_sizes[1] = dcache_wrap_size;
|
|
}
|
|
}
|
|
#if (CONFIG_IDF_TARGET_ESP32S2 && CONFIG_SPIRAM)
|
|
spiram_wrap_sizes[1] = dcache_wrap_size;
|
|
#endif
|
|
for (i = 0; i < 2; i++) {
|
|
if (flash_wrap_sizes[i] != -1) {
|
|
flash_count++;
|
|
flash_wrap_size = flash_wrap_sizes[i];
|
|
}
|
|
}
|
|
for (i = 0; i < 2; i++) {
|
|
if (spiram_wrap_sizes[i] != -1) {
|
|
spiram_count++;
|
|
spiram_wrap_size = spiram_wrap_sizes[i];
|
|
}
|
|
}
|
|
if (flash_count + spiram_count <= 2) {
|
|
flash_spiram_wrap_together = false;
|
|
} else {
|
|
flash_spiram_wrap_together = true;
|
|
}
|
|
ESP_EARLY_LOGI(TAG, "flash_count=%d, size=%d, spiram_count=%d, size=%d,together=%d", flash_count, flash_wrap_size, spiram_count, spiram_wrap_size, flash_spiram_wrap_together);
|
|
if (flash_count > 1 && flash_wrap_sizes[0] != flash_wrap_sizes[1]) {
|
|
ESP_EARLY_LOGW(TAG, "Flash wrap with different length %d and %d, abort wrap.", flash_wrap_sizes[0], flash_wrap_sizes[1]);
|
|
if (spiram_wrap_size == 0) {
|
|
return ESP_FAIL;
|
|
}
|
|
if (flash_spiram_wrap_together) {
|
|
ESP_EARLY_LOGE(TAG, "Abort spiram wrap because flash wrap length not fixed.");
|
|
return ESP_FAIL;
|
|
}
|
|
}
|
|
if (spiram_count > 1 && spiram_wrap_sizes[0] != spiram_wrap_sizes[1]) {
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM wrap with different length %d and %d, abort wrap.", spiram_wrap_sizes[0], spiram_wrap_sizes[1]);
|
|
if (flash_wrap_size == 0) {
|
|
return ESP_FAIL;
|
|
}
|
|
if (flash_spiram_wrap_together) {
|
|
ESP_EARLY_LOGW(TAG, "Abort flash wrap because spiram wrap length not fixed.");
|
|
return ESP_FAIL;
|
|
}
|
|
}
|
|
|
|
if (flash_spiram_wrap_together && flash_wrap_size != spiram_wrap_size) {
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM has different wrap length with flash, %d and %d, abort wrap.", spiram_wrap_size, flash_wrap_size);
|
|
return ESP_FAIL;
|
|
}
|
|
|
|
#ifdef CONFIG_ESPTOOLPY_FLASHMODE_QIO
|
|
flash_support_wrap = true;
|
|
spi_flash_wrap_probe();
|
|
if (!spi_flash_support_wrap_size(flash_wrap_size)) {
|
|
flash_support_wrap = false;
|
|
ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size);
|
|
}
|
|
#else
|
|
ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap.");
|
|
#endif
|
|
|
|
#if (CONFIG_IDF_TARGET_ESP32S2 && CONFIG_SPIRAM)
|
|
extern bool psram_support_wrap_size(uint32_t wrap_size);
|
|
if (!psram_support_wrap_size(spiram_wrap_size)) {
|
|
spiram_support_wrap = false;
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM do not support wrap size %d.", spiram_wrap_size);
|
|
}
|
|
#endif
|
|
|
|
if (flash_spiram_wrap_together && !(flash_support_wrap && spiram_support_wrap)) {
|
|
ESP_EARLY_LOGW(TAG, "Flash and SPIRAM should support wrap together.");
|
|
return ESP_FAIL;
|
|
}
|
|
|
|
if (flash_support_wrap && flash_wrap_size > 0) {
|
|
ESP_EARLY_LOGI(TAG, "Flash wrap enabled, size = %d.", flash_wrap_size);
|
|
spi_flash_wrap_enable(flash_wrap_size);
|
|
esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0));
|
|
}
|
|
#if (CONFIG_IDF_TARGET_ESP32S2 && CONFIG_SPIRAM)
|
|
extern esp_err_t psram_enable_wrap(uint32_t wrap_size);
|
|
if (spiram_support_wrap && spiram_wrap_size > 0) {
|
|
ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled, size = %d.", spiram_wrap_size);
|
|
psram_enable_wrap(spiram_wrap_size);
|
|
esp_enable_cache_spiram_wrap((spiram_wrap_sizes[0] > 0), (spiram_wrap_sizes[1] > 0));
|
|
}
|
|
#endif
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
#endif
|
|
#if CONFIG_IDF_TARGET_ESP32S3
|
|
IRAM_ATTR void esp_config_instruction_cache_mode(void)
|
|
{
|
|
cache_size_t cache_size;
|
|
cache_ways_t cache_ways;
|
|
cache_line_size_t cache_line_size;
|
|
|
|
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB
|
|
Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_INVALID);
|
|
cache_size = CACHE_SIZE_HALF;
|
|
#else
|
|
Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1);
|
|
cache_size = CACHE_SIZE_FULL;
|
|
#endif
|
|
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS
|
|
cache_ways = CACHE_4WAYS_ASSOC;
|
|
#else
|
|
cache_ways = CACHE_8WAYS_ASSOC;
|
|
#endif
|
|
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B
|
|
cache_line_size = CACHE_LINE_SIZE_16B;
|
|
#elif CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B
|
|
cache_line_size = CACHE_LINE_SIZE_32B;
|
|
#else
|
|
cache_line_size = CACHE_LINE_SIZE_64B;
|
|
#endif
|
|
ESP_EARLY_LOGI(TAG, "Instruction cache: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_HALF ? 16 : 32, cache_ways == CACHE_4WAYS_ASSOC ? 4 : 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64));
|
|
Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
|
|
Cache_Invalidate_ICache_All();
|
|
extern void Cache_Enable_ICache(uint32_t autoload);
|
|
Cache_Enable_ICache(0);
|
|
}
|
|
|
|
IRAM_ATTR void esp_config_data_cache_mode(void)
|
|
{
|
|
cache_size_t cache_size;
|
|
cache_ways_t cache_ways;
|
|
cache_line_size_t cache_line_size;
|
|
|
|
#if CONFIG_ESP32S3_DATA_CACHE_32KB
|
|
Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK1, CACHE_MEMORY_INVALID);
|
|
cache_size = CACHE_SIZE_HALF;
|
|
#else
|
|
Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1);
|
|
cache_size = CACHE_SIZE_FULL;
|
|
#endif
|
|
#if CONFIG_ESP32S3_DATA_CACHE_4WAYS
|
|
cache_ways = CACHE_4WAYS_ASSOC;
|
|
#else
|
|
cache_ways = CACHE_8WAYS_ASSOC;
|
|
#endif
|
|
#if CONFIG_ESP32S3_DATA_CACHE_LINE_16B
|
|
cache_line_size = CACHE_LINE_SIZE_16B;
|
|
#elif CONFIG_ESP32S3_DATA_CACHE_LINE_32B
|
|
cache_line_size = CACHE_LINE_SIZE_32B;
|
|
#else
|
|
cache_line_size = CACHE_LINE_SIZE_64B;
|
|
#endif
|
|
// ESP_EARLY_LOGI(TAG, "Data cache: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_HALF ? 32 : 64, cache_ways == CACHE_4WAYS_ASSOC ? 4 : 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64));
|
|
Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
|
|
Cache_Invalidate_DCache_All();
|
|
}
|
|
|
|
static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache)
|
|
{
|
|
uint32_t i_autoload, d_autoload;
|
|
if (icache) {
|
|
i_autoload = Cache_Suspend_ICache();
|
|
}
|
|
if (dcache) {
|
|
d_autoload = Cache_Suspend_DCache();
|
|
}
|
|
REG_SET_BIT(EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_CACHE_FLASH_WRAP_AROUND);
|
|
if (icache) {
|
|
Cache_Resume_ICache(i_autoload);
|
|
}
|
|
if (dcache) {
|
|
Cache_Resume_DCache(d_autoload);
|
|
}
|
|
}
|
|
|
|
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
|
|
static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache)
|
|
{
|
|
uint32_t i_autoload, d_autoload;
|
|
if (icache) {
|
|
i_autoload = Cache_Suspend_ICache();
|
|
}
|
|
if (dcache) {
|
|
d_autoload = Cache_Suspend_DCache();
|
|
}
|
|
REG_SET_BIT(EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_CACHE_SRAM_RD_WRAP_AROUND);
|
|
if (icache) {
|
|
Cache_Resume_ICache(i_autoload);
|
|
}
|
|
if (dcache) {
|
|
Cache_Resume_DCache(d_autoload);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable)
|
|
{
|
|
int icache_wrap_size = 0, dcache_wrap_size = 0;
|
|
int flash_wrap_sizes[2] = {-1, -1}, spiram_wrap_sizes[2] = {-1, -1};
|
|
int flash_wrap_size = 0, spiram_wrap_size = 0;
|
|
int flash_count = 0, spiram_count = 0;
|
|
int i;
|
|
bool flash_spiram_wrap_together, flash_support_wrap = false, spiram_support_wrap = true;
|
|
uint32_t drom0_in_icache = 0;//always 0 in chip7.2.4
|
|
|
|
if (icache_wrap_enable) {
|
|
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B
|
|
icache_wrap_size = FLASH_WRAP_SIZE_16B;
|
|
#elif CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B
|
|
icache_wrap_size = FLASH_WRAP_SIZE_32B;
|
|
#else
|
|
icache_wrap_size = FLASH_WRAP_SIZE_64B;
|
|
#endif
|
|
}
|
|
if (dcache_wrap_enable) {
|
|
#if CONFIG_ESP32S3_DATA_CACHE_LINE_16B
|
|
dcache_wrap_size = FLASH_WRAP_SIZE_16B;
|
|
#elif CONFIG_ESP32S3_DATA_CACHE_LINE_32B
|
|
dcache_wrap_size = FLASH_WRAP_SIZE_32B;
|
|
#else
|
|
dcache_wrap_size = FLASH_WRAP_SIZE_64B;
|
|
#endif
|
|
}
|
|
|
|
uint32_t instruction_use_spiram = 0;
|
|
uint32_t rodata_use_spiram = 0;
|
|
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
|
|
extern uint32_t esp_spiram_instruction_access_enabled(void);
|
|
instruction_use_spiram = esp_spiram_instruction_access_enabled();
|
|
#endif
|
|
#if CONFIG_SPIRAM_RODATA
|
|
extern uint32_t esp_spiram_rodata_access_enabled(void);
|
|
rodata_use_spiram = esp_spiram_rodata_access_enabled();
|
|
#endif
|
|
|
|
if (instruction_use_spiram) {
|
|
spiram_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
flash_wrap_sizes[0] = icache_wrap_size;
|
|
}
|
|
if (rodata_use_spiram) {
|
|
if (drom0_in_icache) {
|
|
spiram_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
spiram_wrap_sizes[1] = dcache_wrap_size;
|
|
}
|
|
} else {
|
|
if (drom0_in_icache) {
|
|
flash_wrap_sizes[0] = icache_wrap_size;
|
|
} else {
|
|
flash_wrap_sizes[1] = dcache_wrap_size;
|
|
}
|
|
}
|
|
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
|
|
spiram_wrap_sizes[1] = dcache_wrap_size;
|
|
#endif
|
|
for (i = 0; i < 2; i++) {
|
|
if (flash_wrap_sizes[i] != -1) {
|
|
flash_count++;
|
|
flash_wrap_size = flash_wrap_sizes[i];
|
|
}
|
|
}
|
|
for (i = 0; i < 2; i++) {
|
|
if (spiram_wrap_sizes[i] != -1) {
|
|
spiram_count++;
|
|
spiram_wrap_size = spiram_wrap_sizes[i];
|
|
}
|
|
}
|
|
if (flash_count + spiram_count <= 2) {
|
|
flash_spiram_wrap_together = false;
|
|
} else {
|
|
flash_spiram_wrap_together = true;
|
|
}
|
|
if (flash_count > 1 && flash_wrap_sizes[0] != flash_wrap_sizes[1]) {
|
|
ESP_EARLY_LOGW(TAG, "Flash wrap with different length %d and %d, abort wrap.", flash_wrap_sizes[0], flash_wrap_sizes[1]);
|
|
if (spiram_wrap_size == 0) {
|
|
return ESP_FAIL;
|
|
}
|
|
if (flash_spiram_wrap_together) {
|
|
ESP_EARLY_LOGE(TAG, "Abort spiram wrap because flash wrap length not fixed.");
|
|
return ESP_FAIL;
|
|
}
|
|
}
|
|
if (spiram_count > 1 && spiram_wrap_sizes[0] != spiram_wrap_sizes[1]) {
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM wrap with different length %d and %d, abort wrap.", spiram_wrap_sizes[0], spiram_wrap_sizes[1]);
|
|
if (flash_wrap_size == 0) {
|
|
return ESP_FAIL;
|
|
}
|
|
if (flash_spiram_wrap_together) {
|
|
ESP_EARLY_LOGW(TAG, "Abort flash wrap because spiram wrap length not fixed.");
|
|
return ESP_FAIL;
|
|
}
|
|
}
|
|
|
|
if (flash_spiram_wrap_together && flash_wrap_size != spiram_wrap_size) {
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM has different wrap length with flash, %d and %d, abort wrap.", spiram_wrap_size, flash_wrap_size);
|
|
return ESP_FAIL;
|
|
}
|
|
|
|
#ifdef CONFIG_ESPTOOLPY_FLASHMODE_QIO
|
|
flash_support_wrap = true;
|
|
spi_flash_wrap_probe();
|
|
if (!spi_flash_support_wrap_size(flash_wrap_size)) {
|
|
flash_support_wrap = false;
|
|
ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size);
|
|
}
|
|
#else
|
|
ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap.");
|
|
#endif
|
|
|
|
|
|
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
|
|
extern bool psram_support_wrap_size(uint32_t wrap_size);
|
|
if (!psram_support_wrap_size(spiram_wrap_size)) {
|
|
spiram_support_wrap = false;
|
|
ESP_EARLY_LOGW(TAG, "SPIRAM do not support wrap size %d.", spiram_wrap_size);
|
|
}
|
|
#endif
|
|
|
|
if (flash_spiram_wrap_together && !(flash_support_wrap && spiram_support_wrap)) {
|
|
ESP_EARLY_LOGW(TAG, "Flash and SPIRAM should support wrap together.");
|
|
return ESP_FAIL;
|
|
}
|
|
|
|
if (flash_support_wrap && flash_wrap_size > 0) {
|
|
ESP_EARLY_LOGI(TAG, "Flash wrap enabled, size = %d.", flash_wrap_size);
|
|
spi_flash_wrap_enable(flash_wrap_size);
|
|
esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0));
|
|
}
|
|
#if (CONFIG_IDF_TARGET_ESP32S3 && CONFIG_SPIRAM)
|
|
extern esp_err_t psram_enable_wrap(uint32_t wrap_size);
|
|
if (spiram_support_wrap && spiram_wrap_size > 0) {
|
|
ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled, size = %d.", spiram_wrap_size);
|
|
psram_enable_wrap(spiram_wrap_size);
|
|
esp_enable_cache_spiram_wrap((spiram_wrap_sizes[0] > 0), (spiram_wrap_sizes[1] > 0));
|
|
}
|
|
#endif
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
#endif
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
|
|
|
|
static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache)
|
|
{
|
|
uint32_t i_autoload;
|
|
if (icache) {
|
|
i_autoload = Cache_Suspend_ICache();
|
|
}
|
|
REG_SET_BIT(EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_CACHE_FLASH_WRAP_AROUND);
|
|
if (icache) {
|
|
Cache_Resume_ICache(i_autoload);
|
|
}
|
|
}
|
|
|
|
esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable)
|
|
{
|
|
int flash_wrap_size = 0;
|
|
bool flash_support_wrap = false;
|
|
|
|
if (icache_wrap_enable) {
|
|
flash_wrap_size = 32;
|
|
}
|
|
|
|
#ifdef CONFIG_ESPTOOLPY_FLASHMODE_QIO
|
|
flash_support_wrap = true;
|
|
spi_flash_wrap_probe();
|
|
if (!spi_flash_support_wrap_size(flash_wrap_size)) {
|
|
flash_support_wrap = false;
|
|
ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size);
|
|
}
|
|
#else
|
|
ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap.");
|
|
#endif // CONFIG_ESPTOOLPY_FLASHMODE_QIO
|
|
|
|
if (flash_support_wrap && flash_wrap_size > 0) {
|
|
ESP_EARLY_LOGI(TAG, "Flash wrap enabled, size = %d.", flash_wrap_size);
|
|
spi_flash_wrap_enable(flash_wrap_size);
|
|
esp_enable_cache_flash_wrap((flash_wrap_size > 0));
|
|
}
|
|
return ESP_OK;
|
|
}
|
|
#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32P4
|
|
//TODO: IDF-5670
|
|
void esp_config_l2_cache_mode(void)
|
|
{
|
|
cache_size_t cache_size;
|
|
cache_line_size_t cache_line_size;
|
|
#if CONFIG_CACHE_L2_CACHE_128KB
|
|
cache_size = CACHE_SIZE_128K;
|
|
#elif CONFIG_CACHE_L2_CACHE_256KB
|
|
cache_size = CACHE_SIZE_256K;
|
|
#else
|
|
cache_size = CACHE_SIZE_512K;
|
|
#endif
|
|
|
|
#if CONFIG_CACHE_L2_CACHE_LINE_64B
|
|
cache_line_size = CACHE_LINE_SIZE_64B;
|
|
#else
|
|
cache_line_size = CACHE_LINE_SIZE_128B;
|
|
#endif
|
|
|
|
Cache_Set_L2_Cache_Mode(cache_size, 8, cache_line_size);
|
|
Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
|
|
}
|
|
#endif
|