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439 lines
18 KiB
C
439 lines
18 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** LP_CLKRST_LP_CLK_CONF_REG register
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* Configures the root clk of LP system
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*/
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#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
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/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
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* Configures the source of LP_SLOW_CLK.
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* 0: RC_SLOW_CLK
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* 1: XTAL32K_CLK
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* 2: RC32K_CLK
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* 3:OSC_SLOW_CLK
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*/
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#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U
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#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
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#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U
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#define LP_CLKRST_SLOW_CLK_SEL_S 0
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/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
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* configures the source of LP_FAST_CLK.
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* 0: RC_FAST_CLK
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* 1: XTAL_D2_CLK
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* 2: XTAL_CLK
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*/
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#define LP_CLKRST_FAST_CLK_SEL 0x00000003U
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#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
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#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U
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#define LP_CLKRST_FAST_CLK_SEL_S 2
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/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
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* reserved
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*/
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#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU
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#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
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#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU
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#define LP_CLKRST_LP_PERI_DIV_NUM_S 4
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/** LP_CLKRST_LP_CLK_PO_EN_REG register
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* Configures the clk gate to pad
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*/
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#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
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/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
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* Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_AON_SLOW_OEN (BIT(0))
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#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
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#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U
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#define LP_CLKRST_AON_SLOW_OEN_S 0
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/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
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* Configures the clock gate to pad of the LP_DYN_FAST_CLK.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_AON_FAST_OEN (BIT(1))
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#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
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#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U
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#define LP_CLKRST_AON_FAST_OEN_S 1
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/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
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* Configures the clock gate to pad of the OSC_SLOW_CLK.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_SOSC_OEN (BIT(2))
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#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
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#define LP_CLKRST_SOSC_OEN_V 0x00000001U
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#define LP_CLKRST_SOSC_OEN_S 2
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/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
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* Configures the clock gate to pad of the RC_FAST_CLK.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_FOSC_OEN (BIT(3))
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#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
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#define LP_CLKRST_FOSC_OEN_V 0x00000001U
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#define LP_CLKRST_FOSC_OEN_S 3
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/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
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* Configures the clock gate to pad of the RC32K_CLK.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_OSC32K_OEN (BIT(4))
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#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
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#define LP_CLKRST_OSC32K_OEN_V 0x00000001U
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#define LP_CLKRST_OSC32K_OEN_S 4
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/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
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* Configures the clock gate to pad of the XTAL32K_CLK.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_XTAL32K_OEN (BIT(5))
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#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
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#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U
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#define LP_CLKRST_XTAL32K_OEN_S 5
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/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
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* Configures the clock gate to pad of the EFUSE_CTRL clock.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6))
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#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
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#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U
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#define LP_CLKRST_CORE_EFUSE_OEN_S 6
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/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
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* Configures the clock gate to pad of the LP_SLOW_CLK.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_SLOW_OEN (BIT(7))
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#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
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#define LP_CLKRST_SLOW_OEN_V 0x00000001U
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#define LP_CLKRST_SLOW_OEN_S 7
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/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
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* Configures the clock gate to pad of the LP_FAST_CLK.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_FAST_OEN (BIT(8))
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#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
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#define LP_CLKRST_FAST_OEN_V 0x00000001U
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#define LP_CLKRST_FAST_OEN_S 8
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/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
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* Configures the clock gate to pad of the RNG clk.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_RNG_OEN (BIT(9))
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#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
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#define LP_CLKRST_RNG_OEN_V 0x00000001U
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#define LP_CLKRST_RNG_OEN_S 9
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/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
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* Configures the clock gate to pad of the LP bus clk.
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* 0: Disable the clk pass clock gate
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* 1: Enable the clk pass clock gate
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*/
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#define LP_CLKRST_LPBUS_OEN (BIT(10))
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#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
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#define LP_CLKRST_LPBUS_OEN_V 0x00000001U
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#define LP_CLKRST_LPBUS_OEN_S 10
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/** LP_CLKRST_LP_CLK_EN_REG register
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* Configure LP root clk source gate
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*/
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#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
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/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
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* Configures the clock gate to LP_FAST_CLK
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* 0: Invalid. The clock gate controlled by hardware fsm
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* 1: Force the clk pass clock gate
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*/
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#define LP_CLKRST_FAST_ORI_GATE (BIT(31))
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#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
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#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U
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#define LP_CLKRST_FAST_ORI_GATE_S 31
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/** LP_CLKRST_LP_RST_EN_REG register
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* Configures the peri of LP system software reset
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*/
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#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
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/** LP_CLKRST_POR_ST_WAIT_FORCE_EN : R/W; bitpos: [27]; default: 0;
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* reserved
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*/
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#define LP_CLKRST_POR_ST_WAIT_FORCE_EN (BIT(27))
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#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_M (LP_CLKRST_POR_ST_WAIT_FORCE_EN_V << LP_CLKRST_POR_ST_WAIT_FORCE_EN_S)
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#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_V 0x00000001U
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#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_S 27
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/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
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* Configures whether or not to reset EFUSE_CTRL always-on part
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* 0: Invalid.No effect
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* 1: Reset
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*/
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#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28))
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#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
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#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U
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#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28
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/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
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* Configures whether or not to reset LP_TIMER
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* 0: Invalid.No effect
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* 1: Reset
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*/
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#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29))
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#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
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#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U
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#define LP_CLKRST_LP_TIMER_RESET_EN_S 29
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/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
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* Configures whether or not to reset LP_WDT and super watch dog
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* 0: Invalid.No effect
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* 1: Reset
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*/
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#define LP_CLKRST_WDT_RESET_EN (BIT(30))
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#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
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#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U
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#define LP_CLKRST_WDT_RESET_EN_S 30
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/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
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* Configures whether or not to reset analog peri, include brownout controller
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* 0: Invalid.No effect
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* 1: Reset
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*/
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#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31))
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#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
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#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U
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#define LP_CLKRST_ANA_PERI_RESET_EN_S 31
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/** LP_CLKRST_RESET_CAUSE_REG register
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* Represents the reset casue
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*/
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#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
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/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
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* Represents the reset cause
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*/
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#define LP_CLKRST_RESET_CAUSE 0x0000001FU
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#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
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#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU
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#define LP_CLKRST_RESET_CAUSE_S 0
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/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
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* Represents the reset flag
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*/
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#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5))
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#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
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#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U
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#define LP_CLKRST_CORE0_RESET_FLAG_S 5
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/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
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* 0: no operation
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*/
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#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29))
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#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
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#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U
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#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29
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/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
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* configure set reset flag
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*/
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#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30))
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#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
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#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U
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#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30
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/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
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* configure clear reset flag
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* 0: no operation
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* 1: clear flag to 0
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*/
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#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31))
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#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
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#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U
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#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31
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/** LP_CLKRST_CPU_RESET_REG register
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* Configures CPU reset
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*/
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#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
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/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
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* configure the hpcore0 luckup reset enable
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* 0: disable
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* 1:enable
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*/
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#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21))
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#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
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#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U
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#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21
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/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
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* configures the reset length of LP_WDT reset CPU
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* Measurement unit: LP_DYN_FAST_CLK
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*/
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#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U
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#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
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#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U
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#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22
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/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
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* Configures whether or not LP_WDT can reset CPU
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* 0: LP_WDT could not reset CPU when LP_WDT timeout
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* 1: LP_WDT could reset CPU when LP_WDT timeout
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*/
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#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25))
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#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
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#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U
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#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25
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/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
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* configure the time between CPU stall and reset
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* Measurement unit: LP_DYN_FAST_CLK
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*/
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#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU
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#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
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#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU
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#define LP_CLKRST_CPU_STALL_WAIT_S 26
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/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
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* Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
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* 0: CPU will not entry stall state before LP_WDT and software reset CPU
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* 1: CPU will entry stall state before LP_WDT and software reset CPU
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*/
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#define LP_CLKRST_CPU_STALL_EN (BIT(31))
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#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
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#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U
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#define LP_CLKRST_CPU_STALL_EN_S 31
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/** LP_CLKRST_FOSC_CNTL_REG register
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* Configures the RC_FAST_CLK frequency
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*/
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#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
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/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
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* Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
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* field
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*/
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#define LP_CLKRST_FOSC_DFREQ 0x000003FFU
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#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
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#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU
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#define LP_CLKRST_FOSC_DFREQ_S 22
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/** LP_CLKRST_RC32K_CNTL_REG register
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* Configures the RC32K_CLK frequency
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*/
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#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
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/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
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* Configures the RC32K_CLK frequency, the clock frequency will increase with this
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* field
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*/
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#define LP_CLKRST_RC32K_DFREQ 0x000003FFU
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#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
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#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU
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#define LP_CLKRST_RC32K_DFREQ_S 22
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/** LP_CLKRST_CLK_TO_HP_REG register
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* Configures the clk gate of LP clk to HP system
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*/
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#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
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/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
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* Configures the clk gate of XTAL32K_CLK to HP system
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* 0: The clk could not pass to HP system
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* 1: The clk could pass to HP system
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*/
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#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28))
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#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
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#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U
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#define LP_CLKRST_ICG_HP_XTAL32K_S 28
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/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
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* Configures the clk gate of RC_SLOW_CLK to HP system
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* 0: The clk could not pass to HP system
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* 1: The clk could pass to HP system
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*/
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#define LP_CLKRST_ICG_HP_SOSC (BIT(29))
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#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
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#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U
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#define LP_CLKRST_ICG_HP_SOSC_S 29
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/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
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* Configures the clk gate of RC32K_CLK to HP system
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* 0: The clk could not pass to HP system
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* 1: The clk could pass to HP system
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*/
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#define LP_CLKRST_ICG_HP_OSC32K (BIT(30))
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#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
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#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U
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#define LP_CLKRST_ICG_HP_OSC32K_S 30
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/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
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* Configures the clk gate of RC_FAST_CLK to HP system
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* 0: The clk could not pass to HP system
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* 1: The clk could pass to HP system
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*/
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#define LP_CLKRST_ICG_HP_FOSC (BIT(31))
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#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
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#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U
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#define LP_CLKRST_ICG_HP_FOSC_S 31
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/** LP_CLKRST_LPMEM_FORCE_REG register
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* Configures the LP_MEM clk gate force parameter
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*/
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#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
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/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
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* Configures whether ot not force open the clock gate of LP MEM
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* 0: Invalid. The clock gate controlled by hardware FSM
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* 1: Force open clock gate of LP MEM
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*/
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#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31))
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#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
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#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U
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#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31
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/** LP_CLKRST_XTAL32K_REG register
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* Configures the XTAL32K parameter
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*/
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#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
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/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
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* Configures DRES
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*/
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#define LP_CLKRST_DRES_XTAL32K 0x00000007U
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#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
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#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U
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#define LP_CLKRST_DRES_XTAL32K_S 22
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/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
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* Configures DGM
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*/
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#define LP_CLKRST_DGM_XTAL32K 0x00000007U
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#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
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#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U
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#define LP_CLKRST_DGM_XTAL32K_S 25
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/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
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* Configures DBUF
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*/
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#define LP_CLKRST_DBUF_XTAL32K (BIT(28))
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#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
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#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U
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#define LP_CLKRST_DBUF_XTAL32K_S 28
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/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
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* Configures DAC
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*/
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#define LP_CLKRST_DAC_XTAL32K 0x00000007U
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#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
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#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U
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#define LP_CLKRST_DAC_XTAL32K_S 29
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/** LP_CLKRST_DATE_REG register
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* Version control register
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*/
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#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
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/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36766288;
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* Version control register
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*/
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#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU
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#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
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#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU
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#define LP_CLKRST_CLKRST_DATE_S 0
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/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
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* configure register clk bypass clk gate
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*/
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#define LP_CLKRST_CLK_EN (BIT(31))
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#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
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#define LP_CLKRST_CLK_EN_V 0x00000001U
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#define LP_CLKRST_CLK_EN_S 31
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#ifdef __cplusplus
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}
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#endif
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