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https://github.com/espressif/esp-idf.git
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c572e0bf5f
Additionally, always enable the partition MD5 check if flash encryption is on in Release mode. This ensures the partition table ciphertext has not been modified (CVE-2021-27926). The exception is pre-V3.1 ESP-IDF bootloaders and partition tables, which don't have support for the MD5 entry.
932 lines
42 KiB
Plaintext
932 lines
42 KiB
Plaintext
menu "ESP32-specific"
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config ESP32_ECO3_CACHE_LOCK_FIX
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bool
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default y
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depends on !FREERTOS_UNICORE && ESP32_SPIRAM_SUPPORT
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choice ESP32_REV_MIN
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prompt "Minimum Supported ESP32 Revision"
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default ESP32_REV_MIN_0
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help
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Minimum revision that ESP-IDF would support.
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ESP-IDF performs different strategy on different esp32 revision.
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config ESP32_REV_MIN_0
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bool "Rev 0"
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config ESP32_REV_MIN_1
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bool "Rev 1"
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config ESP32_REV_MIN_2
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bool "Rev 2"
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config ESP32_REV_MIN_3
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bool "Rev 3"
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select ESP_INT_WDT if ESP32_ECO3_CACHE_LOCK_FIX
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endchoice
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config ESP32_REV_MIN
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int
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default 0 if ESP32_REV_MIN_0
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default 1 if ESP32_REV_MIN_1
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default 2 if ESP32_REV_MIN_2
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default 3 if ESP32_REV_MIN_3
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config ESP32_DPORT_WORKAROUND
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bool
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default "y" if !FREERTOS_UNICORE && ESP32_REV_MIN < 2
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choice ESP32_DEFAULT_CPU_FREQ_MHZ
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prompt "CPU frequency"
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default ESP32_DEFAULT_CPU_FREQ_160
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help
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CPU frequency to be set on application startup.
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config ESP32_DEFAULT_CPU_FREQ_80
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bool "80 MHz"
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config ESP32_DEFAULT_CPU_FREQ_160
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bool "160 MHz"
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config ESP32_DEFAULT_CPU_FREQ_240
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bool "240 MHz"
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endchoice
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config ESP32_DEFAULT_CPU_FREQ_MHZ
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int
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default 80 if ESP32_DEFAULT_CPU_FREQ_80
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default 160 if ESP32_DEFAULT_CPU_FREQ_160
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default 240 if ESP32_DEFAULT_CPU_FREQ_240
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config ESP32_SPIRAM_SUPPORT
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bool "Support for external, SPI-connected RAM"
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default "n"
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help
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This enables support for an external SPI RAM chip, connected in parallel with the
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main SPI flash chip.
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menu "SPI RAM config"
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depends on ESP32_SPIRAM_SUPPORT
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config SPIRAM_BOOT_INIT
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bool "Initialize SPI RAM when booting the ESP32"
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default "y"
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help
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If this is enabled, the SPI RAM will be enabled during initial boot. Unless you
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have specific requirements, you'll want to leave this enabled so memory allocated
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during boot-up can also be placed in SPI RAM.
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config SPIRAM_IGNORE_NOTFOUND
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bool "Ignore PSRAM when not found"
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default "n"
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depends on SPIRAM_BOOT_INIT && !SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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help
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Normally, if psram initialization is enabled during compile time but not found at runtime, it
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is seen as an error making the ESP32 panic. If this is enabled, the ESP32 will keep on
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running but will not add the (non-existing) RAM to any allocator.
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choice SPIRAM_USE
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prompt "SPI RAM access method"
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default SPIRAM_USE_MALLOC
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help
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The SPI RAM can be accessed in multiple methods: by just having it available as an unmanaged
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memory region in the ESP32 memory map, by integrating it in the ESP32s heap as 'special' memory
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needing heap_caps_malloc to allocate, or by fully integrating it making malloc() also able to
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return SPI RAM pointers.
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config SPIRAM_USE_MEMMAP
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bool "Integrate RAM into ESP32 memory map"
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config SPIRAM_USE_CAPS_ALLOC
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bool "Make RAM allocatable using heap_caps_malloc(..., MALLOC_CAP_SPIRAM)"
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config SPIRAM_USE_MALLOC
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bool "Make RAM allocatable using malloc() as well"
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select FREERTOS_SUPPORT_STATIC_ALLOCATION
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endchoice
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choice SPIRAM_TYPE
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prompt "Type of SPI RAM chip in use"
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default SPIRAM_TYPE_AUTO
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config SPIRAM_TYPE_AUTO
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bool "Auto-detect"
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config SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32 or IS25WP032"
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config SPIRAM_TYPE_ESPPSRAM64
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bool "ESP-PSRAM64 or LY68L6400"
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endchoice
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config SPIRAM_SIZE
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int
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default -1 if SPIRAM_TYPE_AUTO
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default 4194304 if SPIRAM_TYPE_ESPPSRAM32
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default 8388608 if SPIRAM_TYPE_ESPPSRAM64
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default 0
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choice SPIRAM_SPEED
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prompt "Set RAM clock speed"
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default SPIRAM_SPEED_40M
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help
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Select the speed for the SPI RAM chip.
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If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
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1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
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2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
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3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz
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Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
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will be occupied by the system. Which SPI host to use can be selected by the config item
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SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
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option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
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(ESPTOOLPY_FLASHFREQ_80M is true)
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config SPIRAM_SPEED_40M
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bool "40MHz clock speed"
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config SPIRAM_SPEED_80M
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depends on ESPTOOLPY_FLASHFREQ_80M
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bool "80MHz clock speed"
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endchoice
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config SPIRAM_MEMTEST
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bool "Run memory test on SPI RAM initialization"
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default "y"
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depends on SPIRAM_BOOT_INIT
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help
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Runs a rudimentary memory test on initialization. Aborts when memory test fails. Disable this for
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slightly faster startop.
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config SPIRAM_CACHE_WORKAROUND
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bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
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depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
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default "y"
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help
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Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
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when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a
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fix in the compiler (-mfix-esp32-psram-cache-issue) that makes sure the specific code that is
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vulnerable to this will not be emitted.
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This will also not use any bits of newlib that are located in ROM, opting for a version that is
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compiled with the workaround and located in flash instead.
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The workaround is not required for ESP32 revision 3 and above.
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menu "SPIRAM cache workaround debugging"
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choice SPIRAM_CACHE_WORKAROUND_STRATEGY
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prompt "Workaround strategy"
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depends on SPIRAM_CACHE_WORKAROUND
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default SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
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help
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Select the workaround strategy. Note that the strategy for precompiled
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libraries (libgcc, newlib, bt, wifi) is not affected by this selection.
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Unless you know you need a different strategy, it's suggested you stay
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with the default MEMW strategy. Note that DUPLDST can interfere with hardware
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encryption and this will be automatically disabled if this workaround is selected.
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'Insert nops' is the workaround that was used in older esp-idf versions. This workaround
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still can cause faulty data transfers from/to SPI RAM in some situation.
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config SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
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bool "Insert memw after vulnerable instructions (default)"
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config SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
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bool "Duplicate LD/ST for 32-bit, memw for 8/16 bit"
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config SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS
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bool "Insert nops between vulnerable loads/stores (old strategy, obsolete)"
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endchoice
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#This needs to be Y only for the dupldst workaround
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config SPIRAM_WORKAROUND_NEED_VOLATILE_SPINLOCK
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bool
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default "y" if SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
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endmenu
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config SPIRAM_BANKSWITCH_ENABLE
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bool "Enable bank switching for >4MiB external RAM"
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default y
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depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
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help
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The ESP32 only supports 4MiB of external RAM in its address space. The hardware does support larger
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memories, but these have to be bank-switched in and out of this address space. Enabling this allows you
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to reserve some MMU pages for this, which allows the use of the esp_himem api to manage these banks.
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#Note that this is limited to 62 banks, as esp_spiram_writeback_cache needs some kind of mapping of
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#some banks below that mark to work. We cannot at this moment guarantee this to exist when himem is
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#enabled.
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If spiram 2T mode is enabled, the size of 64Mbit psram will be changed as 32Mbit, so himem will be
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unusable.
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config SPIRAM_BANKSWITCH_RESERVE
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int "Amount of 32K pages to reserve for bank switching"
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depends on SPIRAM_BANKSWITCH_ENABLE
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default 8
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range 1 62
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help
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Select the amount of banks reserved for bank switching. Note that the amount of RAM allocatable with
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malloc/esp_heap_alloc_caps will decrease by 32K for each page reserved here.
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Note that this reservation is only actually done if your program actually uses the himem API. Without
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any himem calls, the reservation is not done and the original amount of memory will be available
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to malloc/esp_heap_alloc_caps.
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config SPIRAM_MALLOC_ALWAYSINTERNAL
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int "Maximum malloc() size, in bytes, to always put in internal memory"
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depends on SPIRAM_USE_MALLOC
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default 16384
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range 0 131072
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help
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If malloc() is capable of also allocating SPI-connected ram, its allocation strategy will prefer to
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allocate chunks less than this size in internal memory, while allocations larger than this will be
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done from external RAM. If allocation from the preferred region fails, an attempt is made to allocate
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from the non-preferred region instead, so malloc() will not suddenly fail when either internal or
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external memory is full.
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config SPIRAM_TRY_ALLOCATE_WIFI_LWIP
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bool "Try to allocate memories of WiFi and LWIP in SPIRAM firstly. If failed, allocate internal memory"
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depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
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default "n"
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help
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Try to allocate memories of WiFi and LWIP in SPIRAM firstly. If failed, try to allocate internal
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memory then.
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config SPIRAM_MALLOC_RESERVE_INTERNAL
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int "Reserve this amount of bytes for data that specifically needs to be in DMA or internal memory"
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depends on SPIRAM_USE_MALLOC
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default 32768
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range 0 262144
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help
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Because the external/internal RAM allocation strategy is not always perfect, it sometimes may happen
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that the internal memory is entirely filled up. This causes allocations that are specifically done in
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internal memory, for example the stack for new tasks or memory to service DMA or have memory that's
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also available when SPI cache is down, to fail. This option reserves a pool specifically for requests
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like that; the memory in this pool is not given out when a normal malloc() is called.
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Set this to 0 to disable this feature.
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Note that because FreeRTOS stacks are forced to internal memory, they will also use this memory pool;
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be sure to keep this in mind when adjusting this value.
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Note also that the DMA reserved pool may not be one single contiguous memory region, depending on the
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configured size and the static memory usage of the app.
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config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
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bool "Allow external memory as an argument to xTaskCreateStatic"
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default n
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depends on SPIRAM_USE_MALLOC
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help
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Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround,
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normally tasks cannot be safely run with their stack residing in external memory; for this reason
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xTaskCreate and friends always allocate stack in internal memory and xTaskCreateStatic will check if
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the memory passed to it is in internal memory. If you have a task that needs a large amount of stack
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and does not call on ROM code in any way (no direct calls, but also no Bluetooth/WiFi), you can try to
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disable this and use xTaskCreateStatic to create the tasks stack in external memory.
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config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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bool "Allow .bss segment placed in external memory"
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default n
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depends on ESP32_SPIRAM_SUPPORT
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help
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If enabled the option,and add EXT_RAM_ATTR defined your variable,then your variable will be placed in
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PSRAM instead of internal memory, and placed most of variables of lwip,net802.11,pp,bluedroid library
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to external memory defaultly.
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choice SPIRAM_OCCUPY_SPI_HOST
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prompt "SPI host to use for 32MBit PSRAM"
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default SPIRAM_OCCUPY_VSPI_HOST
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depends on SPIRAM_SPEED_80M
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help
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When both flash and PSRAM is working under 80MHz, and the PSRAM is of type 32MBit, one of the HSPI/VSPI
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host will be used to output the clock. Select which one to use here.
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config SPIRAM_OCCUPY_HSPI_HOST
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bool "HSPI host (SPI2)"
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config SPIRAM_OCCUPY_VSPI_HOST
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bool "VSPI host (SPI3)"
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config SPIRAM_OCCUPY_NO_HOST
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bool "Will not try to use any host, will abort if not able to use the PSRAM"
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endchoice
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menu "PSRAM clock and cs IO for ESP32-DOWD"
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config D0WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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depends on ESP32_SPIRAM_SUPPORT
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range 0 33
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default 17
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D0WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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depends on ESP32_SPIRAM_SUPPORT
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range 0 33
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default 16
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-D2WD"
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config D2WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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depends on ESP32_SPIRAM_SUPPORT
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range 0 33
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default 9
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D2WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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depends on ESP32_SPIRAM_SUPPORT
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range 0 33
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default 10
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu
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menu "PSRAM clock and cs IO for ESP32-PICO"
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config PICO_PSRAM_CS_IO
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int "PSRAM CS IO number"
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depends on ESP32_SPIRAM_SUPPORT
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range 0 33
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default 10
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
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For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
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IO.
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For the reference hardware design, please refer to
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https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
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endmenu
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config SPIRAM_SPIWP_SD3_PIN
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int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
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depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
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range 0 33
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default 7
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help
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This value is ignored unless flash mode is set to DIO or DOUT and the SPI flash pins have been
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overriden by setting the eFuses SPI_PAD_CONFIG_xxx.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
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ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. And the psram only has QPI
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mode, the WP pin is necessary, so we need to configure this value here.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set as the value configured in
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bootloader.
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For ESP32-PICO chip, the default value of this config should be 7.
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config SPIRAM_2T_MODE
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bool "Enable SPI PSRAM 2T mode"
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depends on ESP32_SPIRAM_SUPPORT
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default "n"
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help
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Enable this option to fix single bit errors inside 64Mbit PSRAM.
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Some 64Mbit PSRAM chips have a hardware issue in the RAM which causes bit errors at multiple
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fixed bit positions.
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Note: If this option is enabled, the 64Mbit PSRAM chip will appear to be 32Mbit in size.
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Applications will not be affected unless the use the esp_himem APIs, which are not supported
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in 2T mode.
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endmenu # "SPI RAM config"
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config ESP32_MEMMAP_TRACEMEM
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bool
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default "n"
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config ESP32_MEMMAP_TRACEMEM_TWOBANKS
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bool
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default "n"
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config ESP32_TRAX
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bool "Use TRAX tracing feature"
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default "n"
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select ESP32_MEMMAP_TRACEMEM
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help
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The ESP32 contains a feature which allows you to trace the execution path the processor
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has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
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of memory that can't be used for general purposes anymore. Disable this if you do not know
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what this is.
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config ESP32_TRAX_TWOBANKS
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bool "Reserve memory for tracing both pro as well as app cpu execution"
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default "n"
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depends on ESP32_TRAX && !FREERTOS_UNICORE
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select ESP32_MEMMAP_TRACEMEM_TWOBANKS
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help
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The ESP32 contains a feature which allows you to trace the execution path the processor
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has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
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of memory that can't be used for general purposes anymore. Disable this if you do not know
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what this is.
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# Memory to reverse for trace, used in linker script
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config ESP32_TRACEMEM_RESERVE_DRAM
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hex
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default 0x8000 if ESP32_MEMMAP_TRACEMEM && ESP32_MEMMAP_TRACEMEM_TWOBANKS
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default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS
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default 0x0
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choice ESP32_UNIVERSAL_MAC_ADDRESSES
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bool "Number of universally administered (by IEEE) MAC address"
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default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
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help
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Configure the number of universally administered (by IEEE) MAC addresses.
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During initialisation, MAC addresses for each network interface are generated or derived from a
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single base MAC address.
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If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
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Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
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sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
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If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
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receive a universally administered MAC address. These are generated sequentially by adding 0
|
|
and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
|
|
receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
|
|
addresses, respectively.
|
|
When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
|
|
a custom universal MAC address range, the correct setting will depend on the allocation of MAC
|
|
addresses in this range (either 2 or 4 per device.)
|
|
|
|
config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
|
|
bool "Two"
|
|
config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
|
|
bool "Four"
|
|
endchoice
|
|
|
|
config ESP32_UNIVERSAL_MAC_ADDRESSES
|
|
int
|
|
default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
|
|
default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
|
|
|
|
|
|
config ESP32_ULP_COPROC_ENABLED
|
|
bool "Enable Ultra Low Power (ULP) Coprocessor"
|
|
default "n"
|
|
help
|
|
Set to 'y' if you plan to load a firmware for the coprocessor.
|
|
|
|
If this option is enabled, further coprocessor configuration will appear in the Components menu.
|
|
|
|
config ESP32_ULP_COPROC_RESERVE_MEM
|
|
int
|
|
prompt "RTC slow memory reserved for coprocessor" if ESP32_ULP_COPROC_ENABLED
|
|
default 512 if ESP32_ULP_COPROC_ENABLED
|
|
range 32 8192 if ESP32_ULP_COPROC_ENABLED
|
|
default 0 if !ESP32_ULP_COPROC_ENABLED
|
|
range 0 0 if !ESP32_ULP_COPROC_ENABLED
|
|
help
|
|
Bytes of memory to reserve for ULP coprocessor firmware & data.
|
|
|
|
Data is reserved at the beginning of RTC slow memory.
|
|
|
|
choice ESP32_PANIC
|
|
prompt "Panic handler behaviour"
|
|
default ESP32_PANIC_PRINT_REBOOT
|
|
help
|
|
If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
|
|
invoked. Configure the panic handlers action here.
|
|
|
|
config ESP32_PANIC_PRINT_HALT
|
|
bool "Print registers and halt"
|
|
help
|
|
Outputs the relevant registers over the serial port and halt the
|
|
processor. Needs a manual reset to restart.
|
|
|
|
config ESP32_PANIC_PRINT_REBOOT
|
|
bool "Print registers and reboot"
|
|
help
|
|
Outputs the relevant registers over the serial port and immediately
|
|
reset the processor.
|
|
|
|
config ESP32_PANIC_SILENT_REBOOT
|
|
bool "Silent reboot"
|
|
help
|
|
Just resets the processor without outputting anything
|
|
|
|
config ESP32_PANIC_GDBSTUB
|
|
bool "Invoke GDBStub"
|
|
select ESP_GDBSTUB_ENABLED
|
|
help
|
|
Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
|
|
of the crash.
|
|
endchoice
|
|
|
|
config ESP32_DEBUG_OCDAWARE
|
|
bool "Make exception and panic handlers JTAG/OCD aware"
|
|
default y
|
|
help
|
|
The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
|
|
instead of panicking, have the debugger stop on the offending instruction.
|
|
|
|
config ESP32_DEBUG_STUBS_ENABLE
|
|
bool "OpenOCD debug stubs"
|
|
default COMPILER_OPTIMIZATION_LEVEL_DEBUG
|
|
depends on !ESP32_TRAX
|
|
help
|
|
Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging,
|
|
e.g. GCOV data dump.
|
|
|
|
config ESP32_BROWNOUT_DET
|
|
#The brownout detector code is disabled (by making it depend on a nonexisting symbol) because the current
|
|
#revision of ESP32 silicon has a bug in the brown-out detector, rendering it unusable for resetting the CPU.
|
|
bool "Hardware brownout detect & reset"
|
|
default y
|
|
help
|
|
The ESP32 has a built-in brownout detector which can detect if the voltage is lower than
|
|
a specific value. If this happens, it will reset the chip in order to prevent unintended
|
|
behaviour.
|
|
|
|
choice ESP32_BROWNOUT_DET_LVL_SEL
|
|
prompt "Brownout voltage level"
|
|
depends on ESP32_BROWNOUT_DET
|
|
default ESP32_BROWNOUT_DET_LVL_SEL_0
|
|
help
|
|
The brownout detector will reset the chip when the supply voltage is approximately
|
|
below this level. Note that there may be some variation of brownout voltage level
|
|
between each ESP32 chip.
|
|
|
|
#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
|
|
#of the brownout threshold levels.
|
|
config ESP32_BROWNOUT_DET_LVL_SEL_0
|
|
bool "2.43V +/- 0.05"
|
|
config ESP32_BROWNOUT_DET_LVL_SEL_1
|
|
bool "2.48V +/- 0.05"
|
|
config ESP32_BROWNOUT_DET_LVL_SEL_2
|
|
bool "2.58V +/- 0.05"
|
|
config ESP32_BROWNOUT_DET_LVL_SEL_3
|
|
bool "2.62V +/- 0.05"
|
|
config ESP32_BROWNOUT_DET_LVL_SEL_4
|
|
bool "2.67V +/- 0.05"
|
|
config ESP32_BROWNOUT_DET_LVL_SEL_5
|
|
bool "2.70V +/- 0.05"
|
|
config ESP32_BROWNOUT_DET_LVL_SEL_6
|
|
bool "2.77V +/- 0.05"
|
|
config ESP32_BROWNOUT_DET_LVL_SEL_7
|
|
bool "2.80V +/- 0.05"
|
|
endchoice
|
|
|
|
config ESP32_BROWNOUT_DET_LVL
|
|
int
|
|
default 0 if ESP32_BROWNOUT_DET_LVL_SEL_0
|
|
default 1 if ESP32_BROWNOUT_DET_LVL_SEL_1
|
|
default 2 if ESP32_BROWNOUT_DET_LVL_SEL_2
|
|
default 3 if ESP32_BROWNOUT_DET_LVL_SEL_3
|
|
default 4 if ESP32_BROWNOUT_DET_LVL_SEL_4
|
|
default 5 if ESP32_BROWNOUT_DET_LVL_SEL_5
|
|
default 6 if ESP32_BROWNOUT_DET_LVL_SEL_6
|
|
default 7 if ESP32_BROWNOUT_DET_LVL_SEL_7
|
|
|
|
|
|
#Reduce PHY TX power when brownout reset
|
|
config ESP32_REDUCE_PHY_TX_POWER
|
|
bool "Reduce PHY TX power when brownout reset"
|
|
depends on ESP32_BROWNOUT_DET
|
|
default y
|
|
help
|
|
When brownout reset occurs, reduce PHY TX power to keep the code running
|
|
|
|
# Note about the use of "FRC1" name: currently FRC1 timer is not used for
|
|
# high resolution timekeeping anymore. Instead the esp_timer API, implemented
|
|
# using FRC2 timer, is used.
|
|
# FRC1 name in the option name is kept for compatibility.
|
|
choice ESP32_TIME_SYSCALL
|
|
prompt "Timers used for gettimeofday function"
|
|
default ESP32_TIME_SYSCALL_USE_RTC_FRC1
|
|
help
|
|
This setting defines which hardware timers are used to
|
|
implement 'gettimeofday' and 'time' functions in C library.
|
|
|
|
- If both high-resolution and RTC timers are used, timekeeping will
|
|
continue in deep sleep. Time will be reported at 1 microsecond
|
|
resolution. This is the default, and the recommended option.
|
|
- If only high-resolution timer is used, gettimeofday will
|
|
provide time at microsecond resolution.
|
|
Time will not be preserved when going into deep sleep mode.
|
|
- If only RTC timer is used, timekeeping will continue in
|
|
deep sleep, but time will be measured at 6.(6) microsecond
|
|
resolution. Also the gettimeofday function itself may take
|
|
longer to run.
|
|
- If no timers are used, gettimeofday and time functions
|
|
return -1 and set errno to ENOSYS.
|
|
- When RTC is used for timekeeping, two RTC_STORE registers are
|
|
used to keep time in deep sleep mode.
|
|
|
|
config ESP32_TIME_SYSCALL_USE_RTC_FRC1
|
|
bool "RTC and high-resolution timer"
|
|
config ESP32_TIME_SYSCALL_USE_RTC
|
|
bool "RTC"
|
|
config ESP32_TIME_SYSCALL_USE_FRC1
|
|
bool "High-resolution timer"
|
|
config ESP32_TIME_SYSCALL_USE_NONE
|
|
bool "None"
|
|
endchoice
|
|
|
|
choice ESP32_RTC_CLK_SRC
|
|
prompt "RTC clock source"
|
|
default ESP32_RTC_CLK_SRC_INT_RC
|
|
help
|
|
Choose which clock is used as RTC clock source.
|
|
|
|
- "Internal 150kHz oscillator" option provides lowest deep sleep current
|
|
consumption, and does not require extra external components. However
|
|
frequency stability with respect to temperature is poor, so time may
|
|
drift in deep/light sleep modes.
|
|
- "External 32kHz crystal" provides better frequency stability, at the
|
|
expense of slightly higher (1uA) deep sleep current consumption.
|
|
- "External 32kHz oscillator" allows using 32kHz clock generated by an
|
|
external circuit. In this case, external clock signal must be connected
|
|
to 32K_XP pin. Amplitude should be <1.2V in case of sine wave signal,
|
|
and <1V in case of square wave signal. Common mode voltage should be
|
|
0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
|
|
Additionally, 1nF capacitor must be connected between 32K_XN pin and
|
|
ground. 32K_XN pin can not be used as a GPIO in this case.
|
|
- "Internal 8.5MHz oscillator divided by 256" option results in higher
|
|
deep sleep current (by 5uA) but has better frequency stability than
|
|
the internal 150kHz oscillator. It does not require external components.
|
|
|
|
config ESP32_RTC_CLK_SRC_INT_RC
|
|
bool "Internal 150kHz RC oscillator"
|
|
config ESP32_RTC_CLK_SRC_EXT_CRYS
|
|
bool "External 32kHz crystal"
|
|
config ESP32_RTC_CLK_SRC_EXT_OSC
|
|
bool "External 32kHz oscillator at 32K_XP pin"
|
|
config ESP32_RTC_CLK_SRC_INT_8MD256
|
|
bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
|
|
endchoice
|
|
|
|
config ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
|
|
bool "Additional current for external 32kHz crystal"
|
|
depends on ESP32_RTC_CLK_SRC_EXT_CRYS
|
|
default "n"
|
|
help
|
|
Choose which additional current is used for rtc external crystal.
|
|
|
|
- With some 32kHz crystal configurations, the X32N and X32P pins may not
|
|
have enough drive strength to keep the crystal oscillating during deep sleep.
|
|
If this option is enabled, additional current from touchpad 9 is provided
|
|
internally to drive the 32kHz crystal. If this option is enabled, deep sleep current
|
|
is slightly higher (4-5uA) and the touchpad and ULP wakeup sources are not available.
|
|
|
|
config ESP32_RTC_CLK_CAL_CYCLES
|
|
int "Number of cycles for RTC_SLOW_CLK calibration"
|
|
default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256
|
|
default 1024 if ESP32_RTC_CLK_SRC_INT_RC
|
|
range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256
|
|
range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC
|
|
help
|
|
When the startup code initializes RTC_SLOW_CLK, it can perform
|
|
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
|
|
frequency. This option sets the number of RTC_SLOW_CLK cycles measured
|
|
by the calibration routine. Higher numbers increase calibration
|
|
precision, which may be important for applications which spend a lot of
|
|
time in deep sleep. Lower numbers reduce startup time.
|
|
|
|
When this option is set to 0, clock calibration will not be performed at
|
|
startup, and approximate clock frequencies will be assumed:
|
|
|
|
- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
|
|
- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
|
|
In case more value will help improve the definition of the launch of the crystal.
|
|
If the crystal could not start, it will be switched to internal RC.
|
|
|
|
config ESP32_RTC_XTAL_CAL_RETRY
|
|
int "Number of attempts to repeat 32k XTAL calibration"
|
|
default 1
|
|
help
|
|
Number of attempts to repeat 32k XTAL calibration
|
|
before giving up and switching to the internal RC.
|
|
Increase this option if the 32k crystal oscillator
|
|
does not start and switches to internal RC.
|
|
|
|
config ESP32_RTC_XTAL_BOOTSTRAP_CYCLES
|
|
int "Bootstrap cycles for external 32kHz crystal"
|
|
depends on ESP32_RTC_CLK_SRC_EXT_CRYS
|
|
default 5
|
|
range 0 32768
|
|
help
|
|
To reduce the startup time of an external RTC crystal,
|
|
we bootstrap it with a 32kHz square wave for a fixed number of cycles.
|
|
Setting 0 will disable bootstrapping (if disabled, the crystal may take
|
|
longer to start up or fail to oscillate under some conditions).
|
|
|
|
If this value is too high, a faulty crystal may initially start and then fail.
|
|
If this value is too low, an otherwise good crystal may not start.
|
|
|
|
To accurately determine if the crystal has started,
|
|
set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
|
|
|
|
config ESP32_DEEP_SLEEP_WAKEUP_DELAY
|
|
int "Extra delay in deep sleep wake stub (in us)"
|
|
default 2000
|
|
range 0 5000
|
|
help
|
|
When ESP32 exits deep sleep, the CPU and the flash chip are powered on
|
|
at the same time. CPU will run deep sleep stub first, and then
|
|
proceed to load code from flash. Some flash chips need sufficient
|
|
time to pass between power on and first read operation. By default,
|
|
without any extra delay, this time is approximately 900us, although
|
|
some flash chip types need more than that.
|
|
|
|
By default extra delay is set to 2000us. When optimizing startup time
|
|
for applications which require it, this value may be reduced.
|
|
|
|
If you are seeing "flash read err, 1000" message printed to the
|
|
console after deep sleep reset, try increasing this value.
|
|
|
|
choice ESP32_XTAL_FREQ_SEL
|
|
prompt "Main XTAL frequency"
|
|
default ESP32_XTAL_FREQ_40
|
|
help
|
|
ESP32 currently supports the following XTAL frequencies:
|
|
|
|
- 26 MHz
|
|
- 40 MHz
|
|
|
|
Startup code can automatically estimate XTAL frequency. This feature
|
|
uses the internal 8MHz oscillator as a reference. Because the internal
|
|
oscillator frequency is temperature dependent, it is not recommended
|
|
to use automatic XTAL frequency detection in applications which need
|
|
to work at high ambient temperatures and use high-temperature
|
|
qualified chips and modules.
|
|
config ESP32_XTAL_FREQ_40
|
|
bool "40 MHz"
|
|
config ESP32_XTAL_FREQ_26
|
|
bool "26 MHz"
|
|
config ESP32_XTAL_FREQ_AUTO
|
|
bool "Autodetect"
|
|
endchoice
|
|
|
|
# Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h
|
|
config ESP32_XTAL_FREQ
|
|
int
|
|
default 0 if ESP32_XTAL_FREQ_AUTO
|
|
default 40 if ESP32_XTAL_FREQ_40
|
|
default 26 if ESP32_XTAL_FREQ_26
|
|
|
|
config ESP32_DISABLE_BASIC_ROM_CONSOLE
|
|
bool "Permanently disable BASIC ROM Console"
|
|
default n
|
|
help
|
|
If set, the first time the app boots it will disable the BASIC ROM Console
|
|
permanently (by burning an eFuse).
|
|
|
|
Otherwise, the BASIC ROM Console starts on reset if no valid bootloader is
|
|
read from the flash.
|
|
|
|
(Enabling secure boot also disables the BASIC ROM Console by default.)
|
|
|
|
config ESP32_NO_BLOBS
|
|
bool "No Binary Blobs"
|
|
depends on !BT_ENABLED
|
|
default n
|
|
help
|
|
If enabled, this disables the linking of binary libraries in the application build. Note
|
|
that after enabling this Wi-Fi/Bluetooth will not work.
|
|
|
|
config ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
|
|
bool "App compatible with bootloaders before ESP-IDF v2.1"
|
|
select ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS
|
|
default n
|
|
help
|
|
Bootloaders before ESP-IDF v2.1 did less initialisation of the
|
|
system clock. This setting needs to be enabled to build an app
|
|
which can be booted by these older bootloaders.
|
|
|
|
If this setting is enabled, the app can be booted by any bootloader
|
|
from IDF v1.0 up to the current version.
|
|
|
|
If this setting is disabled, the app can only be booted by bootloaders
|
|
from IDF v2.1 or newer.
|
|
|
|
Enabling this setting adds approximately 1KB to the app's IRAM usage.
|
|
|
|
config ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS
|
|
bool "App compatible with bootloader and partition table before ESP-IDF v3.1"
|
|
default n
|
|
help
|
|
Partition tables before ESP-IDF V3.1 do not contain an MD5 checksum
|
|
field, and the bootloader before ESP-IDF v3.1 cannot read a partition
|
|
table that contains an MD5 checksum field.
|
|
|
|
Enable this option only if your app needs to boot on a bootloader and/or
|
|
partition table that was generated from a version *before* ESP-IDF v3.1.
|
|
|
|
If this option and Flash Encryption are enabled at the same time, and any
|
|
data partitions in the partition table are marked Encrypted, then the
|
|
partition encrypted flag should be manually verified in the app before accessing
|
|
the partition (see CVE-2021-27926).
|
|
|
|
config ESP32_RTCDATA_IN_FAST_MEM
|
|
bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
|
|
default n
|
|
depends on FREERTOS_UNICORE
|
|
help
|
|
This option allows to place .rtc_data and .rtc_rodata sections into
|
|
RTC fast memory segment to free the slow memory region for ULP programs.
|
|
This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory
|
|
can be accessed only by PRO_CPU core.
|
|
|
|
config ESP32_USE_FIXED_STATIC_RAM_SIZE
|
|
bool "Use fixed static RAM size"
|
|
default n
|
|
help
|
|
If this option is disabled, the DRAM part of the heap starts right after the .bss section,
|
|
within the dram0_0 region. As a result, adding or removing some static variables
|
|
will change the available heap size.
|
|
|
|
If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
|
|
where its length is set with ESP32_FIXED_STATIC_RAM_SIZE
|
|
|
|
config ESP32_FIXED_STATIC_RAM_SIZE
|
|
hex "Fixed Static RAM size"
|
|
default 0x1E000
|
|
range 0 0x2c200
|
|
depends on ESP32_USE_FIXED_STATIC_RAM_SIZE
|
|
help
|
|
RAM size dedicated for static variables (.data & .bss sections).
|
|
Please note that the actual length will be reduced by BT_RESERVE_DRAM if Bluetooth
|
|
controller is enabled.
|
|
|
|
config ESP32_DPORT_DIS_INTERRUPT_LVL
|
|
int "Disable the interrupt level for the DPORT workarounds"
|
|
default 5
|
|
help
|
|
To prevent interrupting DPORT workarounds,
|
|
need to disable interrupt with a maximum used level in the system.
|
|
|
|
endmenu # ESP32-Specific
|
|
|
|
menu "Power Management"
|
|
|
|
config PM_ENABLE
|
|
bool "Support for power management"
|
|
default n
|
|
help
|
|
If enabled, application is compiled with support for power management.
|
|
This option has run-time overhead (increased interrupt latency,
|
|
longer time to enter idle state), and it also reduces accuracy of
|
|
RTOS ticks and timers used for timekeeping.
|
|
Enable this option if application uses power management APIs.
|
|
|
|
config PM_DFS_INIT_AUTO
|
|
bool "Enable dynamic frequency scaling (DFS) at startup"
|
|
depends on PM_ENABLE
|
|
default n
|
|
help
|
|
If enabled, startup code configures dynamic frequency scaling.
|
|
Max CPU frequency is set to CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ setting,
|
|
min frequency is set to XTAL frequency.
|
|
If disabled, DFS will not be active until the application
|
|
configures it using esp_pm_configure function.
|
|
|
|
config PM_USE_RTC_TIMER_REF
|
|
bool "Use RTC timer to prevent time drift (EXPERIMENTAL)"
|
|
depends on PM_ENABLE && (ESP32_TIME_SYSCALL_USE_RTC || ESP32_TIME_SYSCALL_USE_RTC_FRC1)
|
|
default n
|
|
help
|
|
When APB clock frequency changes, high-resolution timer (esp_timer)
|
|
scale and base value need to be adjusted. Each adjustment may cause
|
|
small error, and over time such small errors may cause time drift.
|
|
If this option is enabled, RTC timer will be used as a reference to
|
|
compensate for the drift.
|
|
It is recommended that this option is only used if 32k XTAL is selected
|
|
as RTC clock source.
|
|
|
|
config PM_PROFILING
|
|
bool "Enable profiling counters for PM locks"
|
|
depends on PM_ENABLE
|
|
default n
|
|
help
|
|
If enabled, esp_pm_* functions will keep track of the amount of time
|
|
each of the power management locks has been held, and esp_pm_dump_locks
|
|
function will print this information.
|
|
This feature can be used to analyze which locks are preventing the chip
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from going into a lower power state, and see what time the chip spends
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in each power saving mode. This feature does incur some run-time
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overhead, so should typically be disabled in production builds.
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config PM_TRACE
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bool "Enable debug tracing of PM using GPIOs"
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depends on PM_ENABLE
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default n
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help
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If enabled, some GPIOs will be used to signal events such as RTOS ticks,
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frequency switching, entry/exit from idle state. Refer to pm_trace.c
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file for the list of GPIOs.
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This feature is intended to be used when analyzing/debugging behavior
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of power management implementation, and should be kept disabled in
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applications.
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endmenu # "Power Management"
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