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https://github.com/espressif/esp-idf.git
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f09b8ae7a4
Based on internal commit 3ef01301fffa552d4be6d81bc9d199c223224305
126 lines
4.5 KiB
C
126 lines
4.5 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "hal/adc_hal.h"
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#if !CONFIG_IDF_TARGET_ESP32C3
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#include "hal/adc_hal_conf.h"
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#endif
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void adc_hal_init(void)
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{
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// Set internal FSM wait time, fixed value.
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adc_ll_digi_set_fsm_time(SOC_ADC_FSM_RSTB_WAIT_DEFAULT, SOC_ADC_FSM_START_WAIT_DEFAULT,
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SOC_ADC_FSM_STANDBY_WAIT_DEFAULT);
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adc_ll_set_sample_cycle(ADC_FSM_SAMPLE_CYCLE_DEFAULT);
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adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT);
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adc_ll_digi_output_invert(ADC_NUM_1, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_1));
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adc_ll_digi_output_invert(ADC_NUM_2, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_2));
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adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
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}
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void adc_hal_deinit(void)
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{
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adc_ll_set_power_manage(ADC_POWER_SW_OFF);
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}
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int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value)
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{
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adc_ll_rtc_enable_channel(adc_n, channel);
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adc_ll_rtc_start_convert(adc_n, channel);
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while (adc_ll_rtc_convert_is_done(adc_n) != true);
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*value = adc_ll_rtc_get_convert_value(adc_n);
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return (int)adc_ll_rtc_analysis_raw_data(adc_n, (uint16_t)(*value));
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}
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#if CONFIG_IDF_TARGET_ESP32C3
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//This feature is currently supported on ESP32C3, will be supported on other chips soon
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/*---------------------------------------------------------------
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DMA setting
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---------------------------------------------------------------*/
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void adc_hal_digi_dma_multi_descriptor(adc_dma_hal_config_t *dma_config, uint8_t *data_buf, uint32_t size, uint32_t num)
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{
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assert(((uint32_t)data_buf % 4) == 0);
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assert((size % 4) == 0);
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dma_descriptor_t *desc = dma_config->rx_desc;
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uint32_t n = 0;
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while (num--) {
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desc[n].dw0.size = size;
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desc[n].dw0.suc_eof = 0;
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desc[n].dw0.owner = 1;
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desc[n].buffer = data_buf;
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desc[n].next = &desc[n+1];
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data_buf += size;
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n++;
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}
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desc[n-1].next = NULL;
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}
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void adc_hal_digi_rxdma_start(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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gdma_ll_rx_reset_channel(adc_dma_ctx->dev, dma_config->dma_chan);
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gdma_ll_rx_set_desc_addr(adc_dma_ctx->dev, dma_config->dma_chan, (uint32_t)dma_config->rx_desc);
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gdma_ll_rx_start(adc_dma_ctx->dev, dma_config->dma_chan);
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}
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void adc_hal_digi_rxdma_stop(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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gdma_ll_rx_stop(adc_dma_ctx->dev, dma_config->dma_chan);
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}
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void adc_hal_digi_ena_intr(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config, uint32_t mask)
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{
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gdma_ll_enable_interrupt(adc_dma_ctx->dev, dma_config->dma_chan, mask, true);
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}
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void adc_hal_digi_clr_intr(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config, uint32_t mask)
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{
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gdma_ll_clear_interrupt_status(adc_dma_ctx->dev, dma_config->dma_chan, mask);
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}
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void adc_hal_digi_dis_intr(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config, uint32_t mask)
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{
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gdma_ll_enable_interrupt(adc_dma_ctx->dev, dma_config->dma_chan, mask, false);
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}
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void adc_hal_digi_set_eof_num(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config, uint32_t num)
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{
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adc_ll_digi_dma_set_eof_num(num);
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}
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void adc_hal_digi_start(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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//Set to 1: the ADC data will be sent to the DMA
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adc_ll_digi_dma_enable();
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//enable sar adc timer
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adc_ll_digi_trigger_enable();
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}
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void adc_hal_digi_stop(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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//Set to 0: the ADC data won't be sent to the DMA
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adc_ll_digi_dma_disable();
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//disable sar adc timer
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adc_ll_digi_trigger_disable();
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}
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void adc_hal_digi_init(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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adc_dma_ctx->dev = &GDMA;
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gdma_ll_enable_clock(adc_dma_ctx->dev, true);
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gdma_ll_clear_interrupt_status(adc_dma_ctx->dev, dma_config->dma_chan, UINT32_MAX);
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gdma_ll_rx_connect_to_periph(adc_dma_ctx->dev, dma_config->dma_chan, GDMA_LL_TRIG_SRC_ADC_DAC);
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}
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#endif
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