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08600cb1a3
The commit 88e4c06028 introduced a loop timeout for all ULP RISC-V I2C
transactions to avoid getting stuck in a forever loop. The loop timeout
was set to 500 msec by default. This commit improves on the concept by
making the loop timeout configurable via a Kconfig option in terms of
CPU ticks. If the timeout is set to -1 value then the transaction loops
will never timeout, therefore restoring the driver behavior before the
timeout was introduced.
The commit also updates the I2C Fast mode timings for esp32s2 which need
to be adjusted due to bus timing constraints.
Closes https://github.com/espressif/esp-idf/issues/11154
142 lines
5.3 KiB
C
142 lines
5.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/gpio_types.h"
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#include "esp_err.h"
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/**
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* @brief ULP RISC-V RTC I2C pin config
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*/
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typedef struct {
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uint32_t sda_io_num; /*!< GPIO pin for SDA signal. Only GPIO#1 or GPIO#3 can be used as the SDA pin. */
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uint32_t scl_io_num; /*!< GPIO pin for SCL signal. Only GPIO#0 or GPIO#2 can be used as the SCL pin. */
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bool sda_pullup_en; /*!< SDA line enable internal pullup. Can be configured if external pullup is not used. */
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bool scl_pullup_en; /*!< SCL line enable internal pullup. Can be configured if external pullup is not used. */
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} ulp_riscv_i2c_pin_cfg_t;
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/**
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* @brief ULP RISC-V RTC I2C timing config
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*/
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typedef struct {
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float scl_low_period; /*!< SCL low period in micro seconds */
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float scl_high_period; /*!< SCL high period in micro seconds */
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float sda_duty_period; /*!< Period between the SDA switch and the falling edge of SCL in micro seconds */
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float scl_start_period; /*!< Waiting time after the START condition in micro seconds */
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float scl_stop_period; /*!< Waiting time before the END condition in micro seconds */
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float i2c_trans_timeout; /*!< I2C transaction timeout in micro seconds */
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} ulp_riscv_i2c_timing_cfg_t;
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/**
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* @brief ULP RISC-V RTC I2C init parameters
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*/
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typedef struct {
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ulp_riscv_i2c_pin_cfg_t i2c_pin_cfg; /*!< RTC I2C pin configuration */
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ulp_riscv_i2c_timing_cfg_t i2c_timing_cfg; /*!< RTC I2C timing configuration */
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} ulp_riscv_i2c_cfg_t;
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/* Default RTC I2C GPIO settings */
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#define ULP_RISCV_I2C_DEFAULT_GPIO_CONFIG() \
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.i2c_pin_cfg.sda_io_num = GPIO_NUM_3, \
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.i2c_pin_cfg.scl_io_num = GPIO_NUM_2, \
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.i2c_pin_cfg.sda_pullup_en = true, \
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.i2c_pin_cfg.scl_pullup_en = true, \
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#if CONFIG_IDF_TARGET_ESP32S3
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/* Nominal I2C bus timing parameters for I2C fast mode. Max SCL freq of 400 KHz. */
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#define ULP_RISCV_I2C_FAST_MODE_CONFIG() \
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.i2c_timing_cfg.scl_low_period = 1.4, \
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.i2c_timing_cfg.scl_high_period = 0.3, \
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.i2c_timing_cfg.sda_duty_period = 1, \
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.i2c_timing_cfg.scl_start_period = 2, \
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.i2c_timing_cfg.scl_stop_period = 1.3, \
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.i2c_timing_cfg.i2c_trans_timeout = 20,
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#elif CONFIG_IDF_TARGET_ESP32S2
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/* Nominal I2C bus timing parameters for I2C fast mode. Max SCL freq on S2 is about 233 KHz due to timing constraints. */
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#define ULP_RISCV_I2C_FAST_MODE_CONFIG() \
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.i2c_timing_cfg.scl_low_period = 2, \
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.i2c_timing_cfg.scl_high_period = 0.7, \
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.i2c_timing_cfg.sda_duty_period = 1.7, \
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.i2c_timing_cfg.scl_start_period = 2.4, \
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.i2c_timing_cfg.scl_stop_period = 1.3, \
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.i2c_timing_cfg.i2c_trans_timeout = 20,
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#endif
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/* Nominal I2C bus timing parameters for I2C standard mode. Max SCL freq of 100 KHz. */
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#define ULP_RISCV_I2C_STANDARD_MODE_CONFIG() \
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.i2c_timing_cfg.scl_low_period = 5, \
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.i2c_timing_cfg.scl_high_period = 5, \
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.i2c_timing_cfg.sda_duty_period = 2, \
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.i2c_timing_cfg.scl_start_period = 3, \
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.i2c_timing_cfg.scl_stop_period = 6, \
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.i2c_timing_cfg.i2c_trans_timeout = 20, \
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/* Default RTC I2C configuration settings. Uses I2C fast mode. */
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//TODO: Move to smaller units of time in the future like nano seconds to avoid floating point operations.
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#define ULP_RISCV_I2C_DEFAULT_CONFIG() \
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{ \
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ULP_RISCV_I2C_DEFAULT_GPIO_CONFIG() \
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ULP_RISCV_I2C_FAST_MODE_CONFIG() \
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}
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/**
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* @brief Set the I2C slave device address
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*
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* @param slave_addr I2C slave address (7 bit)
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*/
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void ulp_riscv_i2c_master_set_slave_addr(uint8_t slave_addr);
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/**
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* @brief Set the I2C slave device sub register address
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*
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* @note The RTC I2C peripheral always expects a slave sub register address to be programmed. If it is not, the I2C
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* peripheral uses the SENS_SAR_I2C_CTRL_REG[18:11] as the sub register address for the subsequent read or write
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* operation.
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*
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* @param slave_reg_addr I2C slave sub register address
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*/
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void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr);
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/**
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* @brief Read from I2C slave device
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*
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* @note The I2C slave device address must be configured at least once before invoking this API.
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*
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* @param data_rd Buffer to hold data to be read
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* @param size Size of data to be read in bytes
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*/
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void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
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/**
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* @brief Write to I2C slave device
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*
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* @note The I2C slave device address must be configured at least once before invoking this API.
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*
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* @param data_wr Buffer which holds the data to be written
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* @param size Size of data to be written in bytes
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*/
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void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size);
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/**
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* @brief Initialize and configure the RTC I2C for use by ULP RISC-V
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* Currently RTC I2C can only be used in master mode
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*
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* @param cfg Configuration parameters
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* @return esp_err_t ESP_OK when successful
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*/
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esp_err_t ulp_riscv_i2c_master_init(const ulp_riscv_i2c_cfg_t *cfg);
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#ifdef __cplusplus
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}
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#endif
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