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Flash operation complete flag was cleared by the core initiating flash operation. If the other core was running an ISR, then IPC task could be late to enter the loop to check s_flash_op_complete by the time next flash operation started. If the flag is cleared on the CPU waiting on this flag, then the race condition can not happen. |
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.. | ||
component.mk | ||
test_cache_disabled.c | ||
test_flash_encryption.c | ||
test_mmap.c | ||
test_partitions.c | ||
test_read_write.c | ||
test_spi_flash.c |