mirror of
https://github.com/espressif/esp-idf.git
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59cf87fe7d
Initialize the pmu sleep machine constant when pmu is initialized, and calculate the pmu sleep time adjustment value and hardware configuration value according to the machine constant during system sleep. Calibrate fast OSC before each sleep and use the calibration value to calculate PMU hardware wait cycles when use the fast OSC as the work clock.
93 lines
2.2 KiB
C
93 lines
2.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#ifndef CONFIG_IDF_TARGET_ESP32
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#include "soc/system_reg.h"
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#endif // not CONFIG_IDF_TARGET_ESP32
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#include "soc/rtc.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32H4
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#include "esp32h4/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/rtc.h"
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#include "esp_private/esp_pmu.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/rtc.h"
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#endif
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#include "esp_log.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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#include "esp_attr.h"
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static const char *TAG = "fpga";
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extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
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static void s_warn(void)
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{
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ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work");
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}
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void bootloader_clock_configure(void)
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{
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s_warn();
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esp_rom_uart_tx_wait_idle(0);
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uint32_t xtal_freq_mhz = 40;
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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uint32_t apb_freq_hz = 20000000;
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#elif CONFIG_IDF_TARGET_ESP32H4
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uint32_t apb_freq_hz = 32000000;
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#else
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uint32_t apb_freq_hz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000;
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#endif // CONFIG_IDF_TARGET_ESP32S2
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ets_update_cpu_frequency(apb_freq_hz / 1000000);
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#ifdef RTC_APB_FREQ_REG
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REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
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#endif
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REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
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}
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/* Placed in IRAM since test_apps expects it to be */
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void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
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{
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uint8_t *buffer_bytes = (uint8_t *)buffer;
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for (int i = 0; i < length; i++) {
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buffer_bytes[i] = 0x5A;
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}
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}
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void esp_clk_init(void)
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{
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s_warn();
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#if SOC_PMU_SUPPORTED
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pmu_init();
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#endif
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}
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void esp_perip_clk_init(void)
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{
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}
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/**
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* @brief No-op function, used to force linking this file
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*
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*/
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void esp_common_include_fpga_overrides(void)
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{
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}
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