Taavi Hein f7749e18a8 gpio: Bitmask overflow fix in gpio_reset_pin ...

For pins 32 and up the BIT(nr) macro used here overflowed,
causing undetermined GPIO pins to be reset.
Example: freeing SPI device/bus where CS is on pin 33
caused debug UART to cease communication, TXD0 was
disabled.

Fixed as BIT64(nr) macro, to be used elsewhere as needed.
For example in definitions like GPIO_SEL_32..GPIO_SEL_39.

2018-08-08 15:31:17 +03:00

..

soc

gpio: Bitmask overflow fix in gpio_reset_pin

2018-08-08 15:31:17 +03:00