mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
6b8d4dfe14
1. add check in the gdma driver, to prevent multiple channels connecting to the same peripheral 2. memory copy DMA ID will occupy the peripheral's DMA ID on some ESP targets (e.g. esp32c3/s3). We should search for a free one when install async memcpy driver. Closes https://github.com/espressif/esp-idf/issues/10575
480 lines
13 KiB
C
480 lines
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stddef.h> /* Required for NULL constant */
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/gdma_types.h"
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#include "soc/gdma_struct.h"
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#include "soc/gdma_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
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#define GDMA_LL_RX_EVENT_MASK (0x06A7)
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#define GDMA_LL_TX_EVENT_MASK (0x1958)
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// any "valid" peripheral ID can be used for M2M mode
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#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1CD)
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#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
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#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<12)
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#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<11)
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#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<10)
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#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<9)
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#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<8)
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#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<7)
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#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<6)
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#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<5)
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#define GDMA_LL_EVENT_TX_EOF (1<<4)
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#define GDMA_LL_EVENT_TX_DONE (1<<3)
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#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2)
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#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
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#define GDMA_LL_EVENT_RX_DONE (1<<0)
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///////////////////////////////////// Common /////////////////////////////////////////
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/**
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* @brief Enable DMA clock gating
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*/
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static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable)
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{
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dev->misc_conf.clk_en = enable;
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}
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///////////////////////////////////// RX /////////////////////////////////////////
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/**
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* @brief Get DMA RX channel interrupt status word
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
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}
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/**
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* @brief Enable DMA RX channel interrupt
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*/
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static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK);
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} else {
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dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK);
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}
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}
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/**
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* @brief Clear DMA RX channel interrupt
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK);
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}
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/**
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* @brief Get DMA RX channel interrupt status register address
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*/
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static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
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{
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return (volatile void *)(&dev->intr[channel].st);
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}
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/**
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* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
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*/
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static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf1.in_check_owner = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading data, disabled by default
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*/
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static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.in_data_burst_en = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
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*/
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static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_conf0.indscr_burst_en = enable;
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}
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/**
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* @brief Reset DMA RX channel FSM and FIFO pointer
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_conf0.in_rst = 1;
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dev->channel[channel].in.in_conf0.in_rst = 0;
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}
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/**
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* @brief Check if DMA RX FIFO is full
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* @param fifo_level only supports level 1
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*/
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static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.val & 0x01;
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}
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/**
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* @brief Check if DMA RX FIFO is empty
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* @param fifo_level only supports level 1
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*/
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static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.val & 0x02;
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}
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/**
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* @brief Get number of bytes in RX FIFO
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* @param fifo_level only supports level 1
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*/
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static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].in.infifo_status.infifo_cnt;
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}
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/**
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* @brief Pop data from DMA RX FIFO
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*/
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static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_pop.infifo_pop = 1;
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return dev->channel[channel].in.in_pop.infifo_rdata;
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}
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/**
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* @brief Set the descriptor link base address for RX channel
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
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{
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dev->channel[channel].in.in_link.addr = addr;
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}
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/**
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* @brief Start dealing with RX descriptors
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.start = 1;
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}
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/**
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* @brief Stop dealing with RX descriptors
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.stop = 1;
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}
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/**
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* @brief Restart a new inlink right after the last descriptor
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_link.restart = 1;
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}
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/**
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* @brief Enable DMA RX to return the address of current descriptor when receives error
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*/
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static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].in.in_link.auto_ret = enable;
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}
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/**
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* @brief Check if DMA RX FSM is in IDLE state
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*/
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static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_link.park;
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}
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/**
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* @brief Get RX success EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_suc_eof_des_addr;
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}
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/**
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* @brief Get RX error EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_err_eof_des_addr;
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}
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/**
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* @brief Get current RX descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].in.in_dscr;
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}
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/**
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* @brief Set priority for DMA RX channel
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*/
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static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
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{
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dev->channel[channel].in.in_pri.rx_pri = prio;
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}
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/**
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* @brief Connect DMA RX channel to a given peripheral
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*/
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static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
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{
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dev->channel[channel].in.in_peri_sel.sel = periph_id;
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dev->channel[channel].in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);
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}
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/**
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* @brief Disconnect DMA RX channel from peripheral
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*/
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static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].in.in_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
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dev->channel[channel].in.in_conf0.mem_trans_en = false;
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}
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///////////////////////////////////// TX /////////////////////////////////////////
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/**
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* @brief Get DMA TX channel interrupt status word
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
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}
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/**
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* @brief Enable DMA TX channel interrupt
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*/
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static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK);
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} else {
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dev->intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK);
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}
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}
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/**
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* @brief Clear DMA TX channel interrupt
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK);
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}
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/**
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* @brief Get DMA TX channel interrupt status register address
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*/
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static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
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{
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return (volatile void *)(&dev->intr[channel].st);
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}
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/**
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* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
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*/
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static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf1.out_check_owner = enable;
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}
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/**
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* @brief Enable DMA TX channel burst sending data, disabled by default
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*/
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static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.out_data_burst_en = enable;
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}
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/**
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* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
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*/
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static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.outdscr_burst_en = enable;
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}
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/**
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* @brief Set TX channel EOF mode
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*/
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static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
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{
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dev->channel[channel].out.out_conf0.out_eof_mode = mode;
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}
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/**
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* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
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*/
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static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->channel[channel].out.out_conf0.out_auto_wrback = enable;
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}
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/**
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* @brief Reset DMA TX channel FSM and FIFO pointer
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_conf0.out_rst = 1;
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dev->channel[channel].out.out_conf0.out_rst = 0;
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}
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/**
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* @brief Check if DMA TX FIFO is full
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* @param fifo_level only supports level 1
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*/
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static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.val & 0x01;
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}
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/**
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* @brief Check if DMA TX FIFO is empty
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* @param fifo_level only supports level 1
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*/
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static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.val & 0x02;
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}
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/**
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* @brief Get number of bytes in TX FIFO
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* @param fifo_level only supports level 1
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*/
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static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->channel[channel].out.outfifo_status.outfifo_cnt;
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}
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/**
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* @brief Push data into DMA TX FIFO
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*/
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static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
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{
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dev->channel[channel].out.out_push.outfifo_wdata = data;
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dev->channel[channel].out.out_push.outfifo_push = 1;
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}
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/**
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* @brief Set the descriptor link base address for TX channel
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
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{
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dev->channel[channel].out.out_link.addr = addr;
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}
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/**
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* @brief Start dealing with TX descriptors
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_link.start = 1;
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}
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/**
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* @brief Stop dealing with TX descriptors
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_link.stop = 1;
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}
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/**
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* @brief Restart a new outlink right after the last descriptor
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*/
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__attribute__((always_inline))
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static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_link.restart = 1;
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}
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/**
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* @brief Check if DMA TX FSM is in IDLE state
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*/
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static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].out.out_link.park;
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}
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/**
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* @brief Get TX EOF descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].out.out_eof_des_addr;
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}
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/**
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* @brief Get current TX descriptor's address
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*/
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__attribute__((always_inline))
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static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->channel[channel].out.out_dscr;
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}
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/**
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* @brief Set priority for DMA TX channel
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*/
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static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
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{
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dev->channel[channel].out.out_pri.tx_pri = prio;
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}
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/**
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* @brief Connect DMA TX channel to a given peripheral
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*/
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static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
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{
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(void)periph;
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dev->channel[channel].out.out_peri_sel.sel = periph_id;
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}
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/**
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* @brief Disconnect DMA TX channel from peripheral
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*/
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static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
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{
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dev->channel[channel].out.out_peri_sel.sel = GDMA_LL_INVALID_PERIPH_ID;
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}
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#ifdef __cplusplus
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}
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#endif
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