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244 lines
7.1 KiB
C
244 lines
7.1 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdarg.h>
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#include "esp_attr.h"
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#include "esp_spi_flash.h" //for ``g_flash_guard_default_ops``
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#include "esp_flash.h"
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#include "esp_flash_partitions.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "hal/spi_types.h"
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#endif
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#include "driver/spi_common_internal.h"
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/*
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* OS functions providing delay service and arbitration among chips, and with the cache.
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*
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* The cache needs to be disabled when chips on the SPI1 bus is under operation, hence these functions need to be put
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* into the IRAM,and their data should be put into the DRAM.
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*/
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typedef struct {
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spi_bus_lock_dev_handle_t dev_lock;
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} app_func_arg_t;
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typedef struct {
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app_func_arg_t common_arg; //shared args, must be the first item
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bool no_protect; //to decide whether to check protected region (for the main chip) or not.
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} spi1_app_func_arg_t;
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IRAM_ATTR static void cache_enable(void* arg)
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{
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g_flash_guard_default_ops.end();
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}
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IRAM_ATTR static void cache_disable(void* arg)
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{
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g_flash_guard_default_ops.start();
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}
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static IRAM_ATTR esp_err_t spi_start(void *arg)
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{
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spi_bus_lock_dev_handle_t dev_lock = ((app_func_arg_t *)arg)->dev_lock;
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// wait for other devices (or cache) to finish their operation
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esp_err_t ret = spi_bus_lock_acquire_start(dev_lock, portMAX_DELAY);
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if (ret != ESP_OK) {
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return ret;
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}
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spi_bus_lock_touch(dev_lock);
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t spi_end(void *arg)
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{
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return spi_bus_lock_acquire_end(((app_func_arg_t *)arg)->dev_lock);
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}
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static IRAM_ATTR esp_err_t spi1_start(void *arg)
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{
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#if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
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//use the lock to disable the cache and interrupts before using the SPI bus
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return spi_start(arg);
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#else
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//directly disable the cache and interrupts when lock is not used
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cache_disable(NULL);
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#endif
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t spi1_end(void *arg)
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{
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#if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
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return spi_end(arg);
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#else
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cache_enable(NULL);
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return ESP_OK;
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#endif
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}
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static IRAM_ATTR esp_err_t delay_us(void *arg, unsigned us)
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{
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ets_delay_us(us);
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t spi_flash_os_yield(void *arg)
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{
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#ifdef CONFIG_SPI_FLASH_YIELD_DURING_ERASE
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vTaskDelay(CONFIG_SPI_FLASH_ERASE_YIELD_TICKS);
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#endif
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return ESP_OK;
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}
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static IRAM_ATTR esp_err_t main_flash_region_protected(void* arg, size_t start_addr, size_t size)
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{
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if (((spi1_app_func_arg_t*)arg)->no_protect || esp_partition_main_flash_region_safe(start_addr, size)) {
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//ESP_OK = 0, also means protected==0
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return ESP_OK;
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} else {
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return ESP_ERR_NOT_SUPPORTED;
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}
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}
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static DRAM_ATTR spi1_app_func_arg_t main_flash_arg = {};
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//for SPI1, we have to disable the cache and interrupts before using the SPI bus
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static const DRAM_ATTR esp_flash_os_functions_t esp_flash_spi1_default_os_functions = {
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.start = spi1_start,
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.end = spi1_end,
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.region_protected = main_flash_region_protected,
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.delay_us = delay_us,
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.yield = spi_flash_os_yield,
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};
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static const esp_flash_os_functions_t esp_flash_spi23_default_os_functions = {
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.start = spi_start,
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.end = spi_end,
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.delay_us = delay_us,
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.yield = spi_flash_os_yield
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};
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static spi_bus_lock_dev_handle_t register_dev(int host_id)
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{
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spi_bus_lock_handle_t lock = spi_bus_lock_get_by_id(host_id);
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spi_bus_lock_dev_handle_t dev_handle;
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spi_bus_lock_dev_config_t config = {.flags = SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED};
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esp_err_t err = spi_bus_lock_register_dev(lock, &config, &dev_handle);
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if (err != ESP_OK) {
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return NULL;
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}
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return dev_handle;
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}
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esp_err_t esp_flash_init_os_functions(esp_flash_t *chip, int host_id, int* out_dev_id)
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{
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spi_bus_lock_dev_handle_t dev_handle = NULL;
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// Skip initializing the bus lock when the bus is SPI1 and the bus is not shared with SPI Master
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// driver, leaving dev_handle = NULL
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bool skip_register_dev = (host_id == SPI_HOST);
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#if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
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skip_register_dev = false;
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#endif
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if (!skip_register_dev) {
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dev_handle = register_dev(host_id);
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}
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if (host_id == SPI1_HOST) {
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//SPI1
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chip->os_func = &esp_flash_spi1_default_os_functions;
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chip->os_func_data = heap_caps_malloc(sizeof(spi1_app_func_arg_t),
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MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (chip->os_func_data == NULL) {
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return ESP_ERR_NO_MEM;
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}
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*(spi1_app_func_arg_t*) chip->os_func_data = (spi1_app_func_arg_t) {
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.common_arg = {
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.dev_lock = dev_handle,
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},
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.no_protect = true,
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};
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} else if (host_id == SPI2_HOST || host_id == SPI3_HOST) {
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//SPI2, SPI3
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chip->os_func = &esp_flash_spi23_default_os_functions;
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chip->os_func_data = heap_caps_malloc(sizeof(app_func_arg_t),
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MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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if (chip->os_func_data == NULL) {
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return ESP_ERR_NO_MEM;
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}
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*(app_func_arg_t*) chip->os_func_data = (app_func_arg_t) {
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.dev_lock = dev_handle,
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};
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} else {
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return ESP_ERR_INVALID_ARG;
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}
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// Bus lock not initialized, the device ID should be directly given by application.
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if (dev_handle) {
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*out_dev_id = spi_bus_lock_get_dev_id(dev_handle);
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}
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return ESP_OK;
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}
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esp_err_t esp_flash_deinit_os_functions(esp_flash_t* chip)
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{
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if (chip->os_func_data) {
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spi_bus_lock_dev_handle_t dev_lock = ((app_func_arg_t*)chip->os_func_data)->dev_lock;
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// SPI bus lock is possible not used on SPI1 bus
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if (dev_lock) {
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spi_bus_lock_unregister_dev(dev_lock);
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}
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free(chip->os_func_data);
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}
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chip->os_func = NULL;
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chip->os_func_data = NULL;
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return ESP_OK;
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}
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esp_err_t esp_flash_init_main_bus_lock(void)
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{
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spi_bus_lock_init_main_bus();
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spi_bus_lock_set_bg_control(g_main_spi_bus_lock, cache_enable, cache_disable, NULL);
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esp_err_t err = spi_bus_lock_init_main_dev();
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if (err != ESP_OK) {
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return err;
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}
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return ESP_OK;
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}
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esp_err_t esp_flash_app_enable_os_functions(esp_flash_t* chip)
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{
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main_flash_arg = (spi1_app_func_arg_t) {
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.common_arg = {
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.dev_lock = g_spi_lock_main_flash_dev, //for SPI1,
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},
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.no_protect = false,
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};
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chip->os_func = &esp_flash_spi1_default_os_functions;
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chip->os_func_data = &main_flash_arg;
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return ESP_OK;
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}
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