esp-idf/components/soc
Konstantin Kondrashov 868da0741c aes/sha/mpi: Bugfix a use of shared registers.
This commit resolves a blocking in esp_aes_block function.

Introduce:
The problem was in the fact that AES is switched off at the moment when he should give out the processed data. But because of the disabled, the operation can not be completed successfully, there is an infinite hang. The reason for this behavior is that the registers for controlling the inclusion of AES, SHA, MPI have shared registers and they were not protected from sharing.

Fix some related issue with shared using of AES SHA RSA accelerators.

Closes: https://github.com/espressif/esp-idf/issues/2295#issuecomment-432898137
2018-11-26 02:42:37 +00:00
..
esp32 aes/sha/mpi: Bugfix a use of shared registers. 2018-11-26 02:42:37 +00:00
include/soc soc: Fix check_long_hold_gpio and move def to soc 2018-06-26 12:47:55 +05:00
test soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
CMakeLists.txt cmake: make main a component again 2018-09-13 11:13:27 +08:00
component.mk Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00