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358 lines
11 KiB
C
358 lines
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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Tests for the dac device driver on ESP32-S2 only
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*/
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp_system.h"
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#include "esp_intr_alloc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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#include "driver/rtc_io.h"
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#include "driver/gpio.h"
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#include "unity.h"
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#include "esp_system.h"
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#include "esp_event.h"
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#include "esp_wifi.h"
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#include "esp_log.h"
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#include "nvs_flash.h"
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#include "test_utils.h"
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#include "soc/soc.h"
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#include "soc/spi_reg.h"
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#include "soc/adc_periph.h"
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#include "soc/dac_periph.h"
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#include "soc/spi_periph.h"
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#include "test/test_common_adc.h"
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#include "driver/dac.h"
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#include "soc/system_reg.h"
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#include "esp32s2/rom/lldesc.h"
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#include "test/test_adc_dac_dma.h"
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static const char *TAG = "test_adc";
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#define PLATFORM_SELECT (1) //0: pxp; 1: chip
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#if (PLATFORM_SELECT == 0) //PXP platform
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#include "soc/syscon_reg.h"
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#define SET_BREAK_POINT(flag) REG_WRITE(SYSCON_DATE_REG, flag)
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//PXP clk is slower.
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#define SYS_DELAY_TIME_MOM (1/40)
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#define RTC_SLOW_CLK_FLAG 1 // Slow clock is 32KHz.
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static void test_pxp_deinit_io(void)
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{
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for (int i = 0; i < 22; i++) {
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rtc_gpio_init(i);
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}
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}
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#else
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//PXP clk is slower.
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#define SET_BREAK_POINT(flag)
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#define SYS_DELAY_TIME_MOM (1)
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#define RTC_SLOW_CLK_FLAG 0 // Slow clock is 32KHz.
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#endif
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#define SAR_SIMPLE_NUM 512 // Set out number of enabled unit.
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typedef struct dma_msg {
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uint32_t int_msk;
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uint8_t *data;
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uint32_t data_len;
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} dac_dma_event_t;
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static QueueHandle_t que_dac = NULL;
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static uint8_t link_buf[2][SAR_SIMPLE_NUM*2] = {0};
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static lldesc_t dma1 = {0};
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static lldesc_t dma2 = {0};
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/*******************************************/
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/** DAC-DMA INIT CODE */
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/*******************************************/
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/**
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* DMA liner initialization and start.
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* @param is_loop
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* - true: The two dma linked lists are connected end to end, with no end mark (eof).
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* - false: The two dma linked lists are connected end to end, with end mark (eof).
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* @param int_mask DMA interrupt types.
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*/
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uint32_t dac_dma_linker_init(bool is_alter, bool is_loop)
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{
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/* The DAC output is a sawtooth wave. */
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if (is_alter) {
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for(int i=0; i<SAR_SIMPLE_NUM*2; i++) {
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if(i%2){
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link_buf[0][i] = i%256;
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}else{
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link_buf[0][i] = 256-i%256;
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}
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if(i%2){
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link_buf[1][i] = i%256;
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}else{
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link_buf[1][i] = 256-i%256;
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}
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}
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} else {
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for(int i=0; i<SAR_SIMPLE_NUM; i++) {
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link_buf[0][i] = i%256;
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link_buf[1][i] = i%256;
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}
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}
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dma1 = (lldesc_t) {
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.size = (is_alter) ? SAR_SIMPLE_NUM*2 : SAR_SIMPLE_NUM,
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.length = (is_alter) ? SAR_SIMPLE_NUM*2 : SAR_SIMPLE_NUM,
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.eof = 0,
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.owner = 1,
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.buf = &link_buf[0][0],
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.qe.stqe_next = &dma2,
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};
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dma2 = (lldesc_t) {
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.size = (is_alter) ? SAR_SIMPLE_NUM*2 : SAR_SIMPLE_NUM,
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.length = (is_alter) ? SAR_SIMPLE_NUM*2 : SAR_SIMPLE_NUM,
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.owner = 1,
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.buf = &link_buf[1][0],
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};
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if (is_loop) {
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dma2.eof = 0;
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dma2.qe.stqe_next = &dma1;
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} else {
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dma2.eof = 1;
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dma2.qe.stqe_next = NULL;
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}
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return (uint32_t)&dma1;
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}
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/** ADC-DMA ISR handler. */
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static IRAM_ATTR void dac_dma_isr(void * arg)
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{
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uint32_t int_st = REG_READ(SPI_DMA_INT_ST_REG(3));
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int task_awoken = pdFALSE;
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dac_dma_event_t adc_evt;
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adc_evt.int_msk = int_st;
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REG_WRITE(SPI_DMA_INT_CLR_REG(3), int_st);
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xQueueSendFromISR(que_dac, &adc_evt, &task_awoken);
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ESP_EARLY_LOGV(TAG, "int msk%x, raw%x", int_st, REG_READ(SPI_DMA_INT_RAW_REG(3)));
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if (task_awoken == pdTRUE) {
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portYIELD_FROM_ISR();
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}
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}
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/**
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* Testcase: Check the interrupt types of DAC-DMA.
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*/
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void test_dac_dig_dma_intr_check(dac_digi_convert_mode_t mode)
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{
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ESP_LOGI(TAG, " >> %s - dac mode %d<< ", __func__, mode);
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dac_dma_event_t evt;
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dac_digi_init();
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const dac_digi_config_t cfg = {
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.mode = mode,
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.interval = 100,
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.dig_clk.use_apll = false, // APB clk
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.dig_clk.div_num = 79,
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.dig_clk.div_b = 1,
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.dig_clk.div_a = 0,
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};
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dac_digi_controller_config(&cfg);
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dac_output_enable(DAC_CHANNEL_1);
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dac_output_enable(DAC_CHANNEL_2);
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/* DAC-DMA linker init */
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if (que_dac == NULL) {
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que_dac = xQueueCreate(5, sizeof(dac_dma_event_t));
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} else {
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xQueueReset(que_dac);
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}
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uint32_t int_mask = SPI_OUT_DONE_INT_ENA | SPI_OUT_EOF_INT_ENA | SPI_OUT_TOTAL_EOF_INT_ENA;
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uint32_t dma_addr = dac_dma_linker_init(mode, false);
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adc_dac_dma_isr_register(dac_dma_isr, NULL, int_mask);
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adc_dac_dma_linker_start(DMA_ONLY_DAC_OUTLINK, (void *)dma_addr, int_mask);
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/* ADC-DMA start output */
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dac_digi_start();
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/* Check interrupt type */
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while (int_mask) {
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TEST_ASSERT_EQUAL( xQueueReceive(que_dac, &evt, 2000 / portTICK_PERIOD_MS), pdTRUE );
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ESP_LOGI(TAG, "DAC-DMA intr type 0x%x", evt.int_msk);
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if (evt.int_msk & int_mask) {
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int_mask &= (~evt.int_msk);
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}
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}
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ESP_LOGI(TAG, "DAC-DMA intr test over");
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adc_dac_dma_linker_deinit();
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adc_dac_dma_isr_deregister(dac_dma_isr, NULL);
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TEST_ESP_OK( dac_digi_deinit() );
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}
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TEST_CASE("DAC-DMA interrupt test", "[dac]")
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{
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test_dac_dig_dma_intr_check(DAC_CONV_NORMAL);
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test_dac_dig_dma_intr_check(DAC_CONV_ALTER);
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}
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/*******************************************/
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/** SPI DMA INIT CODE */
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/*******************************************/
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#include "sys/queue.h"
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static bool adc_dac_dma_isr_flag = false;
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/*---------------------------------------------------------------
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INTERRUPT HANDLER
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---------------------------------------------------------------*/
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typedef struct adc_dac_dma_isr_handler_ {
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uint32_t mask;
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intr_handler_t handler;
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void* handler_arg;
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SLIST_ENTRY(adc_dac_dma_isr_handler_) next;
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} adc_dac_dma_isr_handler_t;
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static SLIST_HEAD(adc_dac_dma_isr_handler_list_, adc_dac_dma_isr_handler_) s_adc_dac_dma_isr_handler_list =
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SLIST_HEAD_INITIALIZER(s_adc_dac_dma_isr_handler_list);
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portMUX_TYPE s_isr_handler_list_lock = portMUX_INITIALIZER_UNLOCKED;
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static intr_handle_t s_adc_dac_dma_isr_handle;
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static IRAM_ATTR void adc_dac_dma_isr_default(void* arg)
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{
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uint32_t status = REG_READ(SPI_DMA_INT_ST_REG(3));
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adc_dac_dma_isr_handler_t* it;
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portENTER_CRITICAL_ISR(&s_isr_handler_list_lock);
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SLIST_FOREACH(it, &s_adc_dac_dma_isr_handler_list, next) {
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if (it->mask & status) {
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portEXIT_CRITICAL_ISR(&s_isr_handler_list_lock);
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(*it->handler)(it->handler_arg);
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portENTER_CRITICAL_ISR(&s_isr_handler_list_lock);
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}
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}
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portEXIT_CRITICAL_ISR(&s_isr_handler_list_lock);
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REG_WRITE(SPI_DMA_INT_CLR_REG(3), status);
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}
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static esp_err_t adc_dac_dma_isr_ensure_installed(void)
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{
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esp_err_t err = ESP_OK;
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portENTER_CRITICAL(&s_isr_handler_list_lock);
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if (s_adc_dac_dma_isr_handle) {
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goto out;
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}
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REG_WRITE(SPI_DMA_INT_ENA_REG(3), 0);
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REG_WRITE(SPI_DMA_INT_CLR_REG(3), UINT32_MAX);
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err = esp_intr_alloc(ETS_SPI3_DMA_INTR_SOURCE, 0, &adc_dac_dma_isr_default, NULL, &s_adc_dac_dma_isr_handle);
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if (err != ESP_OK) {
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goto out;
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}
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out:
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portEXIT_CRITICAL(&s_isr_handler_list_lock);
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return err;
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}
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esp_err_t adc_dac_dma_isr_register(intr_handler_t handler, void* handler_arg, uint32_t intr_mask)
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{
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esp_err_t err = adc_dac_dma_isr_ensure_installed();
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if (err != ESP_OK) {
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return err;
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}
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adc_dac_dma_isr_handler_t* item = malloc(sizeof(*item));
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if (item == NULL) {
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return ESP_ERR_NO_MEM;
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}
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item->handler = handler;
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item->handler_arg = handler_arg;
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item->mask = intr_mask;
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portENTER_CRITICAL(&s_isr_handler_list_lock);
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SLIST_INSERT_HEAD(&s_adc_dac_dma_isr_handler_list, item, next);
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portEXIT_CRITICAL(&s_isr_handler_list_lock);
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return ESP_OK;
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}
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esp_err_t adc_dac_dma_isr_deregister(intr_handler_t handler, void* handler_arg)
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{
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adc_dac_dma_isr_handler_t* it;
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adc_dac_dma_isr_handler_t* prev = NULL;
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bool found = false;
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portENTER_CRITICAL(&s_isr_handler_list_lock);
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SLIST_FOREACH(it, &s_adc_dac_dma_isr_handler_list, next) {
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if (it->handler == handler && it->handler_arg == handler_arg) {
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if (it == SLIST_FIRST(&s_adc_dac_dma_isr_handler_list)) {
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SLIST_REMOVE_HEAD(&s_adc_dac_dma_isr_handler_list, next);
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} else {
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SLIST_REMOVE_AFTER(prev, next);
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}
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found = true;
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free(it);
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break;
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}
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prev = it;
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}
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portEXIT_CRITICAL(&s_isr_handler_list_lock);
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return found ? ESP_OK : ESP_ERR_INVALID_STATE;
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}
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void adc_dac_dma_linker_start(spi_dma_link_type_t type, void *dma_addr, uint32_t int_msk)
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{
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_APB_SARADC_CLK_EN_M);
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_DMA_CLK_EN_M);
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN);
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REG_CLR_BIT(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_DMA_RST_M);
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REG_CLR_BIT(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST_M);
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REG_WRITE(SPI_DMA_INT_CLR_REG(3), 0xFFFFFFFF);
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REG_WRITE(SPI_DMA_INT_ENA_REG(3), int_msk | REG_READ(SPI_DMA_INT_ENA_REG(3)));
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if (type & DMA_ONLY_ADC_INLINK) {
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START);
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SET_PERI_REG_BITS(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_ADDR, (uint32_t)dma_addr, 0);
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REG_SET_BIT(SPI_DMA_CONF_REG(3), SPI_IN_RST);
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REG_CLR_BIT(SPI_DMA_CONF_REG(3), SPI_IN_RST);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP);
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START);
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}
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if (type & DMA_ONLY_DAC_OUTLINK) {
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REG_SET_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_STOP);
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REG_CLR_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_START);
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SET_PERI_REG_BITS(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_ADDR, (uint32_t)dma_addr, 0);
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REG_SET_BIT(SPI_DMA_CONF_REG(3), SPI_OUT_RST);
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REG_CLR_BIT(SPI_DMA_CONF_REG(3), SPI_OUT_RST);
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REG_CLR_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_STOP);
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REG_SET_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_START);
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}
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}
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void adc_dac_dma_linker_stop(spi_dma_link_type_t type)
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{
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if (type & DMA_ONLY_ADC_INLINK) {
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START);
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}
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if (type & DMA_ONLY_DAC_OUTLINK) {
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REG_SET_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_STOP);
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REG_CLR_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_START);
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}
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}
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void adc_dac_dma_linker_deinit(void)
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{
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adc_dac_dma_linker_stop(DMA_BOTH_ADC_DAC);
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REG_WRITE(SPI_DMA_INT_CLR_REG(3), 0xFFFFFFFF);
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REG_WRITE(SPI_DMA_INT_ENA_REG(3), 0);
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adc_dac_dma_isr_flag = false;
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}
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/*******************************************/
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/** SPI DMA INIT CODE END */
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/*******************************************/
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#endif // CONFIG_IDF_TARGET_ESP32S2
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