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52e3f09b32
Common spi functionality for sharing the SPI bus between modules is moved from esp_driver_spi to a more fitting location in esp_hw_support (shared HW resource control). This also allows us to decouple the spi_flash driver from esp_driver_spi, removing esp_driver_spi and esp_ringbuf from G1 builds.
64 lines
2.9 KiB
Plaintext
64 lines
2.9 KiB
Plaintext
menu "ESP-Driver:SPI Configurations"
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depends on SOC_GPSPI_SUPPORTED
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config SPI_MASTER_IN_IRAM
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bool "Place transmitting functions of SPI master into IRAM"
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default n
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depends on !FREERTOS_PLACE_FUNCTIONS_INTO_FLASH
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select SPI_MASTER_ISR_IN_IRAM
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select ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM
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help
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Normally only the ISR of SPI master is placed in the IRAM, so that it
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can work without the flash when interrupt is triggered.
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For other functions, there's some possibility that the flash cache
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miss when running inside and out of SPI functions, which may increase
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the interval of SPI transactions.
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Enable this to put ``queue_trans``, ``get_trans_result`` and
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``transmit`` functions into the IRAM to avoid possible cache miss.
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This configuration won't be available if `CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH` is enabled.
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During unit test, this is enabled to measure the ideal case of api.
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config SPI_MASTER_ISR_IN_IRAM
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bool "Place SPI master ISR function into IRAM"
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default y
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depends on !HEAP_PLACE_FUNCTION_INTO_FLASH
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select PERIPH_CTRL_FUNC_IN_IRAM
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select HAL_SPI_MASTER_FUNC_IN_IRAM
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select ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM
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help
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Place the SPI master ISR in to IRAM to avoid possible cache miss.
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Enabling this configuration is possible only when HEAP_PLACE_FUNCTION_INTO_FLASH
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is disabled since the spi master uses can allocate transactions buffers into DMA
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memory section using the heap component API that ipso facto has to be placed in IRAM.
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Also you can forbid the ISR being disabled during flash writing
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access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
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config SPI_SLAVE_IN_IRAM
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bool "Place transmitting functions of SPI slave into IRAM"
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default n
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select SPI_SLAVE_ISR_IN_IRAM
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help
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Normally only the ISR of SPI slave is placed in the IRAM, so that it
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can work without the flash when interrupt is triggered.
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For other functions, there's some possibility that the flash cache
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miss when running inside and out of SPI functions, which may increase
|
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the interval of SPI transactions.
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Enable this to put ``queue_trans``, ``get_trans_result`` and
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``transmit`` functions into the IRAM to avoid possible cache miss.
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config SPI_SLAVE_ISR_IN_IRAM
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bool "Place SPI slave ISR function into IRAM"
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default y
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select PERIPH_CTRL_FUNC_IN_IRAM
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select HAL_SPI_SLAVE_FUNC_IN_IRAM
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help
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Place the SPI slave ISR in to IRAM to avoid possible cache miss.
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Also you can forbid the ISR being disabled during flash writing
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access, by add ESP_INTR_FLAG_IRAM when initializing the driver.
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endmenu # SPI Configuration
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