Angus Gratton 9a2d251912 Merge branch 'feature/coredump_refactor_riscv_support_v4.3' into 'release/v4.3' ... espcoredump: code refactoring and add support for RISC-V implementation (backport v4.3) See merge request espressif/esp-idf!12680		2021-03-12 07:47:02 +00:00
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corefile	fix(coredump): parse registers values from stack	2021-01-29 11:12:21 +08:00
include	Merge branch 'feature/coredump_refactor_riscv_support_v4.3' into 'release/v4.3'	2021-03-12 07:47:02 +00:00
include_core_dump	espcoredump: code refactoring and add support for RISC-V implemetation	2021-03-10 12:19:00 +08:00
src	espcoredump: code refactoring and add support for RISC-V implemetation	2021-03-10 12:19:00 +08:00
test	core dump: modify the test according to the refactor	2021-01-21 15:14:59 +08:00
CMakeLists.txt	espcoredump: code refactoring and add support for RISC-V implemetation	2021-03-10 12:19:00 +08:00
component.mk	espcoredump: code refactoring and add support for RISC-V implemetation	2021-03-10 12:19:00 +08:00
espcoredump.py	core dump: rewrite espcoredump.py with corefile package	2021-01-21 15:14:59 +08:00
Kconfig	espcoredump: code refactoring and add support for RISC-V implemetation	2021-03-10 12:19:00 +08:00
linker.lf	ci: exempt upstream libmbedtls mapping for sha256	2021-01-19 11:17:18 +08:00
sdkconfig.rename	espcoredump: remove ESP32 prefix from config options	2020-09-30 20:22:27 +05:30