Sudeep Mohanty f244a8b209 ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2 ... This commit fixes an issue where in the ULP RISC-V I2C example causes a spurious wakeup of the main CPU because of a Trap signal when the ULP core does not meet the wakeup threshold values. This was due to the fact that the RTC_CNTL_COCPU_DONE signal was being set before the RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V core to not reset properly on each cycle. Closes https://github.com/espressif/esp-idf/issues/10301		2023-01-02 14:21:24 +01:00
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include	Add ULP-RISCV print and bitbanged UART tx API	2022-07-29 12:18:01 +08:00
start.S	ulp-riscv: add support for using ADC as well as an example show-casing it.	2022-07-11 09:31:22 +08:00
ulp_riscv_adc.c	ulp: migrate tests to pytest embedded	2022-08-03 09:36:17 +08:00
ulp_riscv_print.c	Add ULP-RISCV print and bitbanged UART tx API	2022-07-29 12:18:01 +08:00
ulp_riscv_uart.c	Add ULP-RISCV print and bitbanged UART tx API	2022-07-29 12:18:01 +08:00
ulp_riscv_utils.c	ulp-riscv: ULP RISC-V I2C example gets stuck on esp32s2	2023-01-02 14:21:24 +01:00