mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-21 06:56:11 -04:00
216 lines
9.2 KiB
C
216 lines
9.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <strings.h>
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "esp_efuse.h"
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#include "esp_efuse_table.h"
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#include "esp_flash_encrypt.h"
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#include "esp_secure_boot.h"
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#if CONFIG_IDF_TARGET_ESP32
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#define CRYPT_CNT ESP_EFUSE_FLASH_CRYPT_CNT
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#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT
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#else
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#define CRYPT_CNT ESP_EFUSE_SPI_BOOT_CRYPT_CNT
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#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT
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#endif
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static const char *TAG = "flash_encrypt";
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#ifndef BOOTLOADER_BUILD
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void esp_flash_encryption_init_checks()
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{
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esp_flash_enc_mode_t mode;
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#ifdef CONFIG_SECURE_FLASH_CHECK_ENC_EN_IN_APP
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if (!esp_flash_encryption_enabled()) {
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ESP_LOGE(TAG, "Flash encryption eFuse bit was not enabled in bootloader but CONFIG_SECURE_FLASH_ENC_ENABLED is on");
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abort();
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}
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#endif // CONFIG_SECURE_FLASH_CHECK_ENC_EN_IN_APP
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// First check is: if Release mode flash encryption & secure boot are enabled then
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// FLASH_CRYPT_CNT *must* be write protected. This will have happened automatically
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// if bootloader is IDF V4.0 or newer but may not have happened for previous ESP-IDF bootloaders.
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#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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#ifdef CONFIG_SECURE_BOOT
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if (esp_secure_boot_enabled() && esp_flash_encryption_enabled()) {
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bool flash_crypt_cnt_wr_dis = esp_efuse_read_field_bit(WR_DIS_CRYPT_CNT);
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if (!flash_crypt_cnt_wr_dis) {
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uint8_t flash_crypt_cnt = 0;
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esp_efuse_read_field_blob(CRYPT_CNT, &flash_crypt_cnt, CRYPT_CNT[0]->bit_count);
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if (flash_crypt_cnt == (1<<(CRYPT_CNT[0]->bit_count))-1) {
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// If encryption counter is already max, no need to write protect it
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// (this distinction is important on ESP32 ECO3 where write-procted FLASH_CRYPT_CNT also write-protects UART_DL_DIS)
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} else {
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ESP_LOGE(TAG, "Flash encryption & Secure Boot together requires FLASH_CRYPT_CNT efuse to be write protected. Fixing now...");
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esp_flash_write_protect_crypt_cnt();
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}
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}
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}
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#endif // CONFIG_SECURE_BOOT
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#endif // CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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// Second check is to print a warning or error if the current running flash encryption mode
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// doesn't match the expectation from project config (due to mismatched bootloader and app, probably)
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mode = esp_get_flash_encryption_mode();
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if (mode == ESP_FLASH_ENC_MODE_DEVELOPMENT) {
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#ifdef CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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ESP_LOGE(TAG, "Flash encryption settings error: app is configured for RELEASE but efuses are set for DEVELOPMENT");
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ESP_LOGE(TAG, "Mismatch found in security options in bootloader menuconfig and efuse settings. Device is not secure.");
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#else
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ESP_LOGW(TAG, "Flash encryption mode is DEVELOPMENT (not secure)");
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#endif // CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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} else if (mode == ESP_FLASH_ENC_MODE_RELEASE) {
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ESP_LOGI(TAG, "Flash encryption mode is RELEASE");
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}
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}
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#endif // BOOTLOADER_BUILD
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/**
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* This former inlined function must not be defined in the header file anymore.
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* As it depends on efuse component, any use of it outside of `bootloader_support`,
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* would require the caller component to include `efuse` as part of its `REQUIRES` or
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* `PRIV_REQUIRES` entries.
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* Attribute IRAM_ATTR must be specified for the app build.
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*/
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bool IRAM_ATTR esp_flash_encryption_enabled(void)
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{
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uint32_t flash_crypt_cnt = 0;
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#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
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flash_crypt_cnt = efuse_ll_get_flash_crypt_cnt();
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#else
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#if CONFIG_IDF_TARGET_ESP32
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esp_efuse_read_field_blob(ESP_EFUSE_FLASH_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_FLASH_CRYPT_CNT[0]->bit_count);
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#else
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esp_efuse_read_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_SPI_BOOT_CRYPT_CNT[0]->bit_count);
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#endif
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#endif
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/* __builtin_parity is in flash, so we calculate parity inline */
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bool enabled = false;
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while (flash_crypt_cnt) {
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if (flash_crypt_cnt & 1) {
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enabled = !enabled;
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}
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flash_crypt_cnt >>= 1;
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}
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return enabled;
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}
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void esp_flash_write_protect_crypt_cnt(void)
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{
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esp_efuse_write_field_bit(WR_DIS_CRYPT_CNT);
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}
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esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
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{
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bool flash_crypt_cnt_wr_dis = false;
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esp_flash_enc_mode_t mode = ESP_FLASH_ENC_MODE_DEVELOPMENT;
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if (esp_flash_encryption_enabled()) {
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/* Check if FLASH CRYPT CNT is write protected */
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flash_crypt_cnt_wr_dis = esp_efuse_read_field_bit(WR_DIS_CRYPT_CNT);
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if (!flash_crypt_cnt_wr_dis) {
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uint8_t flash_crypt_cnt = 0;
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esp_efuse_read_field_blob(CRYPT_CNT, &flash_crypt_cnt, CRYPT_CNT[0]->bit_count);
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if (flash_crypt_cnt == (1 << (CRYPT_CNT[0]->bit_count)) - 1) {
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flash_crypt_cnt_wr_dis = true;
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}
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}
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if (flash_crypt_cnt_wr_dis) {
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#if CONFIG_IDF_TARGET_ESP32
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bool dis_dl_cache = esp_efuse_read_field_bit(ESP_EFUSE_DISABLE_DL_CACHE);
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bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DISABLE_DL_ENCRYPT);
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bool dis_dl_dec = esp_efuse_read_field_bit(ESP_EFUSE_DISABLE_DL_DECRYPT);
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/* Check if DISABLE_DL_DECRYPT, DISABLE_DL_ENCRYPT & DISABLE_DL_CACHE are set */
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if ( dis_dl_cache && dis_dl_enc && dis_dl_dec ) {
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mode = ESP_FLASH_ENC_MODE_RELEASE;
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}
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
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bool dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
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bool dis_dl_dcache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
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if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) {
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mode = ESP_FLASH_ENC_MODE_RELEASE;
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}
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#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
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bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
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bool dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
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if (dis_dl_enc && dis_dl_icache) {
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mode = ESP_FLASH_ENC_MODE_RELEASE;
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#ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
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// This chip supports two types of key: AES128_DERIVED and AES128.
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// To be in RELEASE mode, it is important for the AES128_DERIVED key that XTS_KEY_LENGTH_256 be write-protected.
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bool xts_key_len_256_wr_dis = esp_efuse_read_field_bit(WR_DIS_CRYPT_CNT);
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mode = (xts_key_len_256_wr_dis) ? ESP_FLASH_ENC_MODE_RELEASE : ESP_FLASH_ENC_MODE_DEVELOPMENT;
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#endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
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}
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#endif
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}
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} else {
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mode = ESP_FLASH_ENC_MODE_DISABLED;
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}
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return mode;
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}
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void esp_flash_encryption_set_release_mode(void)
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{
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esp_flash_enc_mode_t mode = esp_get_flash_encryption_mode();
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if (mode == ESP_FLASH_ENC_MODE_RELEASE) {
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return;
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}
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if (mode == ESP_FLASH_ENC_MODE_DISABLED) {
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ESP_LOGE(TAG, "Flash encryption eFuse is not enabled, abort..");
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abort();
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return;
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}
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// ESP_FLASH_ENC_MODE_DEVELOPMENT -> ESP_FLASH_ENC_MODE_RELEASE
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esp_efuse_batch_write_begin();
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if (!esp_efuse_read_field_bit(WR_DIS_CRYPT_CNT)) {
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size_t flash_crypt_cnt = 0;
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esp_efuse_read_field_cnt(CRYPT_CNT, &flash_crypt_cnt);
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if (flash_crypt_cnt != CRYPT_CNT[0]->bit_count) {
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esp_efuse_write_field_cnt(CRYPT_CNT, CRYPT_CNT[0]->bit_count - flash_crypt_cnt);
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}
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}
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#if CONFIG_IDF_TARGET_ESP32
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esp_efuse_write_field_bit(ESP_EFUSE_DISABLE_DL_CACHE);
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esp_efuse_write_field_bit(ESP_EFUSE_DISABLE_DL_ENCRYPT);
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esp_efuse_write_field_bit(ESP_EFUSE_DISABLE_DL_DECRYPT);
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
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#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
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#ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
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// For AES128_DERIVED, FE key is 16 bytes and XTS_KEY_LENGTH_256 is 0.
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// It is important to protect XTS_KEY_LENGTH_256 from further changing it to 1. Set write protection for this bit.
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// Burning WR_DIS_CRYPT_CNT, blocks further changing of eFuses: DIS_DOWNLOAD_MANUAL_ENCRYPT, SPI_BOOT_CRYPT_CNT, [XTS_KEY_LENGTH_256], SECURE_BOOT_EN.
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esp_efuse_write_field_bit(WR_DIS_CRYPT_CNT);
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#endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
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#else
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ESP_LOGE(TAG, "Flash Encryption support not added, abort..");
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abort();
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#endif
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esp_efuse_disable_rom_download_mode();
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esp_efuse_batch_write_commit();
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if (esp_get_flash_encryption_mode() != ESP_FLASH_ENC_MODE_RELEASE) {
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ESP_LOGE(TAG, "Flash encryption mode is DEVELOPMENT, abort..");
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abort();
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}
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ESP_LOGI(TAG, "Flash encryption mode is RELEASE");
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}
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