LonerDan 1d0442bf99 fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V ...

According to the ESP32-S2/S3 TRM, the output pin's mode is set in the RTC_GPIO_PINn_REG
by programming the RTC_GPIO_PINn_PAD_DRIVER bit. The current ULP RISC-V RTCIO driver
however, incorrectly programs the RTC_IO_TOUCH_PADn_REG register field RTC_IO_TOUCH_PADn_DRV.
This commit fixes the bug.

2024-06-19 09:02:37 +02:00

..

cmake

tools: cmake: check tool supported version with idf_tools.py

2022-10-18 12:27:55 +04:00

ld

ulp-riscv: add support for using ADC as well as an example show-casing it.

2022-07-11 09:31:22 +08:00

test_apps

TWDT: Use the new TWDT Kconfig options in the examples and tests

2023-03-07 10:23:43 +08:00

ulp_common

rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in

2022-05-24 22:59:41 +08:00

ulp_fsm

fix ULP FSM reg ops with addr > 0xFF

2023-06-15 14:00:57 +02:00

ulp_riscv

fix(ulp-risc-v): Set RTC GPIO output mode in the correct register for ULP RISC-V

2024-06-19 09:02:37 +02:00

.build-test-rules.yml

ulp: migrate tests to pytest embedded

2022-08-03 09:36:17 +08:00

CMakeLists.txt

build system: re-add -Wno-format as private flag for some components

2022-08-03 16:42:47 +04:00

component_ulp_common.cmake

ulp: use quotes when specifying files for embedding ulp binaries

2020-02-18 00:12:56 +00:00

esp32ulp_mapgen.py

Drop support for unsupported Python versions

2021-06-21 21:48:49 +02:00

Kconfig

Add ULP-RISCV print and bitbanged UART tx API

2022-07-29 12:18:01 +08:00

project_include.cmake

ulp-riscv: add support for using ADC as well as an example show-casing it.

2022-07-11 09:31:22 +08:00

sdkconfig.rename.esp32

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00

sdkconfig.rename.esp32s2

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00