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https://github.com/espressif/esp-idf.git
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eef66789d4
components/bt: Do not use feature: timer support isr dispatch method disable controller after wake up finished. protect critical section of power down choose clk in sleep components/coex: mac bb power down in light sleep components/coex: Macro changed components/os: protect reserved interrupt number update phy to phy_version 300,6e46ba7,Jan 25 2021 some bugfix
72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "hal/interrupt_controller_hal.h"
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#include "soc/soc_caps.h"
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#if __riscv
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#include "riscv/instruction_decode.h"
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static bool is_interrupt_number_reserved(int interrupt_number)
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{
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//TODO. Workaround to reserve interrupt number 1 for Wi-Fi and 5&8 for Bluetooth.
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if (interrupt_number == 1 || interrupt_number == 5 || interrupt_number == 8) {
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return true;
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}
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extern int _vector_table;
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extern int _interrupt_handler;
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const intptr_t pc = (intptr_t)(&_vector_table + interrupt_number);
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/* JAL instructions are relative to the PC there are executed from. */
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const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc);
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return destination != (intptr_t)&_interrupt_handler;
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}
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#endif
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int_type_t interrupt_controller_hal_desc_type(int interrupt_number)
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{
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#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
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const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
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return (int_desc[interrupt_number].type);
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#else
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return (INTTP_NA);
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#endif
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}
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int interrupt_controller_hal_desc_level(int interrupt_number)
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{
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#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
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const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
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return (int_desc[interrupt_number].level);
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#else
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return 1;
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#endif
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}
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int_desc_flag_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number)
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{
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#ifndef SOC_CPU_HAS_FLEXIBLE_INTC
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const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
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return (int_desc[interrupt_number].cpuflags[cpu_number]);
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#else
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#if __riscv
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return is_interrupt_number_reserved(interrupt_number) ? INTDESC_RESVD : INTDESC_NORMAL;
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#else
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return INTDESC_NORMAL;
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#endif
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#endif
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}
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