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3017b65d4d
In previous gpio default isr, interrupt status bits get cleared at the exit of the isr. However, for edge-triggered interrupt type, the interrupt status bit should be cleared before entering the per-pin handlers to avoid any potential interrupt lost. Closes https://github.com/espressif/esp-idf/pull/6853 |
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dedic_gpio.c | ||
gpio.c | ||
rtc_io.c |