mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
ee0ee4887f
This commit does the following:
- removes the xCoreID member from the TCB when building for single-core
- xCoreID is no longer hard set to 0 when calling "PinnedToCore" task creation
functions in single-core
- Tidy up or add missing xCoreID asserts for functions that take xCoreID as an
argument:
- Functions that set/query a variable of a particular core will call
taskVALID_CORE_ID() to ensure ) 0 <= xCoreID < configNUMBER_OF_CORES
- Task creation functions that accept xCoreID also call taskVALID_CORE_ID()
but also allow tskNO_AFFINITY.
- Fix TaskStatus_t
- Remove xCoreID from TaskStatus_t if configTASKLIST_INCLUDE_COREID is not
defined.
- Set xCoreID to 0 when calling vTaskGetInfo() in single-core builds
439 lines
17 KiB
ArmAsm
439 lines
17 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "portmacro.h"
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#include "freertos/FreeRTOSConfig.h"
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#include "soc/soc_caps.h"
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#include "riscv/rvruntime-frames.h"
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.extern pxCurrentTCBs
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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#include "esp_private/hw_stack_guard.h"
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#endif
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.global port_uxInterruptNesting
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.global port_xSchedulerRunning
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.global xIsrStackTop
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.global pxCurrentTCBs
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.global vTaskSwitchContext
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.global xPortSwitchFlag
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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.global xIsrStackBottom
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.global esp_hw_stack_guard_monitor_stop
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.global esp_hw_stack_guard_monitor_start
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.global esp_hw_stack_guard_set_bounds
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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.section .text
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#if SOC_CPU_COPROC_NUM > 0
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#if SOC_CPU_HAS_FPU
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/* Bit to set in mstatus to enable the FPU */
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#define CSR_MSTATUS_FPU_ENABLE (1 << 13)
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/* Bit to clear in mstatus to disable the FPU */
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#define CSR_MSTATUS_FPU_DISABLE (3 << 13)
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.macro save_fpu_regs frame=sp
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fsw ft0, RV_FPU_FT0(\frame)
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fsw ft1, RV_FPU_FT1(\frame)
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fsw ft2, RV_FPU_FT2(\frame)
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fsw ft3, RV_FPU_FT3(\frame)
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fsw ft4, RV_FPU_FT4(\frame)
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fsw ft5, RV_FPU_FT5(\frame)
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fsw ft6, RV_FPU_FT6(\frame)
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fsw ft7, RV_FPU_FT7(\frame)
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fsw fs0, RV_FPU_FS0(\frame)
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fsw fs1, RV_FPU_FS1(\frame)
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fsw fa0, RV_FPU_FA0(\frame)
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fsw fa1, RV_FPU_FA1(\frame)
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fsw fa2, RV_FPU_FA2(\frame)
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fsw fa3, RV_FPU_FA3(\frame)
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fsw fa4, RV_FPU_FA4(\frame)
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fsw fa5, RV_FPU_FA5(\frame)
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fsw fa6, RV_FPU_FA6(\frame)
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fsw fa7, RV_FPU_FA7(\frame)
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fsw fs2, RV_FPU_FS2(\frame)
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fsw fs3, RV_FPU_FS3(\frame)
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fsw fs4, RV_FPU_FS4(\frame)
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fsw fs5, RV_FPU_FS5(\frame)
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fsw fs6, RV_FPU_FS6(\frame)
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fsw fs7, RV_FPU_FS7(\frame)
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fsw fs8, RV_FPU_FS8(\frame)
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fsw fs9, RV_FPU_FS9(\frame)
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fsw fs10, RV_FPU_FS10(\frame)
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fsw fs11, RV_FPU_FS11(\frame)
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fsw ft8, RV_FPU_FT8 (\frame)
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fsw ft9, RV_FPU_FT9 (\frame)
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fsw ft10, RV_FPU_FT10(\frame)
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fsw ft11, RV_FPU_FT11(\frame)
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.endm
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.macro restore_fpu_regs frame=sp
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flw ft0, RV_FPU_FT0(\frame)
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flw ft1, RV_FPU_FT1(\frame)
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flw ft2, RV_FPU_FT2(\frame)
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flw ft3, RV_FPU_FT3(\frame)
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flw ft4, RV_FPU_FT4(\frame)
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flw ft5, RV_FPU_FT5(\frame)
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flw ft6, RV_FPU_FT6(\frame)
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flw ft7, RV_FPU_FT7(\frame)
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flw fs0, RV_FPU_FS0(\frame)
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flw fs1, RV_FPU_FS1(\frame)
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flw fa0, RV_FPU_FA0(\frame)
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flw fa1, RV_FPU_FA1(\frame)
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flw fa2, RV_FPU_FA2(\frame)
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flw fa3, RV_FPU_FA3(\frame)
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flw fa4, RV_FPU_FA4(\frame)
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flw fa5, RV_FPU_FA5(\frame)
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flw fa6, RV_FPU_FA6(\frame)
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flw fa7, RV_FPU_FA7(\frame)
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flw fs2, RV_FPU_FS2(\frame)
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flw fs3, RV_FPU_FS3(\frame)
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flw fs4, RV_FPU_FS4(\frame)
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flw fs5, RV_FPU_FS5(\frame)
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flw fs6, RV_FPU_FS6(\frame)
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flw fs7, RV_FPU_FS7(\frame)
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flw fs8, RV_FPU_FS8(\frame)
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flw fs9, RV_FPU_FS9(\frame)
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flw fs10, RV_FPU_FS10(\frame)
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flw fs11, RV_FPU_FS11(\frame)
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flw ft8, RV_FPU_FT8(\frame)
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flw ft9, RV_FPU_FT9(\frame)
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flw ft10, RV_FPU_FT10(\frame)
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flw ft11, RV_FPU_FT11(\frame)
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.endm
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.macro fpu_read_dirty_bit reg
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csrr \reg, mstatus
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srli \reg, \reg, 13
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andi \reg, \reg, 1
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.endm
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.macro fpu_clear_dirty_bit reg
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li \reg, 1 << 13
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csrc mstatus, \reg
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.endm
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.macro fpu_enable reg
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li \reg, CSR_MSTATUS_FPU_ENABLE
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csrs mstatus, \reg
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.endm
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.macro fpu_disable reg
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li \reg, CSR_MSTATUS_FPU_DISABLE
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csrc mstatus, \reg
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.endm
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.global vPortTaskPinToCore
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.global vPortCoprocUsedInISR
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.global pxPortUpdateCoprocOwner
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/**
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* @brief Save the current FPU context in the FPU owner's save area
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*
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* @param sp Interuptee's RvExcFrame address
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*
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* Note: Since this routine is ONLY meant to be called from _panic_handler routine,
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* it is possible to alter `s0-s11` registers
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*/
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.global rtos_save_fpu_coproc
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.type rtos_save_fpu_coproc, @function
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rtos_save_fpu_coproc:
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/* If we are in an interrupt context, we have to abort. We don't allow using the FPU from ISR */
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#if ( configNUM_CORES > 1 )
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csrr a2, mhartid /* a2 = coreID */
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slli a2, a2, 2 /* a2 = coreID * 4 */
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la a1, port_uxInterruptNesting /* a1 = &port_uxInterruptNesting */
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add a1, a1, a2 /* a1 = &port_uxInterruptNesting[coreID] */
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lw a1, 0(a1) /* a1 = port_uxInterruptNesting[coreID] */
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#else /* ( configNUM_CORES <= 1 ) */
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lw a1, (port_uxInterruptNesting) /* a1 = port_uxInterruptNesting */
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#endif /* ( configNUM_CORES > 1 ) */
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/* SP still contains the RvExcFrame address */
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mv a0, sp
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bnez a1, vPortCoprocUsedInISR
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/* Enable the FPU needed by the current task */
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fpu_enable a1
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mv s0, ra
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call rtos_current_tcb
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/* If the current TCB is NULL, the FPU is used during initialization, even before
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* the scheduler started. Consider this a valid usage, the FPU will be disabled
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* as soon as the scheduler is started anyway*/
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beqz a0, rtos_save_fpu_coproc_norestore
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mv s1, a0 /* s1 = pxCurrentTCBs */
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/* Prepare parameters of pxPortUpdateCoprocOwner */
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mv a2, a0
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li a1, FPU_COPROC_IDX
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csrr a0, mhartid
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call pxPortUpdateCoprocOwner
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/* If the save area is NULL, no need to save context */
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beqz a0, rtos_save_fpu_coproc_nosave
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/* Save the FPU context in the structure */
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lw a0, RV_COPROC_SA+FPU_COPROC_IDX*4(a0) /* a0 = RvCoprocSaveArea->sa_coprocs[FPU_COPROC_IDX] */
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save_fpu_regs a0
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csrr a1, fcsr
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sw a1, RV_FPU_FCSR(a0)
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rtos_save_fpu_coproc_nosave:
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#if ( configNUM_CORES > 1 )
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/* Pin current task to current core */
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mv a0, s1
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csrr a1, mhartid
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call vPortTaskPinToCore
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#endif /* configNUM_CORES > 1 */
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/* Check if we have to restore a previous FPU context from the current TCB */
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mv a0, s1
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call pxPortGetCoprocArea
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/* Get the enable flags from the coprocessor save area */
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lw a1, RV_COPROC_ENABLE(a0)
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/* To avoid having branches below, set the FPU enable flag now */
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ori a2, a1, 1 << FPU_COPROC_IDX
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sw a2, RV_COPROC_ENABLE(a0)
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/* Check if the former FPU enable bit was set */
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andi a2, a1, 1 << FPU_COPROC_IDX
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beqz a2, rtos_save_fpu_coproc_norestore
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/* FPU enable bit was set, restore the FPU context */
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lw a0, RV_COPROC_SA+FPU_COPROC_IDX*4(a0) /* a0 = RvCoprocSaveArea->sa_coprocs[FPU_COPROC_IDX] */
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restore_fpu_regs a0
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lw a1, RV_FPU_FCSR(a0)
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csrw fcsr, a1
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rtos_save_fpu_coproc_norestore:
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/* Return from routine via s0, instead of ra */
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jr s0
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.size rtos_save_fpu_coproc, .-rtos_save_fpu_coproc
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#endif /* SOC_CPU_HAS_FPU */
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#endif /* SOC_CPU_COPROC_NUM > 0 */
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/**
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* @brief Get current TCB on current core
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*/
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.type rtos_current_tcb, @function
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rtos_current_tcb:
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#if ( configNUM_CORES > 1 )
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csrr a1, mhartid
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slli a1, a1, 2
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la a0, pxCurrentTCBs /* a0 = &pxCurrentTCBs */
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add a0, a0, a1 /* a0 = &pxCurrentTCBs[coreID] */
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lw a0, 0(a0) /* a0 = pxCurrentTCBs[coreID] */
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#else
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/* Recover the stack of next task */
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lw a0, pxCurrentTCBs
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#endif /* ( configNUM_CORES > 1 ) */
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ret
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.size, .-rtos_current_tcb
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/**
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* This function makes the RTOS aware about an ISR entering. It takes the
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* current task stack pointer and places it into the pxCurrentTCBs.
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* It then loads the ISR stack into sp.
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* TODO: ISR nesting code improvements ?
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* In the routines below, let's use a0-a5 registers to let the compiler generate
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* 16-bit instructions.
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*/
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.global rtos_int_enter
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.type rtos_int_enter, @function
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rtos_int_enter:
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#if ( configNUM_CORES > 1 )
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csrr a5, mhartid /* a5 = coreID */
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slli a5, a5, 2 /* a5 = coreID * 4 */
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la a0, port_xSchedulerRunning /* a0 = &port_xSchedulerRunning */
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add a0, a0, a5 /* a0 = &port_xSchedulerRunning[coreID] */
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lw a0, (a0) /* a0 = port_xSchedulerRunning[coreID] */
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#else
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lw a0, port_xSchedulerRunning /* a0 = port_xSchedulerRunning */
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#endif /* ( configNUM_CORES > 1 ) */
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beqz a0, rtos_int_enter_end /* if (port_xSchedulerRunning[coreID] == 0) jump to rtos_int_enter_end */
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/* Increment the ISR nesting count */
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la a0, port_uxInterruptNesting /* a0 = &port_uxInterruptNesting */
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#if ( configNUM_CORES > 1 )
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add a0, a0, a5 /* a0 = &port_uxInterruptNesting[coreID] // a5 already contains coreID * 4 */
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#endif /* ( configNUM_CORES > 1 ) */
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lw a1, 0(a0) /* a1 = port_uxInterruptNesting[coreID] */
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addi a2, a1, 1 /* a2 = a1 + 1 */
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sw a2, 0(a0) /* port_uxInterruptNesting[coreID] = a2 */
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/* If we reached here from another low-priority ISR, i.e, port_uxInterruptNesting[coreID] > 0, then skip stack pushing to TCB */
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bnez a1, rtos_int_enter_end /* if (port_uxInterruptNesting[coreID] > 0) jump to rtos_int_enter_end */
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#if SOC_CPU_COPROC_NUM > 0
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/* Disable the FPU to forbid the ISR from using it. We don't need to re-enable it manually since the caller
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* will restore `mstatus` before returning from interrupt. */
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fpu_disable a0
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#endif /* SOC_CPU_COPROC_NUM > 0 */
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* esp_hw_stack_guard_monitor_stop(); pass the scratch registers */
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ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE a0 a1
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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/* Save the current sp in pxCurrentTCBs[coreID] and load the ISR stack on to sp */
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#if ( configNUM_CORES > 1 )
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la a0, pxCurrentTCBs /* a0 = &pxCurrentTCBs */
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add a0, a0, a5 /* a0 = &pxCurrentTCBs[coreID] // a5 already contains coreID * 4 */
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lw a0, (a0) /* a0 = pxCurrentTCBs[coreID] */
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sw sp, 0(a0) /* pxCurrentTCBs[coreID] = sp */
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la a0, xIsrStackTop /* a0 = &xIsrStackTop */
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add a0, a0, a5 /* a0 = &xIsrStackTop[coreID] // a5 already contains coreID * 4 */
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lw sp, (a0) /* sp = xIsrStackTop[coreID] */
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#else
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lw a0, pxCurrentTCBs /* a0 = pxCurrentTCBs */
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sw sp, 0(a0) /* pxCurrentTCBs[0] = sp */
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lw sp, xIsrStackTop /* sp = xIsrStackTop */
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#endif /* ( configNUM_CORES > 1 ) */
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#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
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/* Prepare the parameters for esp_hw_stack_guard_set_bounds(xIsrStackBottom, xIsrStackTop); */
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#if ( configNUM_CORES > 1 )
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/* Load the xIsrStack for the current core and set the new bounds */
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la a0, xIsrStackBottom
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add a0, a0, a5 /* a0 = &xIsrStackBottom[coreID] */
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lw a0, (a0) /* a0 = xIsrStackBottom[coreID] */
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#else
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lw a0, xIsrStackBottom
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#endif /* ( configNUM_CORES > 1 ) */
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mv a1, sp
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/* esp_hw_stack_guard_set_bounds(xIsrStackBottom[coreID], xIsrStackTop[coreID]);
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*/
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ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE a2
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ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE a0 a1
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#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
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rtos_int_enter_end:
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ret
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/**
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* @brief Restore the stack pointer of the next task to run.
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*
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* @param a0 Former mstatus
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*
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* @returns New mstatus (potentially with coprocessors disabled)
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*/
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.global rtos_int_exit
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.type rtos_int_exit, @function
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rtos_int_exit:
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/* To speed up this routine and because this current routine is only meant to be called from the interrupt
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* handler, let's use callee-saved registers instead of stack space. Registers `s3-s11` are not used by
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* the caller */
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mv s11, a0
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#if ( configNUM_CORES > 1 )
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csrr a1, mhartid /* a1 = coreID */
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slli a1, a1, 2 /* a1 = a1 * 4 */
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la a0, port_xSchedulerRunning /* a0 = &port_xSchedulerRunning */
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add a0, a0, a1 /* a0 = &port_xSchedulerRunning[coreID] */
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lw a0, (a0) /* a0 = port_xSchedulerRunning[coreID] */
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#else
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lw a0, port_xSchedulerRunning /* a0 = port_xSchedulerRunning */
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#endif /* ( configNUM_CORES > 1 ) */
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beqz a0, rtos_int_exit_end /* if (port_uxSchedulerRunning == 0) jump to rtos_int_exit_end */
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/* Update nesting interrupts counter */
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la a2, port_uxInterruptNesting /* a2 = &port_uxInterruptNesting */
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#if ( configNUM_CORES > 1 )
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add a2, a2, a1 /* a2 = &port_uxInterruptNesting[coreID] // a1 already contains coreID * 4 */
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#endif /* ( configNUM_CORES > 1 ) */
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lw a0, 0(a2) /* a0 = port_uxInterruptNesting[coreID] */
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/* Already zero, protect against underflow */
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beqz a0, isr_skip_decrement /* if (port_uxInterruptNesting[coreID] == 0) jump to isr_skip_decrement */
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addi a0, a0, -1 /* a0 = a0 - 1 */
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sw a0, 0(a2) /* port_uxInterruptNesting[coreID] = a0 */
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/* May still have interrupts pending, skip section below and exit */
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bnez a0, rtos_int_exit_end
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isr_skip_decrement:
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/* If the CPU reached this label, a2 (uxInterruptNesting) is 0 for sure */
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/* Schedule the next task if a yield is pending */
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la a0, xPortSwitchFlag /* a0 = &xPortSwitchFlag */
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#if ( configNUM_CORES > 1 )
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add a0, a0, a1 /* a0 = &xPortSwitchFlag[coreID] // a1 already contains coreID * 4 */
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#endif /* ( configNUM_CORES > 1 ) */
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lw a2, 0(a0) /* a2 = xPortSwitchFlag[coreID] */
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beqz a2, no_switch /* if (xPortSwitchFlag[coreID] == 0) jump to no_switch */
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/* Preserve return address and schedule next task. To speed up the process, and because this current routine
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* is only meant to be called from the interrupt handle, let's save some speed and space by using callee-saved
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* registers instead of stack space. Registers `s3-s11` are not used by the caller */
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mv s10, ra
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#if ( SOC_CPU_COPROC_NUM > 0 )
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/* In the cases where the newly scheduled task is different from the previously running one,
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* we have to disable the coprocessor(s) to let them trigger an exception on first use.
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* Else, if the same task is scheduled, do not change the coprocessor(s) state. */
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call rtos_current_tcb
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mv s9, a0
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call vTaskSwitchContext
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call rtos_current_tcb
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beq a0, s9, rtos_int_exit_no_change
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/* Disable the coprocessors in s11 register (former mstatus) */
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li a0, ~CSR_MSTATUS_FPU_DISABLE
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and s11, s11, a0
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rtos_int_exit_no_change:
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|
#else /* ( SOC_CPU_COPROC_NUM == 0 ) */
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|
call vTaskSwitchContext
|
|
#endif /* ( SOC_CPU_COPROC_NUM > 0 ) */
|
|
mv ra, s10
|
|
|
|
/* Clears the switch pending flag */
|
|
la a0, xPortSwitchFlag /* a0 = &xPortSwitchFlag */
|
|
#if ( configNUM_CORES > 1 )
|
|
/* C routine vTaskSwitchContext may change the temp registers, so we read again */
|
|
csrr a1, mhartid /* a1 = coreID */
|
|
slli a1, a1, 2 /* a1 = a1 * 4 */
|
|
add a0, a0, a1 /* a0 = &xPortSwitchFlag[coreID]; */
|
|
#endif /* ( configNUM_CORES > 1 ) */
|
|
sw zero, 0(a0) /* xPortSwitchFlag[coreID] = 0; */
|
|
|
|
no_switch:
|
|
|
|
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
|
|
/* esp_hw_stack_guard_monitor_stop(); pass the scratch registers */
|
|
ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE a0 a1
|
|
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
|
|
|
|
|
|
#if ( configNUM_CORES > 1 )
|
|
/* Recover the stack of next task and prepare to exit */
|
|
csrr a1, mhartid
|
|
slli a1, a1, 2
|
|
la a0, pxCurrentTCBs /* a0 = &pxCurrentTCBs */
|
|
add a0, a0, a1 /* a0 = &pxCurrentTCBs[coreID] */
|
|
lw a0, 0(a0) /* a0 = pxCurrentTCBs[coreID] */
|
|
lw sp, 0(a0) /* sp = previous sp */
|
|
#else
|
|
/* Recover the stack of next task */
|
|
lw a0, pxCurrentTCBs
|
|
lw sp, 0(a0)
|
|
#endif /* ( configNUM_CORES > 1 ) */
|
|
|
|
|
|
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
|
|
/* esp_hw_stack_guard_set_bounds(pxCurrentTCBs[0]->pxStack,
|
|
* pxCurrentTCBs[0]->pxEndOfStack);
|
|
*/
|
|
lw a1, PORT_OFFSET_PX_END_OF_STACK(a0)
|
|
lw a0, PORT_OFFSET_PX_STACK(a0)
|
|
ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE a2
|
|
/* esp_hw_stack_guard_monitor_start(); */
|
|
ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE a0 a1
|
|
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
|
|
|
|
rtos_int_exit_end:
|
|
mv a0, s11 /* a0 = new mstatus */
|
|
ret
|